DESIGN INFORMATION Trace A is the time-corrected input pulse and trace B the residue amplifier output. The light compensation permits very fast slewing but excessive ringing amplitude over a protracted time results. The ringing is so severe that it feeds through during a portion of the sample gate off-period, although no overdrive results. When sampling is initiated (just prior to the sixth vertical division) the ringing is seen to be in its final stages, although still offensive. Total settling time is about 2.8µ s. Figure 9 presents the opposite extreme. Here, a large value compensation capacitor eliminates all ringing but slows down the amplifier so much that settling stretches out to 3.3µs. The best case appears in Figure 10. This photo was taken with the compensation capacitor carefully chosen for the best possible settling time. Damping is tightly controlled and settling time goes down to 1.7µ s. A = 5V/DIV Settling Times of Various Amplifiers The previous results, using the LT1468 amplifier, provide extremely fast settling times with high accuracy over temperature. Many applications can tolerate reduced speed, reduced temperature stability or both. Settling times for a number of amplifiers, along with commentary, can be found in LTC Application Note 74, Figure 34. “Optimized” settling times were recorded after individually trimming the feedback capacitors. The “conservative” times represent the worst-case settling times using standard-value compensation capacitors with no trimming. Conclusion B = 500µV/DIV 500ns/DIV Figure 10. Optimal feedback capacitance yields a tightly damped signature and the best settling time (tSETTLE = 1.7µs). The sampling-based settling-time circuit appears to be a very useful measurement solution. Expanded discussion and tutorial appear in this article’s “root” publication: L TC Application Note 74, Component and Measurement Advances Ensure 16Bit DAC Settling Time. Net1 and Net2 Serial Interface Chip Set Supports Test Mode by David Soo Some serial networks use a test mode to exercise all of the circuits in the interface. The network is divided into local and remote data terminal equipment (DTE) and data-circuitterminating equipment (DCE), as shown in Figure 1. Once the network is placed in a test mode, the local DTE will transmit on the driver circuits and expect to receive the same signals back from either a local or remote DCE. These tests are called local or remote loopback. As introduced in the February 1998 issue of Linear Technology, the LTC1543/LTC1544/LTC1344A chip set has taken the integrated approach LOCAL DTE LOCAL DCE LL to multiple protocol. By using this chip set, the Net1 and Net2 design work is done. The LTC1545 extends the family by offering test mode capability. By replacing the 6-circuit LTC1544 with the 9-circuit LTC1545, the optional circuits TM (Test Mode), RL (Remote Loopback) and LL (Local Loopback) can now be implemented. Figure 2 shows a typical application using the LTC1543, LTC1545 and LTC1344A. By just mapping the chip pins to the connector, the design of the interface port is complete. The chip set supports the V.28, V.35, V.36, RS449, EIA-530, EIA-530A or X.21 protocols in either DTE or DCE mode. REMOTE RL DCE REMOTE DTE Shown here is a DCE mode connection to a DB-25 connector. The mode-select pins, M0, M1 and M2, are used to select the interface protocol, as summarized in Table 1. Table 1. Mode pin functions LTC1543/LTC1545 Mode Name M2 M1 M0 Not Used 0 0 0 EIA-530A 0 0 1 EIA-530 0 1 0 X.21 0 1 1 V.35 1 0 0 RS449/V.36 1 0 1 RS232/V.28 1 1 0 No Cable 1 1 1 Figure 1. Serial network 34 Linear Technology Magazine • November 1998 DESIGN INFORMATION C6 C7 C8 100pF 100pF 100pF 3 8 11 12 13 LTC1344A VCC 5V C1 1µF C5 1µF LTC1543 5 RXD RXC D2 7 R1 9 SCTE R2 10 TXD 11 12 13 NC 14 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 VCC 3 23 16 22 17 21 9 RXD A (104) RXD B RXC A (115) RXC B D3 8 TXC VEE C12 1µF 24 D1 6 2 C4 3.3µF M0 C2– 27 VEE 26 CHARGE 2 C1+ PUMP 4 VCC 25 1 C1 M1 C2 1µF – 21 LATCH VCC DCE/DTE C2 VDD + C3 1µF C13 1µF + 28 M2 14 3 R3 20 15 19 12 18 24 17 11 16 2 15 14 M0 7 M1 M2 1 VEE DCE/DTE TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101) VCC C10 1µF C9 1µF 1,19 VCC 2,20 VDD 3 CTS D1 4 DSR VEE GND D2 5 LTC1545 R1 7 DTR R2 R3 9 RI RL R5 18 11 12 13 NC 14 33 32 6 31 22 30 8 29 10 28 20 27 23 CTS A (106) CTS B DSR A (107) DSR B D5 M0 D4ENB M1 M2 R4EN DCD A (109) DCD B DTR A (108) DTR B 4 RTS A (105) 19 RTS B 24 R4 17 TM 5 13 25 D4 10 LL 34 26 8 RTS C11 1µF 35 D3 6 DCD DB-25 FEMALE CONNECTOR 36 RI (125)* 23 18 22 21 21 25 LL (141) RL (140) TM (142) 15 16 NC *OPTIONAL: FOR USE WITH DB-26 CONNECTOR DCE/DTE M0 M1 M2 1544 F24 Figure 2. Typical application: Controller-selectable DCE port with DB-25 connector Linear Technology Magazine • November 1998 35