DESIGN FEATURES A 10MB/s Multiple-Protocol Chip Set Supports Net1 and Net2 Standards by David Soo Introduction Typical Application With the increase in multinational computer networks comes the need for the network equipment to support different serial protocols. One solution is to provide a different serial interface board for each market. This can become unmanageable as product volume increases. The issues of board swapping and inventory are often discounted. Another solution is to place all of the serial interfaces, each isolated, on a single board. For example, when the product is sold with V.35, the serial cable is mapped to that section of the board. This requires a large connector plus signal routing and board space. The best solution is to support many different serial protocols on one connector, but that requires the circuitry for each serial protocol to share the same connector pins. At first glance this may not appear to be difficult. Further examination reveals conflicting line-termination standards that require resistors to be switched to the connector pins. As the designer becomes occupied with the details of the interface specification, there is always the possibility that one small detail will be missed. This compliance headache causes designers to seek out a cost-effective integrated solution. With the LTC1543, LTC1544 and LTC1344A, LTC has taken the integrated approach to multiple-protocol. It does not make sense to use a handful of standard interface parts when Net1 and Net2 compliance is guaranteed with the LTC1543, LTC1544 and LTC1344A. Detecon, Inc. documents this compliance in Test Report No. NET2/102201/97. With this chip set, network designers can concentrate on functions that increase the end-product value rather than on standards compliance. Like the LTC1343 software-selectable multiprotocol transceiver, introduced in the August, 1996 issue of Linear Technology , the LTC1543/LTC1544/ LTC1344A chip set creates a complete software-selectable serial interface using an inexpensive DB25 connector. The main difference between these parts is the division of functions: the LTC1343 can be configured as a data/clock chip or as a control-signal chip using the CTRL/ CLK pin, whereas the LTC1543 is a dedicated data/clock chip and the LTC1544 is a control-signal chip. The chip set supports the V.28 (RS232), V.35, V.36, RS449, EIA-530, EIA-530A and X.21 protocols in either DTE or DCE mode. Figure 1 shows a typical application using the LTC1543, LTC1544 and LTC1344A. By just mapping the chip pins to the connector, the design of the interface port is complete. The figure shows a DCE mode connection to a DB-25 connector. The LTC1543 contains three drivers and three receivers, whereas the LTC1544 contains four drivers and four receivers. The L TC1344A contains six switchable resistive terminators that are connected only to the high speed clock and data signals. When the interface protocol is Linear Technology Magazine • February 1998 Table 1. Mode pin functions LTC1543/LTC1544 Mode Name Not Used EIA-530A EIA-530 X.21 V.35 RS449/V.36 RS232/V.28 No Cable M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 changed via the mode selection pins, M2, M1 and M0, the drivers, receivers and line terminators are placed in their proper configuration. The mode pin functions are summarized in Table 1. There are internal 50µA pullup current sources on the mode select pins, DCE/DTE and the INVERT pins. DTE vs DCE Operation The LTC1543/LTC1544/LTC1344A chip set can be configured for either DTE or DCE operation in one of two ways. The first way is when the chip set is a dedicated DTE or DCE port with a connector of appropriate gender. The second way is when the port has one connector that can be configured for DTE or DCE operation by rerouting the signals to the chip set using a dedicated DTE or DCE cable. Figure 1 is an example of a dedicated DCE port using a female DB-25 connector. The complement to this port is the DTE-only port using a male DB25 connector, as shown in Figure 2. If the port must accommodate both DTE and DCE modes, the mapping of the drivers and receivers to connector pins must change accordingly. For example, in Figure 1, driver 1 in the LTC1543 is connected to pin 3 and pin 16 of the DB-25 connector. In DTE mode, as shown in Figure 2, driver 1 is mapped to pins 2 and 14 of the DB25 connector. A port that can be configured for either DTE or DCE operation is shown in Figure 3. This configuration requires separate cables for proper signal routing. Cable-Selectable Multiprotocol Interface The interface protocol may be selected by simply plugging the appropriate interface cable into the connector. A cable-selectable multiprotocol DTE/ DCE interface is shown in Figure 4. text continued on page 32/figures on pp. 18–22 17 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 + 3 1 C3 C1 + 1.0µF 1.0µF C5 1µF 2 4 + 5 RXD 6 RXC 7 8 TXC 9 SCTE TXD 10 11 12 13 14 NC 28 CHARGE PUMP D1 D2 27 26 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 MO M1 M2 VCC VEE 5.0V VCC DCE/DTE LATCH 21 VCC 1 + C2 1.0µF DB-25 FEMALE CONNECTOR C4 + 3.3µF 25 24 3 23 16 22 17 21 9 20 15 19 12 18 24 17 11 16 2 15 14 RXD A (104) RXD B RXC A (115) RXC B D3 R1 R2 R3 M0 M1 M2 DCE/DTE 7 1 LTC1543 TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101) VCC 1 VCC 2 V DD CTS DSR 3 4 5 DCD DTR RTS LL 6 7 8 10 9 11 12 13 14 NC VEE GND D1 D2 28 27 26 5 25 13 24 6 23 22 CTS A (106) CTS B DSR A (107) DSR B D3 R1 R2 R3 R4 22 8 21 10 20 20 19 23 18 4 17 19 16 18 DCD A (109) DCD B DTR A (108) DTR B RTS A (105) RTS B LL A (141) D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 M2 M1 M0 1544_01.eps Figure 1. Controller-selectable DCE port with DB-25 connector 18 Linear Technology Magazine • February 1998 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 3 1 + C3 C1 + 1.0µF 1.0µF C5 1µF 2 4 + CHARGE PUMP 27 26 5 6 SCTE 7 8 TXC 9 RXC 10 D1 D2 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 M1 MO 21 1 + C2 1.0µF DB-25 MALE CONNECTOR C4 + 3.3µF 25 TXD RXD 28 M2 VCC VEE 5.0V VCC DCE/DTE LATCH 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 TXD A (103) TXD B SCTE A (113) SCTE B D3 R1 R2 R3 11 M0 12 M1 13 M2 14 DCE/DTE 7 1 LTC1543 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SGND (102) SHIELD (101) VCC 1 VCC 2 V DD RTS DTR 3 D1 4 D2 5 DCD DSR CTS LL 28 27 26 4 25 19 24 20 23 23 RTS A (105) RTS B DTR A (108) DTR B D3 6 R1 7 R2 8 R3 10 R4 9 11 12 13 14 VEE GND 22 8 21 10 20 6 19 22 18 5 17 13 16 18 DCD A (109) DCD B DSR A (107) DSR B CTS A (106) CTS B LL A (141) D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 M2 M1 M0 1544_02.eps Figure 2. Controller-selectable multiprotocol DTE port with DB-25 connector Linear Technology Magazine • February 1998 19 DESIGN FEATURES C6 100pF C8 100pF C7 100pF 8 3 11 12 13 LTC1344A 14 2 + 3 1 C3 C1 + 1.0µF 1.0µF C5 1µF 2 4 + 28 CHARGE PUMP 27 26 DTE_SCTE/ DCE_RXC 6 7 DTE_TXC/ DCE_TXC 8 DTE_RXC/ DCE_SCTE 9 DTE_RXD/ DCE_TXD 10 D1 D2 4 6 7 9 10 M1 MO 21 16 15 18 17 19 20 22 23 24 1 + C2 1.0µF DB-25 CONNECTOR C4 + 3.3µF 25 5 DTE_TXD/ DCE_RXD 5 M2 VEE VCC 5.0V VCC DCE/DTE LATCH 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 R1 R2 R3 7 1 LTC1543 1 VCC 2 V DD DTE_RTS/ DCE_CTS 3 DTE_DTR/ DCE_DSR 4 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 DTE_CTS/ DCE_RTS 8 DTE_LL/ DCE_LL 10 9 11 12 13 14 DCE RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B D3 11 M0 12 M1 13 M2 14 DCE/DTE VCC DTE TXD A VEE GND D1 D2 SGND SHIELD 28 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B LL A LL A D3 R1 R2 R3 R4 22 8 21 10 20 6 19 22 18 5 17 13 16 18 D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 DCE/DTE M2 M1 M0 1544_03.eps Figure 3. Controller-selectable DTE/DCE port with DB-25 connector 20 Linear Technology Magazine • February 1998 DESIGN FEATURES CABLE WIRING FOR DTE/DCE SELECTION PIN 25 V.35 PIN 7 PIN 7 DTE PIN 7 RS449, V.36 NC PIN 7 DCE NC RS232 PIN 7 NC 8 VCC C3 C1 + 1.0µF 1.0µF C5 1µF 28 2 4 CHARGE PUMP + 27 26 5 DTE_SCTE/ DCE_RXC 6 D1 D2 7 DTE_TXC/ DCE_TXC 8 DTE_RXC/ DCE_SCTE 9 DTE_RXD/ DCE_TXD 10 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 + C2 1.0µF 21 1 VCC DB-25 CONNECTOR C4 + 3.3µF 25 DTE_TXD/ DCE_RXD 13 LATCH 14 2 + 12 LTC1344A 5.0V VCC 3 1 11 M1 MO MODE 3 C8 100pF M2 PIN 18 PIN 21 C7 100pF DCE/DTE MODE C6 100pF VEE CABLE WIRING FOR MODE SELECTION 24 2 23 14 22 24 21 11 20 15 19 12 18 17 17 9 16 3 15 16 DTE TXD A DCE RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B D3 R1 R2 R3 11 M0 12 M1 13 M2 NC 14 DCE/DTE 7 1 SG SHIELD LTC1543 25 VCC 1 VCC 2 V DD DTE_RTS/ DCE_CTS 3 DTE_DTR/ DCE_DSR 4 D1 D2 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 DTE_CTS/ DCE_RTS 8 21 18 26 4 25 19 24 20 23 23 DCE/DTE M1 M0 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B D3 R1 R2 R3 10 R4 9 11 12 13 14 VEE GND 28 27 22 8 21 10 20 6 19 22 18 5 17 13 16 D4 M0 15 M1 INVERT NC M2 DCE/DTE LTC1544 1544_04.eps Figure 4. Cable-selectable multiprotocol DTE/DCE port Linear Technology Magazine • February 1998 21 DESIGN FEATURES C6 100pF 3 C8 100pF 11 C7 100pF 8 12 13 LTC1344A 14 2 + C3 + C1 1.0µF 1.0µF C5 1µF 1 2 4 3 + DTE_LL/ DCE_TM 5 DTE_TXD/ DCE_RXD 6 DTE_SCTE/ DCE_RXC 7 44 9 10 12 13 DTE_TXC/ DCE_TXC DTE_RXC/ DCE_SCTE 14 DTE_RXD/ DCE_TXD 15 DTE_TM/ DCE_LL 16 R1 100k LB VCC D3 4 5 DTE_DCD/ DCE_DCD 6 DTE_DSR/ DCE_DTR 7 8 10 9 10 16 15 18 17 19 20 22 23 24 MO 1 DB-25 CONNECTOR DTE 18 2 37 14 36 24 35 11 DCE LL A TM A TXD A RXD A TXD B RXD B SCTE A RXC A SCTE B RXC B TXC A TXC A TXC B TXC B RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B TM A LL A 34 D4 33 32 15 31 12 30 17 29 28 9 3 27 16 26 25 21 DCE 19 M2 M1 18 M0 17 7 R1 R2 R3 1 VCC 2 V DD DTE_DTR/ DCE_DSR 7 38 40 GND EC 24 23 LB LTC1343 3 DTE_RL/ DCE_RL D2 R4 20 CTRL 22 LATCH 11 25 INVERT 423SET DTE_RTS/ DCE_CTS DTE_CTS/ DCE_RTS 39 8 6 C4 + 3.3µF 41 D1 4 21 + C2 1.0µF 43 42 CHARGE PUMP 5 M2 M1 VEE VCC 5.0V VCC DCE/DTE LATCH VEE GND D1 D2 SG VCC 1 SHIELD 28 27 26 4 25 19 24 20 23 23 RTS A CTS A RTS B CTS B DTR A DSR A DTR B DSR B DCD A DCD A DCD B DCD B DSR A DTR A DSR B DTR B CTS A RTS A CTS B RTS B RL A RL A D3 R1 R2 R3 R4 22 8 21 10 20 6 19 22 18 5 17 13 16 21 9 D4 11 M0 15 12 M1 INVERT NC 13 M2 14 DCE/DTE LTC1544 DCE/DTE M2 M1 M0 1544_05.eps Figure 5. Controller-selectable multiprotocol DTE/DCE port with RLL, LL, TM and DB-25 connector 22 Linear Technology Magazine • February 1998 CONTINUATIONS Tracking the growing popularity of portable communication systems, the LTC1623 makes a very handy singleslot 3.3V/5V PC Card switch matrix. As shown in Figure 3, this circuit enables a system controller to switch either a 3.3V or a 5V supply to any of its SMBus-addressed peripherals. Besides N-channel switches, the LTC1623 can also be used to control a P-channel switch, as shown in Figure 4. As a result, the load connected to the P-channel switch will be turned on upon power-up of the LTC1623, whereas the other load must wait for a valid address and command to be powered. VCC 2.7V TO 5.5V 10µF VCC DATA Adding Optional Test Signal In some cases, the optional test signals local loopback (LL), remote loopback (RL) and test mode (TM) are required but there are not enough drivers and receivers available in the Q1 Si3442DV 0.1µF 1k LTC1623 GB (PROGRAMMABLE) 0.1µF AD0 Q2 Si6433DQ AD1 GND DISPLAY FAN 1623 F02 Figure 4. LTC1623 controlling a P-channel switch (Q2) Conclusion With a standby current of only 17µA and a tiny 8-lead MSOP (or SO) footprint, the LTC1623 offers a simple and efficient solution for managing system peripherals using the SMBus architecture. Conclusion LTC1543, continued from page 17 The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable. The internal pull-up current sources ensure a binary 1 when a pin is left unconnected and also ensure that the LTC1543/LTC1544/LTC1344A enter the no-cable mode when the cable is removed. In the no-cable mode, the LTC1543/LTC1544 power supply current drops to less than 200µ A and all of the LTC1543/ LTC1544 driver outputs will be forced into the high impedance state. 1k GA CLK (FROM SMBus) LTC1543/LTC1544 to handle these extra signals. The solution is to combine the LTC1544 with the LTC1343. By using the LTC1343 to handle the clock and data signals, the chip set gains one extra single-ended driver/ receiver pair. This configuration is shown in Figure 5. In the world of network equipment, the product differentiation is mostly in the software and not in the serial interface. The LTC1543, LTC1544 and LTC1344A provide a simple yet comprehensive solution to standards compliance for multiple-protocol serial interface. Compliance Testing A European standard EN 45001 test report is available for the LTC1543/ LTC1544/LTC1344A chip set. The report provides documentation on the compliance of the chip set to Layer 1 of the NET1 and NET2 standard. A copy of this test report is available from LTC or from Detecon, Inc. at 1175 Old Highway 8, St. Paul, MN 55112. Authors can be contacted at (408) 432-1900 LTC1562 continued from page 5 Quadruple 3rd Order 100kHz Butterworth Lowpass Filter Another example of the flexibility of the virtual-ground inputs is the ability to add an extra, independent real pole by replacing the input resistor in Figure 2 with an R-C-R “T” network. In Figure 10, a 10k input resistor has been split into two parts and the parallel combination of the two forms a 100kHz real pole with the 680pF 32 Conclusion external capacitor. Four such 3rd order Butterworth lowpass filters can be built from one LTC1562. The same technique can add additional real poles to other filter configurations as well, for example, augmenting Figure 4’s circuit to obtain a dual 5th order filter from a single LTC1562. The LTC1562 is the first truly compact universal active filter, yet it offers instrumentation-grade performance rivaling much larger discrete-component designs. It serves applications in the 10kHz–150kHz range with an SNR as high as 100dB or more (16+ equivalent bits). The LTC1562 is ideal for modems and other communications systems and for DSP antialiasing or reconstruction filtering. Linear Technology Magazine • February 1998