Data Sheet

MMA2301KEG
Rev 1, 11/2012
Freescale Semiconductor
Data Sheet: Technical Data
Surface Mount
Micromachined Accelerometer
MMA2301KEG
The MMA series of silicon capacitive, micromachined accelerometers feature
signal conditioning, a 4-pole low pass filter and temperature compensation.
Zero-g offset full scale span and filter cut-off are factory set and require no
external devices. A full system self-test capability verifies system functionality.
Features
•
•
•
•
•
•
•
•
•
•
Integral Signal Conditioning
Linear Output
Ratiometric Performance
4th Order Bessel Filter Preserves Pulse Shape Integrity
Calibrated Self-test
Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status
Transducer Hermetically Sealed at Wafer Level for Superior Reliability
Robust Design, High Shocks Survivability
Robust Design, High Shock Survivability
Qualified AEC-Q100, Rev. F Grade 2 (-40C/ +105C)
MMA2301KEG: X-AXIS SENSITIVITY
MICROMACHINED
ACCELEROMETER
±200g
Typical Applications
•
•
KEG SUFFIX (Pb-FREE)
16-LEAD SOIC
CASE 475-01
Vibration Monitoring and Recording
Impact Monitoring
ORDERING INFORMATION
Device Name
Temperature Range
Case No.
Package
MMA2301EG
–40to 125C
475-01
SOIC-16
MMA2301EGR2
–40to 125C
475-01
SOIC-16, Tape & Reel
MMA2301KEG*
–40to 125C
475-01
SOIC-16
MMA2301KEGR2*
–40to 125C
475-01
SOIC-16, Tape & Reel
*Part number sourced from a different facility.
VDD
G-Cell
Sensor
ST
Self-Test
Integrator
Gain
Control Logic and
EPROM Trim Circuits
Filter
Oscillator
Temp
Clock
Generator
VOUT
VSS
N/C
N/C
N/C
ST
VOUT
STATUS
VSS
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
STATUS
Figure 1. Simplified Accelerometer Functional Block Diagram
© 2009, 2012 Freescale Semiconductor, Inc. All rights reserved.
Figure 2. Pin Connections
Table 1. Maximum Ratings
(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.)
Rating
Symbol
Value
Unit
Powered Acceleration (all axes)
Gpd
1500
g
Unpowered Acceleration (all axes)
Gupd
2000
g
Supply Voltage
VDD
–0.3 to +7.0
V
Ddrop
1.2
m
Tstg
–40 to +125
°C
Drop Test
(1)
Storage Temperature Range
1. Dropped onto concrete surface from any axis.
ELECTRO STATIC DISCHARGE (ESD)
WARNING: This device is sensitive to electrostatic
discharge.
Although the accelerometers contain internal 2 kV ESD
protection circuitry, extra precaution must be taken by the
user to protect the chip from ESD. A charge of over 2000 volts
can accumulate on the human body or associated test
equipment. A charge of this magnitude can alter the
performance or cause failure of the chip. When handling the
accelerometer, proper ESD precautions should be followed
to avoid exposing the device to discharges which may be
detrimental to its performance.
MMA2301KEG
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Table 2. Operating Characteristics
(Unless otherwise noted: -40C  TA  +105C, 4.75  VDD  5.25, Acceleration = 0g, Loaded output)(1)
Characteristic
Symbol
Min
Typ
Max
Unit
VDD
IDD
TA
gFS
4.75
3.0
-40
—
5.0
—
—
225
5.25
6.0
+125
—
V
mA
C
g
VOFF
VOFF,V
S
SV
f -3dB
NLOUT
2.4
0.46 VDD
9.5
1.86
360
-1.0
2.5
0.50 VDD
10.0
2.0
400
—
2.6
0.54 VDD
10.5
2.14
440
1.0
V
V
mV/g
mV/g/V
Hz
% FSO
nRMS
nPSD
nCLK
—
—
—
—
110
2.0
2.8
—
—
mVrms
V/(Hz1/2)
mVpk
Self-Test
Output Response(7)
Input Low
Input High
Input Loading(8)
Response Time(9)
gST
VIL
VIH
IIN
tST
24
VSS
0.7 x VDD
-30
—
30
—
—
-100
2.0
36
0.3 x VDD
VDD
-260
10
g
V
V
A
ms
Status(10) (11)
Output Low (Iload = 100 A)
Output High (Iload = 100 A)
VOL
VOH
—
VDD -0.8
—
—
0.4
—
V
V
Minimum Supply Voltage (LVD Trip)
VLVD
2.7
3.25
4.0
V
fmin
50
—
260
kHz
Output Stage Performance
Electrical Saturation Recovery Time(12)
Full Scale Output Range (IOUT = 200 A)
Capacitive Load Drive(13)
Output Impedance
tDELAY
VFSO
CL
ZO
—
0.25
—
—
0.2
—
—
300
—
VDD -0.25
100
—
ms
V
pF

Mechanical Characteristics
Transverse Sensitivity(14)
Package Resonance
VXZ,YZ
fPKG
—
—
—
10
5.0
—
% FSO
kHz
Operating Range(2)
Supply Voltage(3)
Supply Current
Operating Temperature Range
Acceleration Range
Output Signal
Zero g (TA = 25C, VDD = 5.0 V)(4)
Zero g
Sensitivity (TA = 25C, VDD = 5.0 V)(5)
Sensitivity
Bandwidth Response
Nonlinearity
Noise
RMS (.01-1 kHz)
Power Spectral Density
Clock Noise (without RC load on output)(6)
Clock Monitor Fail Detection Frequency
1. For a loaded output the measurements are observed after an RC filter consisting of a 1 k resistor and a 0.01 F capacitor to ground.
2. These limits define the range of operation for which the part will meet specification.
3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits
the device may operate as a linear device but is not guaranteed to be in calibration.
4. The device can measure both + and - acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output
will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2.
5. The device is calibrated at 35g.
6. At clock frequency 70 kHz.
7. VOFF calculated with typical sensitivity.
8. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages.
9. Time for the output to reach 90% of its final value after a self-test is initiated.
10. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is
high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application.
11. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The
Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 us, unless a fault condition continues to exist.
12. Time for amplifiers to recover after an acceleration signal causing them to saturate.
13. Preserves phase margin (60) to guarantee output amplifier stability.
14. A measure of the device's ability to reject an acceleration applied 90 from the true axis of sensitivity.
MMA2301KEG
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Freescale Semiconductor, Inc.
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PRINCIPLE OF OPERATION
The Freescale accelerometer is a surface-micromachined
integrated-circuit accelerometer.
The device consists of a surface micromachined
capacitive sensing cell (g-cell) and a CMOS signal
conditioning ASIC contained in a single integrated circuit
package. The sensing element is sealed hermetically at the
wafer level using a bulk micromachined “cap'' wafer.
The g-cell is a mechanical structure formed from
semiconductor materials (polysilicon) using semiconductor
processes (masking and etching). It can be modeled as two
stationary plates with a moveable plate in-between. The
center plate can be deflected from its rest position by
subjecting the system to an acceleration (Figure 3).
When the center plate deflects, the distance from it to one
fixed plate will increase by the same amount that the distance
to the other plate decreases. The change in distance is a
measure of acceleration.
The g-cell plates form two back-to-back capacitors
(Figure 4). As the center plate moves with acceleration, the
distance between the plates changes and each capacitor's
value will change, (C = A/D). Where A is the area of the
plate,  is the dielectric constant, and D is the distance
between the plates.
The CMOS ASIC uses switched capacitor techniques to
measure the g-cell capacitors and extract the acceleration
data from the difference between the two capacitors. The
ASIC also signal conditions and filters (switched capacitor)
the signal, providing a high level output voltage that is
ratiometric and proportional to acceleration.
Acceleration
Figure 3. Transducer Physical Model and
Equivalent Circuit Model
SPECIAL FEATURES
Filtering
The Freescale accelerometers contain an onboard 2-pole
switched capacitor filter. A Bessel implementation is used
because it provides a maximally flat delay response (linear
phase) thus preserving pulse shape integrity. Because the
filter is realized using switched capacitor techniques, there is
no requirement for external passive components (resistors
and capacitors) to set the cut-off frequency.
Self-Test
The sensor provides a self-test feature that allows the
verification of the mechanical and electrical integrity of the
accelerometer at any time before or after installation. This
feature is critical in applications such as automotive airbag
systems where system integrity must be ensured over the life
of the vehicle. A fourth “plate'' is used in the g-cell as a selftest plate. When the user applies a logic high input to the selftest pin, a calibrated potential is applied across the self-test
plate and the moveable plate. The resulting electrostatic
2

1 V 
force  Fe = --- A ------ causes the center plate to deflect.
2 d2 

The resultant deflection is measured by the accelerometer's
control ASIC and a proportional output voltage results. This
procedure assures that both the mechanical (g-cell) and
electronic sections of the accelerometer are functioning.
Status
Freescale accelerometers include fault detection circuitry
and a fault latch. The Status pin is an output from the fault
latch, OR'd with self-test, and is set high whenever the
following event occurs:
• Parity of the EPROM bits becomes odd in number.
The fault latch can be reset by a rising edge on the self-test
input pin, unless one (or more) of the fault conditions
continues to exist.
MMA2301KEG
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BASIC CONNECTIONS
PINOUT DESCRIPTION
2
3
4
5
ST
VOUT
STATUS
VSS
VDD
6
7
12
11
10
8
9
PCB Layout
N/C
16
15
14
13
N/C
N/C
N/C
N/C
N/C
STATUS
P1
ST
P0
N/C
VOUT
R
VSS
1 k
N/C
VDD
C
A/D In
C 0.01 F
0.1 F
Microcontroller
1
N/C
N/C
Accelerometer
N/C
VSS
C 0.1 F
VDD
VRH
C
0.1 F
Table 3. Pin Descriptions
Power Supply
Pin No.
Pin Name
1 thru 3
N/C
Leave unconnected.
4
ST
Logic input pin used to initiate selftest.
5
VOUT
6
STATUS
7
VSS
The power supply ground.
8
VDD
The power supply input.
9 thru 13
Trim pins
14 thru 16
—
VDD
Logic
Input
C1
0.1 F
Description
Output voltage of the accelerometer.
Logic output pin to indicate fault.
Used for factory trim. Leave
unconnected.
No internal connection. Leave
unconnected.
MMA2301KEG
4 ST
8 VDD
7 VSS
6
VOUT 5
Status
R1
1 k
Output
Signal
C2
0.01 F
Figure 5. Recommend PCB Layout for Interfacing
Accelerometer to Microcontroller
NOTES:
• Use a 0.1 F capacitor on VDD to decouple the power
source.
• Physical coupling distance of the accelerometer to the
microcontroller should be minimal.
• Place a ground plane beneath the accelerometer to
reduce noise, the ground plane should be attached to all
of the open ended terminals shown in Figure 5
• Use an RC filter of 1 k and 0.01 F on the output of the
accelerometer to minimize clock noise (from the switched
capacitor filter circuit).
• PCB layout of power and ground should not couple power
supply noise.
• Accelerometer and microcontroller should not be a high
current path.
A/D sampling rate and any external power supply
switching frequency should be selected such that they do not
interfere with the internal accelerometer sampling frequency.
This will prevent aliasing errors.
Figure 4. SOIC Accelerometer with Recommended
Connection Diagram
MMA2301KEG
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Dynamic Acceleration Sensing Direction
Acceleration of the package
in the +X direction (center
plate moves in the -X
direction) will result in an
increase in the output.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
x
x
Activation of Self Test
moves the center plate in
the X direction, resulting in
an increase in the output.
16-Pin SOIC Package
N/C pins are recommended to be left FLOATING
Top View
Static Acceleration Sensing Direction
8 7
6 5
4 3
2 1
Direction of Earth's gravity field.*
9 10 11 12 13 14 15 16
Front View
Side View
* When positioned as shown, the Earth's gravity will result in a positive 1g output.
MMA2301KEG
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MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the surface mount packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct
0.380 in.
9.65 mm
footprint, the packages will self-align when subjected to a
solder reflow process. It is always recommended to design
boards with a solder mask layer to avoid bridging and
shorting between solder pads.
0.050 in.
1.27 mm
0.024 in.
0.610 mm
0.080 in.
2.03 mm
Figure 6. Footprint SOIC-16 (Case 475-01)
MMA2301KEG
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PACKAGE DIMENSIONS
PAGE 1 OF 2
CASE 475-01
ISSUE C
16-LEAD SOIC
MMA2301KEG
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PACKAGE DIMENSIONS
PAGE 2 OF 2
CASE 475-01
ISSUE C
16-LEAD SOIC
MMA2301KEG
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Freescale Semiconductor, Inc.
9
Table 4. Revision History
Revision
number
Revision
date
1
11/2012
Description of changes
• Table 2. Operating Characteristics, added footnote for Self-Test Output Response, updated page
4: Principle of Operation
MMA2301KEG
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MMA2301KEG
Rev. 1
11/2012