Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MMA8653FC
Rev. 2.2, 03/2015
An Energy-Efficient Solution by Freescale
MMA8653FC 3-Axis, 10-bit Digital
MMA8653FC
Accelerometer
The MMA8653FC is an intelligent, low-power, three-axis, capacitive micromachined
accelerometer with 10 bits of resolution. This accelerometer is packed with
embedded functions with flexible user-programmable options, configurable to two
interrupt pins. Embedded interrupt functions enable overall power savings, by
relieving the host processor from continuously polling data. There is access to
either low-pass or high-pass filtered data, which minimizes the data analysis
required for jolt detection and faster transitions. The device can be configured to
generate inertial wake-up interrupt signals from any combination of the
configurable embedded functions, enabling the MMA8653FC to monitor inertial
events while remaining in a low-power mode during periods of inactivity. The
MMA8653FC is available in a small 10-pin DFN package (2 mm x 2 mm x 1 mm).
Top and Bottom View
Features
•
•
•
•
•
•
•
•
•
•
1.95 V to 3.6 V supply voltage
1.62 V to 3.6 V digital interface voltage
±2 g, ±4 g, and ±8 g dynamically selectable full-scale ranges
Output Data Rates (ODR) from 1.56 Hz to 800 Hz
10-bit digital output
I2C digital output interface with programmable interrupts
One embedded channel of configurable motion detection (Freefall)
Orientation (Portrait/Landscape) detection with fixed hysteresis of 15°.
Configurable automatic ODR change triggered by the Auto-Wake/Sleep
state change
Self-Test
Typical applications
•
•
•
•
•
•
•
•
10-pin DFN
2 mm x 2 mm x 1 mm
Case 98ASA00301D
Top View
10 SDA
VDD
1
SCL
2
9
GND
INT1
3
8
VDDIO
BYP
4
7
GND
INT2
5
6
GND
Tilt compensation in e-compass applications
Pin Connections
Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/
Front position identification)
Notebook, tablet, e-reader, and laptop tumble and freefall detection
Real-time orientation detection (virtual reality and gaming 3D user orientation
feedback)
Real-time activity analysis (pedometer step counting, freefall drop detection for HDD, dead-reckoning GPS backup)
Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)
Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)
User interface (tilt menu scrolling)
ORDERING INFORMATION
Part Number
Temperature Range
Package Description
Shipping
MMA8653FCR1
-40°C to +85°C
DFN-10
Tape and Reel
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© 2013–2015 Freescale Semiconductor, Inc. All rights reserved.
Table 1. Feature comparison of the MMA865xFC devices
Feature
ADC Resolution (bits)
MMA8652FC
MMA8653FC
12
10
Digital Sensitivity in 2 g mode (counts/g)
1024
256
Low-Power Mode
Yes
Yes
Auto-WAKE
Yes
Yes
Auto-SLEEP
Yes
Yes
32-Level FIFO
Yes
No
Low-Pass Filter
Yes
Yes
High-Pass Filter
Yes
No
Transient Detection with High-Pass Filter
Yes
No
Fixed Orientation Detection
No
Yes
Programmable Orientation Detection
Yes
No
Data-Ready Interrupt
Yes
Yes
Single-Tap Interrupt
Yes
No
Double-Tap Interrupt
Yes
No
Directional Tap Interrupt
Yes
No
Freefall Interrupt
Yes
Yes
Motion Interrupt with Direction
Yes
No
MMA8653FC
2
Sensors
Freescale Semiconductor, Inc.
Contents
1
Block Diagram and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 I2C interface characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Zero-g offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Device calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 8-bit or 10-bit data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Low power modes vs. high resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Auto-WAKE/SLEEP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 Freefall detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.6 Orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.7 Interrupt register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8 Serial I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 System status and ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Data configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.6 Portrait/Landscape configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Freefall/Motion configuration and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.8 Auto-WAKE/SLEEP detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.9 System and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.10 Data calibration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Mounting Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Overview of soldering considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 Halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3 PCB mounting/soldering recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1 Tape dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 Device orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Related Documentation
The MMA8653FC device features and operations are described in a variety of reference manuals, user guides, and application
notes. To find the most-current versions of these documents:
1.
Go to the Freescale homepage at:
http://www.freescale.com/
2.
3.
In the Keyword search box at the top of the page, enter the device number MMA8653FC.
In the Refine Your Result pane on the left, click on the Documentation link.
Sensors
Freescale Semiconductor, Inc.
MMA8653FC
3
MMA8653FC
4
Sensors
Freescale Semiconductor, Inc.
1
Block Diagram and Pin Descriptions
1.1
Block diagram
BYP
VDD
VDDIO
Voltage
Regulator
Clock
GEN
Internal
OSC
INT1
INT2
GND
Y-axis
Transducer
MUX
X-axis
Transducer
C-to-V
Converter
Gain
AAF
Embedded
Functions
ADC
I2 C
Interface
SDA
SCL
Anti-Aliasing
Filter
Z-axis
Transducer
Orientation Detection
with hysteresis and
Z-lockout
Freefall
Detection
Auto-WAKE/Auto-SLEEP configurable with debounce counter and multiple motion interrupts for control
MODE Options
Low Power
Low Noise + Power
High Resolution
Normal
ACTIVE Mode
WAKE
ACTIVE Mode
Auto-WAKE/SLEEP
SLEEP
MODE Options
Low Power
Low Noise + Power
High Resolution
Normal
Figure 1. MMA8653 block diagram
MMA8653FC
Sensors
Freescale Semiconductor, Inc.
5
1.2
Pin descriptions
SDA 10
1
VDD
GND
SCL
VDDIO
INT1
GND
BYP
GND 6
5
INT2
Figure 2. Pin connections (bottom view)
Table 1. Pin descriptions
Pin #
Pin Name
1
VDD
2
Description
Notes
Power supply
Device power is supplied through the VDD line. Power supply decoupling capacitors
should be placed as close as possible to pin 1 and pin 8 of the device.
SCL(1)
I2C Serial Clock
7-bit I2C device address is 0x1D.
3
INT1
Interrupt 1 output
The interrupt source and pin settings are user-programmable through the I2C interface.
4
BYP
Internal regulator output
capacitor connection
5
INT2
Interrupt 2 output
6
GND
Ground
7
GND
Ground
8
VDDIO
9
GND
10
SDA(1)
See INT1.
Digital Interface Power supply
Ground
I2C Serial Data
See SCL.
1. The control signals SCL and SDA are not tolerant of voltages higher than VDDIO + 0.3 V. If VDDIO is removed, then the control signals SCL
and SDA will clamp any logic signals with their internal ESD protection diodes. The SDA and SCL I2C connections are open drain, and
therefore require a pullup resistor to VDDIO.
1.3
Typical application circuit
Top View
VDD
1 F
0.1 F
VDDIO
1 k
1
10
2
9
3
8
4
7
5
6
SDA
VDDIO
1 k
SCL
BYP
INT1
VDDIO
0.1 F
0.1 F
INT2
Note: 4.7 k Pullup resistors on INT1/INT2 can be added for open-drain operation.
Figure 3. Typical application circuit
MMA8653FC
6
Sensors
Freescale Semiconductor, Inc.
2
Mechanical and Electrical Specifications
2.1
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum
rating conditions for extended periods may affect device reliability.
Table 2. Maximum ratings
Rating
Symbol
Value
Unit
Maximum acceleration (all axes, 100 s)
gmax
10,000
g
Supply voltage
VDD
–0.3 to +3.6
V
Vin
–0.3 to VDDIO + 0.3
V
Ddrop
1.8
m
Input voltage on any control pin (SCL, SDA)
Drop test
Operating temperature range
TOP
–40 to +85
°C
Storage temperature range
TSTG
–40 to +125
°C
Symbol
Value
Unit
HBM
±2000
V
Table 3. ESD and latch-up protection characteristics
Rating
Human body model
Machine model
Charge device model
Latch-up current at T = 85°C
MM
±200
V
CDM
±500
V
ILU
±100
mA
This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part.
This part is ESD-sensitive. Improper handling can cause permanent damage to the part.
MMA8653FC
Sensors
Freescale Semiconductor, Inc.
7
2.2
Mechanical characteristics
Table 4. Mechanical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, TA = 25°C, unless otherwise noted
Parameter
Full-Scale measurement range
Sensitivity
Symbol
FS
So
Test Conditions
Min
Typ
Max
Unit
FS[1:0] set to 00
±2 g mode
±2
FS[1:0] set to 01
±4 g mode
±4
FS[1:0] set to 10
±8 g mode
±8
FS[1:0] set to 00
±2 g mode
256
FS[1:0] set to 01
±4 g mode
128
FS[1:0] set to 10
±8 g mode
64
±2.5
%
–40°C to 85°C
0.0074
%/°C
g
LSB/g
Sensitivity accuracy
Soa
Sensitivity change vs. temperature
TCS
Zero-g level offset accuracy (1)
TyOff
25
mg
TyOffPBM
33.5
mg
–40°C to 85°C
0.27
mg/°C
x
+22.5
y
+26
z
+195.5
Zero-g level offset accuracy,
post-board mount (2)
Zero-g level change vs. temperature
TCO
Self-Test output change (±2 g mode)
STOC
ODR accuracy
ODRa
Output data bandwidth
Output noise
Operating temperature range
3.1
BW
RMS
LSB
ODR/3
Normal mode ODR = 400 Hz
TAGOC
%
ODR/2
182
–40
Hz
µg/Hz
85
°C
1. Before board mount.
2. Post-board mount offset specifications are based on an 8-layer PCB, relative to 25°C.
MMA8653FC
8
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Freescale Semiconductor, Inc.
2.3
Electrical characteristics
Table 5. Electrical characteristics at VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C, unless otherwise noted
Parameter
Supply voltage
Interface supply voltage
Low Power mode
Normal mode
Boot-Up current
Value of capacitor on BYP pin
Symbol
Test Conditions
VDD
VDDIO
IddLP
Idd
Min
Typ
Max
Unit
1.95
2.5
3.6
V
1.62
1.8
3.6
V
ODR = 1.563 Hz
6.5
ODR = 6.25 Hz
6.5
ODR = 12.5 Hz
6.5
ODR = 50 Hz
15
ODR = 100 Hz
26
ODR = 200 Hz
49
ODR = 400 Hz
94
ODR = 800 Hz
184
ODR = 1.563 Hz
27
ODR = 6.25 Hz
27
ODR = 12.5 Hz
27
ODR = 50 Hz
27
ODR = 100 Hz
49
ODR = 200 Hz
94
ODR = 400 Hz
184
ODR = 800 Hz
184
IddBoot
VDD = 2.5 V, the current during
the Boot sequence is integrated
over 0.5 ms, using a
recommended bypass cap
A
A
1
Cap
–40°C to 85°C
IddStby
25°C
Digital high-level input voltage
SCL, SDA
VIH
VDD = 3.6 V, VDDIO = 3.6 V
Digital low-level input voltage
SCL, SDA
VIL
VDD = 1.95 V, VDDIO = 1.62 V
High-level output voltage
INT1, INT2
VOH
VDD = 3.6 V, VDDIO = 3.6 V,
IO = 500 A
Low-level output voltage
INT1, INT2
VOL
VDD = 1.95 V, VDDIO = 1.62 V,
IO = 500 A
0.1*VDDIO
Low-level output voltage
SDA
VOLS
IO = 3 mA
0.4
Output source current INT1, INT2
Isource
Voltage high level
VOUT = 0.9 x VDDIO
2
mA
Output sink current INT1, INT2
Isink
Voltage high level
VOUT = 0.9 x VDDIO
3
mA
Power-on ramp time
Tpr
Standby current
75
mA
100
470
nF
1.4
5
A
V
0.7*VDDIO
0.3*VDDIO
0.9*VDDIO
V
V
0.001
V
V
1000
ms
500
µs
Tbt
Time from VDDIO on and
VDD > VDD min until I2C is
ready for operation,
Cbyp = 100 nf
Turn-on time
Ton1
Time to obtain valid data from
Standby mode to Active mode
2/ODR + 1 ms
-
Turn-on time
Ton2
Time to obtain valid data from
valid voltage applied
2/ODR + 2 ms
-
85
°C
Boot time
Operating temperature range
TAGOC
350
–40
MMA8653FC
Sensors
Freescale Semiconductor, Inc.
9
2.4
I2C interface characteristic
Table 6. I2C slave timing values (1)
Parameter
Symbol
I2C Fast Mode
Min
Max
400
Unit
SCL clock frequency
fSCL
0
Bus-free time between STOP and START condition
tBUF
1.3
s
(Repeated) START hold time
tHD;STA
0.6
s
Repeated START setup time
tSU;STA
0.6
s
STOP condition setup time
tSU;STO
0.6
kHz
s
s
SDA data hold time
tHD;DAT
0.05
SDA setup time
tSU;DAT
100
ns
SCL clock low time
tLOW
1.3
s
SCL clock high time
tHIGH
0.6
SDA and SCL rise time
tr
SDA and SCL fall time
SDA valid time
tf
(4)
SDA valid acknowledge time
tSP
Capacitive load for each bus line
Cb
1.
2.
3.
4.
5.
20 + 0.1 Cb
300
ns
20 + 0.1 Cb
(3)
300
ns
tVD;ACK
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
s
(3)
tVD;DAT
(5)
0.9
(2)
0
0.9
(2)
s
0.9
(2)
s
50
ns
400
pF
All values referred to VIH(min) (0.3 VDD) and VIL(max) (0.7 VDD) levels.
This device does not stretch the LOW period (tLOW) of the SCL signal.
Cb = total capacitance of one bus line in pF.
tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
VIL = 0.3 VDD
VIH = 0.7 VDD
Figure 4. I2C slave timing diagram
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Terminology
3.1
Sensitivity
The sensitivity is represented in counts/g.
•
In ±2 g mode, sensitivity = 256 counts/g.
•
In ±4 g mode, sensitivity = 128 counts/g.
•
In ±8 g mode, sensitivity = 64 counts/g.
3.2
Zero-g offset
Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A
sensor stationary on a horizontal surface will measure 0 g in X-axis and 0 g in Y-axis, whereas the Z-axis will measure 1 g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as a 2's
complement number). A deviation from ideal value in this case is called Zero-g offset.
Offset is to some extent a result of stress on the MEMS sensor, and therefore the offset can slightly change after mounting the
sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
3.3
Self-Test
Self-Test can be used to verify the transducer and signal chain functionality without the need to apply external mechanical
stimulus.
When Self-Test is activated:
•
An electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case, the sensor outputs will
exhibit a change in their DC levels which, are related to the selected full scale through the device sensitivity.
•
The device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by
the electrostatic test-force.
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4
Modes of Operation
ACTIVE
SLEEP
OFF
STANDBY
WAKE
Figure 5. Operating modes for MMA8653FC
Table 7. Operating modes
Mode
OFF
I2C Bus State
Powered down
VDD
VDDIO
Description
<1.8 V
VDDIO can be > VDD
• The device is powered off.
• All analog and digital blocks are shutdown.
• I2C bus inhibited.
STANDBY
I2C communication with
MMA8653FC is possible
ON
VDDIO = High
VDD = High
ACTIVE bit is cleared
• Only digital blocks are enabled.
• Analog subsystem is disabled.
• Internal clocks disabled.
ACTIVE
(WAKE/SLEEP)
I2C communication with
MMA8653FC is possible
ON
VDDIO = High
VDD = High
ACTIVE bit is set
All blocks are enabled (digital, analog).
Some registers are reset when transitioning from STANDBY to ACTIVE. These registers are all noted in the device memory map
register table.
The SLEEP and WAKE modes are ACTIVE modes. For more information about how to use the SLEEP and WAKE modes and
how to transition between these modes, see Section 5.
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5
Functionality
The MMA8653FC is a low-power, digital output 3-axis linear accelerometer with a I2C interface with embedded logic used to detect
events and notify an external microprocessor over interrupt lines.
•
8-bit or 10-bit data
•
Four different oversampling options that allow for the optimum resolution vs. current consumption trade-off to be made for a
given application
•
Low-power and auto-WAKE/SLEEP modes for reducing current consumption
•
Freefall detection (one channel)
•
Single default angle for portrait landscape detection algorithm, for addressing screen orientation
•
Two independent interrupt output pins that are programmable among four interrupt sources (Data Ready, Freefall,
Orientation, Auto-WAKE)
All functionality is available in ±2 g, ±4 g or ±8 g dynamic measurement ranges. There are many configuration settings for enabling
all of the different functions. Separate application notes are available to help configure the device for each embedded functionality.
5.1
Device calibration
The device is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non-Volatile Memory
(NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the
end application is not necessary. However, the MMA8653FC allows you to adjust the offset for each axis after power-up, by
changing the default offset values. The user offset adjustments are stored in three volatile 8-bit registers (OFF_X, OFF_Y,
OFF_Z).
5.2
8-bit or 10-bit data
The measured acceleration data is stored in the following registers as 2’s complement 10-bit numbers:
•
OUT_X_MSB, OUT_X_LSB
•
OUT_Y_MSB, OUT_Y_LSB
•
OUT_Z_MSB, OUT_Z_LSB
The most significant eight bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use
these three registers (and ignore the OUT_X/Y/Z_LSB registers). To use only 8-bit results, the F_READ bit in CTRL_REG1 must
be set. When the F_READ bit is cleared, the fast read mode is disabled.
•
When the full-scale is set to ±2 g, the measurement range is –2 g to +1.996 g, and each count corresponds to (1/256) g
(3.8 mg) at 10-bit resolution.
•
When the full-scale is set to ±4 g, the measurement range is –4 g to +3.992 g, and each count corresponds to (1/128) g
•
(7.8 mg) at 10-bit resolution.
•
When the full-scale is set to ±8 g, the measurement range is –8 g to +7.984 g, and each count corresponds to (1/64) g
(15.6 mg) at 10-bit resolution.
•
If only the 8-bit results are used, then the resolution is reduced by a factor of 16.
For more information about the data manipulation between data formats and modes, see application note AN4083, Data
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers. There is a device driver available that can be used
with the Sensor Toolbox demo board (LFSTBEB865xFC) with this application note.
Table 8. Accelerometer 10-bit output data
10-bit Data
Range ±2 g
(3.9 mg/LSB)
Range ±4 g
(7.8 mg/LSB)
Range ±8 g
(15.6 mg/LSB)
01 1111 1111
1.996 g
+3.992 g
+7.984 g
01 1111 1110
1.992 g
+3.984 g
+7.968 g
…
…
…
…
00 0000 0001
0.003 g
+0.007 g
+0.015 g
00 0000 0000
0.000 g
0.000 g
0.000 g
11 1111 1111
–0.003 g
–0.007 g
–0.015 g
…
…
…
…
10 0000 0001
–1.961 g
–3.992 g
–7.984 g
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Table 8. Accelerometer 10-bit output data (Continued)
10-bit Data
Range ±2 g
(3.9 mg/LSB)
Range ±4 g
(7.8 mg/LSB)
Range ±8 g
(15.6 mg/LSB)
10 0000 0000
–2.000 g
–4.000 g
–8.000 g
8-bit Data
Range ±2 g (15.6 mg)
Range ±4 g (31.25 mg)
Range ±8 g (62.5 mg)
0111 1111
1.984 g
+3.968 g
+7.937 g
0111 1110
1.968 g
+3.937 g
+7.875 g
…
…
…
…
0000 0001
+0.015 g
+0.031 g
+0.062 g
0000 0000
0.000 g
0.000 g
0.000 g
1111 1111
–0.015 g
–0.031 g
–0.062 g
…
…
…
…
1000 0001
–1.984 g
–3.968 g
–7.937 g
1000 0000
–2.000 g
–4.000 g
–8.000 g
Range ±4 g
(31.25 mg/LSB)
Range ±8 g
(62.5 mg/LSB)
Table 9. Accelerometer 8-bit output data
8-bit Data
5.3
Range ±2 g
(15.6 mg/LSB)
0111 1111
1.9844 g
+3.9688 g
+7.9375 g
0111 1110
1.9688 g
+3.9375 g
+7.8750 g
…
…
…
…
0000 0001
+0.0156 g
+0.0313 g
+0.0625 g
0000 0000
0.000 g
0.0000 g
0.0000 g
1111 1111
–0.0156 g
–0.0313 g
–0.0625 g
…
…
…
…
1000 0001
–1.9844 g
–3.9688 g
–7.9375 g
1000 0000
–2.0000 g
–4.0000 g
–8.0000 g
Low power modes vs. high resolution modes
The MMA8653FC can be optimized for lower power modes or for higher resolution of the output data. One of the oversampling
schemes of the data can be activated when MODS = 10 in Register 0x2B, which will improve the resolution of the output data
only. The highest resolution is achieved at 1.56 Hz.
There is a trade-off between low power and high resolution. Low power can be achieved when the oversampling rate is
reduced. When MODS = 11, the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz.
5.4
Auto-WAKE/SLEEP mode
The MMA8653FC can be configured to transition between sample rates (with their respective current consumption) based on
four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically
transition to a higher sample rate (higher current consumption) when needed, but spends the majority of the time in the SLEEP
mode (lower current) when the device does not require higher sampling rates.
•
Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This
may also interrupt the processor to transition from a SLEEP mode to a higher power mode.
•
SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user-definable timeout period.
The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode, to
save on current during this period of inactivity.
The Interrupts that can WAKE the device from SLEEP are Orientation detection and Freefall detection. The interrupts that can
keep the device from falling asleep are the same interrupts that can wake the device.
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5.5
Freefall detection
MMA8653FC has an interrupt architecture for detecting a Freefall.
•
Freefall can be enabled.
•
Freefall is detected when the acceleration magnitude is less than the configured threshold.
The freefall configuration does not use a high-pass filter.
The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is
below a user-specified threshold for a user-definable amount of time. Usable threshold levels are typically between ±100 mg and
±500 mg.
5.6
Orientation detection
The MMA8653FC incorporates an advanced orientation detection algorithm with the ability to detect all six orientations shown in
Figure 6. The algorithm uses a single default trip point setting. The transition from portrait to landscape is fixed at 45° midpoint
angle and ±15° hysteresis angle. This allows for smooth transitions from portrait to landscape at approximately 30° and
landscape to portrait at approximately 60° (Figure 7).
Top View
Side View
PORTRAIT UP
BACK
Pin 1
Earth Gravity
LANDSCAPE LEFT
Xout @ 0 g
Yout @ –1 g
Zout @ 0 g
Xout @ 0 g
Yout @ 0 g
Zout @ –1 g
LANDSCAPE RIGHT
FRONT
Xout @ 0 g
Yout @ 0 g
Zout @ 1 g
Xout @ –1 g
Yout @ 0 g
Zout @ 0 g
PORTRAIT DOWN
Xout @ 1 g
Yout @ 0 g
Zout @ 0 g
Z
Pin 1
X
Xout @ 0 g
Yout @ 1 g
Zout @ 0 g
Y
(Top View)
Direction of the
Detectable Accelerations
Figure 6. Sensitive axes orientation
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PORTRAIT
90°
PORTRAIT
90°
Landscape-to-Portrait
Trip Angle = 60°
Portrait-to-Landscape
Trip Angle = 30°
0° Landscape
0° Landscape
Figure 7. Landscape-to-Portrait transition trip angles
Based on the known functionality of linear accelerometers, when a device is oriented at a certain angle from flat and the device is
rotating at slow angular speeds about the Z-axis, it is not possible to detect changes in acceleration. The angle at which the device
no longer detects the orientation change is referred to as the “Z-lockout angle” (Figure 8).
The MMA8653FC orientation detection algorithm is configured to operate when the device is oriented at an angle of 29° or
greater from flat (Zout = –1 g or Zout = 1 g), with an accuracy of ±2°.
.
When lifting the device upright from the
flat position, orientation detection will be
active for orientation angles greater than
29° from flat. This is the only setting
available.
UPRIGHT
90°
NORMAL
DETECTION
REGION
Z-LOCK
LOCKOUT
REGION
0° FLAT
Figure 8. Z-Tilt angle lockout transition
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5.7
Interrupt register configurations
There are four configurable interrupts in the MMA8653FC: Data Ready, Motion/Freefall, Orientation, and Auto-SLEEP events.
Configurable interrupts
These four interrupt sources can be
routed to one of two interrupt pins.
The interrupt source must be enabled
and configured.
If the event flag is asserted because
the event condition is detected, then
the corresponding interrupt pin (INT1
or INT2) will assert.
Data Ready
Motion/Freefall
INT1
Interrupt
Controller
Orientation
INT2
Auto-SLEEP
7
INT ENABLE
7
INT CFG
Figure 9. System interrupt generation
•
The MMA8653FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus
simplifying data synchronization in the digital system that uses the device.
•
The MMA8653FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded
functions of the device for Motion, Freefall, and Orientation.
Serial I2C interface
5.8
Acceleration data may be accessed through an I2C interface, thus making the device particularly suitable for direct interfacing to
a microcontroller. The acceleration data and configuration registers embedded inside the MMA8653FC are accessed through the
I2C serial interface (Table 10).
•
To enable the I2C interface, VDDIO line must be tied high (to the interface supply voltage). If VDD is not present and VDDIO
is present, then the MMA8653FC is in OFF mode—and communications on the I2C interface are ignored.
•
The I2C interface may be used for communications between other I2C devices; the MMA8653FC does not affect the I2C bus.
Table 10. Serial Interface pins
Pin Name
Pin Description
2C
Serial Clock
SCL
I
SDA
I2C Serial Data
Notes
There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the
Serial Data line (SDA).
• SDA is a bidirectional line used for sending and receiving the data to/from the interface.
• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus
is free, both SCL and SDA lines are high.
The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 11).
I2C operation:
1.
2.
3.
The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a high-tolow transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is
considered busy.
The next byte of data transmitted after START contains the slave address in the first seven bits. The eighth bit tells
whether the Master is receiving data from the slave or is transmitting data to the slave.
After a start condition and when an address is sent, each device in the system compares the first seven bits with its
address. If the device’s address matches the sent address, then the device considers itself addressed by the Master.
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4.
5.
6.
The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The
transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it
remains stable low during the high period of the acknowledge clock period.
A Master may also issue a repeated START during a data transfer. The MMA8653FC expects repeated STARTs to be
used to randomly read from specific registers.
A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer
is always terminated by a STOP.
The MMA8653FC's standard slave address is 0011101 or 0x01D.
Table 11. I2C Device address sequence
5.8.1
1.
2.
3.
4.
5.
Master
Command
[6:0]
Device address
[6:0]
Device address
R/W
8-bit final
value
Read
0011101
0x1D
1
0x3B
Write
0011101
0x1D
0
0x3A
Single-byte read
The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send
the command, note that the data returned is sent with the MSB first after the data is received. Figure 10 shows the
timing diagram for the accelerometer 8-bit I2C read operation.
The Master (or MCU) transmits a start condition (ST) to the MMA8653FC [slave address (0x1D), with the R/W bit set to
“0” for a write], and the MMA8653FC sends an acknowledgement.
Next the Master (or MCU) transmits the address of the register to read, and the MMA8653FC sends an
acknowledgement.
The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8653FC (0x1D), with the
R/W bit set to “1” for a read from the previously selected register.
The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge
(NAK) the transmitted data, but transmits a stop condition to end the data transfer.
ST Device Address[7:1]
Register
Address[7:0]
W
AK
Slave
SR Device Address[7:1] R
AK
NAK SP
AK
Data[7:0]
Figure 10. Single-Byte Read timing (I2C)
NOTE
For the following subsections, use the following legend.
Legend
ST: Start Condition
SP: Stop Condition
NAK: No Acknowledge
SR: Repeated Start Condition
AK: Acknowledge
R: Read = 1
5.8.2
W: Write = 0
Multiple byte read
(See Table 11 for next auto-increment address.)
1.
2.
3.
4.
When performing a multi-byte read or “burst read”, the MMA8653FC automatically increments the received register
address commands after a read command is received.
After following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each
MMA8653FC acknowledgment (AK) is received,
Until a no acknowledge (NAK) occurs from the Master,
Followed by a stop condition (SP), which signals the end of transmission.
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Master
ST Device Address[7:1]
W
AK
Slave
AK
Master
Slave
Register Address[7:0]
Data[7:0]
SR Device Address[7:1] R
AK
AK
Data[7:0]
AK
AK
Data[7:0]
NAK SP
Data[7:0]
Figure 11. Multiple Byte Read timing (I2C)
5.8.3
1.
2.
3.
4.
Master
Single byte write
To start a write command, the Master transmits a start condition (ST) to the MMA8653FC, slave address ($1D) with the
R/W bit set to “0” for a write,
The MMA8653FC sends an acknowledgement.
Next the Master (MCU) transmits the address of the register to write to, and the MMA8653FC sends an
acknowledgement.
Then the Master (or MCU) transmits the 8-bit data to write to the designated register, and the MMA8653FC sends an
acknowledgement that it has received the data. Because this transmission is complete, the Master transmits a stop
condition (SP) to the data transfer. The data sent to the MMA8653FC is now stored in the appropriate register.
ST Device Address[7:1]
W
Register Address[7:0]
AK
Slave
Data[7:0]
AK
SP
AK
Figure 12. Single Byte Write timing (I2C)
5.8.4
Multiple byte write
(See Table 11 for next auto-increment address.)
1.
2.
Master
After a write command is received, the MMA8653FC automatically increments the received register address
commands.
Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers
after each MMA8653FC acknowledgment (ACK) is received.
ST Device Address[7:1]
Slave
W
Register Address[7:0]
AK
Data[7:0]
AK
Data[7:0]
AK
SP
AK
Figure 13. Multiple Byte Write timing (I2C)
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6
Register Descriptions
6.1
Register address map
Table 12. MMA8653FC register address map
Field
STATUS(1),(2)
(1)
OUT_X_MSB
(1)
OUT_X_LSB
(1)
Auto-Increment Address
Register
Address
F_READ = 0 F_READ = 1
R
0x00
0x01
R
0x01
0x02
0x03
Output
—
[7:0] are 8 MSBs of 10-bit sample.
R
0x02
0x03
0x00
Output
—
[7:6] are 2 LSBs of 10-bit real-time sample
Type
Default
00000000
Hex
Value
Comment
0x00 Real time status
OUT_Y_MSB
R
0x03
0x04
0x05
Output
—
[7:0] are 8 MSBs of 10-bit real-time sample
OUT_Y_LSB(1)
R
0x04
0x05
0x00
Output
—
[7:6] are 2 LSBs of 10-bit real-time sample
OUT_Z_MSB(1)
R
0x05
0x06
0x00
Output
—
[7:0] are 8 MSBs of 10-bit real-time sample
R
0x06
Output
—
[7:6] are 2 LSBs of 10-bit real-time sample
Reserved
R
0x07–0x0A
—
00000000
0x00 Reserved. Read return 0x00.
SYSMOD
R
0x0B
0x0C
00000000
0x00 Current System Mode
R
0x0C
0x0D
00000000
0x00 Interrupt status
R
0x0D
0x0E
01001010
0x5A Device ID (0x5A)
R/W
0x0E
0x0F
00000000
0x00 Dynamic Range Settings
R
0x0F
—
00000000
0x00 Reserved. Read return 0x00.
R
0x10
0x11
00000000
0x00 Landscape/Portrait orientation status
R/W
0x11
0x12
10000000
0x80 Landscape/Portrait configuration.
(1)
OUT_Z_LSB
(1),(2)
INT_SOURCE
(3)
WHO_AM_I
(3),(4)
XYZ_DATA_CFG
Reserved
(1),(2)
PL_STATUS
(3),(4)
PL_CFG
(3),(4)
0x00
R/W
0x12
0x13
00000000
0x00 Landscape/Portrait debounce counter
PL_BF_ZCOMP(3)
R
0x13
0x14
01000100
0x44 Back/Front, Z-Lock Trip threshold
PL_THS_REG(3)
R
0x14
0x15
10000100
0x84 Portrait to Landscape Trip angle
FF_MT_CFG(3),(4)
R/W
0x15
0x16
00000000
0x00
FF_MT_SRC(1),(2)
R
0x16
0x17
00000000
0x00 Freefall/Motion event source register
R/W
0x17
0x18
00000000
0x00 Freefall/Motion threshold register
R/W
0x18
0x19
00000000
0x00 Freefall/Motion debounce counter
R
0x19–0x28
—
00000000
0x00 Reserved. Read return 0x00.
PL_COUNT
(3),(4)
FF_MT_THS
(3),(4)
FF_MT_COUNT
Reserved
(3),(4)
Freefall/Motion functional block
configuration
R/W
0x29
0x2A
00000000
0x00 Counter setting for Auto-SLEEP/WAKE
(3),(4)
R/W
0x2A
0x2B
00000000
0x00 Data Rates, ACTIVE Mode.
(3),(4)
CTRL_REG2
R/W
0x2B
0x2C
00000000
0x00 Sleep Enable, OS Modes, RST, ST
CTRL_REG3(3),(4)
R/W
0x2C
0x2D
00000000
0x00 Wake from Sleep, IPOL, PP_OD
(3),(4)
R/W
0x2D
0x2E
00000000
0x00 Interrupt enable register
(3),(4)
0x2F
00000000
0x00 Interrupt pin (INT1/INT2) map
ASLP_COUNT
CTRL_REG1
CTRL_REG4
R/W
0x2E
(3),(4)
OFF_X
R/W
0x2F
0x30
00000000
0x00 X-axis offset adjust
OFF_Y(3),(4)
R/W
0x30
0x31
00000000
0x00 Y-axis offset adjust
OFF_Z(3),(4)
R/W
0x31
0x0D
00000000
0x00 Z-axis offset adjust
CTRL_REG5
1.
2.
3.
4.
The register data is only valid in ACTIVE mode.
Register contents are reset when transition from STANDBY to ACTIVE mode occurs.
Register contents are preserved when transition from ACTIVE to STANDBY mode occurs.
Modification of this register’s content can only occur when device is in STANDBY mode, except CTRL_REG1 ACTIVE bit and CTRL_REG2 RST bit.
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6.2
Register bit map
Table 13. MMA8653FC register bit map
Reg
Field
Definition
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
STATUS
Data Status
R
ZYXOW
ZOW
YOW
XOW
ZYXDR
ZDR
YDR
XDR
01
OUT_X_MSB
10-bit X Data
R
XD9
XD8
XD7
XD6
XD5
XD4
XD3
XD2
02
OUT_X_LSB
10-bit X Data
R
XD1
XD0
0
0
0
0
0
0
03
OUT_Y_MSB
10-bit Y Data
R
YD9
YD8
YD7
YD6
YD5
YD4
YD3
YD2
04
OUT_Y_LSB
10-bit Y Data
R
YD1
YD0
0
0
0
0
0
0
05
OUT_Z_MSB
10-bit Z Data
R
ZD9
ZD8
ZD7
ZD6
ZD5
ZD4
ZD3
ZD2
06
OUT_Z_LSB
10-bit Z Data
R
ZD1
ZD0
0
0
0
0
0
0
07–0A Reserved
—
R
0
0
0
0
0
0
0
0
0B
SYSMOD
System Mode
R
0
0
0
0
0
0
SYSMOD1
SYSMOD0
0C
INT_SOURCE
Interrupt Status
R
SRC_ASLP
0
0
SRC_LNDPRT
0
SRC_FF_MT
0
SRC_DRDY
0D
WHO_AM_I
ID Register
R
0
1
0
1
1
0
1
0
0E
XYZ_DATA_CFG
Data Config
R/W
0
0
0
0
0
0
FS1
FS0
0F
Reserved
—
R
—
—
—
—
—
—
—
—
10
PL_STATUS
Portrait Landscape Status
R
NEWLP
LO
0
0
0
LAPO[1]
LAPO[0]
BAFRO
11
PL_CFG
Portrait Landscape Configuration
R/W
DBCNTM
PL_EN
0
0
0
0
0
0
12
PL_COUNT
Portrait Landscape Debounce
R/W
DBNCE[7]
DBNCE[6]
DBNCE[5]
DBNCE[4]
DBNCE[3]
DBNCE[2]
DBNCE[1]
DBNCE[0]
PL_BF_ZCOMP
Portrait Landscape
Back/Front Z Comp
R
0
1
0
0
0
1
0
0
13
14
PL_THS_REG
Portrait Landscape Threshold
R
1
0
0
0
0
1
0
0
15
FF_MT_CFG
Freefall/Motion Config
R/W
ELE
OAE
ZEFE
YEFE
XEFE
0
0
0
16
FF_MT_SRC
Freefall/Motion Status
R
EA
0
ZHE
ZHP
YHE
YHP
XHE
XHP
17
FF_MT_THS
Freefall/Motion Threshold
R/W
DBCNTM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
18
FF_MT_COUNT
Freefall/Motion
Debounce
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
—
R
—
—
—
—
—
—
—
—
29
ASLP_Count
Counter setting for
Auto-SLEEP/WAKE
R/W
D7
D6
D5
D4
D3
D2
D1
D0
2A
CTRL_REG1
Control Reg1
R/W
ASLP_RATE1
ASLP_RATE0
DR2
DR1
DR0
0
F_READ
ACTIVE
19–28
2B
CTRL_REG2
Control Reg2
R/W
ST
RST
—
SMODS1
SMODS0
SLPE
MODS1
MODS0
2C
CTRL_REG3
Control Reg3
R/W
—
—
WAKE_LNDPRT
—
WAKE_FF_MT
0
IPOL
PP_OD
2D
CTRL_REG4
Control Reg4
R/W
INT_EN_ASLP
—
—
INT_EN_LNDPRT
—
INT_EN_FF_MT
0
INT_EN_DRDY
2E
CTRL_REG5
Control Reg5
R/W
INT_CFG_ASLP
—
—
INT_CFG_LNDPRT
—
INT_CFG_FF_MT
0
INT_CFG_DRDY
2F
OFF_X
X 8-bit offset
R/W
D7
D6
D5
D4
D3
D2
D1
D0
30
OFF_Y
Y 8-bit offset
R/W
D7
D6
D5
D4
D3
D2
D1
D0
31
OFF_Z
Z 8-bit offset
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Note: Bits showing “—” can read as either 0 or 1, and these bits have no definition.
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6.3
Data registers
The following are the data registers for the MMA8653FC device. For more information about data manipulation in the
MMA8653FC, see application note AN4083, Data Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers.
•
When accessing the 8-bit data, the F_READ bit (register 0x2A) is set, which modifies the auto-incrementing to skip over the
LSB data.
•
When the F_READ bit is cleared, the 12-bit data is read, accessing all 6 bytes sequentially (X_MSB, X_LSB, Y_MSB,
Y_LSB, Z_MSB, Z_LSB).
6.3.1
0x00: STATUS Data Status register
Data Status register 0x00 reflects the real-time status information of the X, Y and Z sample data; it contains the X, Y, and Z data
overwrite and data ready flag.
These registers contain the X-axis, Y-axis, and Z-axis 12-bit output sample data (expressed as 2's complement numbers).
Table 14. 0x00 STATUS: Data Status register (Read-Only)
Back to Register Address Map
Bit 7
ZYXOW
Bit 6
ZOW
Bit 5
YOW
Bit 4
XOW
Bit 3
ZYXDR
Bit 2
ZDR
Bit 1
YDR
Bit 0
XDR
Table 15. STATUS register bits
Bit(s)
7
Field
ZYXOW
Description
6
ZOW
Z-axis data overwrite
5
YOW
Y-axis data overwrite
4
XOW
X-axis data overwrite
3
ZYXDR
Notes
X, Y, Z-axis data overwrite
• Set whenever a new acceleration data is produced before completing the retrieval of the previous set.
This event occurs when the content of at least one acceleration data register (i.e., OUT_X, OUT_Y, OUT_Z) has been
overwritten.
• Cleared when the high bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels are
read.
0 No data overwrite has occurred (default)
1 Previous X, Y, or Z data was overwritten by new X, Y, or Z data before it (the previous X, Y, or Z data) was read
For # = Z, Y, or X:
• Set whenever a new acceleration sample related to
the #-axis is generated before the retrieval of the
previous sample. When this occurs, the previous
sample is overwritten.
• Cleared whenever the OUT_#_MSB register is read.
0 No data overwrite has occurred (default)
1 Previous Z-axis data was overwritten by new #-axis
data before it (the previous #-axis data) was read
X, Y, Z-axis new data ready
• Set when a new sample for any of the enabled channels is available.
• Cleared when the high-bytes of the acceleration data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the channels
are read.
0 No new set of data ready (default)
1 A new set of data is ready
2
ZDR
Z-axis new data available
1
YDR
Y-axis new data available
0
XDR
X-axis new data available
For # = Z, Y, or X
• Set whenever a new acceleration sample related to
the #-axis is generated.
• Cleared whenever the OUT_#_MSB register is read.
0 No new #-axis data ready (default)
1 New #-axis data is ready
Table 16. 0x01 OUT_X_MSB: X_MSB register (Read-Only)
Bit 7
XD9
Bit 6
XD8
Bit 5
XD7
Bit 4
XD6
Back to Register Address Map
Bit 3
XD5
Bit 2
XD4
Table 17. 0x02 OUT_X_LSB: X_LSB register (Read-Only)
Bit 7
XD1
Bit 6
XD0
Bit 5
0
Bit 4
0
Bit 1
XD3
Bit 0
XD2
Back to Register Address Map
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
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Table 18. 0x03 OUT_Y_MSB: Y_MSB register (Read-Only)
Bit 7
YD9
Bit 6
YD8
Bit 5
YD7
Bit 4
YD6
Back to Register Address Map
Bit 3
YD5
Bit 2
YD4
Table 19. 0x04 OUT_Y_LSB: Y_LSB register (Read-Only)
Bit 7
YD1
Bit 6
YD0
Bit 5
0
Bit 4
0
Bit 6
ZD8
Bit 5
ZD7
Bit 4
ZD6
Bit 3
0
Bit 2
0
Bit 6
ZD0
Bit 5
0
Bit 4
0
Bit 1
0
Bit 0
0
Back to Register Address Map
Bit 3
ZD5
Bit 2
ZD4
Table 21. 0x06 OUT_Z_LSB: Z_LSB register (Read-Only)
Bit 7
ZD1
Bit 0
YD2
Back to Register Address Map
Table 20. 0x05 OUT_Z_MSB: Z_MSB register (Read-Only)
Bit 7
ZD9
Bit 1
YD3
Bit 1
ZD3
Bit 0
ZD2
Back to Register Address Map
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
•
OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored in the autoincrementing address range of 0x01 – 0x06, to reduce reading the status followed by 10-bit axis data to 7 bytes. If the
F_READ bit is set (0x2A bit 1), then auto-increment will skip over LSB registers (to access the MSB data only). This will
shorten the data acquisition from seven bytes to four bytes.
•
The LSB registers can only be read immediately following the read access of the corresponding MSB register.
—
A random read access to the LSB registers is not possible.
—
Reading the MSB register and then the LSB register in sequence ensures that both bytes (LSB and MSB) belong
to the same data sample, even if a new data sample arrives between reading the MSB and the LSB byte.
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6.4
System status and ID registers
6.4.1
0x0B: SYSMOD System Mode register
The System mode register indicates the current device operating mode. Applications using the Auto-SLEEP/WAKE mechanism
should use the SYSMOD register to synchronize the application with the device operating mode transitions.
Table 22. 0x0B SYSMOD: System Mode register (Read-Only)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Back to Register Address Map
Bit 3
0
Bit 2
0
Bit 1
SYSMOD1
Bit 0
SYSMOD0
Table 23. SYSMOD register
Bit(s)
Field
7–2
0
1–0
6.4.2
Description
Reserved
SYSMOD[1:0]
System Mode
00 STANDBY mode (default)
01 WAKE mode
10 SLEEP mode
0x0C: INT_SOURCE System Interrupt Status register
In the interrupt source register, the status of the various embedded features can be determined.
•
The bits that are set (logic ‘1’) indicate which function has asserted an interrupt.
•
The bits that are cleared (logic ‘0’) indicate which function has not asserted (or has deasserted) an interrupt.
INT_SOURCE register bits are set by a low-to-high transition, and are cleared by reading the appropriate interrupt source register.
For example, the SRC_DRDY bit is cleared when the ZYXDR bit (STATUS register) is cleared, but the SRC_DRDY bit is not
cleared by simply reading the STATUS register (0x00), but is cleared by reading all the X, Y, and Z MSB data.
Table 24. 0x0C INT_SOURCE: System Interrupt Status register (Read Only)
Bit 7
SRC_ASLP
Bit 6
0
Bit 5
0
Bit 4
SRC_LNDPRT
Bit 3
0
Back to Register Address Map
Bit 2
SRC_FF_MT
Bit 1
0
Bit 0
SRC_DRDY
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Table 25. INT_SOURCE register
Bit(s)
Field
Description
7
SRC_ASLP
Auto-SLEEP/WAKE interrupt status bit
• WAKE-to-SLEEP transition occurs when no interrupt occurs for a time period that exceeds the userspecified limit (ASLP_COUNT). This causes the system to transition to a user-specified low ODR setting.
• SLEEP-to-WAKE transition occurs when the user-specified interrupt event has woken the system; thus
causing the system to transition to a user-specified high ODR setting.
• Reading the SYSMOD register clears the SRC_ASLP bit.
1 An interrupt event that can cause a WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition has
occurred.
0 No WAKE-to-SLEEP or SLEEP-to-WAKE system mode transition interrupt event has occurred. (default)
6
0
5
0
4
SRC_LNDPRT
3
0
2
SRC_FF_MT
1
0
0
6.4.3
SRC_DRDY
Landscape/Portrait Orientation interrupt status bit
• SRC_LNDPRT bit is asserted whenever the NEWLP bit (PL_STATUS register) is asserted and the interrupt
has been enabled.
• SRC_LNDPRT bit is cleared by reading the PL_STATUS register.
1 An interrupt was generated due to a change in the device orientation status.
0 No change in orientation status was detected. (default)
Freefall/Motion interrupt status bit
• SRC_FF_MT bit is asserted whenever the EA bit (FF_MT_SRC register) is asserted and the FF_MT
interrupt has been enabled.
• SRC_FF_MT bit is cleared by reading the FF_MT_SRC register.
1 The Freefall/Motion function interrupt is active.
0 No Freefall or Motion event was detected. (default)
Data Ready Interrupt bit status bit
• SRC_DRDY bit is asserted when the ZYXOW and/or ZYXDR bit is set and the interrupt has been enabled.
• SRC_DRDY bit is cleared by reading the X, Y, and Z data.
1 The X, Y, Z data ready interrupt is active (indicating the presence of new data and/or data overrun).
0 The X, Y, Z interrupt is not active. (default)
0x0D: WHO_AM_I Device ID register
The device identification register identifies the part. The default value is 0x5A (for MMA8653FC).
This value is programmed by Freescale before the part leaves the factory. For custom alternate values, contact Freescale.
Table 26. 0x0D: WHO_AM_I Device ID register (Read-Only)
Bit 7
0
Bit 6
1
Bit 5
0
Bit 4
1
Back to Register Address Map
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
0
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6.5
Data configuration registers
6.5.1
0x0E: XYZ_DATA_CFG register
The XYZ_DATA_CFG register sets the dynamic range.
Table 27. 0x0E: XYZ_DATA_CFG register (Read/Write)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Back to Register Address Map
Bit 3
0
Bit 2
0
Bit 1
FS1
Bit 0
FS0
Table 28. XYZ Data Configuration register
Bit(s)
Field
7–2
0
1–0
FS[1:0]
Description
Output buffer data format using full scale
00 ±2 g (default)
The default full scale value range is
±2 g.
Table 29. Full-Scale Range
FS1
FS0
Full-Scale Range
0
0
±2 g
0
1
±4 g
1
0
±8 g
1
1
Reserved
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6.6
Portrait/Landscape configuration and status registers
For more information about the different user-configurable settings and example code, see application note AN4083, Data
Manipulation and Basic Settings for Xtrinsic MMA865xFC Accelerometers.
6.6.1
0x10: PL_STATUS Portrait/Landscape Status register
To get updated information on any change in orientation, read the Portrait/Landscape Status register (read Bit 7, or read the other
bits for more orientation data). For more about Portrait Up, Portrait Down, Landscape Left, Landscape Right, Back, and Front
orientations, see Figure 6. The interrupt is cleared when reading the PL_STATUS register.
Table 30. 0x10 PL_STATUS Register (Read-Only)
Bit 7
NEWLP
Bit 6
LO
Bit 5
0
Back to Register Address Map
Bit 4
0
Bit 3
0
Bit 2
LAPO[1]
Bit 1
LAPO[0]
Bit 0
BAFRO
Table 31. PL_STATUS register
Bit(s)
7
Field
NEWLP
6
LO
5–3
0
2–1
LAPO[1:0](1)
0
BAFRO
Description
Landscape/Portrait status change flag
• NEWLP is set to 1 after the first orientation detection after a STANDBY-to-ACTIVE transition, and whenever a
change in LO, BAFRO, or LAPO occurs.
• NEWLP bit is cleared anytime PL_STATUS register is read.
0 No change (default)
1 BAFRO and/or LAPO and/or Z-Tilt lockout value has changed
Z-Tilt Angle Lockout
0 Lockout condition has not been detected (default)
1 Z-Tilt lockout trip angle has been exceeded.
Lockout has been detected.
Landscape/Portrait orientation
00 Portrait Up: Equipment standing vertically in the normal orientation (default)
01 Portrait Down: Equipment standing vertically in the inverted orientation
10 Landscape Right: Equipment is in landscape mode to the right
11 Landscape Left: Equipment is in landscape mode to the left.
Back or Front orientation
0 Front: Equipment is in the front-facing orientation (default)
1 Back: Equipment is in the back-facing orientation
1. The default power-up state is BAFRO = 0, LAPO = 00, and LO = 0.
•
The orientation mechanism state change is limited to a maximum 1.25 g.
The current position is locked if the absolute value of the acceleration experienced on any of the three axes is greater than
1.25 g.
•
LAPO, BAFRO, and LO continue to change when NEWLP is set.
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6.6.2
0x11 Portrait/Landscape Configuration register
The Portrait/Landscape Configuration register enables the portrait/landscape function and sets the behavior of the debounce
counter.
Table 32. 0x11 PL_CFG register (Read/Write)
Bit 7
DBCNTM
Bit 6
PL_EN
Back to Register Address Map
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Table 33. PL_CFG register
Bit(s)
Field
7
DBCNTM
6
PL_EN
5–0
0
6.6.3
Description
Debounce counter mode selection
0 Decrements debounce whenever the condition of interest is no longer valid.
1 Clears the counter whenever the condition of interest is no longer valid. (default)
Portrait/Landscape detection enable
0 Portrait/Landscape Detection is disabled. (default)
1 Portrait/Landscape Detection is enabled.
0x12 Portrait/Landscape Debounce register
The Portrait/Landscape Debounce register sets the debounce count for the orientation state transition. The minimum debounce
latency is determined by the data rate (which is set by the product of the selected system ODR and PL_COUNT registers). Any
transition from WAKE to SLEEP (or SLEEP to Wake) resets the internal Landscape/Portrait debounce counter.
NOTE
The debounce counter weighting (time step) changes, based on the ODR and the
Oversampling mode. Table 36 explains the time step value for all sample rates and all
Oversampling modes.
Table 34. 0x12 PL_COUNT register (Read/Write)
Bit 7
DBNCE[7]
Bit 6
DBNCE[6]
Bit 5
DBNCE[5]
Back to Register Address Map
Bit 4
DBNCE[4]
Bit 3
DBNCE[3]
Bit 2
DBNCE[2]
Bit 1
DBNCE[1]
Bit 0
DBNCE[0]
Table 35. PL_COUNT register
Bit(s)
7–0
Field
DBCNE[7:0]
Description
Debounce Count value
0000_0000 (default)
Table 36. PL_COUNT relationship with the ODR
Max Time Range (s)
Time Step (ms)
ODR
(Hz)
Normal
LPLN
HighRes
LP
Normal
LPLN
HighRes
LP
800
0.319
0.319
0.319
0.319
1.25
1.25
1.25
1.25
400
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
200
1.28
1.28
0.638
1.28
5
5
2.5
5
100
2.55
2.55
0.638
2.55
10
10
2.5
10
50
5.1
5.1
0.638
5.1
20
20
2.5
20
12.5
5.1
20.4
0.638
20.4
20
80
2.5
80
6.25
5.1
20.4
0.638
40.8
20
80
2.5
160
1.56
5.1
20.4
0.638
40.8
20
80
2.5
160
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6.6.4
0x13: PL_BF_ZCOMP Back/Front and Z Compensation register
The Z-Lock angle compensation bits fix the Z-lockout angle to 30° upon power up. The Back to Front trip angle is fixed to ±75°.
Table 37. 0x13: PL_BF_ZCOMP register (Read only)
Bit 7
0
Bit 6
1
Bit 5
0
Back to Register Address Map
Bit 4
0
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
Table 38. PL_BF_ZCOMP register
6.6.5
Bit(s)
Field
7–0
0100 0100
Description
Notes
0x14: P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register
This register represents the Portrait-to-Landscape trip threshold register used to set the trip angle for transitioning from Portrait
to Landscape mode and from Landscape to Portrait mode. This register includes a value for the hysteresis.
Table 39. 0x14: P_L_THS_REG register (Read only)
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Back to Register Address Map
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
Table 40. P_L_THS_REG register
Bit(s)
Field
7–0
1000 0100
Description
Notes
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6.7
Freefall/Motion configuration and status registers
The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15:
FF_MTG_CFG, bit 6). The freefall/motion detection block can be disabled by setting all three bits (ZEFE, YEFE, XEFE) to zero.
Depending on the register bits ELE (0x15: FF_MTG_CFG, bit 7) and OAE (0x15: FF_MTG_CFG, bit 6), each of the freefall and
motion detection block can operate in four different modes.
6.7.1
Motion and freefall modes
6.7.1.1
Mode 1: Freefall detection with ELE = 0, OAE = 0
In this mode, the EA bit (0x16: FF_MTG_CFG, bit 7) indicates a freefall event after the debounce counter is complete. The ZEFE,
YEFE, and XEFE control bits determine which axes are considered for the freefall detection. Once the EA bit is set, and DBCNTM
= 0, the EA bit can get cleared only after the delay specified by FF_MT_COUNT. This is because the counter is in decrement
mode. If DBCNTM = 1, then the EA bit is cleared as soon as the freefall condition disappears, and will not be set again before
the delay specified by FF_MT_COUNT has passed. Reading the FF_MT_SRC register does not clear the EA bit.
The event flags (0x16) ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any
debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
6.7.1.2
Mode 2: Freefall detection with ELE = 1, OAE = 0
In this mode, the EA event bit indicates a freefall event after the debounce counter. Once the debounce counter reaches the time
value for the set threshold, the EA bit is set, and the EA bit remains set until the FF_MT_SRC register is read. When the
FF_MT_SRC register is read, the EA bit and the debounce counter are cleared, and a new event can only be generated after the
delay specified by FF_MT_CNT. The ZEFE, YEFE, and XEFE control bits determine which axes are considered for the freefall
detection. While EA = 0, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g
event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set.
The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP are latched when the EA event bit is set. The event flags ZHE, ZHP, YHE,
YHP, XHE, and XHP will start changing only after the FF_MT_SRC register has been read.
6.7.1.3
Mode 3: Motion detection with ELE = 0, OAE = 1
In this mode, the EA bit indicates a motion event after the debounce counter time is reached. The ZEFE, YEFE, and XEFE control
bits determine which axes are taken into consideration for motion detection. Once the EA bit is set and if DBCNTM = 0, the EA
bit can get cleared only after the delay specified by FF_MT_COUNT. If DBCNTM = 1, then the EA bit is cleared as soon as the
motion high g condition disappears.
The event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g event) without any
debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. Reading the FF_MT_SRC does not clear
any flags, nor is the debounce counter reset.
6.7.1.4
Mode 4: Motion detection with ELE = 1, OAE = 1
In this mode, the EA bit indicates a motion event after debouncing. The ZEFE, YEFE, and XEFE control bits determine which
axes are taken into consideration for motion detection. Once the debounce counter reaches the threshold, the EA bit is set, and
the EA bit remains set until the FF_MT_SRC register is read. When the FF_MT_SRC register is read, all register bits are cleared
and the debounce counter are cleared and a new event can only be generated after the delay specified by FF_MT_CNT.
While the bit EA is zero, the event flags ZHE, ZHP, YHE, YHP, XHE, and XHP reflect the motion detection status (i.e., a high g
event) without any debouncing, provided that the corresponding bits ZEFE, YEFE, and/or XEFE are set. When the EA bit is set,
these bits (ZHE, ZHP, YHE, YHP, XHE, XHP) keep their current value until the FF_MT_SRC register is read.
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6.7.2
0x15: FF_MT_CFG Freefall/Motion Configuration register
This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function.
Table 41. 0x15 FF_MT_CFG register (Read/Write)
Bit 7
ELE
Bit 6
OAE
Bit 5
ZEFE
Back to Register Address Map
Bit 4
YEFE
Bit 3
XEFE
Bit 2
0
Bit 1
0
Bit 0
0
Table 42. FF_MT_CFG register
Bit(s)
Field
Description
ELE
Event Latch Enable: Event flags are latched into FF_MT_SRC register.
ELE denotes whether the enabled event flag will to be latched into the FF_MT_SRC register or whether the event flag
status in the FF_MT_SRC will indicate the real-time status of the event.
• If ELE bit is set to 1, then the event flags are frozen when the EA bit gets set, and the event flags are cleared by
reading the FF_MT_SRC source register.
• Reading the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits.
0 Event flag latch disabled (default)
1 Event flag latch enabled
OAE
Motion detect / Freefall detect flag selection
Selects between Motion (logical OR combination) and Freefall (logical AND combination) detection.
0 Freefall flag (Logical AND combination) (default)
1 Motion flag (Logical OR combination)
ZEFE
Event flag enable on Z
ZHFE enables the detection of a motion or freefall event when the measured acceleration data on Z channel is beyond
the threshold set in FF_MT_THS register.
• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC
register.
0 Event detection disabled (default)
1 Raise event flag on measured acceleration value beyond preset threshold
YEFE
Event flag enable on Y event
YEFE enables the detection of a motion or freefall event when the measured acceleration data on Y channel is beyond
the threshold set in FF_MT_THS register.
• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC
register.
0 Event detection disabled (default)
1 Raise event flag on measured acceleration value beyond preset threshold
3
XEFE
Event flag enable on X event
XEFE enables the detection of a motion or freefall event when the measured acceleration data on X channel is beyond
the threshold set in FF_MT_THS register.
• If ELE bit (FF_MT_CFG register) is set to 1, then new event flags are blocked from updating the FF_MT_SRC
register.
0 Event detection disabled (default)
1 Raise event flag on measured acceleration value beyond preset threshold
2–0
0
7
6
5
4
+8 g
Low-g + Threshold (Freefall)
0g
Low-g – Threshold (Freefall)
–8 g
Figure 14. FF_MT_CFG low-g threshold (freefall)
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6.7.3
0x16: FF_MT_SRC Freefall/Motion Source register
The Freefall/Motion Source register keeps track of the acceleration event that is triggering (or has triggered, if ELE bit in
FF_MT_CFG register is set to 1) the event flag. In particular, EA is set to 1 when the logical combination of acceleration events
flags specified in FF_MT_CFG register is true. This EA bit is used in combination with the values in INT_EN_FF_MT and
INT_CFG_FF_MT register bits to generate the freefall/motion interrupts.
•
An X,Y, or Z motion is true when the acceleration value of the X or Y or Z channel is higher than the preset threshold value
defined in the FF_MT_THS register.
•
An X, Y, and Z low event is true when the acceleration value of the X and Y and Z channel is lower than or equal to the preset
threshold value defined in the FF_MT_THS register.
Table 43. 0x16: FF_MT_SRC Freefall/Motion Source register (Read-Only)
Bit 7
EA
Bit 6
0
Bit 5
ZHE
Bit 4
ZHP
Bit 3
YHE
Back to Register Address Map
Bit 2
YHP
Bit 1
XHE
Bit 0
XHP
Table 44. Freefall/Motion Source register
Bit(s)
Field
7
EA
6
0
5
4
3
2
1
0
Description
Event Active flag
0 No event flag has been asserted (default)
1 One or more event flags has been asserted.
See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit.
ZHE
Z-Motion flag
ZHE bit always reads zero if the ZEFE control bit is set to zero.
0 No Z motion event detected (default)
1 Z motion has been detected
ZHP
Z-Motion Polarity Flag
ZHP bit always reads zero if the ZEFE control bit is set to zero.
0 Z event was positive g (default)
1 Z event was negative g
YHE
Y-Motion Flag
YHE bit always reads zero if the YEFE control bit is set to zero.
0 No Y motion event detected (default)
1 Y motion has been detected
YHP
Y-Motion Polarity Flag
YHP bit always reads zero if the YEFE control bit is set to zero.
0 Y event detected was positive g (default)
1 Y event was negative g
XHE
X-Motion Flag
XHE bit always reads zero if the XEFE control bit is set to zero.
0 No X motion event detected (default)
1 X motion has been detected
XHP
X-Motion Polarity Flag
XHP bit always reads zero if the XEFE control bit is set to zero.
0 X event was positive g (default)
1 X event was negative g
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6.7.4
0x17: FF_MT_THS Freefall and Motion Threshold register
FF_MT_THS is the threshold register used to detect freefall motion events.
•
The unsigned 7-bit FF_MT_THS threshold register holds the threshold for the freefall detection where the magnitude of
the X and Y and Z acceleration values is lower or equal than the threshold value.
•
Conversely, the FF_MT_THS also holds the threshold for the motion detection where the magnitude of the X or Y or Z
acceleration value is higher than the threshold value.
Table 45. 0x17 FF_MT_THS register (Read/Write)
Bit 7
DBCNTM
Bit 6
THS6
Bit 5
THS5
Back to Register Address Map
Bit 4
THS4
Bit 3
THS3
Bit 2
THS2
Bit 1
THS1
Bit 0
THS0
Table 46. FF_MT_THS register
Bit(s)
Field
Description
7
DBCNTM
Debounce counter mode selection
0 Increments or decrements debounce (default)
1 Increments or clears counter.
6–0
THS[6:0]
Freefall /Motion Threshold
000_0000 (default)
The threshold resolution is 0.063 g/LSB and the threshold register has a range of 0 to 127 counts. The maximum range is to ±8 g.
Note that even when the full scale value is set to ±2 g or ±4 g, the motion still detects up to ±8 g.
The DBCNTM bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not
true.
•
When the DBCNTM bit is 1, the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true
as shown in Figure 15, (b).
•
While the DBCNTM bit is set to 0, the debounce counter is decremented by 1 whenever the inertial event of interest is no
longer true (Figure 15, (c)) until the debounce counter reaches 0 or until the inertial event of interest becomes active.
Decrementing the debounce counter acts as a median enabling the system to filter out irregular spurious events (which might
impede the detection of inertial events).
6.7.5
0x18 FF_MT_COUNT Debounce register
The Debounce register sets the number of debounce sample counts for the event trigger.
Table 47. 0x18 FF_MT_COUNT register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Bit 4
D4
Back to Register Address Map
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 48. FF_MT_COUNT register
Bit(s)
7–0
Field
D[7:0]
Description
Count value
0000_0000 (default)
The Debounce register sets the minimum number of debounce sample counts that continuously match the detection condition
selected by you for the freefall/motion event.
When the internal debounce counter reaches the FF_MT_COUNT value, a freefall/motion event flag is set. The debounce
counter will never increase beyond the FF_MT_COUNT value. The time step used for the debounce sample count depends on
the ODR chosen and the Oversampling mode, as shown in Table 49.
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Table 49. FF_MT_COUNT relationship with the ODR
Max Time Range (s)
Time Step (ms)
ODR
(Hz)
Normal
LPLN
HighRes
LP
Normal
LPLN
HighRes
LP
800
0.319
0.319
0.319
0.319
1.25
1.25
1.25
1.25
400
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
200
1.28
1.28
0.638
1.28
5
5
2.5
5
100
2.55
2.55
0.638
2.55
10
10
2.5
10
50
5.1
5.1
0.638
5.1
20
20
2.5
20
12.5
5.1
20.4
0.638
20.4
20
80
2.5
80
6.25
5.1
20.4
0.638
40.8
20
80
2.5
160
1.56
5.1
20.4
0.638
40.8
20
80
2.5
160
High g Event on
all 3-axis
(Motion Detect)
Count Threshold
(a)
FF
Counter
Value
FFEA
High g Event on
all 3-axis
(Motion Detect)
DBCNTM = 1
Count Threshold
Debounce
Counter
Value
(b)
EA
High g Event on
all 3-axis
(Motion Detect)
DBCNTM = 0
Count Threshold
Debounce
Counter
Value
(c)
EA
Figure 15. DBCNTM bit function
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6.8
Auto-WAKE/SLEEP detection
6.8.1
0x29: ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write)
The ASLP_COUNT register sets the minimum time period of inactivity required to switch the part between Wake and Sleep
status. At the end of the time period, the device switches its ODR rate automatically when the Auto-WAKE /SLEEP function is
enabled.
•
Wake ODR is set by CTRL_REG1[DR] bits.
•
Sleep ODR is set by CTRL_REG1[ASLP_RATE] bits.
•
Auto WAKE/SLEEP function is enabled by asserting the CTRL_REG2[SLPE] bit.
Table 50. 0x29 ASLP_COUNT register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Back to Register Address Map
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 51. ASLP_COUNT register
Bit(s)
Field
7–0
D[7:0]
Description
Duration value
0000_0000 (default)
D7–D0 defines the minimum duration time needed to change the current ODR value from DR to ASLP_RATE. The time step and
maximum value depend on the ODR chosen (as shown in Table 52).
Table 52. ASLP_COUNT relationship with ODR
Output Data Rate
(ODR)
Duration
(sec)
ODR Time Step
(ms)
ASLP_COUNT Step
(ms)
800 Hz
0 to 81
1.25
320
400 Hz
0 to 81
2.5
320
200 Hz
0 to 81
5
320
100 Hz
0 to 81
10
320
50 Hz
0 to 81
20
320
12.5 Hz
0 to 81
80
320
6.25 Hz
0 to 81
160
320
1.56 Hz
0 to 162
640
640
For functional blocks that may be monitored for inactivity (to trigger the “return to SLEEP” event), see Table 53.
Table 53. SLEEP/WAKE mode gates and triggers
Will the event restart the timer
and delay “Return to SLEEP”?
Will the event
WAKE from SLEEP?
SRC_LNDPRT
Yes
Yes
SRC_FF_MT
Yes
Yes
SRC_ASLP
No*
No*
SRC_DRDY
No
No
Interrupt Source
•
Two interrupt sources can WAKE the device: Orientation and Motion/Freefall. One or more of these functions can be
enabled.
—
To WAKE the device, the desired function(s) must be enabled in CTRL_REG4 register and set to WAKE-to-SLEEP
in CTRL_REG3 register.
—
All enabled functions still run in SLEEP mode at the SLEEP ODR.
Only the functions that have been selected for WAKE from SLEEP will actually WAKE the device (as configured in
register 0x2C).
—
The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP, nor does the data ready interrupt.
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•
MMA8653FC has two functions that can be used to keep the sensor from falling asleep: Orientation and Motion/Freefall.
•
Auto-SLEEP bit:
6.9
—
If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode.
—
If Auto-SLEEP interrupt is enabled, then transitioning from ACTIVE mode to Auto-SLEEP mode (or vice versa)
generates an interrupt.
System and control registers
NOTE
Except for STANDBY mode selection, the device must be in STANDBY mode to change any
of the fields within CTRL_REG1 (0x2A).
6.9.1
0x2A: CTRL_REG1 System Control 1 register
CTRL_REG1 register configures the Auto-WAKE sample frequency, output data rate selection, and enables the fast-read mode
and STANDBY/ACTIVE mode selection.
Table 54. 0x2A CTRL_REG1 register (Read/Write)
Bit 7
ASLP_RATE1
Bit 6
ASLP_RATE0
Bit 5
DR2
Back to Register Address Map
Bit 4
DR1
Bit 3
DR0
Bit 2
0
Bit 1
F_READ
Bit 0
ACTIVE
Table 55. CTRL_REG1 register
Bit(s)
Field
Description
7–6
ASLP_RATE[1:0]
5–3
DR[2:0]
2
0
1
F_READ
Fast-read mode: Data format is limited to single byte
0 Normal mode (default)
1 Fast Read Mode
0
ACTIVE
Full-scale selection
0 STANDBY mode (default)
1 ACTIVE mode
Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode.
See Table 56.
00 (default)
Data rate selection
See Table 57.
000 (default)
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Table 56. SLEEP mode rates
ASLP_RATE1
ASLP_RATE0
Frequency (Hz)
0
0
50
0
1
12.5
1
0
6.25
1
1
1.56
Notes
When the device is in Auto-SLEEP mode, the system ODR and the
data rate for all the system functional blocks are overridden by the data
rate set by the ASLP_RATE field.
DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples in WAKE mode. The default value is 000 for a data rate
of 800 Hz.
Table 57. System output data-rate selection
DR2
DR1
DR0
ODR
(Hz)
Period
(ms)
Notes
0
0
0
800
1.25
default
0
0
1
400
2.5
0
1
0
200
5
0
1
1
100
10
1
0
0
50
20
1
0
1
12.5
80
1
1
0
6.25
160
1
1
1
1.56
640
The ACTIVE bit selects between STANDBY mode and ACTIVE mode.
Table 58. Full-Scale selection using ACTIVE bit
Active bit
Mode
0
STANDBY (default)
1
ACTIVE
•
The F_Read bit selects between normal and Fast Read mode.
When selected, the auto-increment counter will skip over the LSB data bytes.
Data read from the FIFO will skip over the LSB data, reducing the acquisition time.
•
Note that F_READ can only be changed when FMODE = 00.
•
The F_READ bit applies for the output registers.
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6.9.2
0x2B: CTRL_REG2 System Control 2 register
CTRL_REG2 register is used to enable Self-Test, Software Reset, and Auto-SLEEP. In addition, it enables you to configure the
SLEEP and WAKE mode power scheme selection (oversampling modes).
Table 59. 0x2B CTRL_REG2 register (Read/Write)
Bit 7
ST
Bit 6
RST
Bit 5
—
Back to Register Address Map
Bit 4
SMODS1
Bit 3
SMODS0
Bit 2
SLPE
Bit 1
MODS1
Bit 0
MODS0
Table 60. CTRL_REG2 register
Bit(s)
Field
7
ST
6
RST
5
—
4–3
SMODS[1:0]
2
SLPE
1–0
MODS[1:0]
Description
Self-Test Enable
Activates the self-test function.
• When ST is set, the X, Y, and Z outputs will shift.
0 Self-Test disabled (default)
1 Self-Test enabled
Software Reset
RST bit is used to activate the software reset.
• The reset mechanism is enabled in both STANDBY and ACTIVE modes.
0 Device reset disabled (default)
1 Device reset enabled.
Could be 0 or 1.
SLEEP mode power scheme selection
See Table 61 and Table 62
00 (default)
Auto-SLEEP enable
0 Auto-SLEEP is not enabled (default)
1 Auto-SLEEP is enabled.
ACTIVE mode power scheme selection
See Table 61 and Table 62
00 (default)
When the reset bit is enabled, all registers are reset and are loaded with default values. Writing ‘1’ to the RST bit immediately
resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode.
The I2C communication system is reset to avoid accidental corrupted data access.
At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero.
The (S)MODS[1:0] bits select which Oversampling mode is to be used, as shown in Table 61. The Oversampling modes are
available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0].
Table 61. (S)MODS Oversampling modes
(S)MODS1
(S)MODS0
0
0
Power Mode
Normal
0
1
Low Noise Low Power
1
0
High Resolution
1
1
Low Power
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Table 62. MODS Oversampling modes averaging values at each ODR
Mode
ODR
(Hz)
6.9.3
Normal (00)
Low Noise Low Power (01)
High Resolution (10)
Low Power (11)
Current A
OS Ratio
Current A
OS Ratio
Current A
OS Ratio
Current A
OS Ratio
1.56
27
128
9
32
184
1024
6.5
16
6.25
27
32
9
8
184
256
6.5
4
12.5
27
16
9
4
184
128
6.5
2
50
27
4
27
4
184
32
15
2
100
49
4
49
4
184
16
26
2
200
94
4
94
4
184
8
49
2
400
184
4
184
4
184
4
94
2
800
184
2
184
2
184
2
184
2
0x2C: CTRL_REG3 Interrupt Control register
CTRL_REG3 register is used to control the Auto-WAKE/SLEEP function by setting the orientation or Freefall/Motion as an
interrupt to wake. CTRL_REG3 register also configures the interrupt pins INT1 and INT2.
Table 63. 0x2C CTRL_REG3 register (Read/Write)
Bit 7
—
Bit 6
—
Bit 5
WAKE_LNDPRT
Back to Register Address Map
Bit 4
—
Bit 3
WAKE_FF_MT
Bit 2
0
Bit 1
IPOL
Bit 0
PP_OD
Table 64. CTRL_REG3 register
Bit(s)
Field
7–6
—
5
WAKE_LNDPRT
4
—
3
WAKE_FF_MT
2
0
1
Wake from Orientation interrupt
0 Orientation function is bypassed in SLEEP mode. (default)
1 Orientation function interrupt can wake up system
Could be 0 or 1.
Wake from Freefall/Motion interrupt
0 Freefall/Motion function is bypassed in SLEEP mode. (default)
1 Freefall/Motion function interrupt can wake up
Interrupt polarity
Selects the polarity of the interrupt signals.
When IPOL is 0 (default value), any interrupt event is signaled with a logical 0.
0 ACTIVE low (default)
1 ACTIVE high
IPOL
0
6.9.4
Description
Could be 0 or 1.
PP_OD
Push-Pull/Open-Drain selection on interrupt pad
Configures the interrupt pins to Push-Pull or to Open-Drain mode.
The Open-Drain configuration can be used for connecting multiple interrupt signals on the same interrupt line.
0 Push-Pull (default)
1 Open Drain
0x2D: CTRL_REG4 Interrupt Enable register (Read/Write)
CTRL_REG4 register enables the following interrupts: Auto-WAKE/SLEEP, Orientation Detection, Freefall/Motion, and Data
Ready.
Table 65. 0x2D CTRL_REG4 Interrupt Enable register (Read/Write)
Bit 7
INT_EN_ASLP
Bit 6
—
Bit 5
—
Bit 4
INT_EN_LNDPRT
Back to Register Address Map
Bit 3
—
Bit 2
Bit 1
INT_EN_FF_MT
0
Bit 0
INT_EN_DRDY
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Table 66. CTRL_REG4 register
Bit(s)
7
Field
INT_EN_ASLP
Auto-SLEEP/WAKE Interrupt Enable
6
—
Could be 0 or 1.
5
—
Could be 0 or 1.
4
INT_EN_LNDPRT
Orientation (Landscape/Portrait) Interrupt Enable
3
—
Could be 0 or 1.
2
INT_EN_FF_MT
Freefall/Motion Interrupt Enable
0
INT_EN_DRDY
Data Ready Interrupt Enable
6.9.5
Description
0 interrupt is disabled (default)
1 interrupt is enabled
Note: The corresponding functional block interrupt
enable bit enables the functional block to route
its event detection flags to the system’s interrupt
controller. The interrupt controller routes the
enabled functional block interrupt to the INT1 or
INT2 pin.
0x2E CTRL_REG5 Interrupt Configuration register (Read/Write)
CTRL_REG5 register maps the desired interrupts to INT2 or INT1 pins.
The system’s interrupt controller, shown in Figure 9, uses the corresponding bit field in the CTRL_REG5 register to determine the
routing table for the INT1 and INT2 interrupt pins.
•
If the bit value is 0, then the functional block’s interrupt is routed to INT2.
•
If the bit value is 1, then the functional block’s interrupt is routed to INT1.
One or more functions can assert an interrupt pin; therefore a host application responding to an interrupt should read the
INT_SOURCE (0x0C) register, to determine the appropriate sources of the interrupt.
Table 67. 0x2E: CTRL_REG5 Interrupt Configuration register
Back to Register Address Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT_CFG_ASLP
—
—
INT_CFG_LNDPRT
—
INT_CFG_FF_MT
0
INT_CFG_DRDY
Table 68. 0x2E CTRL_REG5 register
Bit(s)
Field
Description
7
INT_CFG_ASLP
Auto-SLEEP/WAKE INT1/INT2 Configuration
6
—
Could be 0 or 1.
5
—
Could be 0 or 1.
4
INT_CFG_LNDPRT
Orientation INT1/INT2 Configuration
3
—
Could be 0 or 1.
2
INT_CFG_FF_MT
Freefall/motion INT1/INT2 Configuration
1
0
0
INT_CFG_DRDY
0 Interrupt is routed to INT2 pin (default)
1 Interrupt is routed to INT1 pin
Data Ready INT1/INT2 Configuration
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6.10
Data calibration registers
The 2’s complement offset correction registers values are used to realign the Zero-g position of the X, Y, and Z-axis after the
device is mounted on a board. The resolution of the offset registers is 1.96 mg/LSB. The 2’s complement 8-bit value would result
in an offset compensation range ±250 mg for each axis.
6.10.1
0x2F: OFF_X Offset Correction X register
Table 69. 0x2F OFF_X register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Back to Register Address Map
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 70. OFF_X register
Bit(s)
7–0
6.10.2
Field
D[7:0]
Description
X-axis offset value
0000_0000 (default)
0x30: OFF_Y Offset Correction Y register
Table 71. 0x30 OFF_Y register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Back to Register Address Map
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 72. OFF_Y register
Bit(s)
7–0
6.10.3
Field
D[7:0]
Description
Y-axis offset value
0000_0000 (default)
0x31: OFF_Z Offset Correction Z register
Table 73. 0x31 OFF_Z register (Read/Write)
Bit 7
D7
Bit 6
D6
Bit 5
D5
Back to Register Address Map
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
Table 74. OFF_Z register
Bit(s)
7–0
Field
D[7:0]
Description
Z-axis offset value
0000_0000 (default)
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7
Mounting Guidelines
Surface mount printed circuit board (PCB) layout is a critical portion of the total design. The footprint for the surface mount
packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the
correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and
mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package
after board mounting. The MMA865xFC digital output accelerometers use the DFN package platform. This section describes
suggested methods of soldering these devices to the PCB for consumer applications.
7.1
Overview of soldering considerations
Information provided here is based on experiments executed on DFN devices. They do not represent exact conditions present
at a customer site. Therefore, this information should be used as guidance only and process and design optimizations are
recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil
designs, the package will self-align during the solder reflow process.
7.2
Halogen content
This package is designed to be Halogen Free, exceeding most industry and customer standards. Halogen Free means that no
homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or
bromine (Br) in excess of 900 ppm or 0.09% weight/weight.
7.3
PCB mounting/soldering recommendations
1.
2.
3.
4.
5.
6.
7.
The PCB land should be designed as Non Solder Mask Defined (NSMD) as shown in Figure 16.
No additional via pattern underneath package.
PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 16.
Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm
Stencil opening = PCB land pad – 0.05 mm smaller all around = 0.55 mm x 0.175 mm.
Stencil thickness is 100 or 125 µm.
Do not place any components or vias at a distance less than 2 mm from the package land area. This may cause
additional package stress if it is too close to the package land area.
8. Signal traces connected to pads are as symmetric as possible. Put dummy traces on NC pads, to have same length of
exposed trace for all pads.
9. Use a standard pick and place process and equipment. Do not use a hand soldering process.
10. Use caution when putting an assembled PCB into an enclosure, noting where the screw-down holes are and if any
press-fitting is involved. It is important that the assembled PCB remain flat after assembly, to ensure optimal electronic
operation of the device.
11. The PCB should be rated for the multiple lead-free reflow condition with max 260°C temperature.
12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale
DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), having halide free molding compound
(green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper
(Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully
for soldering the devices.
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0.200
2x2 DFN Package
1.950
All measurements
are in mm.
0.225
0.725
0.600
2.525
PCB landing pad
Solder mask opening
Package outline
Figure 16. Package mounting measurements
Table 75. Board mounting guidelines
Description
Value (mm)
Landing Pad Width
0.225
Landing Pad Length
0.600
Solder Mask Pattern Width
0.725
Solder Mask Pattern Length
1.950
Landing Pad Extended Length
0.200
I/O Pads Extended Length
2.525
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8
Tape and Reel
8.1
Tape dimensions
Figure 17. Carrier tape
8.2
Device orientation
Reel
Pin 1 location
Carrier tape
User direction of feed
Sprocket holes
Cover tape
Figure 18. Device orientation on carrier tape
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9
Package Dimensions
This drawing is located at http://cache.freescale.com/files/shared/doc/package_info/98ASA00301D.pdf.
Figure 19. Case 98ASA00301D, 10-Lead DFN—page 1
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Figure 20. Case 98ASA00301D, 10-Lead DFN—page 2
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Figure 21. Case 98ASA00301D, 10-Lead DFN—page 3
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10
Revision History
Table 76. Revision history for MMA8653FC
Revision
number
Revision
date
0
08/2012
• Initial release.
1.0
02/2013
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.0
06/2014
• Section 1.2: Updated Descriptions for Pins 3 and 4.
• Section 6.9.2: Replaced contents of Table 64.
2.1
12/2014
• Section 6.74: Corrected value in paragraph following Table 46, was 0.63 to 0.063.
2.2
03/2015
• Section 5.8: Updated paragraph before Table 11.
Description of changes
Title and introductory text, changed 12-bit to 10-bit.
Feature comparison table: Orientation Detection features (2) rewritten for clarification.
Section 1: Topics reordered for clarification and consistency.
Table 4: Self-Test Output Change, x, y, and z specification values changed.
Tables 8, 9: Changed units to emg/LSB.
Section 5.5: Freefall detection rewritten for clarification.
Section 5.6 Orientation detection rewitten for clarification.
Section 6.4: FIFO-related content deleted.
Section 6.5.1: FIFO-related content deleted.
Table 19: bit field values deleted.
Section 6.7.4: rewritten for clarification.
Section 6.8.2: replaced Figure 32.
Table 32: FIFO-related content deleted.
Section 6.10.1: FIFO-related content deleted.
Note following Table 39: deleted as unnecessary.
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© 2015 Freescale Semiconductor, Inc.
Document Number: MMA8653FC
Rev. 2.2
03/2015