DESIGN INFORMATION Rail-to-Rail 14-Bit Dual DAC in a Space Saving 16-Pin SSOP Package by Hassan Malik Linear Technology introduces the LTC1654, a 14-bit rail-to-rail voltage output dual DAC in a space saving 16-pin SSOP package. This part offers a convenient solution for applications where density, resolution and power are critical parameters. The LTC1654 is guaranteed to be 14-bit monotonic over temperature with a typical differential nonlinearity of only 0.3LSB. The supply voltage range is 2.7V to 5.5V. The LTC1654 is software programmable for two different speed/power modes of operation: a FAST mode with 3.5µs settling time and 750µA supply current and a SLOW mode with 8µs settling time and 450µA supply current. Either of the two DACs can be independently set to the FAST or the SLOW mode of operation. The output amplifiers swing to within 450mV of either supply rail when sourcing or sinking 5mA and are capable of driving over 300pF of load capacitance. The output noise voltage density at 1kHz is 540nV/√Hz in SLOW mode and 320nV/√Hz in FAST mode. The LTC1654 has separate REFHI and REFLO pins for each DAC and two different gain modes. A gain of one is set by connecting the X1 /X1/2 pin to REFLO and a gain of one-half is set by connecting this pin to VOUT. The two different gain modes allow the user to set different output spans. The REFHI inputs have an operating range from ground to VCC and the REFLO inputs have an operating range from ground to VCC – 1.5V. A block diagram of the part is shown in Figure 1. The LTC1654 allows each of the DACs to be individually shut down, in which state they consume less than 4µA/DAC. The REFHI input goes into a high impedance state when the DAC is in shutdown. The respective speed states are retained in shutdown as long as the supply voltage is maintained above the minimum value of 2.7V. When the supply voltage is first applied, both DACs are active and in SLOW mode, with all zeros loaded in the input shift register and DAC latches. The LTC1654 has a double-buffered 3-wire serial interface consisting of clock, data and chip select pins. This interface is SPI/QSPI and continued on page 33 MICROWIRE is a trademark of National Semiconductor Corp. 2.7V TO 5.5V 16 5 CS/LD 3 SCK 4 SDI LTC1654 VCC REFHI B 14 VOUT B 15 CONTROL LOGIC µP INPUT LATCH DAC REGISTER + DAC B – 32-BIT SHIFT REGISTER INPUT LATCH VCC 7 SDO 2 CLR DAC REGISTER + DAC A X1/X1/2 B 1 REFHI A 10 VOUT A 9 X1/X1/2 A 8 – POWER-ON RESET DGND 6 REFLO B REFLO A 13 11 AGND 12 Figure 1. LTC1654 block diagram 28 Linear Technology Magazine • February 2001 DESIGN IDEAS In all cases, the adjustment range of trimmer circuits should be minimized, either by adjustment of the DAC output signal or by padding the varactor with series and parallel capacitance. This will reduce the phase noise contribution from the DAC and offset variation effects, as well as to minimize the harmonic distortion introduced by the varactor. The wideband noise of the LTC1662, as with any micropower DAC, is a potential pitfall in these applications, as it may degrade phase noise performance; however, the Figure 3a. Range of phase shift vs frequency for Figure 2b’s circuit LTC1662 has the virtue of very low 1/f noise. Bandwidth limiting the output to less than 1Hz will produce the benefit of low noise. If your application is not sensitive to low frequency phase noise, the output filters may not be necessary. Figure 3b. Maximum gain variation vs frequency for Figure 2b’s circuit 2.0 2.0 INL (LSB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 8192 16383 INPUT CODE Figure 2. LTC1654 typical integral nonlinearity (INL) LTC1654, continued from page 28 MICROWIRE™ compatible. The maximum clock rate is 33MHz. Double buffering allows individual load and update capability for each DAC. There are three different methods for loading data into the serial interface: a 24-bit word without daisy chaining, a 32-bit word without daisy chaining and a 32-bit word with daisy chaining. The 24-bit word loading method requires eight bits for control and address followed by sixteen bits of data. The last two LSBs in the 16-bit Linear Technology Magazine • February 2001 data segment are “don’t cares.” The 32-bit word loading method without daisy chaining requires eight “don’t cares” followed by eight bits for control and address and sixteen bits of data. The 32-bit word loading method with daisy chaining is the same as above except that the DOUT pin is used. When the REFHI pins are connected to VCC and the LTC1654 is configured for a gain of one, the voltage outputs swing from ground to VCC. The typical differential and integral nonlinearities are shown in Figures 2 and 3, respectively. VOUT is as follows for the two different gain configurations: Gain of one (X1 /X1/2 pin connected to REFLO): VOUT = (VREFHI – VREFLO) • (SDI/16384) + VREFLO where SDI is the decimal representation of the digital data input. Gain of one-half (X 1 /X 1/2 pin connected to VOUT ): 1.5 1.0 DNL (LSB) 1.5 0.5 0 –0.5 –1.0 –1.5 –2.0 0 8192 16383 INPUT CODE Figure 3. LTC1654 typical differential nonlinearity (DNL) VOUT = (1/2)(VREFHI – VREFLO) • (SDI/16384) + VREFLO In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V. Similarly, limiting can occur near full-scale when the REFHI pin is tied to VCC. This can be avoided by ensuring that VREFHI is less than VCC by at least 15mV or by using the gain of one-half configuration. 33