DESIGN INFORMATION Dual 60µA 10-Bit Serial DAC in MS-8 Saves Power and Space by Vic Schrader Introduction DACs; the data path is double buffered to allow for simultaneous updates. The digital inputs have internal Schmitt triggers, which eliminate the need for external Schmitts when the input signals are slow or noisy, such as when using optoisolators. The block diagram of the LTC1661 is shown in Figure 1. 3 2.9 VREF = VCC CODE = 512 2.8 VCC = 5.5V 2.7 VOUT (V) The LTC1661 is a dual, serially addressable 10-bit, rail-to-rail voltage output DAC with Sleep mode. Operating on a single 2.7V–5.5V supply rail, its small size and low power consumption make it most appropriate for use in products with stringent space and/or power constraints. In the 8-lead MSOP package, it occupies just 0.02in2 of board space, 50% less area than a standard SO-8 package; each buffered DAC draws just 60µA of supply current at 5V (48µA at 3V). Sleep mode operation further reduces total supply-plus-reference current to just 1µA. The LTC1661 has a reference-tooutput gain of one and the REF pin can be tied to VCC for ratiometric, 0Vto-VCC output without the use of a separate reference. Each of the output amplifiers is stable driving capacitive loads of up to 1000pF, so the designer need not be concerned with the capacitance of long board traces. The serial interface is SPI/ MICROWIRE™-compatible and uses a simple, flexible control word that allows the addressing of individual 2.6 VCC = 5V 2.5 2.4 2.3 VCC = 4.5V 2.2 2.1 SOURCE 2 Performance –30 –20 –10 Load Driving Despite its tiny operating current, the LTC1661 can deliver substantial load currents; Figure 2 shows output voltage vs load current performance. At VCC = 5V, the LTC1661 can drive over 20mA into a grounded load, the equivalent of driving a 250Ω load over the full 0V-to-VCC range. The output impedance is just 0.5Ω. The LTC1661 output amplifiers have been optimized for driving capacitive loads (see Figure 3). Capacitances of up to 1000pF, or greater than or equal to 10µF, may be driven directly; in between these values, a small resistor may be inserted Linearity The LTC1661 uses a patented architecture that guarantees monotonicity over the full industrial temperature range. Differential nonlinearity (DNL) is typically ±0.1LSB (±0.75 max) (see Figures 4 and 5). 5 LATCH VOUT B 6 LATCH VCC 7 LATCH GND LATCH 30 in series with the load to successfully drive any capacitance. The example in Figure 3 shows a 20Ω resistor placed in series with a 1µF load to stabilize the combination. 8 CONTROL LOGIC 20 Figure 2. The LTC1661 drives over 20mA into a grounded load at 5V VOUT A 10-BIT DAC A SINK 0 10 IOUT (mA) 10-BIT DAC B ADDRESS DECODER SHIFT REGISTER 1 2 3 4 CS/LD SCK DIN REF Figure 1. LTC1661 block diagram: each DAC draws just 60µA at 5V. Double-buffered input logic allows simultaneous updates. 26 Linear Technology Magazine • November 2000 DESIGN INFORMATION Operation Serial Interface 20Ω 1/2 LTC1661 The simple-yet-flexible SPI/MICROWIRE-compatible interface uses a 16-bit input word, which is divided into Control and Data sections (see Figure 6). The Control section of the word specifies the desired operation and selects one or both DACs to receive the instruction, whereas the Data section specifies the DAC input code. Data is captured on the rising edge of the clock with CS/LD held at a logic low. Once the full 16-bit word has been captured, the rising edge of CS/LD executes the instruction. OR C ≤ 1000pF OR C ≥ 10µF 1µF Figure 3. Allowable capacitive loads; the rail-to-rail output amplifiers have been optimized for driving capacitance. 2.0 0.75 0.60 Conclusion Low supply current, power-saving Sleep mode and extremely compact size make the LTC1661 ideal for battery-powered devices, while its ease of use, high performance and wide supply range make it an excellent choice for a wide spectrum of voltage adjustment and trimmer potentiometer applications. 1.0 0.40 0.5 0.20 LSB LSB 1.5 0 0 –0.5 –0.20 –1.0 –0.40 –1.5 –0.60 –2.0 0 256 512 CODE 768 –0.75 1023 0 Figure 4. LTC1661 integral nonlinearity (INL) 256 512 CODE 768 1023 Figure 5. LTC1661 differential nonlinearity; patented architecture guarantees monotonicity MICROWIRE is a trademark of National Semiconductor Corp. SCK DIN 1 A3 2 A2 3 A1 CONTROL CODE 4 A0 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 11 D3 12 D2 INPUT CODE 13 D1 14 D0 15 X1 16 X0 DON’T CARE INPUT WORD W0 CS/LD (LTC1661 RESPONDS) (SCK ENABLED) Figure 6. The simple 3-wire interface is used for software control of the individual DAC channels. Loading of input codes, updates and Sleep mode control are all available. http://www.linear-tech.com/ezone/zone.html Articles, Design Ideas, Tips from the Lab… Linear Technology Magazine • November 2000 27