DS2568 02

®
RT2568
DDR Termination Regulator
General Description
Features
The RT2568 is a sink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count systems. The RT2568 possesses a high
speed operating amplifier that provides fast load transient
response and only requires a minimum 10μF x 3 ceramic
output capacitor. The RT2568 supports remote sensing
functions and all features required to power the DDRIII
and Low Power DDRIII / DDRIV VTT bus termination
according to the JEDEC specification. In addition, the
RT2568 provides an open-drain PGOOD signal to monitor
the output regulation and an EN signal that can be used
to discharge VTT during S3 (suspend to RAM) for DDR
applications.

VIN Input Voltage Range: 1.1V to 3.5V

VCNTL Input Voltage Range: 2.9V to 5.5V
Support Ceramic Capacitors
Power Good Indicator
10mA Source/Sink Reference Output
Meet DDRI, DDRII JEDEC Spec
Support DDRIII, Low Power DDRIII/DDRIV VTT
Applications
Soft-Start Function
UVLO and OCP Protection
Thermal Shutdown
The RT2568 is available in the thermal efficient package,
WDFN-10L 3x3.

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Applications

Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV, Copier/Printer, Set-Top Box
Marking Information
5W= : Product Code
5W=YM
DNN
YMDNN : Date Code
Simplified Application Circuit
RT2568
VIN
VIN
VCNTL
R1
R3
REFIN
C1
PGOOD
C2
R2
VCNTL
C4
Power Good Indicator
VOUT
SENSE
REFOUT
REFOUT
C3
EN
EN
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DS2568-02 August 2015
VOUT
C5
PGND
GND
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RT2568
Ordering Information
Pin Configurations
RT2568
Package Type
QW : WDFN-10L 3x3 (W-Type)
REFIN
VIN
VOUT
PGND
SENSE
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :

1
2
3
4
5
GND
(TOP VIEW)
11
10
9
8
7
6
VCNTL
PGOOD
GND
EN
REFOUT
WDFN-10L 3x3
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
REFIN
Reference Input.
2
VIN
Power Input of the Regulator.
3
VOUT
Power Output of the Regulator.
4
PGND
Power Ground of the Regulator.
5
SENSE
Voltage Sense Input for the Regulator. Connect to positive terminal of the
output capacitor or the load.
6
REFOUT
Reference Output. Connect to GND through a 0.1F ceramic capacitor.
7
EN
Enable Control Input. For DDR VTT application, connect EN to SLP_S3. For
other applications, use EN as the ON/OFF function.
9
PGOOD
Power Good Open-Drain Output. Connect a pull-up resistor between this pin
and VCNTL pin.
10
VCNTL
Control Voltage Input. Connect this pin to the 3.3V or 5V power supply. A
ceramic decoupling capacitor with a value 4.7F is required.
8,
GND
11 (Exposed Pad)
Analog Ground. Connect to negative terminal of the output capacitor. The
exposed pad must be soldered to a large PCB and connected to GND for
maximum power dissipation.
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DS2568-02 August 2015
RT2568
Function Block Diagram
EN VCNTL
REFIN
Control
Logic
Thermal
Protection
Buffer
VIN
+
OCP
-
REFOUT
VOUT
SENSE
OP
+
PGOOD
Power
Good
Driver
+
OCP
-
GND
PGND
Operation
The RT2568 is a linear sink/source DDR termination
regulator with current capability up to 3A. The RT2568
builds in a high-side N-MOSFET which provides current
sourcing and a low-side N-MOSFET which provides current
sinking. All the control circuits are supplied by the power
VCNTL. In normal operation, the error amplifier OP adjusts
the gate driving voltage of the power MOSFET to achieve
SENSE voltage well tracking the REFIN voltage.
Both the source and sink currents are detected by the
internal sensing resistor, and the OCP function will work
to limit the current to a designed value when overload
happens. Furthermore, the current will be folded back to
be one half if VOUT is out of the power good window.
Buffer
This function provides REFOUT output equal to REFIN
with 10mA source/sink current capability.
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DS2568-02 August 2015
Power Good
When the SENSE voltage is in the power good window
and lasts for a certain delay time, then the PGOOD pin
will be high impedance and the PGOOD voltage will be
pulled high by the external resistor.
Control Logic
This block includes VCNTL UVLO, REFIN UVLO and
Enable/Disable functions, and provides logic control to
the whole chip.
Thermal Protection
Both the high-side and low-side power MOSFETs will be
turned off when the junction temperature is higher than
typically 160°C, and be released to normal operation when
junction temperature falls below 120°C typically.
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RT2568
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------Input Voltage, EN, REFIN, SENSE ----------------------------------------------------------------------------------Output Voltage, VOUT, REFOUT, PGOOD -------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------CDM (Charged Device Model) ------------------------------------------------------------------------------------------
Recommended Operating Conditions



−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
2.5W
40°C/W
7.5°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
2kV
(Note 4)
Control Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.9V to 5.5V
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 1.1V to 3.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VIN = 1.5V, VEN = VCNTL = 3.3V, VREFIN = VSENSE = 0.75V, COUT = 10μF x 3, TA = −40°C to 85°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VEN = VCNTL, No Load
--
0.7
1
mA
VEN = 0V, VREFIN = 0V, No Load
--
65
80
VEN = 0V, VREFIN > 0.4V, No Load
--
200
400
Supply Current
VCNTL Supply Current
IVCNTL
VCNTL Shutdown Current
ISHDN_VCNTL
VIN Supply Current
IVIN
VEN = VCNTL, No Load
--
1
50
A
VIN Shutdown Current
ISHDN_VIN
VEN = 0V, No Load
--
0.1
50
A
VIN = 1.5V, VREFIN = 0.75V,
IOUT = 0A
--
0.75
--
VIN = 1.35V, VREFIN = 0.675V,
IOUT = 0A
--
0.675
--
VIN = 1.2V, VREFIN = 0.6V,
IOUT = 0A
--
0.6
--
IOUT < ±2A, VLDOIN = 1.5V,
VOUT_OS = VOUT  VOUTO
25
--
25
IOUT < ±2A, VLDOIN = 1.35V,
VOUT_OS = VOUT  VOUTO
25
--
25
IOUT < ±2A, VLDOIN = 1.2V,
VOUT_OS = VOUT  VOUTO
25
--
25
A
Output
VTT Output Voltage
VTT Output Voltage Offset
VOUTO
VOUT_OS
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V
mV
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DS2568-02 August 2015
RT2568
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VOUT Source Current Limit ILIM_VOUT_SR
VOUT in PGOOD Window
3
4.5
--
A
VOUT Sink Current Limit
ILIM_VOUT_SK
VOUT in PGOOD Window
3
4.5
--
A
VOUT Discharge
Resistance
RDISCHARGE
VREFIN = 0V, VOUT = 0.3V,
VEN = 0V
--
18
25

VSENSE lower threshold with
respect to REFOUT
--
20
--
VSENSE upper threshold with
respect to REFOUT
--
20
--
PGOOD Hysteresis
--
5
--
Power Good Comparator
PGOOD Threshold
VTH_PGOOD
%
PGOOD Start-Up Delay
TPGDELAY1
Start-up rising delay, VSENSE
within PGOOD range
--
2
--
ms
Output Low Voltage
VLOW_PGOOD
IPGOOD = 4mA
--
--
0.4
V
PGOOD Falling Delay
TPGDELAY2
Falling delay, VSENSE is out of
PGOOD range
--
10
--
s
Leakage Current
VSENSE = VREFIN (PGOOD high
ILEAKAGE _PGOOD impedance),
VPGOOD = VCNTL + 0.2V
--
--
1
A
REFIN Input Current
IREFIN
--
--
1
A
REFIN Voltage Range
VREFIN
0.5
--
1.8
V
REFIN Under-Voltage
Lockout
VUVLO_REFIN
360
390
420
--
20
--
10mA < IREFOUT < 10mA,
VREFIN = 0.75V
15
--
15
10mA < IREFOUT < 10mA,
VREFIN = 0.675V
15
--
15
10mA < IREFOUT < 10mA,
VREFIN = 0.6V
15
--
15
VREFOUT = 0V
10
40
--
mA
VREFOUT = REFIN + 1V
10
40
--
mA
Rising
2.5
2.7
2.85
V
--
120
--
mV
REFIN and REFOUT
REFOUT Voltage Tolerance
VTOL_REFOUT
to VREFIN
REFOUT Source Current
ILIM_REFOUT_SR
Limit
REFOUT Sink Current Limit ILIM_REFOUT_SK
VEN = VCNTL
REFIN Rising
Hysteresis
mV
mV
UVLO/EN
UVLO Threshold
EN Input
Voltage
VUVLO_VCNTL
Hysteresis
Logic-High
VIN_H
1.7
--
--
Logic-Low
VIN_L
--
--
0.3
--
160
--
--
15
--
V
Thermal Shutdown
Thermal Shutdown
Threshold
TSD
Shutdown Temperature
Hysteresis
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DS2568-02 August 2015
(Note 5)
(Note 5)
°C
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RT2568
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
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RT2568
Typical Application Circuit
RT2568
VIN
2
R1
10k
C1
10µF x 2
REFOUT
1
EN
7
PGOOD
REFOUT
EN
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DS2568-02 August 2015
VCNTL
10
REFIN
C2
1nF
R2
10k
6
C3
0.1µF
VIN
9
VOUT 3
SENSE 5
4
PGND
GND
R3
100k
C4
4.7µF
VCNTL
Power Good Indicator
C5
10µF x 3
VOUT
8, 11 (Exposed Pad)
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RT2568
Typical Operating Characteristics
REFOUT Voltage vs. Temperature
1.0
0.9
0.9
REFOUT Voltage (V)
Output Voltage (V)
Output Voltage vs. Temperature
1.0
0.8
0.7
0.6
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
0.5
-50
-25
0
25
50
75
100
0.8
0.7
0.6
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
0.5
125
-50
-25
0
Temperature (°C)
50
75
100
125
VCNTL Shutdown Current vs. Temperature
VCNTL Supply Current vs. Temperature
500.0
350
480.0
460.0
440.0
VCNTL = 5V
420.0
400.0
380.0
360.0
VCNTL = 3.3V
340.0
320.0
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
300.0
-50
-25
0
25
50
75
100
VCNTL Shutdown Current (μA)1
VCNTL Supply Current (μA)1
25
Temperature (°C)
300
250
VCNTL = 5V
200
VCNTL = 3.3V
150
100
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
50
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
UVLO vs. Temperature
Sourcing Current Limit vs. Temperature
3.0
4.0
2.9
3.5
2.8
UVLO (V)
2.7
Current Limit (A)
Rising
2.6
2.5
Falling
2.4
2.3
2.2
VIN = VDDQSNS = 1.5V,
VEN = 2V, VOUT = 0.75V
2.1
2.0
-50
-25
0
25
50
75
100
Temperature (°C)
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125
3.0
2.5
2.0
1.5
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
1.0
-50
-25
0
25
50
75
100
125
Temperature (°C)
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DS2568-02 August 2015
RT2568
Power On from EN
Sinking Current Limit vs. Temperature
4.0
VEN
(2V/Div)
Current Limit (A)
3.5
3.0
VOUT
(0.5V/Div)
2.5
2.0
IOUT
(1A/Div)
1.5
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VREFOUT
(1V/Div)
1.0
-50
-25
0
25
50
75
100
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
Time (100μs/Div)
125
Temperature (°C)
0.75VOUT @ 1.5A Transient Response
Power Off from EN
VEN
(2V/Div)
VOUT
(10mV/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
VREFOUT
(1V/Div)
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
IOUT
(1A/Div)
Source, VIN = 1.5V
Time (500μs/Div)
Time (10μs/Div)
0.75VOUT @ 1.5A Transient Response
VOUT
(10mV/Div)
IOUT
(1A/Div)
Sink, VIN = 1.5V
Time (500μs/Div)
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RT2568
Application Information
Capacitor Selection
Good bypassing is recommended from VLDOIN to GND
to help improve AC performance. A 10μF or greater input
capacitor located as close as possible to the IC is
recommended. The input capacitor must be located at a
distance of less than 0.5 inches from the VLDOIN pin of
the IC.
Adding a 1μF ceramic capacitor close to the VIN pin and
it should be kept away from any parasitic impedance from
the supply power. For stable operation, the total
capacitance of the ceramic capacitor at the VTT output
terminal must be larger than 30μF. The RT2568 is designed
specifically to work with low ESR ceramic output capacitor
in space saving and performance consideration. Larger
output capacitance can reduce the noise and improve load
transient response, stability and PSRR. The output
capacitor should be located near the VTT output terminal
pin as close as possible.
WDFN-10L 3x3 package, the thermal resistance, θJA, is
40°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (40°C/W) = 2.5W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.0
Maximum Power Dissipation (W)1
The RT2568 is a 3.5A sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count system such as notebook PC
applications. The RT2568 possesses a high speed
operating amplifier that provides fast load transient response
and only requires two 10μF ceramic input capacitors and
three 10μF ceramic output capacitors.
Four-Layer PCB
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
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RT2568
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS2568-02 August 2015
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