A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR FEATURES AND BENEFITS • • • • • • • • • • • • • • • • Automotive AEC-Q100 qualified VIN operating range from 3 to 36 V, with 40 V maximum Buck or buck-boost pre-regulator (VREG) Adjustable PWM switching frequency: 250 kHz to 2.4 MHz PWM frequency can be synchronized to external clock Two 5 V internal LDO regulators with foldback shortcircuit protection Power-on reset (NPOR) with fixed delay of 22.5 ms Programmable window watchdog timer with a fixed activation delay of 30 ms Active low, watchdog timer enable/disable pin (WDENn) Dual bandgaps for increased reliability: □□ BG1 for VREG, 5V0, and VCP reference □□ BG2 for V5 reference, and VREG, 5V0, and VCP fault detection Ignition-enable input (ENBAT) Frequency dithering helps reduce EMI/EMC Undervoltage protection for all output rails Pin-to-pin and pin-to-ground tolerant at every pin Thermal shutdown protection −40ºC to 150ºC junction temperature range DESCRIPTION The A4409 is a power management IC that uses a buck or buck-boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage, complete with control, diagnostics, and protections. The output of the pre-regulator supplies a 5 V, 300 mAMIN LDO and a 5 V, 200 mAMIN LDO. Designed to supply CAN or microprocessor power supplies in high-temperature environments, the A4409 is ideal for underhood applications. Enable-input to the A4409 is compatible to a high-voltage battery level (ENBAT). Diagnostic outputs from the A4409 include a power-on-reset output (NPOR) with a fixed 22.5 ms typical delay. Dual bandgaps, one for regulation and one for fault checking, improve long-term reliability of a system designed around the A4409. The A4409 contains a window watchdog timer that can be programmed to accept a wide range of clock frequencies (WDADJ). The watchdog timer has a fixed 30 ms activation delay to accommodate processor startup. The watchdog timer has an enable/disable pin (active low, WDENn) to facilitate initial factory programming or field reflash programming. Continued on next page... PACKAGE: 20-Pin eTSSOP (suffix LP) APPLICATIONS Provides System Power for (µC/DSP, CAN, sensors, etc.) in Automototive Control Modules, such as: • • • • • Not to scale 5 V LDO (V5) with Foldback Protection 6.6 V (VREG) Buck-Boost Pre-Regulator Bandgap 1 Bandgap 2 Electronic Power Steering (EPS) Transmission Control Units (TCU) Advanced Braking Systems (ABS) Emissions Control Modules Other automotive applications Charge Pump Thermal Shutdown (TSD) NPOR Output A4409 Simplified Block Diagram A4409-DS, Rev. 3 5 V LDO (5V0) with Foldback Protection Programmable Window Watchdog Timer with Activation Delay Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 DESCRIPTION (continued) Protection features include dual control loop for pre-regulator rail. In case of a shorted output, all linear regulators feature foldback overcurrent protection. The switching regulator includes pulseby-pulse current limit, hiccup mode short-circuit protection, LX short-circuit protection, missing asynchronous diode protection, and thermal shutdown. The A4409 is supplied in a low-profile (1.2 mm maximum height), 20-lead eTSSOP package (suffix “LP”) with exposed thermal pad. SELECTION GUIDE 1 Part Number Temp. Range Package Packing1 Lead Frame A4409KLPTR-T –40°C to 150°C 20-pin eTSSOP with thermal pad 4000 pieces per 13-in. reel 100% Matte Tin Contact Allegro for additional packing options. SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 1 Characteristic Symbol VIN pin Notes VIN VENBAT ENBAT pin With current limiting resistor2 IENBAT LX pin VLX t < 250 ns t < 50 ns Rating Unit −0.3 to 40 V −0.3 to 8 V −13 to 40 V ±75 mA −0.3 to VIN + 0.3 V −1.5 V VIN + 3 V VVCP, VCPx −0.3 to 50 V −0.3 to 7.5 V Junction Temperature TJ −40 to 150 ºC Storage Temperature Range TS −55 to 150 ºC VCP, CP1, and CP2 pins All other pins Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The higher ENBAT ratings (-13 V and 40 V) are measured at node “A” in the following circuit configuration: 1 Node “A” ≥450 Ω ENBAT + A4409 VENBAT - GND THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Junction-to-Ambient Thermal Resistance Symbol RθJC Test Conditions* eTSSOP-20 (LP) Package Value Unit 32 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 1 µF VBAT CP2 CP1 VCP 2.2 µF VREG DIN VIN 0.1 µF 0603 50-100 µF 50 V KEY_SW BG1_UV BG1 BG1 BG2 2 × 4.7 µF 50 V 1210 LDO EN BG2 BG2 17.4 kΩ OSC2 3.3 nF CLK @ fOSC 100 nA SYNC (optional) CLK1MHz BUCK-BOOST PRE-REGULATOR (VREG) WITH HICCUP MODE BG1 VREG ON VCP UV VREG_OV BG1_UV BG2_UV VIN_UV VCP OV *D1MISSING *ILX(LIM) 5V0 SS OK MASTER IC POR 1Ω tSS VLDO NPOR TIMING FOLDBACK 2.2 µF 5V LDO WDSTART 5V 300 mA 5V0 2.2 µF FOLDBACK WDFAULT 5V0 UV *D1MISSING *ILX(LIM) ON 5V LDO BG2 LDOs ON EN STARTUP / SHUTDOWN SEQUENCE MPOR 5V0 UV VREG_OK 4 × 10 µF 16 V / X7R / 1206 2 kΩ SOFT START BG1 NPOR 6.6 V 250 mA VREG MPOR NPOR Q1 LG FB1 TSD * indicates a latched fault CLK1MHz D2 LX CONNECT LG TO VCC FOR BUCK ONLY MODE FB2 8.66 kΩ REMOVE D2 AND Q1 FOR BUCK ONLY MODE D1 STOP PWM OSC1 FSET/SYNC L1 6.8 µH ≤ 60 mΩTYP 75 mΩ BG2 10 pF 0.1 µA COMP COMP 1 µF CHARGE PUMP BG2_UV BG1 VCC VCP UV/OV 5V 200 mA V5 2.2 µF VREG ON BG2 LDOs ON 5V0 UV 5V0 UV DEGLITCH td(FILT) 5V0 3.3 kΩ ENBAT + 650 kΩ 0.1 µF WD OSC WDADJ CLKIN WDIN WDENn WDENn 13 kΩ tWDTO(SLOW) = 4 ms tWDTO(FAST) = 0.5 ms 3.3 VTYP 2.6 VTYP – ON FALLING DELAY td(off)LDO EN GND WDCLK WDENn = 0 or OPEN enables WD 60 kΩ DEGLITCH td(ENBAT,FILT) WINDOW WATCHDOG TIMER (WWDT) PGND CLK1MHz ONE SHOT tWD(FAULT) WDFAULT WDSTART A4409 Functional Block Diagram / Typical Schematic Buck-Boost Mode (fOSC = 2 MHz) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 VCP 1 20 CP2 VIN 2 19 CP1 ENBAT 3 18 LX GND 4 17 PGND VCC 5 16 LG PAD COMP 6 15 VREG FSET/SYNC 7 14 VLDO NPOR 8 13 WDADJ WDENn 9 12 V5 WDIN 10 11 5V0 Package LP, 20-Pin eTSSOP Pinout Diagram Terminal List Table Number Name Function 1 VCP Charge pump reservoir capacitor 2 VIN Input voltage 3 ENBAT 4 GND Ignition-enable input from the key/switch through a 1 kΩ resistor Ground 5 VCC 6 COMP Error amplifier compensation network pin for the buck-boost pre-regulator Internal voltage regulator bypass capacitor pin 7 FSET/ SYNC Frequency setting and synchronization input 8 NPOR Active low, open-drain regulator fault detection output 9 WDENn Watchdog enable pin: Open/Low – WD is enabled, High – WD is disabled 10 WDIN 11 5V0 Watchdog refresh input (rising edge triggered) from a microcontroller or DSP 5 V, 300 mA regulator output 12 V5 13 WDADJ The watchdog window time is programmed by connecting RADJ from this pin to ground 5 V, 200 mA regulator output 14 VLDO Input for the LDOs 15 VREG Feeback pin for VREG output, connect to VREG converter output capacitors 16 LG 17 PGND 18 LX 19 CP1 Charge pump capacitor connection 20 CP2 Charge pump capacitor connection – PAD Boost gate drive output for the buck-boost pre-regulator Power ground Switching node for the buck-boost pre-regulator Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 ELECTRICAL CHARACTERISTICS – GENERAL SPECIFICATIONS1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit After VIN > VIN(START), VENBAT ≥ 4 V, buck-boost pre-regulator 3 13.5 36 V 5.5 13.5 36 V − 5 V GENERAL SPECIFICATIONS Operating Input Voltage VIN After VIN > VIN(START), VENBAT ≥ 4 V, buck preregulator VIN UVLO Start VIN(START) VIN rising − VIN UVLO Stop VIN(STOP) Supply Quiescent Current1 VIN falling, when in buck-boost mode − − 2.9 V IQ VIN = 13.5 V, VENBAT ≥ 4 V, no load on VREG – 10 – mA IQ(SLEEP) VIN = 13.5 V, VENBAT ≤ 2 V, no load on VREG – – 10 µA PWM SWITCHING FREQUENCY AND DITHERING Switching Frequency Frequency Divide By 2 fOSC RFSET = 8.66 kΩ 1.8 2 2.2 MHz RFSET = 57.6 kΩ 343 400 457 kHz V Start2 VIN(FREQ/2,START) VIN rising, frequency = fOSC/2 18 19 20 Frequency Divide By 2 Stop2 VIN(FREQ/2,STOP) VIN falling, frequency = fOSC/2 17 18 19 V As a percent of fOSC – ±12 – % Frequency Dithering ΔfOSC VIN Dithering START Threshold VIN(DITHER,ON) VIN Dithering STOP Threshold VIN(DITHER,OFF) VIN Dithering Hysteresis VIN(DITHER,HYS) Low range, VIN rising 9 9.5 10 V High range, VIN falling 17 18 19 V Low range, VIN falling 8.5 9 9.5 V High range, VIN rising 18 19 20 V – 500 – mV 4.1 6.6 – V – 65 – kHz – 4.6 – V 160 170 180 ºC – 20 – ºC CHARGE PUMP (VCP) Output Voltage ΔVVCP Switching Frequency fSW(CP) VVCP – VIN VCC OUTPUT Output Voltage VVCC VVREG = 6.6 V Thermal Shutdown Threshold2 TTSD TJ rising Thermal Shutdown Hysteresis2 THYS THERMAL PROTECTION 1 2 Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VIN = 13.5 V, ENBAT = 1, 0.1 A ≤ IVREG ≤ 1 A 6.47 6.6 6.7 V VREG pin open, measured at VLDO pin, VIN = 13.5 V, ENBAT = 1, 0.1 A ≤ IVREG ≤ 1 A 5.88 6 6.12 V OUTPUT VOLTAGE SPECIFICATIONS Pre-Regulator Output Voltage – VREG Regulating VVREG Pre-Regulator Output Voltage – VLDO Regulating VVLDO(REG) PULSE WIDTH MODULATION (PWM) PWM Ramp Offset VPWMOFFSET VCOMP for 0% duty cycle – 400 – mV LX Rising Slew Rate2 SRLX(RISE) VIN = 13.5 V, 10% to 90%, IVREG = 1 A – 1.7 – V/ns LX Falling Slew Rate2 SRLX(FALL) VIN = 13.5 V, 10% to 90%, IVREG = 1 A – 1.5 – V/ns Buck Minimum On-Time2 Buck Minimum Off-Time Buck Maximum Duty Cycle tON(BUCK,MIN) – 85 160 ns tOFF(BUCK,MIN) – 0 – ns DBUCK(MAX) – 100 – % Boost Minimum On-Time tON(BOOST,MIN) – 60 120 ns Boost Maximum Duty Cycle DBOOST(MAX) – 70 – % – 4.5 – A/V COMP to LX Current Gain Slope Compensation2 VIN = 3.5 V gm(POWER) SE fOSC = 2 MHz 3.84 4.8 5.76 A/µs fOSC = 400 kHz 0.76 0.96 1.16 A/µs INTERNAL MOSFET VIN = 13.5 V, TJ = ‒40°C 2, IDS = 0.1 A – 60 75 mΩ VIN = 13.5 V, TJ = 25°C 2, IDS = 0.1 A – 80 100 mΩ VIN = 13.5 V, TJ = 150°C, IDS = 0.1 A – 140 170 mΩ VENBAT ≤ 2 V, VLX = 0 V, VIN = 13.5 V, −40°C ≤ TJ ≤ 85°C 2 – – 10 µA VENBAT ≤ 2 V, VLX = 0 V, VIN = 13.5 V, −40°C ≤ TJ ≤ 125°C 2 – – 100 µA VENBAT ≤ 2 V, VLX = 0 V, VIN = 13.5 V, −40°C ≤ TJ ≤ 150°C – 50 150 µA AVOL – 65 – dB Transconductance gm(EA) 550 750 950 µA/V Output Current IO(EA) – ±75 – µA Maximum Output Voltage VO(EA,MAX) 1.3 1.7 2.1 V Minimum Output Voltage VO(EA,MIN) – – 200 mV – 1 – kΩ MOSFET On Resistance MOSFET Leakage RDS(on) IFET(LEAK) ERROR AMPLIFIER Open Loop Voltage Gain COMP Pull-Down Resistance 1 2 RCOMP HICCUP = 1 or FAULT = 1 or IC disabled Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS – BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS (continued)1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 4.6 – 6.35 V BOOST MOSFET (LG) GATE DRIVER LG High Output Voltage VLG(ON) VIN = 7 V, VVREG = 6.35 V LG Low Output Voltage VLG(OFF) VIN = 13.5 V, VVREG = 6.85 V – 0.2 0.4 V LG Source Current1 ILG(ON) VIN = 7 V, VVREG = 6.35 V, VLG = 1 V – –500 – mA LG Sink Current1 ILG(OFF) VIN = 13.5 V, VVREG = 6.85 V, VLG = 1 V – 500 – mA ILG(LEAK) VIN = 13.5 V, VVREG = 6.6 V, VLG = 3 V – – 10 µA LG Leakage Current2 SOFT START SS Ramp Time SS PWM Frequency Foldback tSS(ramp) fSW(SS) – 1 – ms 0 V ≤ VVREG ≤ 3.3 V, VCOMP = VO(EA,MAX) – fOSC/8 – – 0 V ≤ VVREG ≤ 3.3 V – fOSC/2 – – VVREG > 3.3 V – fOSC – – VVREG < 2.4 V (typical), VCOMP = VO(EA,MAX) – 15 – PWM cycles VVREG > 2.4 V (typical), VCOMP = VO(EA,MAX) – 60 – PWM cycles LX switching stops to LX switching starts, during VREG overcurrent – 2 – ms HICCUP MODE Hiccup OCP PWM Counts Hiccup Mode Recovery Time tHIC(OCP) trec(HIC) CURRENT PROTECTIONS Pulse-by-Pulse Current Limit ILIM 3.6 4.1 4.6 A LX Short-Circuit Current Limit ILIM(LX) 6 7 – A MISSING ASYNCHRONOUS DIODE (D1) PROTECTION Detection Level VD(OPEN) −1.5 −1.3 −0.9 V Time Filtering2 tD(OPEN) 50 – 250 ns 1 2 Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS – LINEAR REGULATOR (LDO) SPECIFICATIONS 1: Valid at 3 V ≤ VIN ≤ 36 V in buckboost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit 10 mA ≤ IV5 ≤ 200 mA, VVREG = 5.4 V 4.9 5 5.1 V IV5 = 200 mA, VVLDO = 4.91 V 4.75 – – V 1 – 22 µF V5 LINEAR REGULATOR V5 Accuracy and Load Regulation V5 Dropout V5 Output Capacitance Range2 VV5 VV5(DROPOUT) CV5(OUT) V5 OVERCURRENT PROTECTION V5 Current Limit1 IV5(LIM) VV5 = 5 V −230 −325 – mA V5 Foldback Current1 IV5(FB) VV5 = 0 V −80 −120 −160 mA – 0.24 1 ms 10 mA ≤ I5V0 ≤ 300 mA, VVREG = 5.4 V 4.9 5 5.1 V I5V0 = 300 mA, VVLDO = 4.91 V 4.75 – – V 1 – 22 µF V5 STARTUP V5 Startup Time2 tV5(START) CV5 ≤ 2.9 µF, load = 25 Ω ±5% (200 mA) 5V0 LINEAR REGULATOR 5V0 Accuracy and Load Regulation 5V0 Dropout 5V0 Output Capacitance Range2 V5V0 V5V0(DROPOUT) C5V0(OUT) 5V0 OVERCURRENT PROTECTION 5V0 Current Limit1 I5V0(LIM) V5V0 = 5 V −345 −485 – mA 5V0 Foldback Current1 I5V0(FB) V5V0 = 0 V −100 −165 −230 mA – 0.24 1 ms 5V0 STARTUP 5V0 Startup Time2 1 2 t5V0(START) C5V0 ≤ 2.9 µF, load = 20 Ω ±5% (250 mA) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS – CONTROL INPUTS 1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit IGNITION-ENABLE (ENBAT) INPUT ENBAT Thresholds ENBAT Hysteresis ENBAT Bias Current1 ENBAT Resistance VENBAT(H) VENBAT rising 2.8 3.2 3.5 V VENBAT(L) VENBAT falling 2.1 2.5 2.8 V VENBAT(H) – VENBAT(L) – 700 – mV TJ = 25°C 2, VENBAT = 3.51 V – 28 45 µA TJ = 150°C, VENBAT = 3.51 V VENBAT(HYS) IIB(ENBAT) – 35 60 µA RENBAT – 650 – kΩ td(ENBAT,FILT) 10 15 20 µs Measure td(off)LDO from the falling edge of ENBAT to the time when all LDOs begin to decay 15 50 100 µs No external SYNC signal – 800 – mV – 3 – µs – 3 – µs ENBAT DEGLITCH Enable Filter/Deglitch Time ENBAT SHUTDOWN DELAY LDO Shutdown Delay td(off)LDO FSET/SYNC INPUT FSET/SYNC Pin Voltage VFSET/SYNC FSET/SYNC Open Circuit (Undercurrent) Detection Time tFSET/SYNC(UC) PWM switching frequency becomes 900 kHz upon detection FSET/SYNC Short-Circuit (Overcurrent) Detection Time tFSET/SYNC(OC) PWM switching frequency becomes 900 kHz disabled upon detection Sync. High Threshold VSYNC(H) VSYNC rising – – 2 V Sync. Low Threshold VSYNC(L) VSYNC falling 0.5 – – V Sync. Input Duty Cycle DSYNC – – 80 % Sync. Input Pulse Width tPW(SYNC) 200 – – ns tT(SYNC) – 10 15 ns Sync. Input Transition Times 2 1 2 Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit NPOR UNDERVOLTAGE PROTECTION THRESHOLDS 5V0 Undervoltage Thresholds 5V0 Undervoltage Hysteresis V5V0(UV,H) V5V0 rising – 4.665 – V V5V0(UV,L) V5V0 falling 4.5 4.625 4.75 V V5V0(UV,H) – V5V0(UV,L) 20 40 60 mV V5V0(UV,HYS) NPOR TURN-ON AND TURN-OFF DELAYS NPOR Turn-On Delay NPOR Turn-Off Propagation Delay td(on)NPOR td(off)NPOR 18 22.5 27 ms ENBAT low to NPOR low, measured after ENBAT deglitch time td(ENBAT,FILT) – – 3 µs NPOR OUTPUT VOLTAGES NPOR Output Low Voltage NPOR Leakage Current1 VNPOR(L) INPOR(LEAK) ENBAT high, VIN ≥ 2.5 V, INPOR = 4 mA – 150 400 mV ENBAT high, VIN = 1.5 V, INPOR = 2 mA – – 800 mV VNPOR = 3.3 V – – 2 µA Applies to undervoltage of the 5V0 voltage 10 15 20 µs NPOR UNDERVOLTAGE FILTERING/DEGLITCH NPOR Undervoltage Filter/Deglitch Times 1 td(NPOR,FILT) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS – DIAGNOSTIC OUTPUTS (continued)1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VVREG rising, PWM disabled 6.8 6.93 7.18 V – 100 – mV VVREG(UV,H) VVREG rising 4.16 4.41 4.64 V VVREG(UV,L) VVREG falling – 4.3 – V VREG, VCP, AND BG THRESHOLDS VREG Overvoltage Threshold VVREG(OV,H) VREG Overvoltage Hysteresis VVREG(OV,HYS) VREG Undervoltage Thresholds VREG Undervoltage Hysteresis VCP Overvoltage Threshold VCP Undervoltage Thresholds VCP Undervoltage Hysteresis BG1 and BG2 Undervoltage Thresholds2 VVREG(UV,HYS) VVREG(UV,H) – VVREG(UV,L) – 100 – mV VVCP(OV,H) VVCP rising, PWM disabled 11 12.5 14 V VVCP(UV,H) VVCP rising, PWM enabled 3 3.2 3.4 V VVCP(UV,L) VVCP falling, PWM disabled – 2.7 – V VVCP(UV,H) – VVCP(UV,L) – 500 – mV BG1 or BG2 rising 1 1.05 1.1 V VVCP(UV,HYS) VBGx(UV) UNDERVOLTAGE AND OVERVOLTAGE FILTERING/DEGLITCH Undervoltage Filter/Deglitch Time td(UV,FILT) 10 15 20 µs Overvoltage Response Time2 td(OV,FILT) – 1 – µs 1 2 Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 ELECTRICAL CHARACTERISTICS – WINDOW WATCHDOG TIMER (WWDT)1: Valid at 3 V ≤ VIN ≤ 36 V in buck-boost mode and VIN having first reached VIN(START), –40ºC ≤ TA = TJ ≤ 150ºC, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VWDENn(L) VWDENn falling, WWDT enabled 0.8 – – V VWDENn(H) VWDENn rising, WWDT disabled – – 2 V – 60 – kΩ WD ENABLE INPUT (WDENn) WDENn Voltage Thresholds WDENn Input Resistance RWDENn WDIN VOLTAGE THRESHOLDS AND CURRENT WDIN Input Voltage Thresholds WDIN Input Current1 VWDIN(L) VWDIN falling, WDADJ pulled low by RADJ VWDIN(H) VWDIN rising, WDADJ charging IWDIN VWDIN = 5 V 0.8 – – V – – 2 V −10 ±1 10 µA WDIN TIMING SPECIFICATIONS WDIN Frequency fWDIN – – 750 Hz WDIN Duty Cycle DWDIN 20 50 80 % tWD(START) 24 30 36 ms tWDTO(FAST) 0.5 – 12.5 ms Watchdog Activation Delay WD PROGRAMMING WD Timeout FAST Range2 WD Timeout SLOW Range2 WD Timeout, FAST Clock WD Timeout, SLOW Clock tWDTO(SLOW) tWDTO(FASTCLK) tWDTO(SLOWCLK) RADJ = 13 kΩ 4 – 100 ms 0.4 0.5 0.6 ms RADJ = 324 kΩ 10 12.5 15 ms RADJ = 13 kΩ 3.2 4 4.8 ms RADJ = 324 kΩ 80 100 120 ms 1.6 2 2.4 ms WD ONE-SHOT TIME WD Pulse Time After WD Fault 1 2 tWD(FAULT) Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). Ensured by design and characterization, not production tested. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 Table 1: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram) Supply Control (0=OFF, 1=ON) A4409 Status Signals A4409 MODE ENBAT MPOR VREG UV 5V0_UV VREG ON LDOs ON X 1 X X 0 0 0 0 1 1 0 0 OFF 1 0 1 1 1 0 STARTUP 1 0 0 1 1 0 ↓ 1 0 0 1 1 1 ↓ 1 0 0 0 1 1 RUN 0 0 0 0 1 1 50 µs DELAY 0 0 0 0 1 0 SHUTDOWN 0 0 0 1 1 0 ↓ 0 0 0 1 0 0 ↓ 0 0 1 1 0 0 OFF RESET TIME X = DON’T CARE MPOR = BG1_UV or BG2_UV or VIN_UV or TSD or VCP_UV or VCP_OV or D1MISSING (latched) + ILIM(LX) (latched) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Table 2: Summary of Fault Mode Operation A4409 RESPONSE TO FAULT NPOR LATCHED FAULT? RESET METHOD or CORRECTION 5V0 undervoltage Closed loop control will try to raise the voltage but may be constrained by the foldback or pulse-bypulse current limit Low NO Decrease the load 5V0 overcurrent Foldback current limit will reduce the output voltage Transitions low if 5V0 < V5V0(UV,L) NO Decrease the load V5 undervoltage Closed loop control will try to raise the voltage but may be constrained by the foldback current limit Not affected NO Decrease the load V5 overcurrent Foldback current limit will reduce the output voltage Not affected NO Decrease the load VREG pin open circuit VLDO pin will take over regulation, power dissipation in IC will increase Not affected NO Connect the VREG pin VREG shorted to ground, VVREG < 2.4 V, VCOMP ≠ EAVO(MAX) Continue to PWM but turn off LX when the highside MOSFET current exceeds ILIM Depends on 5V0 NO Remove the short circuit VREG overcurrent, VVREG < 2.4 V, VCOMP = EAVO(MAX) Enters hiccup mode after 15 OCP faults Depends on 5V0 NO Decrease the load VREG overcurrent, VVREG > 2.4 V, VCOMP = EAVO(MAX) Enters hiccup mode after 60 OCP faults Depends on 5V0 NO Decrease the load VREG asynchronous diode (D1) missing Results in an MPOR after 1 detection, so all regulators are off Low YES Place D1 then cycle ENBAT or VIN Asynchronous diode (D1) short circuited or LX shorted to ground Results in an MPOR after the high-side MOSFET current exceeds ILIM,LX, so all regulators are off Low YES Remove the short then cycle ENBAT or VIN FSET/SYNC pin open circuit Oscillator frequency becomes default frequency 900 kHz Not affected NO Connect the FSET/SYNC pin FSET/SYNC pin shorted to ground Oscillator frequency becomes default frequency 900 kHz Not affected NO Remove the short circuit Charge pump (VCP) overvoltage Results in an MPOR, so all regulators are shut off Depends on 5V0 NO Check VCP/CP1/CP2 pins and components, then cycle ENBAT or VIN Charge pump (VCP) undervoltage Results in an MPOR, so all regulators are shut off Depends on 5V0 NO Check VCP/CP1/CP2 pins and components VCP pin open circuit Results in VCP_UV and an MPOR, so all regulators are shut off Depends on 5V0 NO Connect the VCP pin VCP pin shorted to ground Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in an MPOR, so all regulators are shut off Depends on 5V0 NO Remove the short circuit and replace the A4409 COMP shorted high VREGOV,H will trip, so all regulators are shut off Depends on 5V0 YES Remove the high level from the COMP pin then cycle ENBAT or VIN CP1 or CP2 pin open circuit Results in VCP_UV and an MPOR, so all regulators are shut off Depends on 5V0 NO Connect the CP1 or CP2 pins CP1 pin shorted to ground Results in VCP_UV and an MPOR, so all regulators are shut off Depends on 5V0 NO Remove the short circuit FAULT TYPE and CONDITION Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Table 2: Summary of Fault Mode Operation (continued) A4409 RESPONSE TO FAULT NPOR LATCHED FAULT? RESET METHOD or CORRECTION CP2 pin shorted to ground Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in an MPOR, so all regulators are shut off. Depends on 5V0 NO Remove the short circuit and replace the A4409 BG1 or BG2 undervoltage Results in an MPOR, so all regulators are shut off Depends on 5V0 NO Raise VIN or wait for BGs to power up BG1 or BG2 overvoltage If BG1 is too high, 5V0 will appear to be overvoltage, because BG2 is good. If BG2 is too high, 5V0 will appear to be undervoltage, because BG1 is good. Low NO Replace the A4409 VIN undervoltage Results in an MPOR, so all regulators are shut off Depends on 5V0 NO Raise VIN Thermal shutdown Results in an MPOR, so all regulators are shut off Depends on 5V0 NO Let the A4409 cool WDADJ pin shorted to ground or open circuit A WDADJ fault only affects the NPOR output. The remainder of the A4409 operates normally. Low NO Remove the short circuit or connect the pin FAULT TYPE and CONDITION Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 TIMING DIAGRAMS (Not to Scale) > VIN(START, MAX) VIN SHUT TDOWN SEQUENCE MUST FINISH BEFOR RE RE-START IS ACK KNOWLEDGED ENBAT t < t d(ENBAT,FILT) t d(ENBAT,FILT) L CO OMP fOSC / 2 fOSC LX tSS(ramp) td(SS) VVREEG(UV,H) VR REG V5V0(UV,H) V5V0(UV,L) t d(off)LDO 5V0 5V V0 < V5V0(UV,L) VV50(UV,H) V5 5V0 > V5V0(UV,H) t d(on)NPOR t d(off)NPOR NP POR Figure 1: Startup and Shutdown Sequence Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 13.5 V Deccay rate of the VIN pin will depend on the e total input capa acitance and load ds. VIN PIN: ~6.7 V @ 25ºC VIN VVCC > VVCC(STOP) EN BAT CO OMP 100% Duty Cycle fOSC / 2 fOSC LX tSS(ramp) fOSC VVREEG(UV,H) ~5.6 V @ 25ºC VREG td(SS) V5V0(UV,H) V5V0(UV,L) Dropout will depend on output load 5 5.0V 5V NP POR t d(on)NPOR V Figure 2: Input Undervoltage Timing, when VIN > VIN(STOP) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 13.5 V VIN PIN: ~6 ~.7 V @ 25ºC De ecay rate of the VIN V pin will depend on th he total input cap pacitance and loa ads. V VIN VIN < VIN(STOP) MPOR ENBA AT COM MP fOSC / 2 100% Duty D Cycle fOSC LX fOSC tSS(ramp) VVREG(UV,H) ~5.6 V @ 25ºC VR REG td(SS) V5V0(UV,H) V5V0(UV,L) 5..0V 5V t d(on)NPOR VV5(UV,H) NP POR t d(on)NPOR t d(NPOR,FILT) Figure 3: Input Undervoltage Timing, when VIN < VIN(STOP) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 VR REG EN_H HIC* H HIC* VO(EA,MAX) CO OMP fOSC/8 fOSC/8 15 5× OC CP fOSC/2 fOSC/8 trec(HIC) fOSC/2 fOSC/8 fOSC LX 15× OCP fOSC/2 15× OCP O OCP* Figure 4: VREG Short Circuit to Ground Hiccup Operation * Signal is internal to A4409 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 DESIGN AND COMPONENT SELECTION Setting Up the Pre-Regulator well with the A4409’s slope compensation. This section describes component selection for the A4409 preregulator, including charge-pump circuit, inductor, diodes, boost MOSFET, and input and output capactors. This section also covers loop compensation. Equation 3 can be used to calculate a range of values for the output inductor for buck or buck-boost. Charge Pump Capacitors The charge pump requires two capacitors: a 2.2 µF capacitor connected from pin VCP to pin VIN, and a 1 µF capacitor connected between pins CP1 and CP2. These capacitors should be high quality ceramic capacitors, such as X7R, with a voltage rating of at least 50 V. PWM Switching Frequency When the PWM switching frequency is chosen, the designer should be aware of the minimum controllable on-time, tON(MIN), of the A4409. If the system’s required on-time is less than the A4409’s minimum controllable on-time, then switch-node jitter will occur and the output voltage will have increased ripple or oscillations. The PWM switching frequency should be calculated using equation 1, where tON(BUCK,MIN) is the minimum controllable on-time of the A4409 (160 ns typical), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). fOSC < 6.6 V tON(BUCK,MIN) × VIN(MAX) (1) If the A4409’s synchronization function is used, then the base oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency according to equation 1. RFSET can be estimated using equation 2 below. RFSET = 1 – 1.98 (kΩ) 0.0455 × fOSC (2) ( VREG + VF ) 2 × ( VREG + VF ) ≤ L1 ≤ SE SE where VF is the asynchronous diode forward voltage, fOSC is the programmed oscillator frequency in kHz, and SE slope compensation can be calculated from equation 4 and is in amperes per microsecond (A/µs). The resultant inductor value will be in microhenries (µH). SE = 0.24 × fOSC For peak current mode control, it is well known that the system will become unstable when the duty cycle is above 50% without adequate slope compensation (SE). However, the slope compensation in the A4409 is a fixed value based on the oscillator frequency (fOSC). Therefore, it is important to calculate an inductor value so the falling slope of the inductor current (SF) will work (4) If equation 3 yields an inductor value that is not a standard value, then the next closest available value should be used. The final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. The inductor should not saturate given the peak operating current during overload. Equation 5 calculates the current. In equation 5, VIN(MAX) is the maximum continuous input voltage, such as 16 V, and VF is the asynchronous diodes forward voltage. IPEAK = 4.6 A – SE × ( VREG + VF ) 0.9 × fOSC × ( VIN(MAX)+VF ) (5) After an inductor is chosen, it should be tested during output overload and short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the inductor or the regulator is not damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. Inductor ripple current can be calculated using equation 6 for buck mode and equation 7 for buck-boost mode. ΔIL1 = where fOSC is in MHz. Pre-Regulator Output Inductor (L1) (3) ΔIB / B = ( VIN – VREG ) × VREG fSW × L1× VIN VIN × DBOOST fSW × L1 (6) (7) Pre-Regulator Output Capacitors The output capacitors filter the output voltage to provide an acceptable level of ripple voltage, and they store energy to help Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (ΔVOUT ) is a function of the output capacitors parameters: CO, ESRCO, ESLCO. ΔVOUT = ΔIL1× ESRCO + VIN – VREG ΔIL1 × ESLCO + L1 8× fSW× CO (8) The type of output capacitors will determine which terms of equation 8 are dominant. For ceramic output capacitors, the ESRCO and ESLCO are virtually zero, so the output voltage ripple will be dominated by the third term of equation 8. ΔIL1 ΔVREG = 8× fSW × CO (9) To reduce the voltage ripple of a design using ceramic output capacitors, simply increase the total capacitance, reduce the inductor current ripple (i.e. increase the inductor value), or increase the switching frequency. The transient response of the regulator depends on the number and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount ΔVREG = ΔILOAD × ESRCO + di ESLCO dt (10) After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, it may be more difficult to obtain acceptable gain and phase margins in a a higher bandwidth system. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the Compensation Components section of this datasheet. Ceramic Input Capacitors The ceramic input capacitor or capacitors must limit the voltage ripple at the VIN pin to a relatively low voltage during maximum load. Equation 11 can be used to calculate the minimum input capacitance, CIN ≥ IVREG(MAX)× 0.25 0.9× fSW× 50 mV (11) where IVREG(MAX) is the maximum current from the pre-regulator, IVREG(MAX) ≡ ILINEAR + IAUX + 20 mA (12) where ILINEAR is the sum of all internal linear regulators output currents, and IAUX is any extra current drawn from the VREG output to power other devices external to the A4409. A good design should consider the dc-bias effect on a ceramic capacitor— as the applied voltage approaches the rated value, the capacitance value decreases. An X7R type capacitor should be the primary choice due to its stability with both dc bias and temperature variation. For all ceramic capacitors, the dc-bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size. Also for improved noise performance, it is recommended to add smaller-sized capacitors close to the A4409 VIN pin and the D1 anode. Use a 0.1 µF, 0603 capacitor. Buck-Boost Asynchronous Diode (D1) The highest peak current in the asynchronous diode (D1) occurs during overload and is limited by the A4409. Equation 5 can be used to calculate this current. The highest average current in the asynchronous diode occurs when VIN is at its maximum, DBOOST = 0%, and DBUCK = minimum (10%), IAVG = 0.9 × IVREG(MAX) (13) where IVREG(MAX) is calculated using equation 12. Boost MOSFET (Q1) The RMS current in the boost MOSFET (Q1) occurs when VIN is at its minimum and both the buck and boost operate at their maximum duty cycles (approximately 64% and 58%, respectively), Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 IQ1(RMS) = √ DBOOST × [( ΔIB / B IPEAK − 2 ) 2 ] ΔI + B/B 12 1 < 2 × CO × ESRCO (14) CP = Boost Diode (D2) Pre-Regulator Compensation Components (RZ, CZ, CP) Although the A4409 can operate in buck-boost mode at low input voltages, it can still be considered a buck converter when looking at the control loop. The following equations can be used to calculate the compensation components. (15) 4 2× RZ× fC 60 180 50 135 40 90 PM = 52.5° 30 (16) Determine if the second compensation capacitor (CP) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency or the following relationship is valid: 45 20 0 10 -45 fC = 25.2 kHz 0 -90 -10 -135 GM = 22 dB -20 -30 The series capacitor, CZ, along with the resistor, RZ, set the location of the compensation zero. This zero should be placed no lower than ¼ of the crossover frequency and should be kept to minimum value. Equation 18 can be used to estimate this capacitor value. (18) Phase - ° First, the target crossover frequency for the final system must be selected. Although the A4409 can switch at over 2 MHz, the crossover will be governed by the required phase margin. Since a type II compensation scheme is used, there are limits to the amount of phase that can be added. Therefore, a crossover frequency, fC, of around 40 kHz is selected. The total system phase will drop off at higher crossover frequencies. The RZ selection is based on the gain required at the crossover frequency, and can be calculated by the following simplified equation: COUT × ESR RZ Finally, take a look at the combined bode plot of both the controlto-output and the compensated error amp— see the red curves shown in Figure 5. Careful examination of this plot shows that the magnitude and phase of the entire system are simply the sum of the error amp response (blue) and the control-to-output response (green). As shown in Figure 5, the bandwidth of this system (fC) is 25.2 kHz, the phase margin is 52.5 degrees, and the gain margin is 22 dB. These values are theoretical; actual measured values may be different. Some fine-tuning of the final compensation components may be necessary in the lab. Gain - dB In buck mode, this diode will simply conduct the output current. However, in buck-boost mode, the peak currents in this diode may increase significantly. The A4409 limits the peak current to the value calculated using equation 5. The average current is simply the output current. CZ > (17) If this is the case, then add the second compensation capacitor (CP) to set the pole fP3 at the location of the ESR zero. Determine the CP value by the equation: where IPEAK and ΔIB/B are derived using equations 5 and 7, respectively. 13.36 × × fC × CO RZ = gm(POWER) × gm(EA) fSW 2 -40 100 Total Gain C to O Gain E/A Gain Total Phase C to O Phase E/A Phase 1000 10000 -180 -225 100000 -270 1000000 Frequency - Hz Figure 5: Bode plot of the complete system (red curve) RZ = 6.19 kΩ, CZ = 4.7 nF, CP = 10 pF LO = 33 µH, CO = 4 × 10 µF ceramic Linear Regulators The two linear regulators only require a ceramic capacitor to ensure stable operation. The capacitor can be any value between 1 µF and 22 µF. A 2.2 µF or 4.7 µF capacitor per regulator is recommended. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 Internal Bias (VCC) The internal bias voltage should be decoupled at the VCC pin using a 1 µF, 25 V X7R ceramic capacitor. It is not recommended to use this pin as a source. Signal Pins (NPOR, ENBAT) The NPOR signal is an open drain output and requires an external pull-up resistor. It is recommended to pull NPOR up to the 5V0 rail, so when the A4409 is disabled, NPOR will not be high. The ENBAT is a high-voltage input pin. It does require a currentlimiting resistor when connected to voltages greater than 8 V. There are limitations on this resistor value based on ENBAT sink current, ENBAT enable threshold, and input voltage operating conditions. Minimum ENBAT resistor is 450 Ω. If ENBAT must ensure A4409 is enabled down to the minimum operating voltage, then a resistor less than 3.37 kΩ is recommended. Watchdog (WDENn, WDIN, WDADJ) The A4409 window watchdog circuit monitors an external clock applied to the WDIN pin. This clock should be generated by the microcontroller or DSP. The time between rising edges of the clock must fall within an acceptable “window” or a watchdog fault will be generated. A watchdog fault will set NPOR for tWD(FAULT) (typically 2 ms). A watchdog fault will occur if the time between rising edges is either too short (a FAST fault) or too long (a SLOW fault). WD OSC WDADJ CLKIN WDENn RADJ = 64.9 kΩ for tWDTO(SLOW) = 20 ms WDIN WDENn The watchdog time “window” is programmable via the WDADJ pin according to the following equations: RADJ = 3.24 × tWDTO(SLOW) tWDTO(FAST) = tWDTO(SLOW) / 8 where tWDTO(SLOW) is the nominal watchdog timeout (in ms) and RADJ is the required external resistor value (in kΩ) from the WDADJ pin to ground. Typical watchdog operation under FAST and SLOW fault conditions are shown in Figure 7 and Figure 8. The watchdog is enabled if two conditions are met: 1. the WDENn pin is a logic low, and 2. all regulators (5V0 and V5) have been above their undervoltage thresholds for at least 30 msTYP (tWD(START)). After startup, if no clock edges are detected at WDIN for at least tWD(START) + tWDTO(SLOW), the A4409 will set NPOR low for tWD(FAULT) and reset its counters. This process will repeat until the system recovers and clock edges are applied to WDIN. A timing diagram for the “missing clock” situation is shown in Figure 9. Figure 10 shows the WDFAULT signal during a fast clock fault. WDCLK WDENn = 0 or OPEN enables WD 60 kΩ WDSTART WINDOW WATCHDOG TIMER (WWDT) CLK1MHz ONE SHOT tWD(FAULT) WDFAULT Figure 6: Watchdog Block Diagram Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 tWDTO(FAST) set to 5 ms (±1 ms) tWDTO(SLOW) set to 40 ms (±8 ms) N NPOR WDSTART * S tWD(START) T < 4 ms 6 ms < T < 32 ms tWD(START) WDIN tWD(FAULT) * WDFAULT F Figure 7: Window Watchdog Timer FAST Fault, T = WDIN period * Signal is internal to A4409 tWDTO(FAST) set to 5 ms (±1 ms) tWDTO(SLOW) set to 40 ms (±8 t ms) N NPOR WDSTART* tWD(START) 6 ms < T < 32 ms T > 48 ms tWD(START) WDIN tWD(FAULT) WDFAULT * F Figure 8: Window Watchdog Timer SLOW Fault, T = WDIN period * signal is internal to A4409 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 td(on)NPOR NPOR tWD(START) W DSTART* tWD(START) tWDTO(SLOW) tWD(START) tWDTO(SLOW) WDIN WD DFAULT* S STARTUP tWD(FAULT) tWD(FAULT) Figure 9: Window Watchdog Timer operation during slow clock fault, WDIN stuck low or high * signal is internal to A4409 tWDTO(FAST) N NPOR WDSTART * S tWDTO(FAST) tWDTO(FAST) tWDTO(FAST) td(on)NPOR tWD(START) tWD(START) tWD(START) tWD(START) WDIN WD DFAULT* ST TARTUP tWD(FAULT) tWD(FAULT) tWD(FAULT) tWD(FAULT) Figure 10: Window Watchdog Timer operation during fast clock fault * signal is internal to A4409 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 PCB LAYOUT GUIDELINES Good layout of the power components and high di/dt loops is critical to proper operation of the A4409. It also helps to reduce EMI generation. The first loop to consider is the buck regulator input loop. This consists of the input capacitors C3, C4, and C5, pins 2 and 18 of the A4409, and the diode D2. Figure 11 shows this loop in red. C3 4.7 µF C4 C5 100 pF 0.1 µF C6 C7 2.2 µF 1 µF If the A4409 is configured as a buck-boost, then the boost output loop needs to be considered. This is made up of the boost MOSFET Q1, boost diode D7, and output capacitors C30 and C8. The boost switch node (L1, Q1 drain, and D7 anode) should be as short and as wide as possible to ensure the lowest possible impedance. L1 D7 L1 D D2 Q1 Q U1 GND 3 2 1 VIN V VCP CP1 ENBAT 19 A4409LP 20 CP2 C30 C8 p 180 pF 10 µF GND LX 18 Figure 11: Buck High di/dt Loop An example of how these components may be placed is shown below. Ensure that these components and connecting traces are on the same side of the PCB. Also ensure the enclosed area within the loop is as small as possible. The switch node trace connected to LX should be as short and as wide as possible to ensure the lowest possible impedance. GND Figure 13: Boost Output Loop Layout below shows the boost high di/dt loop. Figure 12 Figure 14: Boost High di/dt Loop Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Also if configured for buck-boost mode, then care must be taken with the gate drive trace. The turn-on pulse is from C17 through A4409 pin 16 to Q1 gate and source back to C17. The turn-off pulse is from Q1 gate to A4409 pin 16 back to Q1 source through the ground. Other sensitive nodes to keep small are the FSET/SYNC to R3, the COMP pin to C15 and C16, and WDADJ pin to RADJ. Figure 16 Figure 15 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 PIN ESD STRUCTURES PIN 8V GND Figure 17: VCC, COMP, FSET/SYNC, NPOR, WDENn, WDIN, 5V0, V5, WDADJ, VLDO, VREG, LG PGND Figure 18: GND, PGND CP1 VIN CP2 8V VCP 40 V LX 40 V Figure 19: VCP, CP1, CP2 Figure 20: VIN, LX ENBAT 40 V Figure 21: ENBAT Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR A4409 PACKAGE OUTLINE DRAWING For Reference Only – Not for Tooling Use (Reference MO-153 ACT) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 6.50 NOM 0.45 0.65 4.20 4º 20 20 0.20 0.09 1.70 C 3.00 4.40 NOM 3.00 6.40 NOM 6.10 A 0.60 NOM 1 1.00 REF 2 1 0.25 BSC 2 4.20 SEATING PLANE 20X C 0.10 1.20 MAX C GAUGE PLANE B SEATING PLANE 0.30 0.19 0.65 BSC 0.05 NOM NNNNNNN YYWW LLLLLLL A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C PCB Layout Reference View 1 B Exposed thermal pad (bottom surface) Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Lot number Figure 22: Package LP, 20-Pin eTSSOP Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 29 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Revision History Number Date Description – October 5, 2015 1 December 14, 2015 2 March 31, 2016 3 June 27, 2016 Initial Release Updated 5V0 Undervoltage Thresholds and Hysteresis in Electrical Characteristics table (page 10). Corrected NPOR Turn-Off Propagation Delay test condition (page 10); Corrected Watchdog Activation Delay symbol (page 12); Added “WDADJ Pin Shorted to Ground or Open Circuit” to Summary of Fault Mode Operation table (page 15); Corrected Figure 1 (page 16); Corrected Figure 3 (page 18); Removed “Window Watchdog Timer Operation During RADJ Fault” figure (page 25); Corrected PCB layout guidelines (page 27). Updated Pin ESD Structures (page 28). Copyright ©2016, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 30