THE MOST VERSATILE NON-VOLATILE PLD TM MachXO Family Optimized for Low Density Applications The MachXO™ family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Combining an optimized look-up table (LUT) architecture with lowcost embedded Flash process technology, the instant-on, easy-touse MachXO devices are the most versatile, non-volatile PLDs for low-density applications. The MachXO PLD family offers the benefits of increased system integration by providing embedded memory, built-in PLLs, flexible multi-voltage high-performance LVDS I/Os, remote field upgrade (TransFR™ technology) and low-power sleep mode, all in a single device. Designed for a broad range of low-density applications that include general purpose I/O expansion, control, bus bridging and power-up management functions, the MachXO PLD family is used in a variety of end markets such as consumer, automotive, communications, computing, industrial and medical. Broad Range of Applications Key Features and Benefits Non-Volatile, Infinitely Reconfigurable • Instant-on, powers up in less than 1mS • Single-chip, no external configuration memory • Excellent design security, no bitstream to intercept Performance to 3.5ns Pin-to-Pin General Purpose I/O Expansion Bus Bridging & Protocol Translation MachXO Power-Up Management MachXO Application Example CPU Device Select ASSP Fan Control FPGA Address & Data Bus MachXO Reset Power Supply Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces: – LVCMOS 3.3/2.5/1.8/1.5/1.2 – LVTTL – PCI* – LVDS*, Bus-LVDS*, LVPECL*, RSDS* sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide and phase shifting GPIO EPROM Flexible LUT Architecture • 256 to 2280 LUT4s • 73 to 271 I/Os with extensive package options • Density migration supported Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Includes dedicated FIFO control logic • Up to 7.7 Kbits distributed RAM FPGA/ASIC/ASSP Configuration External Interface TransFR Technology Allows Simple Field Upgrades Sleep Mode Reduces Standby Power to <100µA System-Level Support • IEEE Standard 1149.1 Boundary Scan • On-board 20MHz oscillator for configuration and user logic • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply Broad Device Offering • Commercial: 0 to 85ºC (TJCOM) • Industrial: -40 to 100ºC (TJIND) • AEC-Q100 qualified: -40 to 125ºC (TJAUTO) * MachXO1200 and 2280 devices only. LATTICESEMI.COM TM MachXO Architecture Architecture Overview MachXO PLDs are designed to offer a low-cost, flexible alternative for applications traditionally served by CPLDs or low-density FPGAs. Built with an extremely efficient architecture, MachXO PLDs deliver excellent pin-to-pin performance, support for highspeed I/Os, embedded block RAM, and sysCLOCK PLLs. PFU Block Diagram Carry Chain MachXO Block Diagram Slice 3 LUT4 FF LUT4 FF On-chip Flash Memory offers instant-on start-up and security from bitstream snooping sysCLOCK PLLs for clock management Slice 2 LUT4 Available in space saving, RoHS compliant package options, MachXO PLDs can be used in a broad range of space constrained applications. Flash Memory FF LUT4 FF From Routing Slice 1 LUT4 To Routing sysMEM Embedded Block RAM (EBR) provides 9kbit true dual port RAM at up to 275MHz Flexible Routing optimized for speed, low-cost, and routability FF LUT4 Programmable Function Unit (PFU) with RAM FF Slice 0 LUT4 Programmable Function Unit without RAM (PFF) FF LUT4 FF Carry Chain sysMEM Configuration Options Single Port Dual Port PseudoDual Port FIFO 8192 x 1 8192 x 1 8192 x 1 8192 x 1 4096 x 2 4096 x 2 4096 x 2 4096 x 2 2048 x 4 2048 x 4 2048 x 4 2048 x 4 1024 x 9 1024 x 9 1024 x 9 1024 x 9 512 x 18 512 x 18 512 x 18 512 x 18 256 x 36 – 256 x 36 256 x 36 JTAG JTAG Port for configuring Flash and SRAM memory MachXO Voltage Options 1.2V VCC 3.3V VCCAUX 1.2 to 3.3V VCCIO 1.8 to 3.3V VCC 3.3V VCCAUX sysIO Buffers support LVCMOS/LVTTL, LVDS and PCI sysCLOCK PLL Block Diagram 1.8 to 3.3V VCCIO Dynamic Delay Adjustment 4 LOCK MachXO Version E MachXO RST Version C CLKI Input Clock Divider Delay Adjust Voltage Controlled Oscillator sysIO Buffer Supports HighBandwidth I/O Standards LVCMOS / LVTTL – Hotsocketing capable – Programmable slew rate – Programmable drive strength – Programmable pull-up, pull-down, bus friendly – Programmable open drain – Programmable Schmitt element Post Scalar Divider Phase / Duty Select Feedback Divider CLKOS CLKOP Secondary Clock Divider CLKOK CLKFB (from post scalar divider output, clock net or external pin) PCI, LVDS, LVPECL, Bus-LVDS, RSDS LATTICESEMI.COM TM Easy Field Updates MachXO Configuration MachXO PLDs include Lattice's exclusive Tr a n s p a r e n t F i e l d R e c o n f i g u r a t i o n (TransFR) technology. TransFR technology allows logic to be updated in the field without interrupting system operation. MachXO PLDs include both Flash and SRAM technology to provide “instant-on” capabilities in a single low-cost device. At power-up, configuration data is transferred from Flash to SRAM cells in less than 1mS. Both SRAM and Flash memory can be programmed from a JTAG port. This combination of SRAM and Flash enables easy field updates via Lattice's unique TransFR technology. MachXO PLDs have a security scheme that prevents readback and, by using Flash internally, Lattice eliminates bit stream snooping. Upgrade Flash FLASH (Configuration 2) Step 1 Program Flash in background while logic functions Logic – SRAM (Configuration 1) Step 2 Precisely control I/Os and initiate Flash to SRAM transfer through JTAG. On-chip Flash memory. MachXO Device Flash Memory Control Logic SRAM Configuration Bits (Controls Device Operation) Massively parallel wide data transfer provides snoop-proof SRAM configuration from Flash. JTAG Port Use JTAG port (IEEE1532/1149.1) to configure SRAM or program Flash. MachXO Sleep Mode Reduces Power by a Factor of 100X! FLASH (Configuration 2) Upgrade SRAM Characteristic SLEEPN Pin Logic – SRAM (Configuration 2) Static ICC Normal Mode Off Sleep Mode High X Low Typically <10mA 0 Typically <100µA Power Supplies Normal Range 0 Normal Range Logic Operation User Defined Non Operational Non Operational I/O Operation User Defined Tri-State (<1mA leakage) Tri-State (<10µA leakage) MachXO Application Examples Low-cost system integration Power Up and Control Boot PROM Processor Address and Data Busses FPGA Data Path Bridge Function Microprocessor Processor Address and Data Busses CPLD Power-up Logic FPGA Boot Logic & Bus Decode MachXO Data Path Power-up Bus Decode I/O Expansion Microcontroller I2C or SPI Power-Up Control Register Bank LED Control Boot PROM Reset Power-On Bridging ASIC Memory LVDS I/O Backplane Low power cycling Non-Volatile MachXO (Power Off for ~ 90% of Duty Cycle) Flexible Multi-Voltage Level shifting ASSP 1.8V MachXO 2.5V LVDS SRAM FPGA (Power Off for ~ 10% of Duty Cycle) 3.3V Microcontroller ASSP MachXO Microprocessor ASIC Backplane 0 ms Configuration 100 ms 200 ms Time Operation 3.3V 2.5V 1.8V Off LATTICESEMI.COM TM Free, Easy-to-Use Lattice Software MachXO Mini development kit Lattice Diamond ® design tools offer a comprehensive design environment for the MachXO architecture and other device families. Featuring design exploration, ease of use, improved design flow, and numerous other features, Diamond allows you to complete designs faster, easier, and with better results than ever before. Use the MachXO Mini Development Kit to test I2C, SPI, UART, SRAM interfaces as well as the 8-bit LatticeMico8™ microcontroller within minutes. Build your own design in less than an hour using free reference designs from Lattice. Learn more at www.latticesemi. com/machxo-mini. Evaluation and Development Boards Lattice offers a number of evaluation and development boards that provide a complete and easy-to-use platform to evaluate the performance of the MachXO, or aid in the development of custom designs. Reference Design Portfolio Lattice offers an expanding portfolio of IP cores and reference designs targeted for low-density applications. Optimized for the MachXO architecture these include popular protocol and connectivity standards such as I2C, SPI, UART and PCI. The reference designs, source codes and documentation can be downloaded for free from the Lattice website. For more information, go to www.latticesemi.com/ip. MachXO Control Development Kit Use the MachXO Control Development Kit to test board diagnostic functions including fan speed control based on temperature monitoring, complete power supply monitoring and reset distribution in conjunction with the Power Manager II POWR1014A and 8-bit LatticeMico8 microcontroller. Test these functions within minutes and build your own designs in less than an hour using the free reference designs from Lattice. Learn more at www.latticesemi.com/machxo-control-kit. Device Selection Guide Parameter LCMXO256 LCMXO640 LCMXO1200 LCMXO2280 256 640 1200 2280 Distributed RAM (Kbits) 2 6.1 6.4 7.7 Embedded Block RAM – EBR (Kbits) – – 9.2 27.6 Number of EBR Blocks – – 1 3 VCC Voltage (V) Options 1.2V or 1.8/2.5/3.3V 1.2V or 1.8/2.5/3.3V 1.2V or 1.8/2.5/3.3V 1.2V or 1.8/2.5/3.3V Number of PLLs – – 1 2 Number of I/O Banks 2 4 8 8 Maximum Number of I/Os 78 159 211 271 Maximum Number of LVDS Pairs* – – 27 33 LUTs Packages & I/O Combinations 100-pin TQFP (14 x 14 mm)** 78 144-pin TQFP (20 x 20 mm) 100-ball csBGA (8 x 8 mm) 78 74 73 73 113 113 113 74 132-ball csBGA (8 x 8 mm) 101 101 101 256-ball caBGA (14 x 14 mm) 159 211 211 256-ball ftBGA (17 x 17 mm) 159 211 211 324-ball ftBGA (19 x 19 mm) 271 * Number of LVDS outputs can be increased by emulating with external resistors. ** In the 100-pin TQFP package, designs can not migrate from LCMXO640 to 1200. Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 [email protected] Copyright © 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispLEVER, ispVM, LatticeMico8, MachXO, sysCLOCK, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. January 2013 Order #: I0176H LATTICESEMI.COM