Naming Convention for AURIXTM Family Primary Option Package Type Frequency – 64 F 200 W Feature Package Core Architecture Package Class Series Architecture TriCore Infineon product identifier Temperature range SA K – TC 2 7 5 T Secondary Option Memory Type Device Memory Size Brand Temp. Range K -40°C - +125 °C L -40°C - +150°C Package Class 9 LFBGA-516 8 BGA-416 7 LFBGA-292 5 LQFP-176 4 L/TQFP-144 3 TQFP-100 2 TQFP-80 0 Bare Die 2014-08-21 Core Architecture T Triple Core D Dual Core S Single Core L Single Core with Lockstep Feature packages - Production Dev., No HSM P Prod. Dev., HSM enabled E Emulation Dev., no HSM F Emulation Dev., HSM enabled A ADAS enhanced, HSM enabled B ADAS enhanced, No HSM X Feature extension, HSM enabled Y SRAM extension, No HSM C Customer specific Flash size code 8 0.5MB 16 1 MB 24 1.5 MB 32 2 MB 40 2.5 MB 64 4 MB 96 6 MB 128 8 MB Copyright © Infineon Technologies AG 2014. All rights reserved. Package type code W LQFP 0.5mm pitch F TQFP 0.4mm pitch V VQFN 0.5mm pitch L BGA 1.0 mm pitch S LFBGA 0.8mm pitch Q Fusion Quad QFP 0.5 mm pitch Page 1 Naming Convention for TriCore® Family Example: SAK-TC1796-256F150E Automotive families: 1: Industry 2: Body 3: Safety 7: Powertrain Code memory size: n*8k Bytes e.g. 64: 64*8k=512k Component specific Prefix SA Temp. Range Code B F H K Type TC1 Variation y xx ED Code Size ## Variation: ED = emulation device Other = blank Mem. Type CPU Freq. L F L = Flashless F = Flash B = 0/ 70 °C F = -40/ 85 °C H = -40/ 110°C K = -40/ 125°C Example: SAK-TC1796-256F150E Copyright © Infineon Technologies AG 2013. All rights reserved. 40 66 80 150 300 Package H H N E H = Quad flat pack HL = L-QFP HM = M-QFP HT = T-QFP E = P-BGA EL = P-LFBGA ET = P-TFBGA EB =P-LBGA U = flip-chip, bare die Page 2 Naming Convention for XMC4000 Family Example: XMC4500–F144K1024 AC Family XMC Core 4 Feature Package 5 0 4 2 0 2 4 1 8 E F Q Pins 144 100 64 48 Temp. Flash [kB] Step K X F 1024 768 512 256 128 64 AA AB AC Silicon Version AA = 01 AB = 02 AC = 03 K = -40° to 125°C X = -40° to 105°C F = -40° to 85°C E = LFBGA | F = LQFP | Q = VQFN 0 = Full Featured < ….. > 8 = Feature Subset 1 = Baseline < ….. > 5 = High-End ARM® Cortex™-M4 with built in DSP, SPFPU, DMA and MPU XMC := Industrial Microcontroller Family based on ARM® Cortex™-M Processors Copyright © Infineon Technologies AG 2013. All rights reserved. Page 3 Naming Convention for XMC1000 Family Example: XMC1302-T038X0200 AA Family XMC Core 1 Feature 3 2 2 0 1 1 0 Package Pins Q T 40 38 28 24 16 Temp. Flash [kB] Step X F 200 128 64 32 16 8 AA Silicon Version AA = 01 X = -40° to 105°C F = -40° to 85°C Q = VQFN | T = TSSOP 2 = Full Featured < ….. > 0 = Feature Subset 1 = Baseline < ….. > 3 = High-End ARM® Cortex™-M0 XMC := Industrial Microcontroller Family based on ARM® Cortex™-M Processors Copyright © Infineon Technologies AG 2013. All rights reserved. Page 4 Naming Convention for 16-bit Family Example: SAF-XC161CJ-14F20F Core: XC16 = C166S V2 C16 = C166 Code memory size: n*8k Bytes e.g. 4: 4*8k=32k (blank for ROMless) CPU Speed: n*1 MHz (blank for Standard speed) Sub-Family Type Prefix SA F K A XC16 1 CJ R F E L # F M E # Key Features Temp. Range: F = -40/ 85 °C K = -40/ 125°C A = -40/ 140°C Package: F = P-TQFP M = P-MQFP E = P-BGA Code Memory Type: R = ROM F = Flash E = OTP L = ROMless Copyright © Infineon Technologies AG 2013. All rights reserved. Page 5 Naming Convention for XC2000 Family Automotive families: 2: Body 3: Safety 7: Powertrain Code memory size: n*8k Bytes e.g. 8: 8*8k=64k Component specific Prefix SA Temp. Range Code F H K Type Series XC2 A M 5X y x z Code Size ## Mem. Type F CPU Freq. 40 66 80 120 Package Bonding R L R = Cooper series-# ED =MCDS device F = -40/ 85 °C H = -40/ 110°C K = -40/ 125°C 3: 6: 8: 9: QFP-64 QFP-100 QFP-144 QFP-176 F = Flash L = L-QFP V = VQFN R = TSSOP Package Package Package Package Copyright © Infineon Technologies AG 2013. All rights reserved. Page 6 Naming Convention for XE166 Family Example: SAF-XE167F-96F80L Temp. Range: F = -40/ 85 °C K = -40/ 125°C Prefix SA Temp. Range F K Industrial series: 0: 38 pin 1: 48 pin 2: 64 pin 4: 100 pin 7: 144 pin 9: 176 pin Silicon: Version Type XE 16# Code memory size: n*8k Bytes e.g. 8: 8*8k=64k F G H K H M N L U Memory Size # Mem. Type F CPU Freq. 40 66 80 100 Package Bonding R V L R Variation C166S V2 CPU Enhanced: 3/5 Volt IO more memory Members: peripheral set R = Cooper F = Flash Copyright © Infineon Technologies AG 2013. All rights reserved. R = TSSOP V = VQFN L = LQFP Page 7 Naming Convention for XC800 Family Code memory size: XC800 Family product n*4k Bytes + 2 digits: component specific e.g. 4: 4*4k=16k 5V = 5V Supply 3V3 = 3V Supply F = Flash R = ROM SA F X K A L XC8xx F = -40°C-85°C X = -40°C-105°C K = -40°C-125°C A = -40°C-140°C L = -40°C-150°C CLM C = CAN L = LIN M = MDU #F #R R F G R = TSSOP F = T/LQFP G = P-DSO V= VQFN Copyright © Infineon Technologies AG 2013. All rights reserved. A I 5V 3V3 A = Automotive I = Industrial Page 8 Naming Convention for C500 Family Example: SAB-C505CA-4EM Core: C5 = C500 (custom) Code memory size: n*8k Bytes e.g. 4: 4*8k=32k (blank for ROMless) Package: M = P-MQFP R = P-TSSOP G = P-DSO Sub-Family Type SA B F K C5 05CA # Temp. Range: B = 0/ 70 °C F = -40/ 85 °C K = -40/ 125°C Copyright © Infineon Technologies AG 2013. All rights reserved. R S E L M R G Code Memory Type: R = ROM S = SRAM E = OTP L = ROMless Page 9