EL5123, EL5223, EL5323, EL5423 ® Data Sheet May 3, 2007 12MHz 4-, 8-, 10- and 12-Channel Rail-toRail Input-Output Buffers The EL5123, EL5223, EL5323, and EL5423 are low power, high voltage rail-to-rail input/output buffers designed primarily for use in reference voltage buffering applications for TFT-LCDs. They are available in quad (EL5123), octal (EL5223), 10-Channel (EL5323), and 12-Channel (EL5423) topologies. All buffers feature a -3dB bandwidth of 12MHz and operate from just 600µA per buffer. This family also features fast slewing and settling times, as well as a continuous output drive capability of 30mA (sink and source). The quad channel EL5123 is available in the 10 Ld MSOP package. The 8-Channel EL5223 is available in both the 20 Ld TSSOP and 24 Ld QFN packages, the 10-Channel EL5323 in the 24 Ld TSSOP and 24 Ld QFN packages, and the 12-Channel EL5423 in the 28 Ld TSSOP and 32 Ld QFN packages. All buffers are specified for operation over the full -40°C to +85°C temperature range. FN7176.2 Features • 12MHz -3dB bandwidth • Supply voltage = 4.5V to 16.5V • Low supply current (per buffer) = 600µA • High slew rate = 15V/µs • Rail-to-rail input/output swing • Ultra-small packages • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • TFT-LCD drive circuits • Electronics notebooks • Electronic games • Touch-screen displays • Personal communication devices • Personal digital assistants (PDA) • Portable instrumentation • Sampling ADC amplifiers • Wireless LANs • Office automation • Active filters • ADC/DAC buffers 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5123, EL5223, EL5323, EL5423 Pinouts 20 VOUT2 21 VOUT1* 22 NC 23 VIN1* 24 VIN2 VIN3 1 19 VOUT3 VIN4 2 18 VOUT4 VIN5 3 17 VOUT5 THERMAL PAD VS+ 4 10 VOUT1 VIN1 1 20 VOUT1 VIN2 2 9 VOUT2 VIN2 2 19 VOUT2 8 VS- VIN3 3 18 VOUT3 VIN3 4 7 VOUT3 VIN4 4 17 VOUT4 VIN4 5 6 VOUT4 VS+ 5 16 VS- VS+ 6 15 VS- VS+ 3 VIN8 7 13 VOUT8 VOUT9 12 14 VOUT7 VOUT10* 11 VIN7 6 NC 10 15 VOUT6 CVIN10* 9 VIN1 1 16 VS- VIN6 5 VIN9 8 EL5223 (20 LD TSSOP) TOP VIEW EL5123 (10 LD MSOP) TOP VIEW EL5223, EL5323 (24 LD QFN) TOP VIEW VIN5 7 14 VOUT5 VIN6 8 13 VOUT6 VIN7 9 12 VOUT7 VIN8 10 11 VOUT8 * NOT AVAILABLE IN EL5223 26 VOUT2 27 VOUT1 28 NC 29 NC 30 NC 31 VIN1 32 VIN2 VIN3 1 25 VOUT3 VIN4 2 24 VOUT4 VIN5 3 23 VOUT5 VIN6 4 22 VOUT6 THERMAL PAD VS+ 5 21 VS- VIN10 9 17 VOUT10 2 VOUT11 16 18 VOUT9 VOUT12 15 VIN9 8 NC 14 19 VOUT8 NC 13 VIN8 7 NC 12 20 VOUT7 VIN12 11 VIN7 6 VIN11 10 EL5323 (24 LD TSSOP) TOP VIEW EL5423 (28 LD TSSOP) TOP VIEW EL5423 (32 LD QFN) TOP VIEW VIN1 1 28 VOUT1 VIN1 1 24 VOUT1 VIN2 2 27 VOUT2 VIN2 2 23 VOUT2 VIN3 3 26 VOUT3 VIN3 3 22 VOUT3 VIN4 4 25 VOUT4 VIN4 4 21 VOUT4 VIN5 5 24 VOUT5 VIN5 5 20 VOUT5 VIN6 6 23 VOUT6 VS+ 6 19 VS- VS+ 7 22 VS- VS+ 7 18 VS- VS+ 8 21 VS- VIN6 8 17 VOUT6 VIN7 9 20 VOUT7 VIN7 9 16 VOUT7 VIN8 10 19 VOUT8 VIN8 10 15 VOUT8 VIN9 11 18 VOUT9 VIN9 11 14 VOUT9 VIN10 12 17 VOUT10 VIN10 12 13 VOUT10 VIN11 13 16 VOUT11 VIN12 14 15 VOUT12 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Ordering Information PART NUMBER PART MARKING TAPE AND REEL PACKAGE PKG. DWG. # EL5123CY P - 10 Ld MSOP (3.0mm) MDP0043 EL5123CY-T7 P 7” 10 Ld MSOP (3.0mm) MDP0043 EL5123CY-T13 P 13” 10 Ld MSOP (3.0mm) MDP0043 EL5123CYZ (Note) BAAAT - 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5123CYZ-T7 (Note) BAAAT 7” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5123CYZ-T13 (Note) BAAAT 13” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5223CL 5223CL - 24 Ld QFN (4mmx5mm) MDP0046 EL5223CL-T7 5223CL 7” 24 Ld QFN (4mmx5mm) MDP0046 EL5223CL-T13 5223CL 13” 24 Ld QFN (4mmx5mm) MDP0046 EL5223CLZ (Note) 5223CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5223CLZ-T7 (Note) 5223CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5223CLZ-T13 (Note) 5223CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5223CR 5223CR - 20 Ld TSSOP (4.4mm) MDP0044 EL5223CR-T7 5223CR 7” 20 Ld TSSOP (4.4mm) MDP0044 EL5223CR-T13 5223CR 13” 20 Ld TSSOP (4.4mm) MDP0044 EL5223CRZ (Note) 5223CRZ - 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5223CRZ-T7 (Note) 5223CRZ 7” 20-Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5223CRZ-T13 (Note) 5223CRZ 13” 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173 EL5323CL 5323CL - 24 Ld QFN (4mmx5mm) MDP0046 EL5323CL-T7 5323CL 7” 24 Ld QFN (4mmx5mm) MDP0046 EL5323CL-T13 5323CL 13” 24 Ld QFN (4mmx5mm) MDP0046 EL5323CLZ (Note) 5323CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5323CLZ-T7 (Note) 5323CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5323CLZ-T13 (Note) 5323CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046 EL5323CR 5323CR - 24 Ld TSSOP (4.4mm) MDP0044 EL5323CR-T13 5323CR 13” 24 Ld TSSOP (4.4mm) MDP0044 EL5323CRZ (Note) 5323CRZ - 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5323CRZ-T7 (Note) 5323CRZ 7” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5323CRZ-T13 (Note) 5323CRZ 13” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044 EL5423CL 5423CL - 32 Ld QFN (5mmx6mm) MDP0046 EL5423CL-T7 5323CL 7” 32 Ld QFN (5mmx6mm) MDP0046 EL5423CL-T13 5423CL 13” 32 Ld QFN (5mmx6mm) MDP0046 EL5423CLZ (Note) 5423CLZ - 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 EL5423CLZ-T7 (Note) 5423CLZ 7” 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 EL5423CLZ-T13 (Note) 5423CLZ 13” 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046 3 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Ordering Information (Continued) PART NUMBER PART MARKING TAPE AND REEL PACKAGE PKG. DWG. # EL5423CR 5423CR - 28 Ld TSSOP (4.4mm) MDP0044 EL5423CR-T7 5423CR 7” 28 Ld TSSOP (4.4mm) MDP0044 EL5423CR-T13 5423CR 13” 28 Ld TSSOP (4.4mm) MDP0044 EL5423CRZ (Note) 5423CRZ - 28 Ld TSSOP (4.4mm) (Pb-free) MDP0044 EL5423CRZ-T7 (Note) 5423CRZ 7” 28 Ld TSSOP (4.4mm) (Pb-free) MDP0044 EL5423CRZ-T13 (Note) 5423CRZ 13” 28 Ld TSSOP (4.4mm) (Pb-free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Absolute Maximum Ratings (TA = 25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ and CL = 10pF to 0V, TA = +25°C Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 0.5 12 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain -4.5V ≤ VOUT ≤ 4.5V 0.99 µV/°C 50 nA 1.01 V/V -4.85 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA IOUT (max) Output Current (Note 2) RL = 10Ω -4.95 4.85 4.95 V ±120 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V IS Supply Current No load (EL5123) 2.4 3.4 mA No load (EL5223) 5.5 6.8 mA No load (EL5323) 6 8.5 mA No load (EL5423) 7.45 10.1 mA 55 DYNAMIC PERFORMANCE SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% tS Settling to +0.1% (AV = +1) BW CS 7 15 V/µs (AV = +1), VO = 2V step 250 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. 5 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Electrical Specifications PARAMETER VS+ =+5V, VS- = 0V, RL = 10kΩ and CL = 10pF to 2.5V, TA = +25°C Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 0.5 12 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5V ≤ VOUT ≤ 4.5V 0.99 µV/°C 50 nA 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -2.5mA VOH Output Swing High IL = +2.5mA IOUT (max) Output Current (Note 2) RL = 10Ω 80 4.85 4.92 V ±120 mA 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current No load (EL5123) 2.4 3.2 mA No load (EL5223) 5.2 6.5 mA No load (EL5323) 5.8 8 mA No load (EL5423) 7.2 9.7 mA 55 DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤ 4V, 20% to 80% 12 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 250 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz CS Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges 6 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ and CL = 10pF to 7.5V, TA = 25°C unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 0.5 14 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance 1 GΩ CIN Input Capacitance 1.35 pF AV Voltage Gain 0.5V ≤ VOUT ≤ 14.5V 0.99 µV/°C 50 nA 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -7.5mA VOH Output Swing High IL = +7.5mA IOUT (max) Output Current (Note 2) 80 14.85 14.95 V RL = 10Ω 120 200 mA 55 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current No load (EL5123) 2.4 3.7 mA No load (EL5223) 5.7 7.1 mA No load (EL5323) 6.2 8.7 mA No load (EL5423) 7.8 10.4 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤ 14V, 20% to 80% 18 V/µs tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step 250 ns BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 12 MHz CS Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. 7 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves 0.018 10 VS=±5V RL=10kΩ 0.016 V =2V IN P-P THD + NOISE (%) 12 VOP-P (V) 8 6 4 2 0.012 0.01 0.008 VS=±5V RL=10kΩ 0 10K 0.014 100K 1M 0.006 1K 10M 10K FREQUENCY (Hz) FIGURE 1. OUTPUT SWING vs FREQUENCY FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 80 10 VS=±5V 70 RL=10kΩ VIN=100mV 60 VS=±5V RL=10kΩ 6 CL=12pF STEP SIZE (V) OVERSHOOT (%) 100K FREQUENCY (Hz) 50 40 30 20 2 -2 -6 10 0 10 100 -10 200 250 300 350 400 450 500 550 600 650 1K CAPACITANCE (pF) SETTLING TIME (ns) FIGURE 3. OVERSHOOT vs LOAD CAPACITANCE FIGURE 4. SETTLING TIME vs STEP SIZE 20 VS=±5V RL=10kΩ NORMALIZED MAGNITUDE (dB) NORMALIZED MAGNITUDE (dB) 20 1000pF 100pF 10 0 12pF 47pF -10 -20 -30 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS CL 8 VS=±5V CL=10pF 10 1kΩ 10kΩ 0 562Ω -10 -20 -30 100K 150Ω 1M 10M 100M FREQUENCY (Hz) FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RL FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves 100 600 VS=±5V TA=25°C OUTPUT IMPEDANCE (Ω) PSRR+ PSRR (dB) 80 60 PSRR- 40 20 VS=±5V 0 1K 10K 100K 1M 480 360 240 120 0 100K 10M 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 7. PSRR vs FREQUENCY FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY 100 20 % OF BUFFERS 10 15 10 5 FREQUENCY (Hz) 6 4 100M 2 10M 0 1M -2 0 100K -4 1 10K -6 VOLTAGE NOISE (nV/√Hz) 25 INPUT OFFSET VOLTAGE (mV) FIGURE 9. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY FIGURE 10. INPUT OFFSET VOLTAGE DISTRIBUTION 2.5 4.955 OUTPUT HIGH VOLTAGE (V) INPUT BIAS CURRENT (nA) VS=±5V 1.5 0.5 -0.5 -1.5 4.95 4.945 4.94 4.935 4.93 4.925 -2.5 -35 -15 5 25 45 65 85 TEMPERATURE (°C) FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE 9 VS=±5V IOUT=5mA -35 -15 5 25 45 65 85 TEMPERATURE (°C) FIGURE 12. OUTPUT HIGH VOLTAGE vs TEMPERATURE FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves 15.1 -4.934 OUTPUT LOW VOLTAGE (V) VS=±5V SLEW RATE (V/µs) 14.9 14.7 14.5 14.3 14.1 VS=±5V IOUT=-5mA -4.938 -4.942 -4.946 -4.95 -4.954 -35 -15 5 25 45 65 85 -35 -15 TEMPERATURE (°C) 25 45 65 85 TEMPERATURE (°C) FIGURE 13. SLEW RATE vs TEMPERATURE FIGURE 14. OUTPUT LOW VOLTAGE vs TEMPERATURE 0.66 1.0014 VS=±5V SUPPLY CURRENT (mA) VS=±5V VOLTAGE GAIN (V/V) 5 1.001 1.0006 1 0.9998 0.65 0.64 0.63 0.62 -35 -15 5 25 45 65 85 -35 TEMPERATURE (°C) -15 5 25 45 65 85 TEMPERATURE (°C) FIGURE 15. VOLTAGE GAIN vs TEMPERATURE FIGURE 16. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE 0.71 SUPPLY CURRENT (mA) TA=25°C VS=±5V RL=10kΩ CL=12pF 0.69 0.67 50mV/DIV 0.65 0.63 4 6 8 10 12 14 16 18 200ns/DIV SUPPLY VOLTAGE (V) FIGURE 17. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE 10 FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 POWER DISSIPATION (W) 2.857W 1V/DIV 2.5 2.703W 2 QFN32 θJA=35°C/W QFN24 θJA=37°C/W 1.5 1 0.5 0 0 1µs/DIV 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE 0.8 FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 758mW 714mW POWER DISSIPATION (W) POWER DISSIPATION (W) 0.7 0.6 0.5 QFN24 θJA=140°C/W 0.4 QFN32 θJA=132°C/W 0.3 0.2 0.1 1.333W 1.2 1.176W TSSOP24 θJA=85°C/W 1.111W 1 0.8 870mW 0.6 TSSOP28 θJA=75°C/W TSSOP20 θJA=95°C/W 0.4 MSOP10 θJA=115°C/W 0.2 0 0 0 25 50 75 85 100 125 150 0 25 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 0.9 75 85 100 125 150 FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 833mW 781mW 0.8 POWER DISSIPATION (W) 50 AMBIENT TEMPERATURE (°C) 0.7 TSSOP24 θJA=128°C/W 714mW 0.6 TSSOP28 θJA=120°C/W 0.5 486mW 0.4 MSOP10 θJA=206°C/W 0.3 0.2 TSSOP20 θJA=140°C/W 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 11 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Applications Information exceeds ±30mA. This limit is set by the design of the internal metal interconnects. Product Description The EL5123, EL5223, EL5323, and EL5423 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (600µA per buffer). These features make the EL5123, EL5223, EL5323, and EL5423 ideal for a wide range of general-purpose applications. When driving a load of 10kΩ and 12pF, the EL5123, EL5223, EL5323, and EL5423 have a -3dB bandwidth of 12MHz and exhibits 15V/µs slew rate. Operating Voltage, Input, and Output Output Phase Reversal The EL5123, EL5223, EL5323, and EL5423 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 25 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur. The EL5123, EL5223, EL5323, and EL5423 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5123, EL5223, EL5323, and EL5423 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5123, EL5223, EL5323, and EL5423 typically extend to within 50mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 24 shows the input and output waveforms for the device. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. 10µs VS=±5V TA=25°C VIN=10VP-P OUTPUT INPUT 5V 5V 1V 1V 10µs VS=±2.5V TA=25°C VIN=6VP-P FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5123, EL5223, EL5323, and EL5423 buffer, it is possible to exceed the 125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX – T AMAX P DMAX = --------------------------------------------dΘ JA where: TJMAX = Maximum junction temperature FIGURE 24. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The EL5123, EL5223, EL5323, and EL5423 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never 12 TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 when sourcing, and P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] when sinking. where: i = 1 to Total number of buffers VS = Total supply voltage ISMAX = Maximum quiescent current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ pin to ground. A 4.7µF tantalum capacitor should then be connected from VS+ pin to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. Driving Capacitive Loads The EL5123, EL5223, EL5323, and EL5423 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. 13 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 14 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN3 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN2 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 15 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Thin Shrink Small Outline Plastic Packages (TSSOP) M20.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- α e A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE A2 c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX α 20 0o 20 7 8o Rev. 1 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 16 FN7176.2 May 3, 2007 EL5123, EL5223, EL5323, EL5423 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7176.2 May 3, 2007