EL5127, EL5227, EL5327, EL5427 ® Data Sheet 2.5MHz 4, 8, 10 & 12 Channel Rail-to-Rail Buffers The EL5127, EL5227, EL5327, and EL5427 are low power, high voltage rail-to-rail input/output buffers designed for use in reference voltage buffering applications in small LCD displays. They are available in quad (EL5127), octal (EL5227), 10-channel (EL5327), and 12-channel (EL5427) topologies. All buffers feature a -3dB bandwidth of 2.5MHz and operate from just 133µA per buffer. This family also features a continuous output drive capability of 30mA (sink and source). The quad channel EL5127 is available in the 10-pin MSOP package. The 8-channel EL5227 is available in both the 20pin TSSOP and 24-pin LPP packages, the 10-channel EL5327 in the 24-pin TSSOP and 24-pin LPP packages, and the 12-channel EL5427 in the 28-pin TSSOP and 32-pin LPP packages. All buffers are specified for operation over the full -40°C to +85°C temperature range. December 13, 2002 FN7111 Features • 2.5MHz -3dB bandwidth • Supply voltage = 4.5V to 16.5V • Low supply current (per buffer) = 133µA • High slew rate = 2.2V/µs • Rail-to-rail input/output swing • Ultra-small packages Applications • TFT-LCD drive circuits • Electronic games • Touch-screen displays • Personal communication devices • Personal digital assistants (PDAs) • Portable instrumentation Ordering Information PART NUMBER PACKAGE TAPE & REEL PKG. NO. EL5127CY 10-Pin MSOP - MDP0043 EL5127CY-T7 10-Pin MSOP 7” MDP0043 EL5127CY-T13 10-Pin MSOP 13” MDP0043 EL5227CL 24-Pin LPP - MDP0046 EL5227CL-T7 24-Pin LPP 7” MDP0046 EL5227CL-T13 24-Pin LPP 13” MDP0046 EL5227CR 20-Pin TSSOP - MDP0044 EL5227CR-T7 20-Pin TSSOP 7” MDP0044 EL5227CR-T13 20-Pin TSSOP 13” MDP0044 EL5327CL 24-Pin LPP - MDP0046 EL5327CL-T7 24-Pin LPP 7” MDP0046 EL5327CL-T13 24-Pin LPP 13” MDP0046 EL5327CR 24-Pin TSSOP - MDP0044 EL5327CR-T7 24-Pin TSSOP 7” MDP0044 EL5327CR-T13 24-Pin TSSOP 13” MDP0044 EL5427CL 32-Pin LPP - MDP0046 EL5427CL-T7 32-Pin LPP 7” MDP0046 EL5427CL-T13 32-Pin LPP 13” MDP0046 EL5427CR 28-Pin TSSOP - MDP0044 EL5427CR-T7 28-Pin TSSOP 7” MDP0044 EL5427CR-T13 28-Pin TSSOP 13” MDP0044 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL5127, EL5227, EL5327, EL5427 Pinouts EL5427 (28-Pin TSSOP) TOP VIEW EL5227 (20-PIN TSSOP) TOP VIEW EL5127 (10-PIN MSOP) TOP VIEW 1 VIN1 VOUT1 28 2 VIN2 VOUT2 27 EL5327 (24-Pin TSSOP) TOP VIEW 1 VIN1 VOUT1 20 3 VIN3 VOUT3 26 1 VIN1 VOUT1 24 VIN1 1 10 VOUT1 2 VIN2 VOUT2 19 4 VIN4 VOUT4 25 2 VIN2 VOUT2 23 VIN2 2 9 VOUT2 3 VIN3 VOUT3 18 5 VIN5 VOUT5 24 3 VIN3 VOUT3 22 VS+ 3 8 VS- 4 VIN4 VOUT4 17 6 VIN6 VOUT6 23 4 VIN4 VOUT4 21 VIN3 4 7 VOUT3 5 VS+ VS- 16 7 VS+ VS- 22 5 VIN5 VOUT5 20 VIN4 5 6 VOUT4 6 VS+ VS- 15 8 VS+ VS- 21 6 VS+ VS- 19 7 VIN5 VOUT5 14 9 VIN7 VOUT7 20 7 VS+ VS- 18 8 VIN6 VOUT6 13 10 VIN8 VOUT8 19 8 VIN6 VOUT6 17 9 VIN7 VOUT7 12 11 VIN9 VOUT9 18 9 VIN7 VOUT7 16 10 VIN8 VOUT8 11 12 VIN1O VOUT10 17 10 VIN8 VOUT8 15 13 VIN11 VOUT11 16 11 VIN9 VOUT9 14 14 VIN12 VOUT12 15 12 VIN10 VOUT10 13 20 VOUT2 21 VOUT1* 22 NC 23 VIN1* 24 VIN2 26 VOUT2 EL5227 & EL5327 (24-Pin LPP) TOP VIEW 27 VOUT1 28 NC 29 NC 30 NC 31 VIN1 32 VIN2 EL5427 (32-Pin LPP) TOP VIEW VIN3 1 25 VOUT3 VIN4 2 24 VOUT4 VIN3 1 19 VOUT3 VIN5 3 23 VOUT5 VIN4 2 18 VOUT4 VIN6 4 22 VOUT6 VIN5 3 17 VOUT5 VS+ 5 Thermal Pad 21 VS- VS+ 4 Thermal Pad 16 VS- VIN10 9 17 VOUT10 2 VOUT9 12 13 VOUT8 VOUT10* 11 VIN8 7 NC 10 18 VOUT9 CVIN10* 9 VIN9 8 VIN9 8 14 VOUT7 VOUT11 16 VIN7 6 VOUT12 15 19 VOUT8 NC 14 VIN8 7 NC 13 15 VOUT6 NC 12 VIN6 5 VIN12 11 20 VOUT7 VIN11 10 VIN7 6 * Not available in EL5227 EL5127, EL5227, EL5327, EL5427 Absolute Maximum Ratings (TA = 25°C) Supply Voltage Between VS+ and VS- . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .VS- -0.5V, VS +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ, CL = 10pF to 0V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 1 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 0V 2 RIN Input Impedance CIN Input Capacitance AV Voltage Gain -4.5V ≤ VOUT ≤ 4.5V µV/°C 50 nA 1 GΩ 1.35 pF 0.99 1.01 V/V -4.85 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA -4.95 VOH Output Swing High IL = +5mA 4.85 4.95 IOUT (max) Max Output Current (Note 2) RL = 10Ω 100 ±120 55 80 V 30 mA POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V dB IS Supply Current No load (EL5127) 0.7 0.9 mA No load (EL5227) 1.2 1.4 mA No load (EL5327) 1.4 2 mA No load (EL5427) 1.6 2.2 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% tS Settling to +0.1% (AV = +1) BW CS 2.2 V/µs (AV = +1), VO = 2V step 900 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz Channel Separation f = 100kHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. 3 0.9 EL5127, EL5227, EL5327, EL5427 Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 10kΩ, CL = 10pF to 2.5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 1 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 2.5V 2 RIN Input Impedance CIN Input Capacitance AV Voltage Gain 0.5V ≤ VOUT ≤ 4.5V µV/°C 50 nA 1 GΩ 1.35 pF 0.99 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA 80 VOH Output Swing High IL = +5mA 4.85 4.95 V IOUT (max) Output Current (Note 2) RL = 10Ω 100 ±120 mA 55 80 dB POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V IS Supply Current No load (EL5127) 0.7 0.9 mA No load (EL5227) 1.1 1.35 mA No load (EL5327) 1.35 1.9 mA No load (EL5427) 1.5 2.05 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤ 4V, 20% to 80% tS Settling to +0.1% (AV = +1) (AV = +1), VO = 2V step BW -3dB Bandwidth CS Channel Separation 0.9 1.5 V/µs 1000 ns RL = 10kΩ, CL = 10pF 2.5 MHz f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ, CL = 10pF to 7.5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 18 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 7.5V 1 TCVOS Average Offset Voltage Drift (Note 1) 5 IB Input Bias Current VCM = 7.5V 2 RIN Input Impedance CIN Input Capacitance AV Voltage Gain 0.5V ≤ VOUT ≤ 14.5V µV/°C 50 nA 1 GΩ 1.35 pF 0.99 1.01 V/V 150 mV OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA 14.85 14.95 V IOUT (max) Output Current (Note 2) RL = 10Ω 100 ±120 mA 4 50 EL5127, EL5227, EL5327, EL5427 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, RL = 10kΩ, CL = 10pF to 7.5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP 55 80 MAX UNIT POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V dB IS Supply Current No load (EL5127) 0.75 0.95 mA No load (EL5227) 1.3 1.55 mA No load (EL5327) 1.5 2.1 mA No load (EL5427) 1.6 2.4 mA DYNAMIC PERFORMANCE SR Slew Rate (Note 3) 1V ≤ VOUT ≤ 14V, 20% to 80% tS Settling to +0.1% (AV = +1) BW CS 2.2 V/µs (AV = +1), VO = 2V step 900 ns -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz Channel Separation f = 5MHz 75 dB NOTES: 1. Measured over operating temperature range. 2. Instantaneous peak current. 3. Slew rate is measured on rising and falling edges. 5 0.9 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves Frequency Response for Various CL Frequency Response for Various RL 20 CL = 10pF VS = ±5V Normalized Magnitude (dB) Normalized Magnitude (dB) 20 10 10kΩ 1kΩ 0 562Ω -10 150Ω -20 -30 1k 10k 100k 1M RL = 10kΩ VS = ±5V 10 47pF 12pF 0 1nF -10 100pF -20 -30 1k 10M 10k 100k Frequency (Hz) Output Impedance vs Frequency 10M Maximum Output Swing vs Frequency 2000 12 Maximum Output Swing (VP-P) TA = 25°C VS = ±5V Output Impedance (Ω) 1M Frequency (Hz) 1600 1200 800 400 0 1k 10k 100k VS = ±5V RL = 10kΩ CL = 12pF TA = 25°C 10 8 6 4 2 0 10k 1M 100k Frequency (Hz) 1M 10M Frequency (Hz) Total Harmonic Distortion + Noise vs Frequency Input Voltage Noise Spectral Density vs Frequency 0.12 300 THD + Noise (%) 10 0.08 0.06 0.04 0.02 10k 1M 100k 10M 0 1k 100M 10k Frequency (Hz) Small Signal Overshoot vs Load Capacitance Input Offset Voltage Distribution 100 16 14 70 % of Buffers 60 50 40 12 10 8 6 30 4 20 2 Capacitance (pF) 6 Input Offset Voltage (mV) 10 8 6 4 2 1k -4 0 100 -6 0 10 -8 Overshoot (%) 80 18 V VSS=±5V = ±5V R RLL=10kΩ = 10kΩ V VIN = ±50mV IN=±50m V TA = 25°C -10 90 100k Frequency (Hz) 0 1k -2 Voltage Noise (nV/√Hz) 0.1 100 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves (Continued) Input Bias Current vs Temperature Output High Voltage vs Temperature 3.5 4.955 3 2.5 2 1.5 VS = ±5V IOUT = 5mA 4.95 Output High Voltage (V) Input Bias Current (nA) VS = ±5V 4.945 4.94 4.935 4.93 1 4.925 -35 -15 5 25 45 85 65 -35 -15 Temperature (°C) Output Low Voltage vs Temperature 25 45 65 85 45 65 85 Voltage Gain vs Temperature -4.938 1.0045 VS = ±5V IOUT = -5mA VS = ±5V 1.004 -4.942 Voltage Gain (V/V) Output Low Voltage (V) 5 Temperature (°C) -4.946 -4.95 1.0035 1.003 1.0025 1.002 -4.954 1.0015 -4.958 1.001 -35 -15 5 25 45 85 65 -35 -15 Temperature (°C) 5 25 Temperature (°C) Slew Rate vs Temperature Supply Current per Channel vs Temperature 2.255 0.185 VS = ±5V Supply Current (mA) Slew Rate (V/µs) 2.245 2.235 2.225 0.18 0.175 0.17 0.165 2.215 -40 VS=±5V -20 0.16 0 20 40 60 -35 80 Temperature (°C) -15 5 25 Temperature (°C) Large Signal Transient Response Supply Current per Channel vs Supply Voltage 0.195 TA = 25°C Supply Current (mA) 0.19 0.185 1V/div 0.18 0.175 0.17 0.165 4 6 8 10 12 Supply Voltage (V) 7 14 16 18 4µs/div 45 65 85 EL5127, EL5227, EL5327, EL5427 Typical Performance Curves (Continued) Small Signal Transient Response 3 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity (4layer) Test Board, LPP exposed diepad soldered to PCB per JESD51-5 2.857W P3 2= 2 /W C 7° =3 1.5 °C 4 P2 35 LP 20mV/di LP /W Power Dissipation (W) 2.5 2.703W 1 0.5 0 1µs/div 0 25 50 75 85 100 125 150 Ambient Temperature (°C) Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1.4 1.2 1.176W 1.111W 1 TSSOP24 θJA=85°C/W 0.8 TSSOP28 θJA=75°C/W 0.6 TSSOP20 θJA=90°C/W 0.4 486mW 0.5 Power Dissipation (W) Power Dissipation (W) 0.6 1.333W Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 0.4 M SO P1 20 0 6° C/ W 0.3 0.2 0.1 0.2 0 0 0 25 50 75 85 100 0 125 25 Ambient Temperature (°C) TSSOP28 θJA=120°C/W 0.5 TSSOP24 θJA=128°C/W 0.4 0.3 0.2 TSSOP20 θJA=140°C/W 0.1 0.8 M SO P1 11 5° 0 C/ W 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0 25 50 75 85 100 0 125 25 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 and SEMI G42-88 (Single Layer) Test Board 0.8 758mW 0.7 714mW 0.6 LPP32 132°C/W 0.5 0.4 LPP24 140°C/W 0.3 0.2 0.1 0 0 25 50 75 85 100 Ambient Temperature (°C) 8 50 75 85 Ambient Temperature (°C) Ambient Temperature (°C) Power Dissipation (W) Power Dissipation (W) 714mW 0.6 125 870mW 0.9 781mW 0.7 100 1 833mW 0.8 75 85 Package Power Dissipation vs Ambient Temperature JEDEC JESD51-7 High Effective Thermal Conductivity Test Board Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board Power Dissipation (W) 0.9 50 Ambient Temperature (°C) 125 150 100 125 EL5127, EL5227, EL5327, EL5427 Applications Information Short Circuit Current Limit Product Description The EL5127, EL5227, EL5327, and EL5427 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (120µA per buffer). These features make the EL5127, EL5227, EL5327, and EL5427 ideal for a wide range of general-purpose applications. When driving a load of 10kΩ and 12pF, the EL5127, EL5227, EL5327, and EL5427 have a -3dB bandwidth of 2.5MHz and exhibits 2.2V/µs slew rate. Operating Voltage, Input, and Output The EL5127, EL5227, EL5327, and EL5427 are specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5127, EL5227, EL5327, and EL5427 specifications are stable over both the full supply range and operating temperatures of -40°C to +85°C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5127, EL5227, EL5327, and EL5427 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 1 shows the input and output waveforms for the device. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. 10µs VS=±5V TA=25°C VIN=10VP-P Output 5V Output Phase Reversal The EL5127, EL5227, EL5327, and EL5427 are immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. 1V 10µs VS=±2.5V TA=25°C VIN=6VP-P 1V FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation Input 5V The EL5127, EL5227, EL5327, and EL5427 will limit the short circuit current to ±120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±30mA. This limit is set by the design of the internal metal interconnects. FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT With the high-output drive capability of the EL5127, EL5227, EL5327, and EL5427 buffer, it is possible to exceed the 125°C “absolute-maximum junction temperature” under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - TAMAX P DMAX = --------------------------------------------Θ JA 9 EL5127, EL5227, EL5327, EL5427 Driving Capacitive Loads where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + - V OUT i ) × I LOAD i ] when sourcing, and: P DMAX = Σi [ V S × I SMAX + ( V OUT i - V S - ) × I LOAD i ] when sinking. where: i = 1 to Total number of buffers VS = Total supply voltage ISMAX = Maximum quiescent current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. The EL5127, EL5227, EL5327, and EL5427 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10kΩ with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 50Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a “snubber” circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150Ω and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1µF ceramic capacitor should be placed from VS+ pin to VS- pin. A 4.7µF tantalum capacitor should then be connected from VS+ pin to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10