IDT 1338C

DATASHEET
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
IDT1338
General Description
Features
The IDT1338 is a serial real-time clock (RTC) device that
consumes ultra-low power and provides a full binary-coded
decimal (BCD) clock/calendar with 56 bytes of battery
backed Non-Volatile Static RAM. The clock/calendar
provides seconds, minutes, hours, day, date, month, and
year information. The clock operates in either the 24-hour
or 12-hour format with AM/PM indicator. The end of the
month date is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. Access to
the clock/calendar registers is provided by an I2C interface
capable of operating in fast I2C mode. Built-in Power-sense
circuitry detects power failures and automatically switches
to the backup supply, maintaining time and date operation.
• Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
• 56-Byte battery-backed Non Volatile RAM for data
storage
•
•
•
•
Fast mode I2C Serial interface
Automatic power-fail detect and switch circuitry
Programmable square-wave output
Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
• Industrial temperature range (-40°C to +85°C)
Applications
• Telecom (Routers, Switches, Servers)
• Handheld (GPS, Point of Sale POS terminals)
• Consumer Electronics (Set-Top Box, Digital Recording,
Network Applications, Digital photo frames)
• Office (Fax/Printers, Copiers)
• Medical (Glucometer, Medicine Dispensers)
• Others (Thermostats, Vending Machines, Modems, Utility
Meters)
Block Diagram
Crystal inside package
for 16-pin SOIC ONLY
X1
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
32.768 kHz
Oscillator and
Divider
MUX/
Buffer
SQW/OUT
X2
VCC
GND
VBAT
Power
Control
Control
Logic
I2C
Interface
56 Byte
RAM
Clock, Calendar
Counter
SCL
SDA
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 1
1 Byte
Control
7 Bytes
Buffer
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Pin Assignment (8-pin MSOP/8-pin SOIC)
X1
8
1
X2
2
VBAT
3
GND
4
IDT
1338
7
VCC
SQW/OUT
RTC
Pin Assignment (16-pin SOIC)
SCL
1
16
SQW/OUT
2
15
GND
3
14
VBAT
13
NC
12
NC
SDA
6
SCL
VCC
5
SDA
NC
4
NC
5
NC
6
11
NC
NC
7
10
NC
NC
8
9
NC
IDT
1338C
Pin Descriptions
Pin
Number
8MSOP,
8SOIC
16SOIC
Pin
Name
1
—
X1
2
—
X2
3
14
VBAT
Backup Supply Input for Lithium Coin Cell or Other Energy Source. Battery voltage must be held
between the minimum and maximum limits for proper operation. Diodes placed in series
between the backup source and the VBAT pin may prevent proper operation. If a backup supply is
not required, VBAT must be connected to ground.
4
15
GND
Connect to ground.
5
16
SDA
Serial data input/output. SDA is the input/output pin for the I2C serial interface. It is an open-drain
output and requires an external pull-up resistor (2 Kohm typical).
6
1
SCL
Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an
open-drain output and requires an external pull-up resistor (2 Kohm typical)
7
2
8
3
VCC
Device power supply. When voltage is applied within specified limits, the device is fully
accessible by I2C and data can be written and read.
—
4 - 13
NC
No connect. These pins are unused and must be connected to ground for proper operation.
Pin Description/Function
Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is designed
for operation with a crystal having a specified load capacitance (CL) of 12.5 pF. An external
32.768 kHz oscillator can also drive the IDT1338. In this configuration, the X1 pin is connected to
the external oscillator signal and the X2 pin is left floating.
SQW/OUT Square-Wave/Output driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin
outputs one of four square-wave frequencies (1 Hz, 4 kHz, 8 kHz, 32 kHz). It is an open drain
output and requires an external pull-up resistor (10K ohm typical). Operates when the device is
powered with VCC or VBAT.
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Typical Operating Circuit
VCC
VCC
2k
2k
CRYSTAL
VCC
X1
VCC
X2
SCL
CPU
SDA
10k
SQW/OUT
IDT1338
GND
VBAT
+
-
Detailed Description
The following sections discuss in detail the Oscillator block,
Power Control block, Clock/Calendar Register Block and
Serial I2C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1338 RTC are:
• Recommended Load Capacitance
• Crystal Effective Series Resistance (ESR)
• Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 3
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
Note: IDT1338CSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal VCC (+3.3 V) and
TA=+25°C.
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the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
PCB Layout
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1338
typically have a frequency tolerance of +/-20ppm at +25°C.
Specifications for a typical 32kHz crystal used with our
device are shown in the table below.
Parameter
Symbol
Nominal Freq.
fO
Series Resistance
ESR
Load Capacitance
CL
Min
Typ
Max Units
32.768
kHz
50
12.5
kΩ
pF
PCB Design Consideration
• Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
• Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
• The oscillation loop current flows between the crystal and
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 KHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
• To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
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Power Control
RTC
Table 1. Power Control
A precise, temperature-compensated voltage reference and
a comparator circuit provides power-control function that
monitors the VCC level. The device is fully accessible and
data can be written and read when VCC is greater than VPF.
However, when VCC falls below VPF, the internal clock
registers are blocked from any access. If VPF is less than
VBAT, the device power is switched from VCC to VBAT when
VCC drops below VPF. If VPF is greater than VBAT, the device
power is switched from VCC to VBAT when VCC drops below
VBAT. The registers are maintained from the VBAT source
until VCC is returned to nominal levels (Table 1). After VCC
returns above VPF, read and write access is allowed after
tREC (see the “Power-Up/Down Timing” diagram).
Supply Condition
Read/Write
Access
Powered
By
VCC < VPF, VCC < VBAT
No
VBAT
VCC < VPF, VCC > VBAT
No
VCC
VCC > VPF, VCC < VBAT
Yes
VCC
VCC > VPF, VCC > VBAT
Yes
VCC
Power-up/down Timing
Table 2. Power-up/down Characteristics
Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
(see note below)
Max.
Units
2
ms
Recovery at Power-up
tREC
VCC Fall Time; VPF(MAX) to VPF(MIN)
tVCCF
300
µs
VCC Rise Time; VPF(MIN) to VPF(MAX)
tVCCR
0
µs
Note: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay
occurs.
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RTC and RAM Address Map
The address map for the RTC and RAM registers shown in Table 3. The RTC registers and control register are located in
address locations 00H to 07H The RAM registers are located in address locations 08H to 3FH. During a multibyte access,
when the register pointer reaches 3FH (the end of RAM space) it wraps around to location 00H (the beginning of the clock
space). On an I2C START, STOP, or register pointer incrementing to location 00H, the current time and date is transferred to
a second set of registers. The time and date in the secondary registers are read in a multibyte data transfer, while the clock
continues to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Table 3. RTC and RAM Address Map
Address
Bit 7
Bit 6
Bit 5
00H
CH
10 seconds
01H
0
10 minutes
02H
0
12/24
03H
0
0
04H
0
0
05H
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Range
Seconds
Seconds
00 - 59
Minutes
Minutes
00 - 59
Hour
Hours
1 - 12
+ AM/PM
00 - 23
Day
1-7
Date
Date
01 - 31
Month
Month
01 - 12
Year
Year
00 - 99
AM/PM
06H
07H
10 hour
10 hour
0
0
0
Day
10 date
0
10 month
10 year
OUT
0
OSF
SQWE
0
08H 3FH
0
RS1
RS0
Control
RAM 56 x 8
00H - FFH
Note: Bits listed as “0” should always be written and read as 0.
Clock and Calendar
Table 3 shows the address map of the RTC registers. The
time and date information is obtained by reading the
appropriate register bytes. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the BCD
format. Bit 7 of Register 0 is the clock halt (CH) bit. When
this bit is set to 1, the oscillator is disabled. When cleared to
0, the oscillator is enabled. The clock can be halted
whenever the timekeeping functions are not required, which
decreases VBAT current.
date registers, the user buffers are synchronized to the
internal registers on any start or stop, and when the address
pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers
occurs on the acknowledge pulse from the device. To avoid
rollover issues, once the countdown chain is reset, the
remaining time and date registers must be written within one
second. If enabled, the 1 Hz square-wave output transitions
high 500 ms after the seconds data transfer, provided the
oscillator is already running.
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result in
undefined operation.
Note that the initial power-on state of all registers,
unless otherwise specified, is not defined. Therefore, it
is important to enable the oscillator (CH = 0) during
initial configuration.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 6
The IDT1338 runs in either 12-hour or 24-hour mode. Bit 6
of the hours register is defined as the 12-hour or 24-hour
mode-select bit. When high, the 12-hour mode is selected.
In the 12-hour mode, bit 5 is the AM/PM bit, with logic high
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being PM. In the 24-hour mode, bit 5 is the second 10-hour
bit (20–23 hours). If the 12/24-hour mode select is changed,
the hours register must be re-initialized to the new format.
On an I2C START, the current time is transferred to a second
set of registers. The time information is read from these
secondary registers, while the clock continues to run. This
eliminates the need to re-read the registers in case of an
update of the main registers during a read.
Table 4. Control Register (07H)
The control register controls the operation of the SQW/OUT pin and provides oscillator status.
Bit #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
OUT
0
OSF
SQWE
0
0
RS1
RS0
POR
1
0
1
1
0
0
1
1
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE
= 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time
period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when
the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are
examples of conditions that may cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC and VBAT are insufficient to support oscillation.
3) The CH bit is set to 1, disabling the oscillator.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves
the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either VCC or
VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the square-wave
output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits.
Table 5. Square Wave Output
OUT
RS1
RS0
SQW Output
SQWE
X
0
0
1 Hz
1
X
0
1
4.096 kHz
1
X
1
0
8.192 kHz
1
X
1
1
32.768 kHz
1
0
X
X
0
0
1
X
X
1
0
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I2C Serial Data Bus
The IDT1338 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions. The IDT1338 operates as
a slave on the I2C bus. Within the bus specifications, a
standard mode (100 kHz maximum clock rate) and a fast
mode (400 kHz maximum clock rate) are defined. The
IDT1338 works in both modes. Connections to the bus are
made via the open-drain I/O lines SDA and SCL.
RTC
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
The following bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
not limited, and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
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Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit. This
is followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
The IDT1338 can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 9
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1338 address, which is 1101000,
followed by the direction bit (R/W), which is 0 for a write.
After receiving and decoding the slave address byte the
slave outputs an acknowledge on the SDA line. After the
IDT1338 acknowledges the slave address + write bit, the
master transmits a register address to the IDT1338. This
sets the register pointer on the IDT1338, with the IDT1338
acknowledging the transfer. The master may then transmit
zero or more bytes of data, with the IDT1338 acknowledging
each byte received. The address pointer increments after
each data byte is transferred. The master generates a STOP
condition to terminate the data write.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1338 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data
Read–Slave Transmitter Mode” figure). The slave address
byte is the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1338 address, which is 1101000, followed by
the direction bit (R/W), which is 1 for a read. After receiving
and decoding the slave address byte the slave outputs an
acknowledge on the SDA line. The IDT1338 then begins to
transmit data starting with the register address pointed to by
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the register pointer. If the register pointer is not written to
before the initiation of a read mode the first address that is
read is the last one stored in the register pointer. The
address pointer is incremented after each byte is
transferred. The IDT1338 must receive a “not acknowledge”
to end a read.
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
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Handling, PCB Layout, and Assembly
The IDT1338 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should
be taken to ensure that excessive shocks are avioded. Ultarsonic cleaning equipment should be avioded to prevent damage
to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line.
All NC (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must
be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device
(MSD) classifications.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1338. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Voltage Range on Any Pin Relative to Ground
-0.3 V to +6.0 V
Storage Temperature
-55 to +125° C
Soldering Temperature
260° C
Recommended DC Operating Conditions
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3 V,
TA = +25°C, unless otherwise noted.) (Note 1)
Parameter
Symbol
Min.
TA
-40
VBAT Input Voltage, Note 2
VBAT
1.3
Pull-up Resistor Voltage (SQW/OUT), Note 2
VPU
Logic 1, Note 2
VIH
Logic 0, Note 2
VIL
Ambient Operating Temperature
Typ.
3.0
Max.
Units
+85
°C
3.7
5.5
V
0.7VCC
VCC + 0.3
V
-0.3
+0.3VCC
V
Supply Voltage
IDT1338-18
IDT1338-31
VCC
VPF
1.8
5.5
VPF
3.3
5.5
1.40
1.62
1.71
2.45
2.7
2.97
V
Power Fail Voltage
IDT1338-18
IDT1338-31
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 11
VPF
IDT1338
V
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DC Electrical Characteristics
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3 V,
TA = +25°C, unless otherwise noted.) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Leakage
ILI
Note 3
1
µA
I/O Leakage
ILO
Note 4
1
µA
VCC > 2 V; VOL = 0.4 V
3.0
mA
VCC < 2 V; VOL = 0.2VCC
3.0
VCC > 2 V; VOL = 0.4 V
3.0
mA
1.71 V < VCC < 2 V;
VOL = 0.2VCC
3.0
mA
1.3 V < VCC < 1.71 V;
VOL = 0.2VCC
250
µA
SDA Logic 0 Output
SQW/OUT Logic 0 Output
Active Supply Current (Note 5)
Standby Current (Note 6)
VBAT Leakage Current (VCC Active)
IOLSDA
IOLSQW
ICCA
ICCS
IDT1338-18
75
150
IDT1338-31; VCC < 3.63 V
120
200
IDT1338-31; 3.63 V < VCC <
5.5 V
µA
325
IDT1338-18
60
100
IDT1338-31; VCC < 3.63 V
85
125
IDT1338-31; 3.63 V < VCC <
5.5 V
µA
200
IBATLKG
25
100
nA
DC Electrical Characteristics
(VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0 V, TA = +25°C, unless
otherwise noted.) (Note 1)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
VBAT Current (OSC ON); VBAT =3.7 V,
SQW/OUT OFF
IBATOSC1 Note 7
800
1200
nA
VBAT Current (OSC ON); VBAT =3.7 V,
SQW/OUT ON
IBATOSC2 Note 7
1025
1400
nA
10
100
nA
VBAT Data-Retention Current
(OSC OFF); VBAT =3.7 V
IBATDAT
Note 7
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AC Electrical Characteristics
(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C) (Note 1)
Parameter
SCL Clock Frequency
Symbol
fSCL
Conditions
Fast Mode
Min.
Hold Time (Repeated) START
Condition, Note 8
Low Period of SCL Clock
High Period of SCL Clock
tBUF
tHD:STA
tLOW
tHIGH
Setup Time for a Repeated START
Condition
tSU:STA
Data Hold Time (Notes 9, 10)
tHD:DAT
Data Setup Time (Note 11)
tSU:DAT
Rise Time of Both SDA and SCL
Signals (Note 12)
tR
Fall Time of Both SDA and SCL Signals
(Note 12)
tF
Setup Time for STOP Condition
tSU:STO
Max. Units
100
400
0
100
Standard Mode
Bus Free Time Between a STOP and
START Condition
Typ.
Fast Mode
1.3
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
4.0
Fast Mode
1.3
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
4.0
Fast Mode
0.6
Standard Mode
4.7
Fast Mode
0
Standard Mode
0
Fast Mode
100
Standard Mode
250
µs
µs
µs
µs
µs
0.9
20 + 0.1CB
300
Standard Mode
20 + 0.1CB
1000
Fast Mode
20 + 0.1CB
300
Standard Mode
20 + 0.1CB
300
0.6
Standard Mode
4.0
Capacitive Load for Each Bus Line
(Note 12)
CB
I/O Capacitance (SDA, SCL)
CI/O
Note 13
Oscillator Stop Flag (OSF) Delay
tOSF
Note 14
µs
ns
Fast Mode
Fast Mode
kHz
ns
ns
µs
100
400
pF
10
pF
ms
WARNING: Negative undershoots below 0.3 V while the device is in battery-backed mode may cause loss
of data.
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: All voltages referenced to ground.
Note 3: SCL only.
Note 4: SDA and SQW/OUT.
Note 5: ICCA—SCL clocking at max frequency = 400 kHz.
Note 6: Specified with the I2C bus inactive.
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Note 7: Measured with a 32.768 kHz crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) +
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
Note 12: CB—total capacitance of one bus line in pF.
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the
voltage range of 0.0V < VCC < VCCMAX and 1.3 V < VBACKUP < 3.7 V.
Timing Diagram
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Typical Operating Characteristics
IBAT vs VBAT
(IDT1338-31)
Icc vs Vcc
(IDT1338-31)
734
25
654
SQWE=1
614
SQWE=0
574
Supply Current (uA)
Supply current (nA)
694
534
494
20
15
SCL=400kHz
SCL=0Hz
10
5
0
1.3
1.8
2.3
2.8
3.3
2.7
3.2
3.7
VBat (V)
4.7
5.2
Oscillator Frequency vs Supply Voltage
IBAT vs Temperature
32767.950000
700
SQWE=1
600
SQWE=0
500
Frequency (Hz)
800
IBAT (nA)
4.2
Vcc (V)
400
-40
-20
0
20
40
60
80
Temperature (C)
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 15
32767.900000
Freq
32767.850000
32767.800000
32767.750000
2.7
3.2
3.7
4.2
4.7
5.2
Oscillator Supply Voltage (V)
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Thermal Characteristics for 8MSOP
Parameter
Symbol
Thermal Resistance Junction to
Ambient
θJA
Thermal Resistance Junction to Case
θJC
Conditions
Min.
Still air
Typ.
Max. Units
95
° C/W
48
° C/W
Thermal Characteristics for 8SOIC
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θ JA
Still air
150
° C/W
θ JA
1 m/s air flow
140
° C/W
θ JA
3 m/s air flow
120
° C/W
40
° C/W
θ JC
Thermal Characteristics for 16SOIC
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
120
° C/W
θJA
1 m/s air flow
115
° C/W
θJA
3 m/s air flow
105
° C/W
58
° C/W
θJC
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Marking Diagram (8 MSOP)
RTC
Marking Diagram (16 SOIC)
16
38GI
YWW$
18GI
YWW$
IDT1338-31DVGI
5
IDT
1338C-31
SRI
#YYWW**$
IDT1338-18DVGI
1
Marking Diagram (8 SOIC)
8
9
8
8
IDT1338C-31SRI
5
16
IDT1339
-18DCGI
#YYWW$
IDT1338
-31DCGI
#YYWW$
1
4
IDT1338-31DCGI
1
IDT
1338C-18
SRI
#YYWW**$
4
IDT1338-18DCGI
9
1
8
IDT1338C-18SRI
Notes:
1. ‘#’ is the lot number.
2. ‘$’ is the assembly mark code.
3. YYWW is the last two digits of the year and week that the
part was assembled.
4. “G” denotes RoHS compliant package.
5. “I” denotes industrial grade.
6. Bottom marking: country of origin if not USA.
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 17
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
C
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Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
8
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
IN D E X
AREA
1
2
D
Min
Max
-1.10
0
0.15
0.79
0.97
0.22
0.38
0.08
0.23
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 Basic
0.40
0.80
0°
8°
0.10
Inches*
Min
Max
-0.043
0
0.006
0.031
0.038
0.008
0.015
0.003
0.009
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
0.016
0.032
0°
8°
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
-C e
b
S E A T IN G
P LA N E
L
aaa
C
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Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
INDEX
AREA
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
E
1 2
D
A
2
A
1
b
Max
-2.65
0.10
-2.05
2.55
0.33
0.51
0.18
0.32
10.10
10.50
10.00
10.65
7.40
7.60
1.27 Basic
0.40
1.27
0°
8°
0.10
Min
Max
-0.104
0.0040
-0.081
0.100
0.013
0.020
0.007
0.013
0.397
0.413
0.394
0.419
0.291
0.299
0.050 Basic
0.016
0.050
0°
8°
0.004
*For reference only. Controlling dimensions in mm.
A
e
Min
Inches*
c
- CSEATING
PLANE
aaa
C
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 20
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Ordering Information
Part / Order Number
1338-18DVGI
1338-18DVGI8
1338-18DCGI
1338-18DCGI8
1338C-18SRI
1338C-18SRI8
1338-31DVGI
1338-31DVGI8
1338-31DCGI
1338-31DCGI8
1338C-31SRI
1338C-31SRI8
Marking
Shipping Packaging
Package
see page 17
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin MSOP
8-pin MSOP
8-pin SOIC
8-pin SOIC
16-pin SOIC
16-pin SOIC
8-pin MSOP
8-pin MSOP
8-pin SOIC
8-pin SOIC
16-pin SOIC
16-pin SOIC
Temperature
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
C
C
C
C
C
C
C
C
C
C
C
C
The IDT1338 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS
requirements. The lead finish is JESD91 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History
Rev.
Originator
Date
A
J. Sarma
01/29/08
New device. Preliminary release.
B
J.Sarma
03/28/08
Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices.
C
J.Sarma
04/03/04
combined -3 and -33 parts to -31
D
J.Sarma
05/19/08
The part number for 16pin RoHS complaint part has now changed from IDT1338C-31SOGI to
IDT1338C-31SRI and the IDT1338C-18SOGI changed to IDT1338C-18SRI
E
J.Sarma
10/29/08
F
J.Sarma
11/10/08
Updated Block Diagram; Typical Operating Characteristics charts.
G
J.Sarma
11/13/08
Updated graphs in “Typical Operating Characteristics; added “Typical Operating Circuit” diagram
H
J.Sarma
11/18/08
Updated graphs in “Typical Operating Characteristics; updated Block Diagram; added “Battery
Backed” to device title.
I
J.Sarma
12/02/08
Updated Typical Operating Characteristics graphs; added marking diagrams.
11/10/09
Added “Handling, PCB Layout, and Assembly” section.
J
Description of Change
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA