APPLICATION NOTE Date: 02-07-05 Page 1 of 3 AN-Number: AN2002-05 Short Circuit Operation of 6.5kV IGBTs This application note presents aspects for driving IGBTs, which allow a safe short circuit operation of 6.5kV IGBTs. The following picture shows a short circuit turn-off of a FZ600R65KF1 with and without a clamping of the gate voltage under identical operation conditions (Vce (black) 1kV/div, Ic (red) 1kA/div, Vge (blue) 5VGE/div). It is apparent that the gate voltage rate of rise on the left side is limited and no overswing occurs: the max. gate voltage reaches 15.3V and the peak short circuit current is limited to approximately 3000A. In contrast, in the picture on the right, the gate voltage rises without clamping to 16.3V and the short circuit current reaches a peak value of 3800A. VGE VCE IC The reason for this behavior is the positive feedback provided by the Miller capacity, which feeds back a positive current into the gate when the collector voltage is rising. This results in an increase in the gate voltage as well as the short circuit peak current. They may exceed the maximum admissible current level (for the FZ600R65KF1 e.g. 6xInom = 3600A), which can lead to the thermal destruction of the module. When considering the tolerances of the line voltages, common working voltages for 6.5kV IGBT are in the range of 3000...4400V DC. Due to a strong increase of the Miller capacity at low Vcc, possible oscillations at short circuit tests at voltages below 2500V. eupec GmbH Max -Planck-Straße 5 D-59581 Warstein Author: Thomas Schütze Tel. +49(0)2902 764-1153 Fax +49(0)2902 764-1150 Email: [email protected] An Infineon Technologies Company www.eupec.com low voltage levels may occur. We strongly recommend not to perform Short circuit operation of 6.5kV IGBTs Date: 02-07-05 Page 2 of 3 AN-Number: AN2002-05 The ISC_peak / Inom. ISC_peak = f(VGE_peak) dependency between 8 peak short circuit current and 7 gate voltage is given in the 6 diagram 5 on the left. To ensure the safe operation 4 3 under short circuit conditions, 2 an effective limitation of the 1 SC peak current by means of 0 12 13 14 15 16 17 clamping the gate voltage to values below 15.3 V has to VGE_peak [V] be guaranteed. Measures to limit the gate voltage and SC current respectively are: 1) Clamping of the gate voltage to a fixed potential If the gate driver can supply a stable, internal 15V, the gate voltage should be clamped to this potential by a feedback diode with a low voltage drop (Schottky diode). The lower the inductive connection between the 15V supply and gate terminals, the more effective this measure will be. 2) Clamping of the gate voltage by gate-emitter Zener diodes The closer the diodes are mounted to +15V Dshottky the auxiliary terminals of the module, the more effective this measure. Diodes with low temperature drift and tolerance Rg (e.g. transient voltage suppressor diVge odes) should be used. Vzge In accordance with the above explanations, the following condition has to be fulfilled at room temperature: Vz*(1+a T*(ϑ-25°C))*(1+tol) ≤ 15.3V with Vz : nominal Zener diode voltage a T: temperature coefficient Short circuit operation of 6.5kV IGBTs Date: 02-07-05 Page 3 of 3 AN-Number: AN2002-05 ϑ: max. operation temperature tol: tolerance of the Zener diode selected: 1.5KE6.8CA plus 1.5KE7.5CA (bi-directional) -4 -1 a T: 8*10 K (~12mV/K) ϑ: 50°C (assumption) with tol: 5% At a chosen gate voltage of 14.0V the turn-on resistor Rgon can be reduced to 2.7 Ohm. This can keep the switching losses at the value given in the data sheet for 15V. The reduction of the gate voltage has a negligible influence on the turn-off losses. 3) Introduction of a negative emitter feedback For this measure the emitter of the gate-driver must not be – as is customary – connected to the auxiliary emitter, but to the main emitter terminals. The induced voltage drop inside the module is superimposed to the externally applied gate voltage. Due to the typically high short circuit di/dts, the negative feedback leads to an effective reduction of the gate voltage. In addition, an overshoot of the gate voltage can be avoided. The impact of this measure is shown in the following picture: T T 3> T 21 > VGE 3> T T 1) Ch 1: 2) Ch 2: 3) Ch 3: 1 kVolt 2 us 10 Volt 2 us 5 Volt 2 us 21 > T VCE 1) Ch 1: 2) Ch 2: 3) Ch 3: 1 kVolt 2 us 10 Volt 2 us 5 Volt 2 us IC This dynamic reduction of the gate voltage also lowers the di/dt of the regular turn-on process. By omitting the CGE which is given in the data sheet, but not required under this operation condition any longer, this measure does not result in an increase in the turn-on losses.