Vortex86EX DMP Electronics INC 32-Bit x86 Micro Processor Overview The Vortex86EX is a high performance and fully static 32- with DMA and interrupt timer/counter included), Fast Ethernet, bit X86 processor with the compatibility of Windows based, FIFO UART, USB2.0 Host and SD/SATA controller within a Linux and most popular 32-bit RTOS. It also integrates 16KB single 288-pin LBGA package to form a system-on-a-chip write through 4-way L1 cache, 128KB write through/write back (SOC). It provides an ideal solution for the embedded system 4-way L2 cache, PCIE bus in at 2.5 GHz, DDR3, ROM to bring about desired performance. controller, xISA, I2C, SPI, IPC (Internal Peripheral Controllers Features – – – Branch target buffer – 32 I/D translation lookaside buffer Embedded I / D Separated L1 Cache – 16K I-Cache, 16K D-Cache 4-way 128KB L2 Cache Write through or write back policy DDRIII Control Interface – 16 bits data bus – 2 rank – – DDRIII clock support up to 300MHz DDRIII size support up to1Gbytes SD Interface – – – – Up to 1 sets PCIE device Supports HS, FS and LS 2 port HDA Controller – 1 input stream, 1 output stream ADC Interface x 8 I2C bus – – For boot up function from SPI flash – Half duplex – Support SPI Flash Size up to 128MB Less than 2.5uA (3.0V) power consumption in Internal RTC Mode while chip is power-off. Compatible with 16C550 / 16C552 Default internal pull-up Supports the programmable baud rate generator with the data rate from 50 to 6M bps The character options are programmable for 1 start bits; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits Support TXD_En Signal on COM1-8 Port 80h output data could be sent to COM1 by software programming Support half-duplex mode Parallel Port – Supports SPP/EPP/ECP mode General Programmable I/O – SPI Boot Interface – – – – Compliant w/t V2.1 Some master code (general call, START and CBUS) not support. 1 sets of 8254 timer controller FIFO UART Port x 10 ( 10 sets COM Port ) – – 1 port Supports FS with 3 programmable endpoint Support Max xISA Clock 33M Real Time Clock – USB 1.1 Device Support – – – – – – PCIE Target Interface USB 2.0 Host Support AT clock programmable 8/16 Bit xISA device with Zero-Wait-State Generate refresh signals to xISA interface during DRAM refresh cycle DMA Controller Interrupt Controller MTBF Counter Counter / Timers SATA 1.5G (1 Port) at IDE Secondary Channel Ethernet MAC Controller + PHY PCIE Control Interface – – – SD x 1 at IDE Primary Channel SATA Interface 1groups of controller, 4 controllers per group Each controller can configure to PWM/Servo/Sensor Interface mode Controller interconnect to the other with routing network in the same group xISA Bus Interface – – – Embedded L2 Cache – Motor Control Interface Support – – Translation Lookaside buffer – Extends CPU instruction set to include Trigonometric, Logarithmic and Exponential Implements ANSI/IEEE standard 754-1985 for binary Floating-Point Architecture Some master code (general call, START and CBUS) not support. – Support SPI Device x2 (Chip Select x2) CAN Bus Controller Branch prediction unit – Full Duplex SPI Controller – 6-stage pipeline Floating point unit support – X86 Processor Core – Supports 80 programmable I / O pins Each GPIO pin can be individually configured to be an input/output pin GPIO_P0~GPIO_P9 can be program by 8051A All GPIO port with interrupt support (input/output) PS / 2 Keyboard and Mouse Interface Support – www.dmp.com.tw Compatible with 8042 controller Vortex86EX DMP Electronics INC 32-Bit x86 Micro Processor Speaker out JTAG Interface supported for S.W. debugging Input clock – – 25 MHz 32.768 KHz Output clock – Operating Voltage Range – one clock output select from 14.318MHz /24MHz / 25MHz/ xISA Clock – Core voltage: 1.2 V ± 5% I / O voltage: 1.5V ± 5% , 3.3 V ± 10 % Operating temperature – -40℃ ~ 85℃ Package Type – Block Diagram www.dmp.com.tw 16x16mm TFBGA-288