Product Information Device Comparisons of A3955 and A4975 The Allegro® A4975 is intended as the “next generation” A3955. The most notable design upgrade is the transition from bipolar to DMOS technology. DMOS offers smaller geometries, higher power densities and better switching performance than bipolar technologies. As a result of these upgrades some parameters have changed which may require BOM changes. In most applications only the sense resistor and REF voltage need to be changed. For customers who are using the A3955 and must convert to the A4975 this document shows what changes need to be made to existing circuits in order to use the new device in a similar way. The data shown here is for reference only. Refer to the datasheets of the individual devices for parameters and detailed functional descriptions. If data in this document does not match the associated device datasheet, then please be aware that the datasheet is the governing specification document in all cases. Package B, 16-pin DIP with exposed tabs Figure 1. Both the A4975 and the A3955 are provided in the 16-pin DIP (B) and 16-pin SOIC (LB) packages, shown here (not to scale). Table of Contents Functional Block Diagrams Absolute Maximum Ratings VSENSE Range Reference Voltage and Current Regulation VREF Range RSENSE Selection VSAT versus RDS(on)X Voltage Drop Thermals Minimum Regulated Output Current Input Logic Levels 296087-AN Package LB, 16-pin SOIC with internally fused pins 2 3 3 3 3 3 3 4 4 5 5 Functional Block Diagrams 10 6 VCC PHASE 15 LOAD SUPPLY OUTB OUTA LOGIC SUPPLY A4975 16 7 V BB GROUND 4 5 UVLO & TSD 12 13 MIXED-DECAY COMPARATOR CURRENT-SENSE COMPARATOR R + – Q SENSE 11 + – S D/A w5 BLANKING DISABLE RS + – RC 3 V TH REF CT RT 2 8 9 14 D0 VCC D1 1 BLANKING GATE D2 PFD PWM LATCH 10 6 VCC PHASE 15 LOAD SUPPLY OUTB OUTA LOGIC SUPPLY A3955 16 7 VBB GROUND 4 5 UVLO & TSD 12 13 MIXED-DECAY COMPARATOR CURRENT-SENSE COMPARATOR Q S ÷3 BLANKING D/A DISABLE RS RC 3 RT V TH CT 2 8 9 14 D0 + – D1 VCC 11 + – R + – SENSE D2 1 BLANKING GATE REF PFD PWM LATCH Dwg. FP-042 296087-AN Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Absolute Maximum Ratings RSENSE Selection The VSENSE absolute maximum rating has changed from the A3955 to the A4975. The differences are shown in table 1. As noted above, the maximum allowable VSENSE voltage is decreased from 1 V to 500 mV. When calculating the value for RSENSE the upper limit is defined by the maximum load current and the maximum allowable sense voltage. For example, if 1 A load current is required, the largest sense resistor that can be used is calculated as: VSENSE Range The absolute maximum voltage on the SENSE pin has been reduced from 1 V (VCC = 5 V) for the A3955 down to 500 mV for the A4975. This makes it necessary for some customers to reduce the size of the current sensing resistor, RSENSE , so that under maximum load current the voltage on the SENSE pin does not exceed 500 mV. Reference Voltage and Current Regulation Current regulation is controlled via the voltage on the REF pin, the selected sense resistor, and the DAC settings. The reference voltage passes through a divider before it is compared to the voltage on the SENSE pin. When the sense voltage reaches the reference voltage level, the PWM latch is tripped. (2) This results in maximum sense resistor of 0.5 Ω. Picking a value slightly lower will provide a guard band for resistor tolerances. VSAT versus RDS(on)X VREF Range The A3955 has an internal divider equal to 3. This divider was increased to 5 in the A4975. As a result the voltage applied to the REF pin will result in a different output current. The new maximum ITRIP formula (DAC set to 100%) is: ITRIP ≈ VREF / (5 × RSENSE) RSENSE (max) = 500 (mV) / 1 (A) = 0.5 (Ω) (1) One of the largest differences between the A3955 and the A4975 is the change from bipolar to DMOS topology. This results in significant improvements to die size. The A4975 bridge is made with a P-channel high side and an N-channel low side. RDS(on) changes significantly with temperature, increasing as temperature rises. For every 100°C rise, RDS(on) increases by a factor of 1.6 times. The A4975 RDS(on) is specified for VBB down to 8 V. For VBB less than 8 V, RDS(on) will be higher (see table 2). Table 1. Absolute Maximum Ratings Comparison Characteristic Sense Voltage 296087-AN Symbol Notes VSENSE Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Rating A4975 A3955 0.5 1.0 Unit A 3 Thermals As stated previously, the A4975 utilizes MOS technology for the output transistors, as opposed to the bipolar transistors of the A3955. The A4975 was found to run cooler than the A3955 when both were run with VCC = 5 V and VBB = 24 V (see figure 2). The A4975 does run hotter as VBB is reduced, but still runs cooler than the A3955 at 1 A output current (see figure 3). A3955 A4975 Output Current (Arms) Figure 2. Temperature versus Output Current Temperature (°C) Note that the voltage drop across the A4975 bridge at 1.5 A is 1.5 V. At first glance the performance appears better than the A3955 which would have the same voltage drop at 0.85 A output current. The difference is that the RDS(on) in the A4975 increases with increasing temperature, resulting in a larger voltage drop at higher temperatures. Assuming an operating temperature rise of 100°C above ambient, the expected RDS(on) would be 1.6 Ω, resulting in a total voltage drop of 2.4 V at 1.5 A. A total drop of 2.4 V at operating temperature is close to the 2.6 V drop across the A3955 at the same output current. Temperature (°C) Voltage Drop Bipolar devices are defined by VCE but DMOS devices are defined by RDS(on). The voltage drop across the A4975 bridge is a function of current and the RDS(on) at the specific junction temperature. In order to make the change from the A3955 to the A4975 as transparent as possible the RDS(on) of the source plus sink drivers was selected to have similar voltage drops under similar load conditions. Tables 2 and 3 compare the A3955 bipolar bridge and the A4975 DMOS bridge. A4975 A3955 VBB (V) Figure 3. Temperature versus Load Supply Voltage Table 2. A4975 Output Resistance (DMOS Bridge) Characteristic Output On Resistance Symbol RDS(on) Test Conditions Total sink and source, IOUT = 1.5 A, VBB > 8 V, TJ = 25°C Limits Min. Typ. Max. – 1 1.4 Unit Ω Table 3. A3955 Output Saturation (Bipolar Bridge) Characteristic Symbol Test Conditions Source, IOUT = –0.85 A Output Saturation Voltage 296087-AN VCE(SAT) Limits Min. Typ. Max. – 1.0 1.2 Unit V Source, IOUT = –1.5 A – 1.3 1.5 V Sink, IOUT = 0.85 A – 0.5 0.6 V Sink, IOUT = 1.5 A – 1.3 1.5 V Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Minimum Regulated Output Current The minimum regulated output current is determined by grounding the reference input while driving a load. The current cannot get down to zero due to the blanking time. With RC values of 30 kΩ and 1000 pF, the A4975 is able to regulate to a lower current, 160 mA, than the A3955 can. The A3955 can only regulate down to 260 mA. See figures 4 and 5. IOUT Input Logic Levels The A4975 uses CMOS type inputs with thresholds that vary with the logic supply voltage. The A3955 has TTL inputs. At higher logic supply voltages the logic high requirement may not be guaranteed. See table 4. Figure 4. A4975 regulation of IOUT (green trace) IOUT Figure 5. A3955 regulation regulation of IOUT (green trace) Table 4. VIN Comparison Limits Characteristic Symbol A4975 A3955 Unit Min. Max. Min. Max. VIN(1) VCC× 0.55 – 2.0 – V VIN(0) – VCC× 0.27 – 0.8 V Logic Input Voltage 296087-AN Test Conditions Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Copyright ©2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 296087-AN Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6