PBSS302PD 40 V, 4 A PNP low VCEsat (BISS) transistor Rev. 02 — 6 December 2007 Product data sheet 1. Product profile 1.1 General description PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a SOT457 (SC-74) small Surface-Mounted Device (SMD) plastic package. NPN complement: PBSS302ND. 1.2 Features n n n n n Ultra low collector-emitter saturation voltage VCEsat 4 A continuous collector current capability IC Up to 15 A peak current Very low collector-emitter saturation resistance High efficiency due to less heat generation 1.3 Applications n n n n n n Power management functions Charging circuits DC-to-DC conversion MOSFET gate driving Power switches (e.g. motors, fans) Thin Film Transistor (TFT) backlight inverter 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −40 V - - −4 A - - −15 A - 55 75 mΩ [1] IC collector current ICM peak collector current single pulse; tp ≤ 1 ms RCEsat collector-emitter saturation resistance IC = −6 A; IB = −600 mA [2] [1] Device mounted on a ceramic Printed-Circuit Board (PCB), Al2O3, standard footprint. [2] Pulse test: tp ≤ 300 µs; δ ≤ 0.02. PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 2. Pinning information Table 2. Pinning Pin Description 1 collector 2 collector 3 base 4 emitter 5 collector 6 collector Simplified outline 6 Symbol 4 5 1, 2, 5, 6 3 1 2 3 4 sym030 3. Ordering information Table 3. Ordering information Type number PBSS302PD Package Name Description Version SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 4. Marking Table 4. Marking codes Type number Marking code PBSS302PD C9 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −40 V VCEO collector-emitter voltage open base - −40 V VEBO emitter-base voltage open collector - −5 V IC collector current - −4 A ICM peak collector current - −15 A IB base current - −0.8 A IBM peak base current single pulse; tp ≤ 1 ms - −2 A Ptot total power dissipation Tamb ≤ 25 °C [2] - 360 mW [3] - 600 mW [4] - 750 mW [1] - 1.1 W [2][5] - 2.5 W [1] single pulse; tp ≤ 1 ms PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 2 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Tj Conditions Min Max Unit junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C [1] Device mounted on a ceramic PCB, Al2O3, standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2. [5] Operated under pulsed conditions: duty cycle δ ≤ 10 % and pulse width tp ≤ 10 ms. 006aaa270 1600 Ptot (mW) 1200 800 (1) (2) (3) 400 0 −75 (4) −25 25 75 125 175 Tamb (°C) (1) Ceramic PCB, Al2O3, standard footprint (2) FR4 PCB, mounting pad for collector 6 cm2 (3) FR4 PCB, mounting pad for collector 1 cm2 (4) FR4 PCB, standard footprint Fig 1. Power derating curves PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 3 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Rth(j-a) Rth(j-sp) Conditions thermal resistance from junction to ambient in free air Min Typ Max Unit [1] - - 350 K/W [2] - - 208 K/W [3] - - 167 K/W [4] - - 113 K/W [1][5] - - 50 K/W - - 45 K/W thermal resistance from junction to solder point [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2. [4] Device mounted on a ceramic PCB, Al2O3, standard footprint. [5] Operated under pulsed conditions: duty cycle δ ≤ 10 % and pulse width tp ≤ 10 ms. 006aaa271 103 Zth(j-a) (K/W) 102 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 4 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 006aaa272 103 Zth(j-a) (K/W) 102 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 10 0.05 0.02 0.01 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 103 tp (s) FR4 PCB, mounting pad for collector 1 cm2 Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aaa273 103 Zth(j-a) (K/W) 102 duty cycle = 1 0.75 0.5 0.33 0.2 10 0.1 0.05 0.02 0.01 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 103 tp (s) FR4 PCB, mounting pad for collector 6 cm2 Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 5 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 7. Characteristics Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter ICBO Conditions collector-base cut-off VCB = −30 V; IE = 0 A current VCB = −30 V; IE = 0 A; Tj = 150 °C Typ Max Unit - - −0.1 µA - - −50 µA ICES collector-emitter cut-off current VCE = −30 V; VBE = 0 V - - −0.1 µA IEBO emitter-base cut-off current VEB = −5 V; IC = 0 A - - −0.1 µA hFE DC current gain VCE = −2 V; IC = −0.5 A 200 - - VCE = −2 V; IC = −1 A [1] 200 - - VCE = −2 V; IC = −2 A [1] 175 - - VCE = −2 V; IC = −4 A [1] 80 - - VCE = −2 V; IC = −6 A [1] 30 - - IC = −0.5 A; IB = −50 mA - −46 −60 mV IC = −1 A; IB = −50 mA - −70 −110 mV IC = −2 A; IB = −200 mA - −120 −180 mV IC = −4 A; IB = −400 mA [1] - −220 −300 mV IC = −6 A; IB = −600 mA [1] - −320 −450 mV RCEsat collector-emitter IC = −6 A; IB = −600 mA saturation resistance [1] - 55 75 mΩ VBEsat base-emitter saturation voltage - −0.8 −0.85 V VCEsat collector-emitter saturation voltage IC = −0.5 A; IB = −50 mA IC = −1 A; IB = −50 mA - −0.84 −0.9 V IC = −1 A; IB = −100 mA [1] - −0.84 −1 V IC = −4 A; IB = −400 mA [1] - −1.0 −1.1 V - −0.8 −1.0 V - 12 - ns - 43 - ns - 55 - ns VBEon base-emitter turn-on VCE = −2 V; IC = −2 A voltage td delay time tr rise time ton turn-on time ts storage time - 241 - ns tf fall time - 80 - ns toff turn-off time - 321 - ns fT transition frequency - 110 - MHz Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz - 50 - pF [1] VCC = −10 V; IC = −2 A; IBon = −0.1 A; IBoff = 0.1 A VCE = −10 V; IC = −0.1 A; f = 100 MHz Pulse test: tp ≤ 300 µs; δ ≤ 0.02. PBSS302PD_2 Product data sheet Min © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 6 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 006aaa282 600 (1) hFE 400 0 −10−1 −8 −10 −40 −4 (3) −1 IB (mA) = −400 −360 −320 −280 −240 −200 −160 −120 −80 IC (A) (2) 200 006aaa288 −12 −102 −103 −104 −105 IC (mA) VCE = −2 V 0 0 −0.4 −0.8 −1.2 −1.6 −2.0 VCE (V) Tamb = 25 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 5. DC current gain as a function of collector current; typical values 006aaa283 −1.6 VBE (V) Fig 6. Collector current as a function of collector-emitter voltage; typical values 006aaa287 −1.3 VBEsat (V) −1.2 −0.9 (1) −0.8 (2) (3) −0.5 −0.4 0 −10−1 −1 −10 −102 −103 −104 −105 IC (mA) VCE = −2 V; Tamb = 25 °C −0.1 −10−1 −1 −10 −102 −103 −104 −105 IC (mA) IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 7. Base-emitter voltage as a function of collector current; typical values Fig 8. Base-emitter saturation voltage as a function of collector current; typical values PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 7 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 006aaa284 −1 VCEsat (V) 006aaa285 −1 VCEsat (V) (1) −10−1 −10−1 (2) (3) (1) (2) −10−2 −10−2 −10−3 −10−1 −1 −10 −102 −103 −104 IC (mA) −10−3 −10−1 (3) −1 −10 −102 −103 −104 −105 IC (mA) Tamb = 25 °C IC/IB = 20 (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB = 10 Fig 9. Collector-emitter saturation voltage as a function of collector current; typical values 006aaa289 102 Fig 10. Collector-emitter saturation voltage as a function of collector current; typical values 006aaa327 103 RCEsat (Ω) RCEsat (Ω) 102 10 10 (1) (2) (3) 1 1 (1) (2) 10−1 10−2 −10−1 (3) 10−1 −1 −10 −102 −103 −104 IC (mA) 10−2 −10−1 −1 −102 −103 −104 IC (A) Tamb = 25 °C IC/IB = 20 (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB = 10 Fig 11. Collector-emitter saturation resistance as a function of collector current; typical values Fig 12. Collector-emitter saturation resistance as a function of collector current; typical values PBSS302PD_2 Product data sheet −10 © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 8 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 8. Test information − IB input pulse (idealized waveform) 90 % − I Bon (100 %) 10 % − I Boff output pulse (idealized waveform) − IC 90 % − I C (100 %) 10 % t td ts tr t on tf t off 006aaa266 Fig 13. BISS transistor switching time definition VBB RB VCC RC Vo (probe) oscilloscope 450 Ω (probe) 450 Ω oscilloscope R2 VI DUT R1 mgd624 VCC = −10 V; IC = −2 A; IBon = −0.1 A; IBoff = 0.1 A Fig 14. Test circuit for switching times PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 9 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 9. Package outline 3.1 2.7 6 3.0 2.5 1.7 1.3 1.1 0.9 5 4 2 3 0.6 0.2 pin 1 index 1 0.40 0.25 0.95 0.26 0.10 1.9 Dimensions in mm 04-11-08 Fig 15. Package outline SOT457 (SC-74) 10. Packing information Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number PBSS302PD Package SOT457 Description 3000 10000 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165 [1] For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping PBSS302PD_2 Product data sheet Packing quantity © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 10 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 11. Soldering 3.45 1.95 solder lands 0.95 solder resist 0.45 0.55 3.30 2.825 occupied area solder paste 1.60 1.70 3.10 3.20 msc422 Dimensions in mm Fig 16. Reflow soldering footprint SOT457 (SC-74) 5.30 solder lands 5.05 0.45 1.45 4.45 solder resist occupied area 1.40 msc423 4.30 Dimensions in mm Fig 17. Wave soldering footprint SOT457 (SC-74) PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 11 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PBSS302PD_2 20071206 Product data sheet - PBSS302PD_1 Modifications: PBSS302PD_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • • • • • • Legal texts have been adapted to the new company name where appropriate. Section 1.1 “General description”: amended Section 1.4 “Quick reference data”: ICM conditions amended Figure 2, 3, 4 and 6: amended Table 5: ICM conditions amended Table 5: IBM conditions amended Table 6: typing error for maximum value on 6 cm2 footprint amended Section 11 “Soldering”: added Section 13 “Legal information”: updated 20050418 Product data sheet PBSS302PD_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 12 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PBSS302PD_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 December 2007 13 of 14 PBSS302PD NXP Semiconductors 40 V, 4 A PNP low VCEsat (BISS) transistor 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Packing information. . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 December 2007 Document identifier: PBSS302PD_2