DATASHEET Programmable Timing Control HubTM for Next Gen P4TM Processor Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA. • Supports spread spectrum modulation, 0 to -0.5% down spread. Recommended Application: CK409 clock, Intel Yellow Cover part Output Features: • 3 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 7 - PCI (33MHz) • 3 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 48MHz • 2 - REF, 14.318MHz • 4 - 3V66, 66.66MHz • 1 - VCH/3V66, selectable 48MHz or 66MHz PCI MHz 33.33 Ref/N3 33.33 33.33 33.33 Hi-Z 33.33 33.33 33.33 33.33 • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning. • Supports undriven differential CPU, SRC pair in PD# and CPU_STOP# for power management. REF USB/DOT MHz MHz 14.318 48.00 Ref/N4 Ref/N5 14.318 48.00 14.318 48.00 14.318 48.00 Hi-Z Hi-Z 14.318 48.00 14.318 48.00 14.318 48.00 14.318 48.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS952601 3V66 MHz 66.66 Ref/N2 66.66 66.66 66.66 Hi-Z 66.66 66.66 66.66 66.66 Supports CPU clks up to 400MHz in test mode. REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PD# 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK Functionality SRC MHz 100/200 Ref/N1 100/200 100/200 100/200 Hi-Z 100/200 100/200 100/200 100/200 • Pin Configuration Key Specifications: • CPU/SRC outputs cycle-cycle jitter < 125ps • 3V66 outputs cycle-cycle jitter < 250ps • PCI outputs cycle-cycle jitter < 250ps • CPU outputs skew: < 100ps • +/- 300ppm frequency accuracy on CPU & SRC clocks CPU B6b5 FS_A FS_B MHz 0 0 100 0 MID Ref/N0 0 1 200 0 1 0 133 1 1 166 1 MID Hi-Z 0 0 200 0 1 400 1 1 0 266 1 1 333 ICS952601 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS_B VDDA GNDA GND IREF FS_A CPU_STOP# PCI_STOP# VDDCPU CPUCLKT2 CPUCLKC2 GND CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT0 CPUCLKC0 GND SRCCLKT SRCCLKC VDD Vtt_PWRGD# VDD48 GND 48MHz_DOT 48MHz_USB SDATA 3V66_4/VCH 56-pin SSOP & TSSOP IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 1 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME REF0 REF1 VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 PIN TYPE DESCRIPTION OUT OUT PWR IN OUT PWR OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT 14.318 MHz reference clock. 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. 21 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nomina 22 23 24 25 26 27 28 3V66_0 3V66_1 VDD3V66 GND 3V66_2 3V66_3 SCLK OUT OUT PWR PWR OUT OUT IN 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Power pin for the 3V66 clocks. Ground pin. 3.3V 66.66MHz clock output 3.3V 66.66MHz clock output Clock pin of SMBus circuitry, 5V tolerant. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 2 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Pin Description (continued) PIN # PIN NAME PIN TYPE 29 3V66_4/VCH OUT 30 31 32 33 34 SDATA 48MHz_USB 48MHz_DOT GND VDD48 I/O OUT OUT PWR PWR 35 Vtt_PWRGD# IN 36 VDD PWR 37 SRCCLKC OUT 38 SRCCLKT OUT 39 GND PWR 40 CPUCLKC0 OUT 41 CPUCLKT0 OUT 42 VDDCPU PWR 43 CPUCLKC1 OUT 44 CPUCLKT1 OUT 45 GND PWR 46 CPUCLKC2 OUT 47 CPUCLKT2 OUT 48 VDDCPU PWR 49 PCI_STOP# IN 50 CPU_STOP# IN 51 FS_A IN 52 IREF OUT 53 54 55 56 GND GNDA VDDA FS_B PWR PWR PWR IN DESCRIPTION 66.66MHz clock output for AGP support. AGP-PCI should be aligned with a skew window tolerance of 500ps. VCH is 48MHz clock output for video controller hub. Data pin for SMBus circuitry, 5V tolerant. 48MHz clock output. 48MHz clock output. Ground pin. Power pin for the 48MHz output.3.3V This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. Power supply for SRC clocks, nominal 3.3V Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic 0 level, when input low. PCI and SRC clocks can be set to Free_Running through I2C. Internal pull-up of 150K nominal. Stops all CPUCLK besides the free running clocks. Internal pull-up of 150K nominal Frequency select pin, see Frequency table for functionality This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. Ground pin for core. 3.3V power for the PLL core. Frequency select pin, see Frequency table for functionality IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 3 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor General Description ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support. Block Diagram PLL2 X1 X2 Frequency Dividers 48MHz, USB, DOT, VCH XTAL REF (1:0) CPUCLKT (2:0) CPUCLKC (2:0) SRCCLKT0 SCLK SDATA CPU_STOP# PCI_STOP# Vtt_PWRGD# PD# FS_A FS_B Programmable Spread PLL1 Programmable Frequency Dividers STOP Logic SRCCLKC0 3V66(4:0) PCICLK (6:0) Control Logic PCICLKF (2:0) I REF Power Groups Pin Number VDD GND 3 6 24 25 10,16 11,17 36 39 55 54 34 33 N/A 53 48, 42 45 Description Xtal, Ref 3V66 [0:3] PCICLK outputs SRCCLK outputs Master clock, CPU Analog 48MHz, PLL, SCLK, SDATA IREF CPUCLK clocks IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 4 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Absolute Maximum Ratings Symbol Parameter Min Max Units VDD_A 3.3V Core Supply Voltage VDD + 0.5V V VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V Ts Storage Temperature -65 150 °C Tambient Ambient Operating Temp 0 70 °C Tcase1 Case Temperature 1 115 °C Tcase2 Case Temperature 2 94 °C ESD prot Input ESD protection human body model 2000 V 1. This case temperature limits the junction temperature to <150 °C for package reliabilty 2. This case temperature limits the junction temperature to <125 °C for long term silicon reliability Notes 1 2 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage Input MID Voltage Input Low Voltage Input High Current VIH VMID VIL I IH 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors 2 1 VSS - 0.3 -5 I IL1 Input Low Current I IL2 VIN = 0 V; Inputs with pull-up resistors Operating Supply Current IDD3.3OP Full Active, CL = Full load; Powerdown Current IDD3.3PD Input Frequency 3 Pin Inductance1 Fi Lpin CIN COUT CINX Input Capacitance1 Clk Stabilization1,2 TSTAB Modulation Frequency Tdrive_SRC Tdrive_PD# Tfall_Pd# Trise_Pd# Tdrive_CPU_Stop# Tfall_CPU_Stop# Trise_CPU_Stop# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time3 SCLK/SDATA Clock/Data Fall Time3 VDD VOL TYP UNITS NOTES V V V uA -5 uA -200 uA 258 29 0.3 14.31818 all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation SRC output enable after PCI_Stop# de-assertion CPU output enable after PD# de-assertion PD# fall time of PD# rise time of CPU output enable after CPU_Stop# de-assertion PD# fall time of PD# rise time of MAX VDD + 0.3 1.8 0.8 5 30 2.7 @ IPULLUP IPULLUP 350 mA 35 12 7 5 6 5 mA mA MHz nH pF pF pF 3 1 1 1 1 1.8 ms 1,2 33 kHz 1 15 ns 1 300 us 1 5 5 ns ns 1 2 10 us 1 5 5 5.5 0.4 ns ns V V mA 1 2 1 1 1 4 TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1 TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1 1 Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2 IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 5 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER SYMBOL Current Source Output Zo1 Impedance Voltage High 1 VHigh Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-t r d-t f Duty Cycle dt3 Skew t sk3 Jitter, Cycle to cycle tjcyc-cyc CONDITIONS MIN V O = Vx 3000 Statistical measurement on single ended signal using oscilloscope math function. 660 Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V V OH = 0.525V VOL = 0.175V Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom TYP 770 MAX UNITS NOTES Ω 1 850 1 mV -150 5 150 756 -7 350 1150 -300 250 550 mV 1 1 1 12 140 mV 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 45 300 5.0015 5.0266 6.0000 6.0018 6.0320 7.5000 7.5023 5.4000 10.0000 10.0030 10.0533 1 mV 332 344 30 30 700 700 125 125 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 49 55 % 1 8 100 ps 1 37 125 ps 1 5.0000 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 6 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 3V66 Mode: 3V66 [4:0] TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 66.66MHz output nominal Tperiod Clock period 66.66MHz output spread VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage V OH @ MIN = 1.0 V IOH Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL Output Low Current VOL @ MAX = 0.4 V Edge Rate Rising edge rate Falling edge rate Edge Rate VOL = 0.4 V, VOH = 2.4 V tr1 Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 Fall Time dt1 VT = 1.5 V Duty Cycle MIN -300 14.9955 14.9955 2.4 TYP Notes 1,2 2 2 1.92 1.97 53.1 38 4 4 2 2 55 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % 15 MAX 300 15.0045 15.0799 0.55 -33 -33 30 1 1 0.5 0.5 45 1 1 1 1 1 Skew tsk1 VT = 1.5 V 38 250 ps 1 Jitter tjcyc-cyc VT = 1.5 V 3V66 139 250 ps 1 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz Electrical Characteristics - PCICLK/PCICLK_F TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX ppm see Tperiod min-max values -300 300 Long Accuracy 29.9910 30 30.0090 33.33MHz output nominal Tperiod Clock period 29.9910 30.1598 33.33MHz output spread IOH = -1 mA VOH 2.4 Output High Voltage IOL = 1 mA VOL 0.55 Output Low Voltage V OH @MIN = 1.0 V -33 IOH Output High Current VOH@ MAX = 3.135 V -33 VOL @ MIN = 1.95 V 30 IOL Output Low Current VOL @ MAX = 0.4 V 38 Edge Rate Rising edge rate 1 4 Falling edge rate 1 4 Edge Rate VOL = 0.4 V, VOH = 2.4 V tr1 0.5 1.92 2 Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 0.5 1.9 2 Fall Time dt1 VT = 1.5 V Duty Cycle 45 51.4 55 VT = 1.5 V tsk1 18 500 Skew tjcyc-cyc VT = 1.5 V 3V66 Jitter 92 250 UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps Notes 1,2 2 2 1 1 1 1 1 1 1 1 Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 2 IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 7 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - 48MHz DOT Clock TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 5-10 pF (unless otherwise specified) PARAMETER SYMBOL Long Accuracy ppm Clock period Output High Voltage Output Low Voltage Tperiod VOH VOL Output High Current IOH Output Low Current IOL Edge Rate Edge Rate CONDITIONS MIN see Tperiod min-max -200 values 66.66MHz output nominal 20.8257 IOH = -1 mA 2.4 IOL = 1 mA V OH @ MIN = 1.0 V -33 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V 30 VOL @ MAX = 0.4 V Rising edge rate 2 Falling edge rate 2 TYP MAX UNITS Notes 200 ppm 1,2 20.8340 2 38 4 4 ns V V mA mA mA mA V/ns V/ns 1 1 0.55 -33 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 0.5 0.71 1 ns 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V 0.5 0.77 1 ns 1 VT = 1.5 V 45 49 55 % 125us period jitter Long Term Jitter (8kHz frequency 0.7 2 ns modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 1 Duty Cycle dt1 1 Electrical Characteristics - VCH, 48MHz, USB TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -200 200 ppm 1,2 Tperiod 66.66MHz output nominal 20.8257 20.8340 ns 2 Clock period VOH IOH = -1 mA Output High Voltage 2.4 V IOL = 1 mA VOL 0.55 V Output Low Voltage V OH @ MIN = 1.0 V -33 mA IOH Output High Current VOH@ MAX = 3.135 V -33 mA VOL @MIN = 1.95 V 30 mA IOL Output Low Current VOL @ MAX = 0.4 V 38 mA Rising edge rate 1 2 V/ns 1 Edge Rate Edge Rate Falling edge rate 1 2 V/ns 1 VOL = 0.4 V, VOH = 2.4 V tr1 1 1.43 2 ns 1 Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time 1 1.33 2 ns 1 VT = 1.5 V dt1 45 48 55 % 1 Duty Cycle 125us period jitter 0.7 6 ns 1 Long Term Jitter (8kHz frequency modulation amplitude) 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 8 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Electrical Characteristics - REF-14.318MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 1 see Tperiod min-max values -300 300 Long Accuracy ppm Tperiod Clock period 14.318MHz output nominal 69.8270 69.8550 1 IOH = -1 mA Output High Voltage 2.4 VOH 1 IOL = 1 mA 0.4 Output Low Voltage VOL V @MIN = 1.0 V, V OH 1 Output High Current -29 -23 IOH OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 1 Output Low Current 29 27 IOL @MAX = 0.4 V 1 VOL = 0.4 V, VOH = 2.4 V 1 1.92 2 Rise Time tr1 1 V = 2.4 V, V = 0.4 V 1 1.92 2 Fall Time tf1 OH OL 1 VT = 1.5 V Skew 26 500 tsk1 1 VT = 1.5 V Duty Cycle 45 53.4 55 dt1 1 V = 1.5 V 284 1000 Jitter tjcyc-cyc T 1 UNITS ppm ns V V mA mA ns ns ps % ps Guaranteed by design, not 100% tested in production. Group to Group Skews at Common Transition Edges GROUP 200MHZ CPU to 3V661 3V66 to PCI DOT-USB DOT-VCH SYMBOL SCPU200-3V66 S3V66-PCI SDOT_USB SDOT_VCH CONDITIONS 3V66 (4:0) leads 200MHZ CPU 3V66 (4:0) leads 33MHz PCI 180 degrees out of phase in phase MIN TYP MAX UNITS -2.1 -1.6 -1.1 ns 1.50 0.00 0.00 2.59 3.50 1.00 1.00 ns ns ns 1. 3V66 MHz CL = 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms. Measured at the pins of the 952601. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 9 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor General I2C serial interface information for the ICS952601 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor Not acknowledge stoP bit 701J—01/25/10 10 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor 2 I C Table: Read-Back Register Pin # Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Name RESERVED RESERVED RESERVED RESERVED PCI_STOP# Bit 3 - Bit 2 - CPU_STOP# Bit 1 - FSB Bit 0 - FSA Control Function RESERVED RESERVED RESERVED RESERVED PCI STOP# Read Back CPU STOP Read Back Freq Select 1 Read Back Freq Select 0 Read Back 1 RESERVED RESERVED RESERVED RESERVED PWD X X X X R READBACK X R READBACK X Type - R R 0 READBACK of CPU(2:0) Frequency X X 2 I C Table: Spreading and Device Behavior Control Register Pin # Name Control Function Byte 1 SRC Free-Running 37,38 SRC/SRC# Bit 7 Control 37,38 SRC Output Control Bit 6 46,47 CPUT2/CPUC2 CPU FREEBit 5 CPUT1/CPUC1 43,44 RUNNING Bit 4 CPUT0/CPUC0 40,41 CONTROL Bit 3 CPUT2/CPUC2 Output Control 46,47 Bit 2 43,44 CPUT1/CPUC1 Output Control Bit 1 40,41 CPUT0/CPUC0 Output Enable Bit 0 Type 0 1 PWD RW FREE-RUN STOPPABLE 0 RW RW RW RW RW RW RW Disable FREE-RUN FREE-RUN FREE-RUN Disable Disable Disable Enable STOPPABLE STOPPABLE STOPPABLE Enable Enable Enable 1 1 1 1 1 1 1 2 I C Table: Output Control Register Pin # Byte 2 Control Function Type 0 1 PWD Bit 7 37,38 0: Driven in PD# RW Driven Hi-Z 0 Bit 6 37,38 0: Driven in PCI_Stop# RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 RW Driven Hi-Z 0 Bit 5 46,47 Bit 4 43,44 Bit 3 40,41 Bit 2 46,47 Bit 1 43,44 Bit 0 40,41 Name SRC_PD# Drive Mode SRC_Stop# Drive Mode CPUT2_PD# Drive Mode CPUT1_PD# Drive Mode CPUT0_PD# Drive Mode CPUT2_Stop Drive Mode CPUT1_Stop Drive Mode CPUT0_Stop Drive Mode 0:driven in PD# 1: Tri-stated 0:driven when stopped 1: Tri-stated IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 11 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor I2C Table: Output Control Register Byte 3 Pin # Type 0 1 PWD RW Enable Disable 1 RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 Bit 7 7,8,9,12,13,14,15, 18,19,20,37,38, PCI_Stop# Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 19 18 15 14 13 12 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function PCI_Stop# Control 0:all stoppable PCI and SRC are stopped Output Control Output Control Output Control Output Control Output Control Output Control Output Control Name Control Function Type 0 1 PWD 0=2x drive RW 2x drive normal 0 Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW Disable FREE-RUN FREE-RUN FREE-RUN Disable Disable Disable Enable STOPPABLE STOPPABLE STOPPABLE Enable Enable Enable 1 0 0 0 1 1 1 Control Function Output Control RESERVED Type RW ` 0 Disable - 1 Enable - PWD 1 0 Output Select RW 3V66 VCH 0 Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable 1 1 1 1 1 I2C Table: Output Control Register Byte 4 Pin # Bit 7 31 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 31 9 8 7 9 8 7 Name 48MHz_USB 2x output drive 48MHz_USB PCIF2 PCIF1 PCIF0 PCICLK_F2 PCICLK_F1 PCICLK_F0 I2C Table: Output Control Register Byte 5 Pin # Name 32 Bit 7 48MHZ_DOT Bit 6 RESERVED 3V66_4/VCH 29 Bit 5 Select 29 Bit 4 3V66_4/VCH 27 Bit 3 3V66_3 26 Bit 2 3V66_2 23 Bit 1 3V66_1 22 Bit 0 3V66_0 PCI FREE-RUN NING CONTROL IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 12 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor I2C Table: Output Control and Fix Frequency Register Byte 6 Pin # Name Control Function 1,2,7,8,9,12,13,14,1 5,18,19,20,22,23,26, Bit 7 Test Clock Mode Test Clock Mode 27,29,31,32,37,38,4 0,41,43,44,46,47 Bit 6 - RESERVED Bit 5 40,41,43,44,46,47 RESERVED Bit 4 37,38 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED RESERVED 7,8,9,12,13,14,15,18 ,19,20,22,23,26,27,2 Spread Spectrum Mode 9,31,32,37,38,40,41, 43,44,46,47 2 REF1 1 REF0 I2C Table: Vendor & Revision ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0 FS_A and FS_B Operation SRC Frequency Select - Type 0 1 PWD - Disable Enable 0 - - - 0 - Normal Test Mode 0 - 100MHz 200MHz 0 - - - 0 Spread OFF Spread ON 0 Output Control Output Control RW RW Disable Disable Enable Enable 1 1 Control Function Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 REVISION ID VENDOR ID IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 13 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor PCI Stop Functionality The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the PCI_STOP register bit. PCI_STOP# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Normal Normal Iref * 6 or Float Low 66MHz Low 48MHz 14.318MHz Note PCI_STOP# Assertion (transition from '1' to '0') The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below. Tsu PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz PCI_STOP# - De-assertion The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free manner. Tsu Tdrive_SRC PCI_STOP# PCIF[2:0] 33MHz PCI[6:0] 33MHz SRC 100MHz SRC# 100MHz IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 14 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor CPU_STOP# Functionality The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously. CPU_STOP# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Iref * 6 or Float Low Normal Normal 66MHz 33MHz 48MHz 14.318MHz Note CPU_STOP# - Assertion (transition from '1' to '0') Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True = HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is programmed to a '1', CPU outputs will be tri-stated. CPU_STOP# CPU CPU# CPU_STOP# - De-assertion (transition from '0' to '1') With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to a voltage greater than 200mV. CPU_Stop# CPU CPU# CPU Internal Tdrive_CPU_Stop, 10nS >200mV IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 15 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor PD#, Power Down PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start without glitches. PWRDWN# CPU CPU # SRC SRC# 3V66 PCIF/PCI USB/DOT REF 1 Normal Normal Normal Normal 66MHz 33MHz 48MHz 14.318MHz 0 Iref * 2 or Float Float Iref * 2 or Float Float Low Low Low Low Note Notes: 1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation. 2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses. PD# Assertion PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held low on their next high to low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated. PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC#, 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 16 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor PD# De-assertion The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD# deassertion. Tstable <1.8mS PWRDWN# CPU, 133MHz CPU#, 133MHz SRC, 100MHz SRC# 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF, 14.31818 Tdrive_PwrDwn# <300µS, >200mV 3V66_4/VCH Pin Functionality The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is 3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising edge of DOT_48 clock. 3V66 3V66_4/VCH DOT_48 7.49nS min IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 17 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Differential Clock Tristate To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop", "SRC_Stop" and "PwrDwn" register bit settings. Signal Pin PD# Pin CPU_Stop# CPU_Stop Tristate Bit Pwrdwn Tristate Bit Non-Stoppable Outputs Stoppable Outputs CPU[2:0} 1 1 X X Running Running CPU[2:0} 1 0 0 X Running Driven @ Iref x 6 CPU[2:0} 1 0 1 X Running Tristate CPU[2:0} 0 X X 0 Driven @ Iref x 2 Driven @ Iref x 2 CPU[2:0} 0 X X 1 Tristate Tristate Notes: 1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running" 2. Iref x 6 and Iref x 2 is the output current in the corresponding mode 3. See Control Registers section for bit address Signal Pin PD# Pin PCI_Stop# PCI_Stop Tristate Bit Pwrdwn Tristate Bit Non-Stoppable Output Stoppable Output SRC 1 1 X X Running Running SR C 1 0 0 X Running Driven @ Iref x 6 SRC 1 0 1 X Running Tristate SRC 0 X X 0 Driven @ Iref x 2 Driven @ Iref x 2 SRC 0 X X 1 Tristate Tristate Notes: 1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running" 2. Iref x 6 and Iref x 2 is the output current in the corresponding mode 3. See Control Registers section for bit address IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 18 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor CPU Clock Tristate Timing The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register. CPU_Stop = Driven, CPU_Pwrdwn = Driven 1.8mS CPU_Stop# PD# CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Notes: 1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks (assuming clock's OE bit is set to "1") CPU_Stop = Tristate, CPU_Pwrdwn = Driven 1.8mS CPU_Stop# PD# CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Notes: 1. Tristate outputs are pulled low by output termination resistors as shown here. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 19 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor CPU_Stop = Driven, CPU_Pwrdwn = Tristate 1.8mS CPU_Stop# PWRDWN# CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Notes: 1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected. 2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately after the 1.8mS windows expires. This applies to all control register bit changes as well. 3. Tristate outputs are pulled low by output termination resistors as shown here. CPU_Stop = Tristate, CPU_Pwrdwn = Tristate 1.8mS CPU_Stop# PWRDWN# CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Notes: 1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of CPU_Stop# and PWRDWN#. 2. Tristate outputs are pulled low by output termination resistors as shown here. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 20 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor SRC Clock Tristate Timing The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register. SRC_Stop = Driven, SRC_Pwrdwn = Driven 1.8mS PCI_Stop# PCI (Free Running) PWRDWN# CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max Notes: 1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output clock (assuming clock's OE bit is set to "1") SRC_Stop = Tristate, Pwrdwn = Tristate 1.8mS PCI_Stop# PCI (Free Running) PWRDWN# CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) 1 PCI clock max Notes: 1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop# and PWRDWN#. 2. Tristate outputs are pulled low by output termination resistors as shown here. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 21 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor PCI_STOP Asserted SRC_Stop = Tristate, SRC_Pwrdwn = Tristate 1.8mS PCI_Stop# PCI (Free Running) PWRDWN# CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) Notes: 1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop# and PWRDWN#. 2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming immediately after the 1.8mS window expires. This applies to all control register bit changes as well. 3. Tristate outputs are pulled low by output termination resistors as shown here. IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 22 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor 56-Lead, 300 mil Body, 25 mil, SSOP c N L E1 E INDEX AREA 1 2 α h x 45° D A SYMBOL A A1 b c D E E1 e h L N a In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A1 -Ce In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE b .10 (.004) C D mm. N MIN 18.31 56 D (inch) MAX 18.55 MIN .720 MAX .730 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information 952601yFLFT Example: XXXX y F LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 23 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor c N L E1 INDEX AREA E 1 2 a D A A2 A1 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 -Ce SEATING PLANE b VARIATIONS N aaa C 56 D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 MAX .555 Reference Doc.: JEDEC Publicat ion 95, M O-153 10-0039 Ordering Information 952601yGLFT Example: XXXX y G LF T Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) IDTTM Progammable Timing Control HubTM for Next Gen P4TM Processor 701J—01/25/10 24 ICS952601 Programmable Timing Control HubTM for Next Gen P4TM Processor Revision History Rev. I J Issue D ate Description 5/4/2005 Updated Ordering Information from "Lead Free" to "Annealed Lead Free" 1/25/2010 Update document template Page # 23-24 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com TM For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 25