W83194BR-B Stepless Clock Gen. For INTEL Brookdale Chipset Date: 02/25/2003 Revision: 2.0 W83194BR-B Data Sheet Revision History NO. Page s 1 n.a. 2 n.a. 4/1/2002 11 All 3 4 Dates Version Web Version Main Contents n.a. All of the versions before 0.50 are for internal use. 1.0 1.0 Change version and version on web site to 1.0 10/1/2002 1.1 1.0 Modify ratio table of CPU, 3V66, and PCI clock selection. 02/20/2003 2.0 2.0 Update new form 5 6 7 8 9 10 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET TABLE OF CONTENT 1. GENERAL DESCRIPTION ..................................................................................... 1 2. PRODUCT FEATURES .......................................................................................... 1 3. PIN CONFIGURATION........................................................................................... 2 4. BLOCK DIAGRAM ................................................................................................. 2 5. PIN DESCRIPTION................................................................................................. 3 5.1 CRYSTAL I/O ........................................................................................................................................ 3 5.2 CPU, 3V66, AND PCI CLOCK OUTPUTS...........................................................................................3 5.3 I2C CONTROL INTERFACE................................................................................................................. 4 5.4 FIXED FREQUENCY OUTPUTS......................................................................................................... 5 5.5 POWER PINS........................................................................................................................................ 5 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ............................ 6 7. I2C CONTROL AND STATUS REGISTERS........................................................... 7 7.1 REGISTER 1: FREQUENCY SELECT REGISTER (DEFAULT = 0) ................................................. 7 7.2 REGISTER 2: CPU CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) .......................................... 7 7.3 REGISTER 3: PCI CLOCK REGISTER (1 = ENABLE, 0 = STOPPED) ............................................ 7 7.4 REGISTER 4: PCI, 48MHZ CLOCK REGISTER (1 = ENABLE, 0 = STOPPED).............................. 8 7.5 REGISTER 5: 3V66 CONTROL REGISTER (1 = ENABLE, 0 = STOPPED) .................................... 8 7.6 REGISTER 6: WATCHDOG CONTROL REGISTER ......................................................................... 8 7.7 REGISTER 7: WATCHDOG TIMER REGISTER ................................................................................ 9 7.8 REGISTER 8: M/N PROGRAM REGISTER........................................................................................ 9 7.9 REGISTER 9: M/N PROGRAM REGISTER........................................................................................ 9 7.10 REGISTER 10: SPREAD SPECTRUM PROGRAMMING REGISTER .........................................10 7.11 REGISTER 11: DIVISOR AND STEP-LESS ENABLE AND SKEW CONTROL REGISTER.......10 7.12 REGISTER 12: WINBOND CHIP ID REGISTER (READ ONLY)................................................11 7.13 REGISTER 13: WINBOND CHIP ID REGISTER (READ ONLY)................................................11 7.14 REGISTER 81: WINBOND TEST REGISTER I ..............................................................................11 7.15 REGISTER 82: WINBOND TEST REGISTER II .............................................................................11 8. ACCESS INTERFACE.......................................................................................... 12 8.1 BLOCK WRITE PROTOCOL..............................................................................................................12 8.2 BLOCK READ PROTOCOL ...............................................................................................................12 8.3 BYTE WRITE PROTOCOL.................................................................................................................12 8.4 BYTE READ PROTOCOL ..................................................................................................................12 9. SPECIFICATIONS ................................................................................................ 13 9.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................13 -I- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 10. ORDERING INFORMATION............................................................................... 13 11. HOW TO READ THE TOP MARKING................................................................ 14 12. PACKAGE DRAWING AND DIMENSIONS ....................................................... 15 - II - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 1. GENERAL DESCRIPTION The W83194BR-B is a Clock Synthesizer for Intel Brook dale 845 chipset. W83194BR-B provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and 3V66 clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-B provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-B also has watch dog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF and 48 MHz provide better than 0.5V /ns slew rate. 2. PRODUCT FEATURES • • • • • • • • • • • • 3 pairs of CPU clock outputs 4 3V66 clock outputs 9 PCI synchronous clocks 2 48 MHz clock outputs for USB and DOT Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.6 to 200MHz Step-less frequency programming I2C 2-Wire serial interface and I2C read back -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Watch Dog Timer and RESET# output pins • 48-pin SSOP package -1- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 3. PIN CONFIGURATION VDDREF XIN XOUT GND FS0& /PCICLK_F1^ FS1& /PCICLK_F2^ VDDPCI GND ENW D* /PCICLK0^ PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_1 3V66_2 3V66_3 RESET# VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF^ /FS2& CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 M ULTISEL0* IREF GND 48M HZ_USB /FS3& 48M HZ_DOT AVDD48 GND 3V66_0 /VCH_CLK /FS4& VDD3V66 GND SCLK* SDATA* VTT_PW RGD /PD#* GND #: Active low ^: These outputs have 1.5 ~ 2X drive strength *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND 4. BLOCK DIAGRAM D iv id er 2 X IN X O U T PL L 2 48M H z X TA L O SC R E F^ PL L 1 S p read S p ectru m V CO CLK 3 3 1 M /N /R atio RO M 3 V 6 6 _ 1 :3 9 L atch & PO R P D #* M U L T S E L 0* C o n tro l L o g ic & C o n fig R eg ister SD A T A * SC L K * I2 C In terface 3V 66_0/ V C H _C L K 3 D iv id er V T T _P W R G D F S < 0 :4 > C P U C L K _ T 0 :2 C P U C L K _ C 0 :2 P C IC L K _ 0 :6 P C IC L K _ F 1 :2 R E SE T # R ref -2- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 5. PIN DESCRIPTION Buffer type symbol Description IN Input INtd120k Input pin and internal 120K pull down OUT Output OD Open Drain I/O Bi-directional Pin I/OD Bi-directional Pin, Open Drain # Active Low * Internal 120kΩ pull-up & Internal 120kΩ pull-down ^ 1.5X~2X strength 5.1 Crystal I/O PIN Pin Name 3 XIN 4 XOUT Type IN OUT Description Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). 5.2 CPU, 3V66, and PCI Clock Outputs PIN Pin Name Type Description 47, 46, 44, 43, 40, 39 CPUCLKT [0:2] CPUCLKC [0:2] OUT Low skew (< 250ps) differential clock outputs for host frequencies of CPU and chipset IN 38 MULTISEL0* Power on trapping for different current reference. The reference current is referred for Pin 37 (IREF). This pin is latched during VTT_PWRGD. This pin is internal pull up 120K. Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are two modes to select different current via power on trapping the Pin 38 (MULTISEL0). The table is show as follows. MULTSEL0 Board Reference Output Ioh @ Z Target Trace R, Iref Current 0 50 Ohms R=221 Ioh=4*Iref 1.0V @ 50 Iref=5.0mA 1 50 Ohms R=475 Ioh=6*Iref 0.7V @ 50 Iref=232mA IN 37 IREF 23 RESET# OD System reset signal when the watch dog is time out. This pin will generate 250mS when the watchdog timer is timeout. -3- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET IN Power good input signal comes from ACPI with high active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL0 input are valid and is ready to sample. This pin is high active. IN Power Down Function. This is internal 120K pull up. This is multifunction pin. When the VTT_PWRGD signal is asserted (this is, turns from a logical Low to high), the pin will be switched into the function of power down (PD#). VTT_PWRGD 26 PD#* 3V66_0 OUT VCH_CLK OUT 31 FS4& PCICLK_F1^ 5 FS0& PCICLK_F2^ 6 FS1& PCICLK0^ 9 ENWD* 10, 11, 12, 15, 16, 17 PCICLK [1:6] 20, 21, 22 3V66_1, 3V66_2, 3V66_3 66MHz or 48MHz outputs selected by I2C register. INtd120k Latched input for FS4 at initial power up for H/W selecting the output frequency of CPU 3V66 and PCI clocks. This is internal 120K pull down. OUT 3.3V free running PCI clock during normal operation. This pin is with x1.5 ~ x2 driving strength. INtd120k Latched input for FS0 at initial power up for H/W selecting the output frequency of CPU, 3V66 and PCI clocks. This is internal 120K pull down. OUT 3.3V free running PCI clock outputs. This pin is with x1.5 ~ x2 driving strength. INtd120k Latched input for FS1 at initial power up for H/W selecting the output frequency of CPU, 3V66 and PCI clocks. This is internal 120K pull down. OUT 3.3V free running PCI clock outputs. This pin is with x1.5 ~ x2 driving strength. IN Latched input for ENWD at initial power up for H/W enable the watch dog timer. This is internal 120K pull up. OUT Low skew (< 250ps) PCI clock outputs. OUT 3.3V output clocks for the chipset. 5.3 I2C Control Interface PIN Pin Name 27 SDATA* 28 SCLK* Type Description 2 I/OD Serial data of I C 2-wire control interface with internal pull-up resistor. IN Serial clock of I2C 2-wire control interface with internal pull-up resistor. -4- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 5.4 Fixed Frequency Outputs PIN 48 34 Pin Name Type REF^ OUT FS2& INtd120k Description 14.318NHz output. This pin is with x1.5 ~ x2 driving strength. Latched input for FS2 at initial power up for H/W selecting the output frequency of CPU, 3V66 and PCI clocks. This is internal 120K pull down. 48MHz_DOT OUT 48MHz clock output for DOT. 48MHz_USB OUT 48MHz clock output for USB. 35 FS3& INtd120k Latched input for FS3 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 5.5 Power Pins PIN Pin Name Description 1, VDDREF 3.3V power supply for REF. 7, 13 VDDPCI 3.3V power supply for PCI. 18, 30 VDD3V66 3.3V power supply for 3V66. 41, 45 VDDCPU 3.3V power supply for CPU. 24 VDDA 33 AVDD48 4, 8, 14, 19, 25, 29, 32, 36, 42 GND 3.3V power supply for analog core. Analog power 3.3V for 48M Hz Ground pin for 3.3 V -5- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 1 bit 6 ~ 2). FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 3V66(MHz) PCI (MHz) 100.90 67.27 33.63 100.30 66.87 33.43 103.00 68.67 34.33 105.00 70.00 35.00 107.00 71.33 35.67 109.00 72.67 36.33 111.00 74.00 37.00 114.00 76.00 38.00 117.00 78.00 39.00 120.00 80.00 40.00 127.00 84.67 42.33 130.00 86.67 43.33 133.33 88.89 44.44 170.00 56.67 28.33 180.00 60.00 30.00 190.00 63.33 31.67 133.90 66.95 33.48 133.33 66.67 33.33 120.00 60.00 30.00 125.00 62.50 31.25 134.90 67.45 33.73 137.00 68.50 34.25 139.00 69.50 34.75 141.00 70.50 35.25 143.00 71.50 35.75 145.00 72.50 36.25 150.00 75.00 37.50 155.00 77.50 38.75 160.00 80.00 40.00 170.00 85.00 42.50 66.67 66.67 33.34 200.00 66.67 33.33 -6- Spread % +/-0.25% -0.5% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% -0.5% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7. I2C CONTROL AND STATUS REGISTERS 7.1 Register 0: Frequency Select Register (Default = 0) Bit 7 6 5 4 3 2 1 0 Name PWD Description 0 Enable Spread Spectrum in the frequency table. EN_SPSP 0 = Normal 1 = Spread Spectrum enabled SSEL [4] 0 SSEL [3] 0 2 SSEL [2] 0 Frequency selection by software via I C. SSEL [1] 0 SSEL [0] 0 0 Enable software program FS [4:0]. 0 = Select frequency by hardware. EN_SSEL 1= Select frequency by software I2C - Bit 6 ~ 2. 0 Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. EN_SAFE_FREQ 1 = reload the safe frequency bit defined at Register 6 bit 4~0. 7.2 Register 1: CPU Clock Register (1 = Enable, 0 = Stopped) Bit Pin NO PWD Description 7 47, 46 1 6 44, 43 1 CPUCLKT2 / C2 CPUCLKT1 / C1 5 40, 39 1 CPUCLKT0 / C0 4 - X FS [4] Read back. 3 - X FS [3] Read back 2 - X FS [2] Read back 1 - X FS [1] Read back 0 - X FS [0] Read back 7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Stopped) Bit Pin NO PWD Description 7 - X 6 17 1 MULTISEL0 trapping pin data read back PCICLK 6 5 16 1 PCICLK 5 4 15 1 PCICLK 4 3 12 1 PCICLK 3 2 11 1 PCICLK 2 1 10 1 PCICLK 1 0 9 1 PCICLK 0 -7- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.4 Register 3: PCI, 48MHz Clock Register (1 = Enable, 0 = Stopped) Bit Pin NO PWD Description 7 34 1 6 35 1 48MHZ_DOT 48MHZ_USB 5 48 1 REF 4 - 1 Reserved 3 EN_VCH_CLK 0 2 - 1 1 = VCH_CLK 48MHz clock output. 0 = 3V66_0 66MHz clock output (default). Reserved 1 6 1 PCICLK_F1 0 5 1 PCICLK_F0 7.5 Register 4: 3V66 Control Register (1 = Enable, 0 = Stopped) Bit Pin NO PWD Description 7 - 1 Reserved 6 - 1 Reserved 5 - 1 Reserved 4 - 1 Reserved 3 22 1 2 21 1 3V66_3 3V66_2 1 20 1 3V66_1 0 31 1 3V66_0/VCH_CLK 7.6 Register 5: Watchdog Control Register Bit Name 7 Reserved PWD Description 0 Reserved X Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. This bit is trapping pin during VTT_PWRGD#. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. 0 Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only. 6 EN_WD 5 WD_TIMEOUT 4 SAF_FREQ [4] 0 3 SAF_FREQ [3] 0 2 SAF_FREQ [2] 0 1 SAF_FREQ [1] 0 0 SAF_FREQ [0] 0 Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits. -8- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.7 Register 6: Watchdog Timer Register Bit Name PWD Description 7 WD_TIME [7] 0 6 WD_TIME [6] 0 5 WD_TIME [5] 0 4 WD_TIME [4] 0 3 WD_TIME [3] 1 2 WD_TIME [2] 0 1 WD_TIME [1] 0 0 WD_TIME [0] 0 Watchdog timeout time. The bit resolution is 250mS. The default time is 8*250mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value. 7.8 Register 7: M/N Program Register Bit Name PWD Description 7 N_DIV [8] 0 Programmable N divisor value. Bit 7 ~0 are defined in the Register 9. 6 TEST1 1 Test bit 1. Winbond test bit, do not change them. 5 TEST0 0 Test bit 0. Winbond test bit, do not change them. 4 M_DIV [4] 0 3 M_DIV [3] 0 2 M_DIV [2] 0 1 M_DIV [1] 0 0 M_DIV [0] 0 Programmable M divisor value. 7.9 Register 8: M/N Program Register Bit Name PWD Description 7 N_DIV [7] 0 6 N_DIV [6] 0 5 N_DIV [5] 0 4 N_DIV [4] 0 3 N_DIV [3] 0 2 N_DIV [2] 0 1 N_DIV [1] 0 0 N_DIV [0] 0 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 8. -9- Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.10 Register 9: Spread Spectrum Programming Register Bit Name PWD Description 7 SP_UP [3] 0 Spread Spectrum Up Counter bit 3. 6 SP_UP [2] 0 Spread Spectrum Up Counter bit 2. 5 SP_UP [1] 0 Spread Spectrum Up Counter bit 1. 4 SP_UP [0] 1 Spread Spectrum Up Counter bit 0 3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 2 SP_DOWN [2] 1 Spread Spectrum Down Counter bit 2 1 SP_DOWN [1] 1 Spread Spectrum Down Counter bit 1 0 SP_DOWN [0] 1 Spread Spectrum Down Counter bit 0 7.11 Register 10: Divisor and Step-less Enable and Skew Control Register Bit Name PWD Description 0 0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 1 bit 0). 0 Reserved 7 EN_MN_PROG 6 Reserved 5 RATIO_SEL [2] 0 4 RATIO_SEL [1] 0 3 RATIO_SEL [0] 0 2 CPU_3V66_SKEW [2] 1 1 CPU_3V66_SKEW [1] 0 0 CPU_3V66_SKEW [0] 0 CPU, 3V66, and PCI ratio selection. The ratio is shown as following table. CPU to 3V66 skew. Table of CPU, 3V66, and PCI clock selection. Reg10 Bit5 SEL2 0 0 0 0 1 1 1 1 Reg10 Bit4 Reg10 Bit3 VCO / CPU VCO / 3V66 VCO / PCI SEL1 SEL0 Ratio Ratio Ratio 0 0 2 4 8 0 1 2 5 10 1 0 2 6 12 1 1 3 6 12 0 0 4 4 8 0 1 4 6 12 1 0 6 6 12 1 1 X X X - 10 - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 7.12 Register 11: Winbond Chip ID Register Bit Name (Read Only) PWD Description 7 CHPI_ID [7] 0 Winbond Chip ID. W83194BR-B is 0x32. 6 CHPI_ID [6] 0 Winbond Chip ID. 5 CHPI_ID [5] 1 Winbond Chip ID. 4 CHPI_ID [4] 1 Winbond Chip ID. 3 CHPI_ID [3] 0 Winbond Chip ID. 2 CHPI_ID [2] 0 Winbond Chip ID. 1 CHPI_ID [1] 1 Winbond Chip ID. 0 CHPI_ID [0] 0 Winbond Chip ID. 7.13 Register 12: Winbond Chip ID Register Bit Name (Read Only) PWD Description 7 SUB_ID [3] 0 Winbond Sub-Chip ID. The sub-chip ID of W83194BR-B is defined as 0001b. 6 SUB_ID [2] 0 Winbond Sub-Chip ID. 5 SUB_ID [1] 0 Winbond Sub-Chip ID. 4 SUB_ID [0] 1 Winbond Sub-Chip ID. 3 VER_ID [3] 0 Winbond Version ID. The Version ID of W83194BR-B is 0001b. 2 VER_ID [2] 0 Winbond Version ID. 1 VER_ID [1] 0 Winbond Version ID. 0 VER_ID [0] 1 Winbond Version ID. 7.14 Register 81: Winbond Test Register I Bit Name 7:0 TEST_REG1 PWD Description 00h Winbond Test Register. User don’t write it, otherwise this chip will get an unexpected result. 7.15 Register 82: Winbond Test Register II Bit Name 7:0 TEST_REG2 PWD Description 04h Winbond Test Register. User don’t write it, otherwise this chip will get an unexpected result. - 11 - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 8. ACCESS INTERFACE The W83194BR-B provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-B is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 12 - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd). Parameter Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) Rating - 0.5 V to + 4.6 V - 0.5 V to + 4.6 V 3.135V to 3.465 V 3.135V to 3.465 V - 65°C to + 150°C - 55°C to + 125°C 0°C to + 70°C 2000V 10. ORDERING INFORMATION Part Number Package Type Production Flow W83194BR-B 48 PIN SSOP Commercial, 0°C to +70°C - 13 - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 11. HOW TO READ THE TOP MARKING W83194BR-B 28051234 814GBB 1st line: Winbond logo and the type number: W83194BR-B 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G BB 814: packages made in '98, week 14 G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. - 14 - Publication Release Date: February 2003 Revision 2.0 W83194BR-B STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET 12. PACKAGE DRAWING AND DIMENSIONS Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Winbond Electronics (H.K.) Ltd. Winbond Electronics Rm. 803, World Trade Square, Tower II (North America) Corp. 123 Hoi Bun Rd., Kwun Tong 2727 North First Street Kowloon, Hong Kong San Jose, California 95134 TEL: 852-27516023-7 TEL: 1-408-9436666 FAX: 852-27552064 FAX: 1-408-9436668 Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. - 15 - Publication Release Date: February 2003 Revision 2.0