A4956 Full-Bridge PWM Gate Driver FEATURES AND BENEFITS • • • • • • • • • • • • • • DESCRIPTION PHASE/ENABLE/MODE control logic Overcurrent indication Adjustable off-time and blank-time Adjustable current limit Adjustable gate drive Synchronous rectification Internal UVLO Crossover-current protection MOSFET VDS protection Voltage output proportional to load current Decay-mode selection for external PWM A4956K is AEC-Q100 Grade 1 qualified Commercial temperature grade (A4956G: –40°C to 105°C) Automotive temperature grade (A4956K: –40°C to 125°C) PACKAGES: 20-Pin QFN (suffix “ES”) with Exposed Thermal Pad Designed for pulse-width-modulated (PWM) control of DC motors, the A4956 is capable of 50 V operation and provides gate drive for an all n-channel external MOSFET bridge. Input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. Internal circuit protection includes VDS protection, thermal shutdown with hysteresis, undervoltage monitoring of VBB, and crossover-current protection. The A4956 is supplied in a low-profile 4×4 mm, 20-contact QFN package (suffix “ES”) and a 20-lead eTSSOP (suffix “LP”), both with exposed thermal pad. 20-Pin eTSSOP (suffix “LP”) with Exposed Thermal Pad Not to scale CP2 CP1 0.1 µF TSD UVLO VIN CHARGE PUMP VCP ISET VBB VREG 0.1 µF VCP RC STANDBY GHA GHB MODE GHA SB Control Logic PHASE GATE DRIVE ENABLE OCLn System Controller OCL Filter optional AIOUT HOLD SA SA GLA GLB GLA ×10 + SENSE – VREF ÷10 GND Functional Block Diagram A4956-DS, Rev. 1 RSENSE Inrush current limit = VREF/10 * RSENSE A4956 Full-Bridge PWM Gate Driver SPECIFICATIONS Selection Guide Part Number A4956GESTR-T A4956GLPTR-T A4956KLPTR-T Ambient Temp Range –40ºC to 105ºC –40ºC to 105ºC –40ºC to 125ºC Packing 1500 pieces per 7-in. reel 4000 pieces per 13-in. reel 4000 pieces per 13-in. reel Notes AEC-Q100 Qualified Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Motor Outputs Sx SENSE VSENSE OCLn Notes Sx – SENSE; VBB – Sx TW < 500 ns Rating Unit 50 V –2 to 52 V –0.5 to 0.5 V –4 to 4 V VOCLn –0.3 to 5.5 V VREF VREF –0.3 to 5.5 V ISET VISET –0.3 to 5.5 V AIOUT VAIOUT –0.3 to 5.5 V –0.3 to 5.5 V Logic Input Voltage Range VIN PHASE, ENABLE, MODE Junction Temperature TJ 150 ºC Storage Temperature Range TS –55 to 150 ºC Operating Temperature Range TA Range G –40 to 105 ºC Range K –40 to 125 ºC Thermal Characteristics (may require derating at maximum conditions, see application information) Characteristic ES Package LP Package Symbol RθJA Test Conditions* Value Unit Cu 37 ºC/W 4-Layer PCB, 1 in2 Cu 28 ºC/W 4-Layer PCB, 1 in2 *Power dissipation and thermal limits must be observed. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4956 1 20 CP1 AIOUT 2 19 VBB OCLn 3 18 CP2 VREF 4 17 VCP ENABLE 5 16 SA OCLn GND 16 VREF 17 ENABLE PHASE 19 18 20 RC Full-Bridge PWM Gate Driver ISET 1 15 AIOUT MODE 2 14 GND SENSE 3 13 CP1 GLB 4 12 VBB PHASE 6 15 GHA GLA 5 11 CP2 RC 7 14 SB 8 13 GHB 9 12 GLA SENSE 10 11 GLB 7 8 9 10 ISET SB SA VCP PAD GHA GHB 6 PAD MODE Package ES, 20-Pin QFN Pin-Outs Package LP, 20-Pin eTSSOP Pin-Outs Terminal List Table Name ISET Number ES Package LP Package 1 8 Function Terminal to set gate drive current MODE 2 9 Digital MODE input SENSE 3 10 Sense resistor connection, low-side gate return GLB 4 11 Gate driver GLA 5 12 Gate driver GHB 6 13 Gate driver SB 7 14 High-side bridge reference GHA 8 15 Gate driver SA 9 16 High-side bridge reference VCP 10 17 Charge pump reservoir cap connection CP2 11 18 Charge pump terminal VBB 12 19 Supply voltage CP1 13 20 Charge pump terminal GND 14 1 Ground AIOUT 15 2 Analog output proportional to VSENSE OCLn 16 3 OCP and OVP output flag, open drain VREF 17 4 Analog OCP reference input ENABLE 18 5 Digital ENABLE input PHASE 19 6 Digital PHASE input RC 20 7 Terminal to set blank- and off-time PAD – – Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4956 Full-Bridge PWM Gate Driver ELECTRICAL CHARACTERISTICS: valid for Temperature Range G version at TJ = 25°C and for Temperature Range K version at TJ = –40°C to 150°C, VBB = 5.5 to 50 V, unless otherwise specified Characteristics VBB Supply Current Symbol Test Conditions IBB IBB SLEEPn = low, Standby Mode Min. Typ. Max. Unit – 6 10 mA – – 5 µA 6.5 6.8 7.5 – 5.2 – Gate Drive High-Side Gate Drive Output GH Low-Side Gate Drive Output GL Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V Relative to VBB, IGATE = 200 µA, VBB = 5.5 V IGATE = 200 µA, VBB = 8 to 50 V 6.5 6.8 7.5 IGATE = 200 µA, VBB = 5.5 V – 5.4 – V V Gate Drive Pull-Up Current IGPU RISET = 30 kΩ; GH = GL = 4 V 21 30 39 mA Gate Drive Pull-Down Current IGPD RISET = 30 kΩ; GH = GL = 4 V 47 68 89 mA tDT – 1000 – ns RGPD 30 50 70 kΩ Dead-Time Passive Pull-Down Resistance Logic Input and Output Logic Output Voltage VOCLn I = 2 mA, Overcurrent Detected – 0.2 0.3 V Logic Output Leakage IOCLn V = 5 V, Normal Operation – – 5 µA PWM Current Limit Flag Timer tOCLn 300 500 600 us VIH 2.0 – – V – – 0.8 V – – 0.4 V Logic Input Voltage VIL VIL(STANDBY) Standby Mode, ENABLE input Logic Input Hysteresis VHYS – 320 – mV Logic Input Pull-Down Resistor RPD 30 50 70 kΩ VREF Input Current IVREF -5 <1 5 µA VREF Input Range VREF 0 – 2.5 V 9.5 – 10.5 V/V –10 – 10 mV – 30 – µs Current Gain Input Offset, SENSE Fixed Off-Time AV VREF = 2.5 V VREF/ VSENSE, VREF = 2.5 V VOSSENSE TOFF RRC = 30 kΩ, CRC = 1 nF Percent Fast Decay PFD Internal PWM chop Blank-Time TBLK RRC = 30 kΩ, CRC = 1 nF Tpu Time until outputs are enabled Standby Timer Power-Up Delay AIOUT Gain AIOUT 13 – % 3 3.9 µs 0.7 1.0 1.3 ms – 50 300 µs 9 10 11 V/V VOSAIOUT –15 – 15 mV Sample-and-Hold Accuracy SHACC – 15 – mV Sample-and-Hold Droop Rate VDROOP – – 1 mV/µs ROUTAIOUT 0.75 1.00 1.45 kΩ 5.10 5.25 5.40 V Input Offset, AIOUT AIOUT Output Impedance AIOUT/VSENSE, VSENSE = 50 to 200 mV – 2.1 Protection Circuits UVLO Enable Threshold UVLOVBB VBB rising UVLO Hysteresis UVLOHYS 200 300 350 mV VDS Threshold VDSTHRES – 2 – V Thermal Shutdown Temperature Thermal Shutdown Hysteresis 1 2 TJTSD Temperature increasing. 150 165 185 °C ΔTJ Recovery = TJTSD – ΔTJ – 30 – °C Specified limits are tested at a single temperature and assured over operating temperature range by design and characterization Target trip level = VDSTH = VDRAIN - Sx (High Side On) or VDSTH = Sx - SENSE (Low Side On) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4956 Full-Bridge PWM Gate Driver Control Logic PHASE ENABLE MODE 10 × VSENSE > VREF OUTA OUTB Function x 0 (>1ms) x x Z Z Sleep (Standby) Mode 0 0 (<1ms) 0 false H L EN Chop, Fast Decay SR * 1 0 (<1ms) 0 false L H EN Chop, Fast Decay SR * 0 1 x false L H Reverse 1 1 x false H L Forward x 0 (<1ms) 1 false L L Slow Decay SR (Brake) 0 1 x true H/L L Internal Chop Reverse, Mixed Decay * 1 1 x true L H/L Internal Chop Forward, Mixed Decay * * In fast decay, outputs change to high-Z state when load current approaches zero, to prevent reversal of current. IOCL = VREF / RSENSE / 10 I_OUT tOCLn OCLn OCLn Output Flag OCLn output function is described in the Functional Description section. A A B B C D D 300 µs AIOUT 0V VSENSE = VREF/10 0V VSENSE ENABLE MODE AIOUT Output A. B. C. D. Internal OCL chop. AIOUT holds while SENSE voltage varies during the mixed-decay off-time. ENABLE chop, MODE = high (slow decay). AIOUT holds while SENSE voltage drops to 0 V during slow decay. Slow-decay timeout. AIOUT is forced to 0 V 300 µs after ENABLE goes low. ENABLE chop, MODE = low (fast decay). AIOUT tracks VSENSE and thus is clamped at 0 V during fast decay. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4956 Full-Bridge PWM Gate Driver FUNCTIONAL DESCRIPTION Device Operation RC The A4956 is designed to operate DC motors. The output drivers are capable of 50 V with gate-driver capability for an all n-channel external MOSFET H-bridge. Control logic includes synchronous rectification to reduce power dissipation. Current limit is regulated by fixed off-time pulse-width-modulated (PWM) control circuitry. The RC terminal is used to set both fixed off-time and blank-time for the internal PWM current control. Refer to the following three sections to select RC component values. Internal PWM Current Control Peak current is regulated by monitoring the voltage on an external sense resistor. VREF IPEAK = (10 × RSENSE) When the peak current is exceeded, the source driver turns off for a fixed period tOFF to chop the current. The outputs operate in mixed-decay mode during tOFF. Refer to the Fixed Off-Time Setting section to set tOFF. The internal current-sense circuit is ignored for tBLANK after PWM transitions. The comparator output is blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, or switching transients related to the capacitance of the load, or both. Refer to the Blank-Time Setting section to set tBLANK. Brake It is important to note that the internal PWM current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF / RMOTOR. Care should be taken to ensure that the maximum ratings of the external MOSFET are not exceeded in worst-case braking situations of high speed and high inertial loads. ISET Fixed Off-Time Setting The internal PWM current-control circuitry uses a one-shot to control the time the drivers remain off. The one-shot off-time (tOFF) is determined by the selection of an external resistor and capacitor connected from the RC timing terminal to ground. The off-time, over a range of values of CRC = 470 to 1500 pF and RRC = 12 to 100 kΩ, is approximated by: tOFF = RRC × CRC + dead time Blank-Time Setting This circuit blanks the output of the current-sense comparator when the outputs are switched by the internal current-control circuitry or by an external PWM chop command. The comparator blanking time, tBLANK, is determined by the selection of an external resistor and capacitor connected from the RC timing terminal to ground, and is approximated by: (3.6/RRC (kΩ)) tBLANK = 2.6 µs × CRC (nF) × e MODE The input terminal MODE is used to select the bridge behavior when the ENABLE input is brought low. Slow-decay or fastdecay mode can be selected. A logic high on the terminal puts the device in slow-decay mode. Slow Decay In slow-decay mode, the low-side switch stays on and the high-side switch turns off. Due to the synchronous rectification feature, the complementary low-side switch turns on after a deadtime. A resistor from ISET terminal to ground sets the magnitude of the gate current. The sink and source current ratios are fixed at approximately 2-to-1 where the pull-down current is approximately two times the pull-up current. RISET should be between 20 and 150 kΩ. Fast Decay SR The formula for determining the gate drive is: Mixed Decay IGATE_HS (mA) = 1.9 + 900 RISET (kΩ) IGATE_LS (mA) = 3.5 + 1700 RISET (kΩ) In fast-decay mode, the high-side and low-side switches turn off, and the complementary pair of switches is turned on, effectively reversing the voltage polarity across the motor winding. When the peak current is reached, as set by the sense resistor and voltage on VREF, the PWM current limiter initiates an off-time. The off-time is determined by the resistor and capacitor on the RC terminal. In mixed-decay mode, the driver will initiate a fast decay, after a dead-time, for 13% of the programmed off-time. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4956 After the fast-decay time expires, the bridge will switch to slow decay for the remaining off-time. When the bridge is operating in fast decay, it will internally prevent current reversal by putting the bridge in a high-Z state if the current through the sense resistor falls close to zero. OCLn Output An open drain logic output will be driven low to indicate system operation. The OCLn terminal is driven low under two conditions: 1. When the system is limiting current to value set by VREF and RSENSE. Once overcurrent events are no longer detected, the A4956 will release the indication after a time tOCLn. 2. When a VDS fault is detected, the OCLn terminal is driven low. It is released when the fault is reset. The OCLn terminal, in combination with the AIOUT terminal, can provide valuable information about how the system is behaving: • Overcurrent events can indicate a motor stall condition, in which case the system controller can respond to the fault condition by reducing PWM duty. When OCLn is low and the voltage on AIOUT is greater than 0 V, the controller is actively limiting current with the internal, fixed off-time PWM current limiter. • In the case of a VDS fault, the OCLn terminal is also driven low, but the AIOUT voltage will be 0 V, because the bridge has been disabled. This notifies the user that a VDS fault has occurred and the driver has been disabled. AIOUT An analog output can be used to monitor current through the external sense resistor (if used). The SENSE voltage is gained by a factor of 10 and fed to the AIOUT terminal. A sample-and-hold circuit is used to capture the voltage across the sense resistor and holds it during periods when the voltage is not representative of the current in the motor. The AIOUT Output diagram illustrates when the voltage is held. The held voltage will droop at a rate equal to VDROOP. In the case of a VDS fault on the bridge, the AIOUT terminal will be discharged to zero volts. Full-Bridge PWM Gate Driver MOSFET VDS Protection The drain-to-source voltage is monitored across the MOSFET any time the MOSFET is on. If the voltage across the MOSFET exceeds VDSTHRES, the bridge is disabled and latched off. In order to prevent false VDS faults, the VDS monitor is blanked immediately after any MOSFET is turned on. The VDS monitor waits for a blank-time defined by the components on the RC terminal before monitoring the VDS level. During the off-time when SR is active, VDS blanking is fixed at 1 μs. VDS Fault When a VDS fault occurs, and the bridge is disabled, and the fault is latched, the OCLn terminal is immediately driven low. The latch can only be reset by going into standby or by dropping VBB below the UVLO threshold. Standby Mode Low power standby mode is activated when ENABLE is held logic LOW for TSTB (typically 1 ms). Standby mode disables most of the internal circuitry, including the charge pump and internal regulator. When coming out of standby mode, the A4956 requires up to 300 µs before the outputs can respond to input commands. TSD If the die temperature increases to approximately TTSD, the full bridge outputs will be disabled until the internal temperature falls below TTSD minus a hysteresis level of THYS. Fault Shutdown In the event of a fault due to excessive junction temperature, or low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition is removed. At power-up, the UVLO circuit disables the drivers until the UVLO thresholds are exceeded. Charge Pump The Charge Pump is used to generate a supply above VBB to drive the high-side MOSFETs. The VCP voltage is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4956 Full-Bridge PWM Gate Driver TERMINAL CIRCUIT DIAGRAMS SX VCP 6.7 V GND 10 V GND VCP GHX VBB GLX ENABLE PHASE RISET AIOUT VREF MODE RC OCLn 8V 6.7 V GND GND SX SENSE CP2 CP1 VCP 8V GND VBB GND GND SENSE VBB 56 V GND 8V GND GND Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4956 Full-Bridge PWM Gate Driver PACKAGE OUTLINE DRAWINGS For Reference Only – Not for Tooling Use (Reference JEDEC MO-220WGGD) Dimensions in millimeters NOT TO SCALE Exact case and lead configuration at supplier discretion within limits shown 0.30 0.50 4.00 ±0.15 20 20 1 2 0.95 A 1 2 4.00 ±0.15 2.45 4.10 2.45 21X D C 0.75 ±0.05 0.08 C SEATING PLANE 4.10 C PCB Layout Reference View +0.05 0.25 –0.07 0.50 BSC +0.15 0.40 –0.10 B A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 2.45 2 1 20 2.45 D Coplanarity includes exposed thermal pad and terminals ES Package, 20-Pin QFN with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4956 Full-Bridge PWM Gate Driver For Reference Only – Not for Tooling Use (Reference MO-153 ACT) NOT TO SCALE Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 6.50 ±0.10 4.20 8º 0º 20 0.20 0.09 C 3.00 4.40 ±0.10 6.40 ±0.20 A 0.60 ±0.15 1 2 0.25 BSC C 20X 0.10 1.00 REF 1.20 MAX C SEATING PLANE SEATING PLANE 0.30 0.19 0.65 BSC 0.45 GAUGE PLANE 0.15 0.00 0.65 NNNNNNN YYWW LLLLLLL 20 1.70 1 D 3.00 6.10 Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Lot number A Terminal #1 mark area 1 B Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) 2 C Exposed thermal pad (bottom surface) 4.20 B D Branding scale and appearance at supplier discretion PCB Layout Reference View LP Package, 20-Pin eTSSOP with Exposed Thermal Pad Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4956 Full-Bridge PWM Gate Driver Revision History Revision Revision Date – February 12, 2015 1 July 14, 2015 Description of Revision Initial Release Updated functional block diagram (page 1); added packing information (page 2); changed references to LSS to SENSE. Copyright ©2015, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11