TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 1.5 to 18 V (4.5 to 25 V bias) Input, 8-A Single Synchronous Step-Down SWIFT™ Converter FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • Integrated 13.8 and 5.9 mΩ MOSFETs With 8-A Continuous Output Current Supports All Ceramic Output Capacitors Reference Voltage 600 mV ±0.5% Tolerance Output Voltage Range: 0.6 V to 5.5 V D-CAP3™ Control Mode With Fast Load-Step Response Auto-Skipping Eco-mode™ for High LightLoad Efficiency FCCM for Tight Output Ripple and Voltage Requirements Eight Selectable Frequency Settings from 200 kHz to 1 MHz Pre-Charged Startup Capability Built-in Output Discharge Circuit Open-Drain Power-Good Output 3.5-mm × 4.5-mm, 28-Pin, QFN Package GND2 RF PGOOD EN VBST N/C SW SW SW SW TPS53513 1 2 3 4 5 6 7 8 9 15 VIN 28 VIN GND1 16 VIN DNC 27 17 NC 26 18 VDD TRIP 19 VREG VO 25 20 GND FB 24 21 MODE VIN 22 PGND 14 PGND 13 PGND 12 PGND 11 PGND 10 DESCRIPTION The TPS53513 is a small-sized, synchronous buck converter with an adaptive on-time D-CAP3 control mode. The device offers ease-of-use and low external-component count for space-conscious power systems. This device features high-performance integrated MOSFETs, accurate 0.5% 0.6-V reference, and an integrated boost switch. Competitive features include very-low external-component count, fast loadtransient response, auto-skip mode operation, internal soft-start control, and no requirement for compensation A forced continuous conduction mode helps meet tight voltage regulation accuracy requirements for performance DSPs and FPGAs. The TPS53513 is available in a 28-pin QFN package and is specified from –40°C to 85°C ambient temperature. PGOOD 23 • • Server and Cloud-Computing POLs Broadband, Networking, and Optical Communications Infrastructure I/O Supplies Supported at the WEBENCH™ Design Center . . EFFICIENCY 100 VOUT 90 EN VREG Efficiency (%) Thermal Pad 80 fSW = 500 KHz, VIN = 12 V, VDD = 5 V TA = 25°C, L OUT = 1 H, Mode = Auto-skip Vout Vout VOUT = 0.6 V V OUT = 1 V Vout Vout VOUT = 1.2 V V OUT = 1.5 V VOUT = 1.8 V V Vout Vout OUT = 2.5 V VOUT = 3.3 V V Vout Vout OUT = 5 V 70 60 0 2 4 6 8 Output Current (A) 10 12 C003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT, D-CAP3, Eco-mode, WEBENCH are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE MAX –0.3 7.7 DC –3 30 Transient < 10 ns –5 32 –0.3 36 EN SW VBST Input voltage range (2) VBST (3) –0.3 6 VBST when transient < 10 ns Output voltage range Temperature (1) (2) (3) UNIT MIN V 38 VDD –0.3 28 VIN –0.3 30 VO, FB, MODE, RF –0.3 6 PGOOD –0.3 7.7 VREG, TRIP –0.3 6 Junction, TJ –40 150 °C Storage, Tstg –55 150 °C V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. Voltage values are with respect to the SW terminal. THERMAL INFORMATION TPS53513 THERMAL METRIC (1) RVE UNITS 28 PINS θJA Junction-to-ambient thermal resistance (2) 37.5 θJCtop Junction-to-case (top) thermal resistance (3) 34.1 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) 2 Junction-to-case (bottom) thermal resistance 18.1 1.8 (7) °C/W 18.1 2.2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Input voltage range Output voltage range TA (1) MAX EN –0.1 7 SW –3 27 VBST –0.1 28 VBST (1) –0.1 5.5 VDD 4.5 25 VIN 1.5 18 VO, FB, MODE, RF –0.1 5.5 PGOOD –0.1 7 VREG, TRIP –0.1 5.5 Operating free-air temperature –40 85 UNIT V V °C Voltage values are with respect to the SW pin. ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1350 1850 µA 850 1150 µA 0.5 µA 603 mV SUPPLY CURRENT IVDD VDD bias current TA = 25°C, No load Power conversion enabled (no switching) IVDDSTBY VDD standby current TA = 25°C, No load Power conversion disabled IVIN(leak) VIN leakage current VEN = 0 V VREF OUTPUT VVREF Reference voltage VVREFTOL Reference voltage tolerance FB w/r/t GND, TA = 25°C 597 600 FB w/r/t GND, TJ = 0°C to 85°C –0.6% 0.5% FB w/r/t GND, TJ = –40°C to 85°C –0.7% 0.5% OUTPUT VOLTAGE IFB FB input current VFB = 600 mV IVODIS VO discharge current VVO = 0.5 V, Power Conversion Disabled 10 50 100 nA 12 15 mA SMPS FREQUENCY VO switching frequency (1) fSW VIN = 12 V, VVO = 3.3 V, RDR < 0.041 250 VIN = 12 V, VVO = 3.3 V, RDR = 0.096 300 VIN = 12 V, VVO = 3.3 V, RDR = 0.16 400 VIN = 12 V, VVO = 3.3 V, RDR = 0.229 500 VIN = 12 V, VVO = 3.3 V, RDR = 0.297 600 VIN = 12 V, VVO = 3.3 V, RDR = 0.375 750 VIN = 12 V, VVO = 3.3 V, RDR = 0.461 850 VIN = 12 V, VVO = 3.3 V, RDR > 0.557 1000 tON(min) Minimum on-time TA = 25°C (2) tOFF(min) Minimum off-time TA = 25°C kHz 60 175 ns 240 310 ns INTERNAL BOOTSTRAP SW VF Forward Voltage VVREG–VBST, TA = 25°C, IF = 10 mA 0.15 0.25 V IVBST VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 µA (1) (2) Resistor divider ratio (RDR) is described in Equation 1. Specified by design. Not production tested. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC THRESHOLD VENH EN enable threshold voltage 1.3 1.4 1.5 V VENL EN disable threshold voltage 1.1 1.2 1.3 V VENHYST EN hysteresis voltage VENLEAK EN input leakage current 0.22 –1 0 V 1 µA SOFT START tSS Soft-start time 1 ms PGOOD COMPARATOR VPGTH VDDQ PGOOD threshold IPG PGOOD sink current tPGDLY PGOOD delay time IPGLK PGOOD leakage current PGOOD in from higher 104% 108% 111% PGOOD in from lower 89% 92% 96% PGOOD out to higher 113% 116% 120% PGOOD out to lower 80% 84% 87% 4 6 0.8 1.0 VPGOOD = 5 V –1 RTRIP = 34.8 kΩ VPGOOD = 0.5 V Delay for PGOOD going in mA 1.2 ms 0 1 µA 50 kΩ 6.2 8.0 9.8 RTRIP = 25.5 kΩ 4.2 6.2 8.2 RTRIP = 34.8 kΩ –10.5 –7.9 –5.3 RTRIP = 25.5 kΩ –8.7 –6.1 –3.5 Delay for PGOOD coming out 2 µs CURRENT DETECTION RTRIP TRIP pin resistance range IOCL Current limit threshold, valley IOCLN Negative current limit threshold, valley VZC Zero cross detection offset 20 0 A A mV PROTECTIONS Wake-up 3.25 3.34 3.41 Shutdown 3.00 3.12 3.19 Wake-up (default) 4.15 4.25 4.35 Shutdown 3.95 4.05 4.15 116% 120% 124% VVREGUVLO VREG undervoltage-lockout (UVLO) threshold voltage VVDDUVLO VDD UVLO threshold voltage VOVP Overvoltage-protection (OVP) threshold voltage OVP detect voltage tOVPDLY OVP propagation delay With 100-mV overdrive VUVP Undervoltage-protection (UVP) threshold voltage UVP detect voltage tUVPDLY UVP delay UVP filter delay 300 64% 68% V V ns 71% 1 ms THERMAL SHUTDOWN Thermal shutdown threshold (3) TSDN Shutdown temperature 140 Hysteresis °C 40 LDO VOLTAGE VREG LDO output voltage VIN = 12 V, ILOAD = 10 mA VDOVREG LDO low droop drop-out voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C ILDOMAX LDO over-current limit VIN = 12 V, TA = 25°C 4.65 170 5 5.45 V 365 mV 200 mA INTERNAL MOSFETS RDS(on)H High-side MOSFET on-resistance TA = 25°C 13.8 15.5 mΩ RDS(on)L Low-side MOSFET on-resistance TA = 25°C 5.9 7.0 mΩ (3) 4 Specified by design. Not production tested. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 DEVICE INFORMATION RF GND1 TRIP VO 28 DNC GND2 RVE PACKAGE 28-PIN (TOP VIEW) 27 26 25 24 1 23 FB PGOOD 2 22 GND EN 3 21 MODE VBST 4 20 VREG TPS53513 NC 5 19 VDD SW 6 18 NC SW 7 17 VIN SW 8 16 VIN SW 9 15 VIN 10 11 12 13 14 PGND PGND PGND PGND PGND Thermal Pad PIN DESCRIPTIONS PIN NAME NO. I/O (1) DESCRIPTION EN 3 I The enable pin turns on the DC-DC switching converter. FB 23 I VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND. GND 22 G This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND plane with a short trace (For example, connect this pin to the thermal pad with a single trace and connect the thermal pad to PGND pins and PGND plane). GND1 27 I Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to ground. GND2 28 I Connect this pin to ground. GND2 is the input of unused internal circuitry and must connect to ground. I The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also selects the ramp coefficient of D-CAP3 mode. MODE 21 5 NC 18 DNC 26 — Not connected. These pins are floating internally. O Do not connect. This pin is the output of unused internal circuitry and must be floating. G These ground pins are connected to the return of the internal low-side MOSFET. 10 11 PGND 12 13 14 PGOOD 2 O Open-drain power-good status signal which provides startup delay after the FB voltage falls within the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs. RF 1 I RF is the SW-frequency configuration pin. Connect this pin to a resistor divider between VREG and GND to program different SW frequency settings. I/O SW is the output switching terminal of the power converter. Connect this pin to the output inductor. 6 SW 7 8 9 (1) I = Input, O = Output, P = Supply, G = Ground Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com PIN DESCRIPTIONS (continued) PIN NAME NO. I/O (1) DESCRIPTION TRIP 25 I/O TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at room temp, 3000 ppm/°C current is sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for detailed OCP setting. VBST 4 P VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch. VDD 19 P Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V. P VIN is the conversion power-supply input pins. 15 VIN 16 17 VREG 20 O VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver. VO 24 I VOUT voltage input to the controller. 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 BLOCK DIAGRAM UV PGOOD + 0.6 V + 8/16% + 0.6 V ± 32% Delay Delay + + OV 0.6 V ± 8/16% 0.6 V+20% VREG Internal Ramp 0.6 V SS Control Logic + + PWM RF UVP / OVP Logic VBST VFB VIN 10 µA GND + 1 SHOT TRIP + OCP LL SW XCON + ZC PGND Control Logic PGND SW FCCM / SKIP RC time Constant + EN 1.4 V / 1.2 V GND x x x x x x On/Off time Minimum On/Off Light load OVP/UVP FCCM/SKIP Soft-Start Enable VO Fault Shut Down LDO VREG + MODE VREGOK VDDOK THOK 3.34 V / 3.12 V + + 140°C / 100°C VDD 4.3 V / 4.03 V DNC GND1 GND2 TPS53513 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com APPLICATION CIRCUIT DIAGRAM R1 6.65 N 18 17 16 VDD NC VIN VIN CIN CIN 2.2 nF 3 × 22 µF 15 PGND 14 PGND 13 PGND 12 PGND 11 PGND 10 SW SW SW TPS53513 SW GND2 19 N/C 28 20 VREG GND1 21 VBST 27 22 MODE DNC 23 EN 26 VIN GND TRIP C4 1 µF PGOOD 25 C3 1 µF R6 150 N FB VO Thermal Pad RF R8 34.8 N 24 PGOOD VIN R2 2 k 1 2 3 4 5 6 7 8 9 PIMB065T±1R0MS-63 R4 249 N R10 100 N Thermal Pad R5 105 N VREG 8 Submit Documentation Feedback EN VOUT R7 0 C2 0.1 µF 1 µH R3 3 COUT 6 × 22 µF COUT 4 × 10 µF C1 470 pF Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 100 100 90 90 Efficiency (%) Efficiency (%) TYPICAL CHARACTERISTICS 80 fSW = 500 KHz, VIN = 12 V, VDD = 5 V TA = 25°C, L OUT = 1 H, Mode = Auto-skip Vout Vout =1V VOUT = 0.6 V V OUT Vout Vout VOUT = 1.2 V V OUT = 1.5 V VOUT = 1.8 V V Vout Vout OUT = 2.5 V VOUT = 3.3 V V Vout Vout OUT = 5 V 70 60 0 2 4 6 8 10 80 fSW = 500 KHz, VIN = 12 V, VDD = 5 V TA = 25°C, L OUT = 1 H, Mode = FCCM Vout Vout =1V VOUT = 0.6 V V OUT Vout Vout VOUT = 1.2 V V OUT = 1.5 V VOUT = 1.8 V V Vout Vout OUT = 2.5 V VOUT = 3.3 V V Vout Vout OUT = 5 V 70 60 12 Output Current (A) 0 90 90 Efficiency (%) Efficiency (%) 100 80 fSW = 1 MHz, VIN = 12 V, VDD = 5 V TA = 25°C, L OUT = 1 H, Mode = Auto-Skip Vout V OUT = 0.6 V V Vout OUT = 1.2 V V Vout OUT = 1.8 V V Vout = 3.3 3.3 V V OUT = 50 0 2 4 6 Vout 1V V OUT = 1 V Vout 1.5 V OUT = 1.5 V Vout 2.5 V OUT = 2.5 V Vout = 55 V V OUT = 8 10 Output Current (A) 70 50 12 0 4 6 8 1.3 fSW = 1 MHz VDD = 5 V VOUT = 1.2 V TA = 25°C LOUT = 1 H Mode = Auto-skip 1.25 1.2 V VIN IN ==55VV VIN 12VV V IN ==12 VIN = 18 V V IN = 18 V 2 4 6 8 10 Output Current (A) Figure 5. Output Voltage vs. Output Current Copyright © 2013, Texas Instruments Incorporated 12 C006 1.15 V VIN IN ==55VV 0 10 Output Current (A) VOUT (V) VOUT (V) 2 Vout 1V V OUT = 1 V Vout 1.5 V OUT = 1.5 V Vout 2.5 V OUT = 2.5 V Vout = 55 V V OUT = Figure 4. Efficiency vs. Output Current 1.2 1.1 12 C004 Vout V OUT = 0.6 V V Vout OUT = 1.2 V V Vout OUT = 1.8 V V Vout = 3.3 3.3 V V OUT = 60 fSW = 500 KHz VDD = 5 V VOUT = 1.2 V TA = 25°C LOUT = 1 H Mode = Auto-skip 1.15 10 fSW = 1 MHz, VIN = 12 V, VDD = 5 V TA = 25°C, L OUT = 1 H, Mode = FCCM Figure 3. Efficiency vs. Output Current 1.25 8 80 C005 1.3 6 Figure 2. Efficiency vs. Output Current 100 60 4 Output Current (A) Figure 1. Efficiency vs. Output Current 70 2 C003 12 C007 VIN 12VV V IN ==12 VIN = 18 V V IN = 18 V 1.1 0 2 4 6 8 10 Output Current (A) 12 C008 Figure 6. Output Voltage vs. Output Current Submit Documentation Feedback 9 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.3 1.2 1.15 fSW = 1 MHz VDD = 5 V TA = 25°C LOUT = 1 H Mode = FCCM VOUT = 1.2 V 1.25 VOUT (V) 1.25 VOUT (V) 1.3 fSW = 500 KHz VDD = 5 V TA = 25°C LOUT = 1 H Mode = FCCM VOUT = 1.2 V 1.2 1.15 V VIN IN ==55VV V VIN IN ==55VV VIN 12VV V IN ==12 VIN 12VV V IN ==12 VIN = 18 V V IN = 18 V 1.1 0 2 4 6 8 10 Output Current (A) VIN = 18 V V IN = 18 V 1.1 12 0 2 4 6 8 C009 Figure 7. Output Voltage vs. Output Current 600 C010 fSW = 500 kHz VDD = 5 V VOUT = 1.2 V TA = 25°C LOUT = 1 H Mode = FCCM VIN = 12 V, VDD = 5 V, TA = 25°C LOUT = 1 H, Mode = FCCM, VOUT = 1.2 V 1000 550 Frequency (KHz) Frequency (KHz) 12 Figure 8. Output Voltage vs. Output Current 1200 Fsw 250KHz KHz fSW ==250 Fsw 500KHz KHz fSW ==500 fSW ==11MHz Fsw MHz 800 10 Output Current (A) 600 500 450 400 V VIN IN ==55VV VIN 12VV V IN ==12 200 1 2 3 4 5 6 7 8 9 10 11 Output Current (A) 12 1 85 Ambient Temperature (°C) Ambient Temperature (°C) 85 70 55 VIN = VDD = 18 V VOUT = 1.2 V fSW = 1 MHz LOUT = 1 µH 2 3 4 5 7 8 9 10 11 12 13 14 15 Output Current (A) Figure 11. Safe Operating Area, VOUT = 1.2 V 10 Submit Documentation Feedback 5 6 7 8 9 10 11 12 C012 70 55 VIN = VDD = 18 V VOUT = 5 V fSW = 1 MHz LOUT = 1 µH 40 25 6 4 Figure 10. Switching Frequency vs. Output Current 100 1 3 Output Current (A) 100 25 2 C011 Figure 9. Switching Frequency vs. Output Current 40 VIN = 18 V V IN = 18 V 400 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Current (A) Figure 12. Safe Operating Area, VOUT = 5 V Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS (continued) VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 0 A Figure 13. Auto-Skip Steady-State Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 0.1 A Figure 15. Auto-Skip Steady-State Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 6 A Figure 17. Auto-Skip Steady-State Operation Copyright © 2013, Texas Instruments Incorporated VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 0 A Figure 14. FCCM Steady-State Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 0.1 A Figure 16. FCCM Steady-State Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 6 A Figure 18. FCCM Steady-State Operation Submit Documentation Feedback 11 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip Idyn = 0 A to 6 A Figure 19. Auto-Skip Mode Load Transient VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM Idyn = 0 A to 6 A Figure 20. VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 0 A Figure 21. Start-Up VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 0 A Figure 22. Start-Up VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 6 A Figure 23. Start-Up 12 Submit Documentation Feedback VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 6 A Figure 24. Start-Up Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 TYPICAL CHARACTERISTICS (continued) VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 0 A Figure 25. Shut-Down Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 6 A Figure 27. Shut-Down Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = Auto-skip IOUT = 0 A VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 0 A Figure 26. Shut-Down Operation VIN = 12 V VOUT = 1.2 V Fsw = 1 MHz Mode = FCCM IOUT = 6 A Figure 28. Shut-Down Operation VIN = 12 V VOUT = 1.2 V Fsw = 500 KHz Mode = Auto-skip IOUT = 0 A Pre-bias = 0.6 V Figure 29. Pre-Bias Operation Copyright © 2013, Texas Instruments Incorporated Figure 30. Overvoltage Protection Submit Documentation Feedback 13 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V VOUT = 1.2 V Fsw = 500 MHz Mode = FCCM Figure 31. Overcurrent Protection . . . THERMAL PERFORMANCE TA = 23°C, fSW = 500 kHz, VIN = 12 V, VOUT = 1.24 V, IOUT = 8 A, RBOOT= 0 Ω, SNB = 3 Ω + 470 pF Inductor: LOUT = 1 µH, PIMB103T-1R0MS-63, 10 mm × 11.2 mm × 3 mm, 5.3 mΩ Figure 32. SP1: 43℃ ℃ (TPS53513), SP2: 35.1℃ ℃ (Inductor) 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 APPLICATION INFORMATION General Description The TPS53513 is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-output voltage point-of-load applications with 8-A or lower output current in computing and similar digital consumer applications. The TPS53513 features proprietary D-CAP3 mode control combined with adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from 1.5 V to 18 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses emulated current information to control the modulation. An advantage of this control scheme is that it does not require a phasecompensation network outside which makes the device easy-to-use and also allows low-external component count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage while increasing switching frequency as needed during load-step transient. Frequency Selection TPS53513 allows users to select the switching frequency by using the RF pin. Table 1 lists the divider ratio and some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more reliable SW-frequency detection, use higher performance resistors. Table 1. Switching Frequency Selection (1) SWITCHING FREQUENCY (fSW) (kHz) RESISTOR DIVIDER RATIO (1) (RDR) EXAMPLE RF FREQUENCY COMBINATIONS RRF_H (kΩ) RRF_L (kΩ) 1000 > 0.557 1 300 850 0.461 180 154 750 0.375 200 120 600 0.297 249 105 500 0.229 240 71.5 400 0.16 249 47.5 300 0.096 255 27 250 < 0.041 270 11.5 Resistor divider ratio (RDR) is described in Equation 1. space RDR = RRF _ L (RRF _ L + RRF _ H ) where • • RRF_L is the low-side resistance of the RF pin resistor divider RRF_H is the high-side resistance of the RF pin resistor divider Copyright © 2013, Texas Instruments Incorporated (1) Submit Documentation Feedback 15 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com D-CAP3 Control and Mode Selection RR SW To comparator CR VOUT Figure 33. Internal RAMP Generation Circuit The TPS53513 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The amplitude of the ramp is determined by the R-C time-constant as shown in Figure 33. At different switching frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude. D-CAP3 Mode From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified as shown in Figure 34. VO CC1 CC2 RC2 SW RC1 VIN Sample and Hold DRVH PWM Comparator RFBH G FB VRAMP + + + VREF Lx Control Logic and Driver RFBL VOUT DRVL RCO COUT RLOAD Figure 34. D-CAP3 Mode The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop operation. For any control topologies supporting no external compensation design, there is a minimum and/or maximum range of the output filter it can support. The output filter used with the TPS53513 is a lowpass L-C circuit. This L-C filter has double pole that is described in Equation 2. 1 fP = 2 ´ p ´ LOUT ´ COUT (2) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS53513. The low frequency L-C double pole has a 180 degree in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases the phase to 90 degree one decade above the zero frequency. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides adequate phase margin for the stability requirement. Table 2. Locating the Zero SWITCHING FREQUENCIES (fSW) (kHz) ZERO (fZ) LOCATION (kHz) 250 and 300 6 400 and 500 7 600 and 750 9 850 and 1000 12 After identifying the application requirements, the output inductance should be designed so that the inductor peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary output capacitance for stable operation. 1 fP = = fZ 2 ´ p ´ LOUT ´ COUT (3) If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and AC bias are 80% and 50% respectively. The effective derating is the product of these two factors, which in this case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the system/applications. Table 3 shows the recommended output filter range for an application design with the following specifications: • Input voltage, VIN = 12 V • Switching frequency, fSW = 600 kHz • Output current, IOUT = 8 A The minimum output capacitance is verified by the small signal measurement conducted on the EVM using the following two criteria: • Loop crossover frequency is less than one-half the switching frequency (300 kHz) • Phase margin at the loop crossover is greater than 50 degrees For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high output capacitance for this type of converter design, then verify the small signal response on the EVM using the following one criteria: • Phase margin at the loop crossover is greater than 50 degrees As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher. However, small signal measurement (bode plot) should be done to confirm the design. Select a MODE pin configuration as shown in Table 3 to double the R-C time-constant option for the maximum output capacitance design and application. Select a MODE pin configuration to use single R-C time constant option for the normal (or smaller) output capacitance design and application. The MODE pin also selects Skip-mode or FCCM-mode operation. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com Table 3. Recommended Component Values COUT(min) (µF) CROSSOVER (kHz) 0.36 PIMB065T-R36MS 3 × 100 247 70 48 62 10 0.68 PIMB065T-R68MS 9 × 22 207 53 25 84 31.6 1.2 PIMB065T-1R2MS 4 × 22 185 57 11 63 3.3 45.3 1.5 PIMB065T-1R5MS 3 × 22 185 57 9 59 5.5 82.5 2.2 PIMB065T-2R2MS 2 × 22 185 51 7 58 VOUT (V) RUPPER (kΩ) LOUT (µH) 0.6 0 1.2 2.5 (1) RLOWER (kΩ) 10 (1) PHASE COUT(max) INTERNAL MARGIN (µF) RC SETTING (1) (°) (µs) 40 30 x 100 40 80 30 x 100 80 30 x 100 80 30 x 100 80 ICC(max) (A) 33% 80 30 x 100 INDUCTOR ΔI/ICC(max) 33% 40 34% 40 8 33% 40 28% All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V. For higher output voltage at or above 2.0 V, additional phase boost might be required in order to secure sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time topology based operation. A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at loop crossover. Refer to TI application note SLVA289 for details. Table 4. Mode Selection and Internal RAMP R-C Time Constant MODE SELECTION ACTION RMODE (kΩ) R-C TIME CONSTANT (µs) 60 275 and 325 50 425 and 525 40 625 and 750 30 850 and 1000 120 275 and 325 100 425 and 525 80 625 and 750 60 850 and 1000 60 275 and 325 50 425 and 525 40 625 and 750 30 850 and 1000 120 275 and 325 100 425 and 525 80 625 and 750 60 850 and 1000 120 275 and 325 100 425 and 525 80 625 and 750 60 850 and 1000 0 Skip Mode Pull down to GND 150 20 Connect to PGOOD FCCM (1) 150 FCCM (1) 18 Connect to VREG 0 SWITCHING FREQUENCIES fSW (kHz) Device goes into Forced CCM (FCCM) after PGOOD becomes high. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 Sample and Hold Circuitry CSP Sampled_CSP C1 Buffer 1 C2 Buffer 2 Figure 35. Sample and Hold Logic Circuitry (Patent Pending) The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry, which is an advance control scheme to boost output voltage accuracy higher on the TPS53513, is one of features of the TPS53513. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage which is produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the TPS53513 more competitive. CSP CSN CSN_NEW (sample at valley of CSP) Figure 36. Continuous Conduction Mode (CCM) With Sample and Hold Circuitry CSP CSN Figure 38. Continuous Conduction Mode (CCM) Without Sample and Hold Circuitry Copyright © 2013, Texas Instruments Incorporated CSP CSN CSN_NEW (sample at valley of CSP) Figure 37. Discontinuous Conduction Mode (DCM) With Sample and Hold Circuitry CSP CSN Figure 39. Discontinuous Conduction Mode (DCM) Without Sample and Hold Circuitry Submit Documentation Feedback 19 TPS53513 www.ti.com 1.25 1.25 1.23 1.23 1.21 1.21 VOUT (V) VOUT (V) SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 VIN = 12 V VDD = 5 V VOUT = 1.2 V fSW = 500 kHz TA = 25°C LOUT = 1 H Mode = FCCM 1.19 1.17 1.15 1 2 3 VIN = 12 V VDD = 5 V VOUT = 1.2 V fSW = 500 kHz TA = 25°C LOUT = 1 H Mode = Auto-skip 1.19 1.17 D-CAP3 D-CAP2 1.15 4 5 6 7 8 9 10 11 Output Current (A) 12 1 3 4 D-CAP2 5 6 7 8 Output Current (A) C013 Figure 40. Output Voltage vs Output Current 2 D-CAP3 9 10 11 12 C014 Figure 41. Output Voltage vs Output Current Auto-Skip Eco-mode™ Light Load Operation While the MODE pin is pulled to GND directly or via 150-kΩ resistor, the TPS53513 automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the operation in detail. As the output current decreases from heavy load condition, the inductor current also decreases until the rippled valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM). The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuousand discontinuous-conduction mode) is calculated as shown in Equation 4. IOUT(LL ) = (VIN - VOUT )´ VOUT 1 ´ 2 ´ L ´ fSW VIN where • fSW is the PWM switching frequency (4) Using only ceramic capacitors is recommended for Auto-skip mode. Adaptive Zero-Crossing The TPS53513 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency. Forced Continuous-Conduction Mode When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an amost constant level over the entire load range which is suitable for applications requiring tight control of the switching frequency at the cost of lower efficiency. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 Power-Good The TPS53513 has power-good output that indicates high when switcher output is within the target. The powergood function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up externally. Current Sense and Overcurrent Protection The TPS53513 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS53513 supports temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 μA typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 5. VTRIP = RTRIP ´ ITRIP where • • • VTRIP is in mV RTRIP is in kΩ ITRIP is in µA (5) The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly connected to the drain terminal of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to compensate the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node. Connect the GND pin to the proper current sensing device, (for example, the source terminal of the low-side MOSFET.) Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, is calculated as shown in Equation 6. IIND(ripple) (VIN - VOUT )´ VOUT VTRIP VTRIP 1 IOCP = + = + ´ 2 2 ´ L ´ fSW VIN 8 ´ RDS(on) 8 ´ RDS(on)L ( ) ( ) where • • RDS(on)L is the on-resistance of the low-side MOSFET RTRIP is in kΩ (6) Equation 6 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be used); in order to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used. During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold and shuts down. For the TPS53513, the overcurrent protection maximum is recommended up to 12 A only. Overvoltage and Undervoltage Protection The TPS53513 monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, the TPS53513 latches OFF both high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side FET is turned on again for a minimum on-time. The TPS53513 operates in this cycle until the output voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by re-toggling EN pin. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 www.ti.com Out-Of-Bounds Operation (OOB) The TPS53513 has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltageprotection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall quickly towards the setpoint. During the operation, the cycle-bycycle negative current limit is also activated to ensure the safe operation of the internal FETs. UVLO Protection The TPS53513 monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO off-threshold voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO on-threshold voltage, the controller turns back on. UVLO is a non-latch protection. Thermal Shutdown The TPS53513 monitors internal temperature. If the temperature exceeds the threshold value (typically 140°C), TPS53513 shuts off. When the temperature falls approximately 40°C below the threshold value, the device turns on. Thermal shutdown is a non-latch protection. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 External Parts Selection The external components selection is a simple process using D-CAP3™ Mode. Select the external components using the following steps 1. CHOOSE THE SW FREQUENCY The SW frequency is configured by the resistor divider on the RF pin. Select one of eight SW frequencies from 250 kHz to 1 MHz. Refer Table 1 for the relationship between the SW frequency and resistor-divider configuration. 2. CHOOSE THE OPERATION MODE Select the operation mode using Table 4. 3. CHOOSE THE INDUCTOR Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output current. Larger ripple current increases output ripple voltage, improves S/N ratio, and helps stable operation. L= 1 IIND(ripple ) ´ fSW ´ (V IN(max ) - VOUT )´V VIN(max ) OUT = 3 IOUT(max ) ´ fSW ´ (V IN(max ) - VOUT )´V OUT VIN(max) (7) The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above peak inductor current before saturation. The peak inductor current is estimated using Equation 8. IIND(peak ) = ( ) VIN(max ) - VOUT ´ VOUT VTRIP 1 + ´ 8 ´ RDS(on ) L ´ fSW VIN(max ) (8) 4. CHOOSE THE OUTPUT CAPACITOR The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM, the output ripple has two components as shown in Equation 9. Equation 10 and Equation 11 define these components. VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) (9) VRIPPLE(C ) = IL(ripple ) 8 ´ COUT ´ fSW (10) VRIPPLE(ESR ) = IL(ripple ) ´ ESR (11) 5. DETERMINE THE VALUE OF R1 AND R2 The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in APPLICATION CIRCUIT DIAGRAM. R1 is connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. The recommended R2 value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 12. V - 0.6 R1 = OUT ´ R2 0.6 (12) LAYOUT CONSIDERATIONS Before beginning a design using the TPS53513, consider the following: • Place the power components (including input and output capacitors, the inductor, and the TPS53513) on the solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and connect at least one inner plane to ground. • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as ground planes and shield the feedback trace from power traces and components. • GND (pin 22) must be connected directly to the thermal pad. Connect the thermal pad to the PGND pins and then to the GND plane. • The GND1 pin (pin 27) and the GND2 pin (pin 28) are not actual GND pins and neither of these pins should be used for dedicated ground connection. The recommendation is to connect GND1 pin (pin 27) and the GND2 pin (pin 28) to the nearby ground. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS53513 SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 • www.ti.com Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC-current loop. Place the feedback resistor near the device to minimize the VFB trace distance. Place the frequency-setting resistor (RRF), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE) close to the device. Use the common GND via to connect the resistors to the GND plane if applicable. Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for each decoupling capacitor and ensure the loop is as small as possible. The PCB trace is defined as switch node, which connects the SW pins and high-voltage side of the inductor. The switch node should be as short and wide as possible. Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection resistor. Do not combine these connections. Place one more small capacitor (2.2 nF- 0402 size) between the VIN and PGND pins. This capacitor must be placed as close to the device as possible. TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction. The value of snubber design starts at 3 Ω + 470 pF. Consider R,C,Cc network (Ripple injection network) component placement and place the AC coupling capacitor, Cc, close to the device, and R and C close to the power stage. See Figure 42 for the layout recommendation. • • • • • • • • • VIN Shape To inner GND plane CIN NC VIN VIN VIN 1 9 1 8 1 7 1 6 1 5 TRIP 2 4 VO 2 6 2 7 1 2 3 4 5 6 7 8 9 SW SW SW SW PGND NC PGND VBST PGND EN PGND PGOOD PGND RF 2 8 GND2 Trace on bottom layer Trace on inner layer GND1 2 5 DNC 1 4 VDD 2 0 1 3 VREG 2 1 1 2 MODE 2 2 1 1 GND 2 3 To VOUT Shape 1 0 FB Cc HF cap. SW Shape GND Shape COUT VOUT Shape LOUT To VREG Pin Cap. Res. Trace on bottom layer Trace of top layer RCC On Bottom layer Trace of bottom layer Trace on inner layer Figure 42. Layout Recommendation 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS53513 www.ti.com SLUSBP9A – SEPTEMBER 2013 – REVISED DECEMBER 2013 REVISION HISTORY Changes from Original (SEPTEMBER 2013) to Revision A Page • Added updates to FEATURES, APPLICATIONS, DESCRIPTION and front page graphics ............................................... 1 • Changed device dimensions from 3,5 mm × 4,5 mm to 3.5 mm × 4.5 mm ......................................................................... 1 • Added updates to Electrical Specifications ........................................................................................................................... 2 • Added updates to Electrical Specifications ........................................................................................................................... 3 • Added updates to PIN DESCRIPTIONS ............................................................................................................................... 5 • Added updates to BLOCK DIAGRAM ................................................................................................................................... 7 • Added THERMAL PERFORMANCE section ...................................................................................................................... 14 • Added updates to APPLICATION INFORMATION section ................................................................................................ 15 Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 28-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS53513RVER ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS53513 TPS53513RVET ACTIVE VQFN RVE 28 250 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS53513 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53513RVER VQFN RVE 28 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS53513RVET VQFN RVE 28 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53513RVER VQFN RVE 28 3000 367.0 367.0 35.0 TPS53513RVET VQFN RVE 28 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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