A3938 Three-Phase Power MOSFET Controller Features and Benefits Description ▪ Drives a wide range of N-channel MOSFETs ▪ Low-side synchronous rectification ▪ Power MOSFET protection ▪ Adjustable dead time for cross-conduction protection ▪ Selectable coast or dynamic brake on power-down or RESET input ▪ Fast/slow current decay modes ▪ Internal PWM current control ▪ Motor lead short-to-ground protection ▪ Internal 5 V regulator ▪ Fault diagnostic output ▪ Thermal shutdown ▪ Undervoltage protection The A3938 is a three-phase, brushless DC motor controller. It has a high-current gate drive capability that allows driving of a wide range of power MOSFETs and can support motor supply voltages to 50 V. The A3938 integrates a bootstrapped high-side driver to minimize the external component count required to drive N-channel MOSFET drivers. Internal fixed off-time, PWM current-control circuitry can be used to regulate the maximum load current to a desired value. The peak load current limit is set by the user’s selection of an input reference voltage and external sensing resistor. A userselected external RC timing network sets the fixed off-time pulse duration. For added flexibility, the PWM input can provide speed/torque control where the internal current control circuit sets a limit on the maximum current. Package 38-pin TSSOP (suffix LD): The A3938 includes a synchronous rectification feature. This shorts out the current path through the power MOSFET reverse body diodes during PWM off-cycle current decay. This can minimize power dissipation in the MOSFETs, eliminate the need for external power clamp diodes, and potentially allow a more economical choice for the MOSFET drivers. The A3938 provides commutation logic for Hall sensors configured for 120-degree spacing. The H-all input pins are pulled-up to an internally-generated 5 V reference. Power MOSFET protection features include: bootstrap capacitor charging current monitor, regulator undervoltage monitor, motor lead short-to-ground, and thermal shutdown. The LD package is lead (Pb) free, with 100% matte tin plated leadframe. Approximate Scale 1:1 RESET 1 38 N/C GLC 2 37 N/C SC 3 36 PGND N/C 4 35 AGND N/C 5 34 DEAD GHC 6 33 REF CC 7 32 SENSE GLB 8 31 RC SB 9 30 PWM GHB 10 29 BRKSEL CB 11 GLA 12 SA 13 GHA 14 CA 15 28 BRKCAP 27 BRAKE 26 DIR 25 H2 24 H3 VREG 16 23 N/C LCAP 17 22 H1 N/C 18 FAULT 19 26301.104H Fault Control Logic 21 VBB 20 MODE A3938 Three-Phase Power MOSFET Controller Selection Guide Part Number Packing A3938SLDTR-T 4000 per reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 50 V VREG Pin, Transient VREG 15 V VIN –0.3 to VLCAP + 0.3 V VSENSE –5 to 1.5 V Logic Input Voltage Range Sense Voltage Range Output Voltage Range V SA, SB, SC Pins GHA, GHB, GHC Pins CA, CB, CC Pins Operating Ambient Temperature TA Range S –5 to 50 V –5 to VBB + 17 V VSx + 17 V –20 to 85 ºC Junction Temperature TJ 150 ºC Storage Temperature Tstg –55 to 150 ºC Thermal Characteristics (may require derating at maximum conditions) Characteristic Package Thermal Resistance Symbol RθJA Test Conditions Min. Units LD package, 4 layer PCB based on JEDEC standard 51 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com ºC/W 2 A3938 Three-Phase Power MOSFET Controller Functional Block Diagram (This diagram shows only one of the three outputs) FAULT O.D. Short to GND TSD A VBB Invalid Hall VREG Undervoltage + VREG LCAP 0.1 uF Regulator + + 10 uF 0.1 uF H1 CA Charge Pump H2 CBOOT 0.1 uF H3 PWM DIR Control Logic High-Side Protection Logic Turn-On Delay High-Side Driver To Phase C GHA RESET SA BRAKE VREG MODE RC CT Low-Side Protection Logic Turn-On Delay Low-Side Driver GLA To Phase B RC Blanking Fixed Off-Time RT SENSE RS REF PGND VREG DEAD Dead-Time Adjust BRKCAP VREGUVLO RESET Power Loss Brake + 4.7uF BRKSEL AGND A For 12 V applications, VBB must be shorted to VREG. For this condition, the absolute maximum rating of 15 V on VREG must be maintained to prevent damage to the A3938. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3938 Three-Phase Power MOSFET Controller ELECTRICAL CHARACTERISTICS1,2 Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 μF, CBOOT = 0.1 μF, CVREG = 10 μF, PWM = 22.5 kHz, square wave, two phases active Characteristics Quiescent Current Symbol IVBB Test Conditions RESET = 1, Coast mode, stopped Min. Typ.1 Max. Units – – 8.0 mA LCAP Regulator VLCAP Ilcap = –3.0 mA 4.75 5 5.25 V VREG =VBB Supply Voltage Range VREG VREG = VBB, observe maximum rating = 15 V 10.8 – 13.2 V – V VREG VBB – 2.5 – VREG Output Voltage 12.4 13 13.6 V VBB = 13.2 V to 18 V, Ivreg = –10 mA VBB = 18 V to 50 V, Ivreg = –10 mA VREG Load Regulation VREGLOAD Ivreg = –1 mA to –30 mA, Coast mode – 25 – mV VREG Line Regulation VREGLIN Ivreg = –10 mA, Coast mode – 40 – mV Control Logic VIN(1) Minimum high level for logical 1 2.0 – – V VIN(0) Maximum low level for logical 0 – – 0.8 V IIN(1) VIN = 2.0 V –30 – –90 μA IIN(0) VIN = 0.8 V –50 – –130 μA Low-Side Drive, Output High VHGL Igx = 0 – V High-Side Drive, Output High VHGH Igx = 0 Logic Input Voltage Logic Input Current Gate Drive VREG – 0.8 VREG – 0.5 10.4 11.6 12.8 V Pull-Up Switch Resistance RDS(ON) Igx = –50 mA – 14 – Ω Pull-Down Switch Resistance RDS(ON) Igx = 50 mA – 4 – Ω Low-Side Switching, 10/90 Rise Time trGL Cload = 3300 pF – 120 – ns Low-Side Switching, 10/90 Fall Time tfGL Cload = 3300 pF – 60 – ns High-Side Switching, 10/90 Rise Time trGH Cload = 3300 pF – 120 – ns High-Side Switching, 10/90 Fall Time tfGH Cload = 3300 pF – 60 – ns Propagation Delay; GHx,GLx Rising Tpr PWM to gate drive out, Cload = 3300 pF – 220 – ns Propagation Delay; GHx,GLx Falling Tpf PWM to gate drive out, Cload = 3300 pF – 110 – ns Dead Time, Maximum tDEAD Vdead = 0, GHx to GLx, Cload = 0 3.5 5.6 7.6 μs Dead Time, Minimum tDEAD IDEAD = 780 μA, GLx to GHx, Cload = 0 50 100 150 ns Continued on next page... Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3938 Three-Phase Power MOSFET Controller ELECTRICAL CHARACTERISTICS1,2 (continued) Unless otherwise noted: TA = 25°C, VBB = 18 V to 50 V, CLCAP = 0.1 μF, CBOOT = 0.1 μF, CVREG = 10 μF, PWM = 22.5 kHz, square wave, two phases active Characteristics Symbol Test Conditions Min. Typ.1 Max. Units 10.4 11.6 12.8 V – 9 12 Ω 100 – – mA Bootstrap Capacitor Bootstrap Capacitor Voltage VCX Icx = 0, Vsx = 0, Vreg = 13 V Bootstrap ROUT RCX Icx = –50 mA Charge Current (Source) ICX Current Limit Circuitry Input Offset Voltage VIO 0 V < Vcmr < 1.5 V – – ±5 mV Input Current , Sense pin IB 0 V < Vcm, Vdiff < 1.5 V – –25 – μA Input Current , Reference pin IB 0 V < Vcm, Vdiff < 1.5 V – 0 – μA tBLANK R = 56 kΩ, C = 470 pF – 0.91 – μs IRC –0.9 –1 –1.1 mA VRCL 1.0 1.1 1.2 V VRCH 2.7 3.0 3.3 V – mA Blank Time RC Charge Current RC Voltage Threshold Protection Circuitry Bootstrap Charge Threshold Short to Ground, Drain-Source Monitor VREG Undervoltage Threshold Icx Vdsh UVLO GHx turns on, and GLx turns off, at Icx – –9 VBB – VSX, high side on 1.3 2.0 2.7 V VREG increasing 9.2 9.7 10.2 V VREG decreasing 8.6 9.1 9.6 V Fault Output Voltage VOUT IOL = 1 mA – – 0.5 V Brake Capacitor Supply Current IBRAKE VBB = 8 V, BRKSEL = 1 – 30 – μA Low Side Gate Voltage VGLBH VBB=0, BRKCAP = 8V – 6.6 – V Thermal Shutdown Temperature TJ – 165 – °C Thermal Shutdown Hysteresis ΔTJ – 10 – °C 1 Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 2 Negative current is defined as conventional current coming out of (sourced from) the specified device terminal. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3938 Three-Phase Power MOSFET Controller Pin Descriptions RESET. A logic input that enables the device. Has internal 50 kΩ pull-up to LCAP. Setting RESET to 1 coasts or brakes the motor, depending on the state of the BRKSEL pin. Setting RESET to 0 enables the gate drive to follow commutation logic. Setting RESET to 1 overrides the BRAKE pin. GLA/GLB/GLC. Low-side gate drive outputs for external MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. SA/SB/SC. Directly connected to the motor terminals, these pins sense the voltages switched across the load. The pins are also connected to the negative side of the bootstrap capacitors and the negative supply connections for the floating high-side drivers. GHA/GHB/GHC. High-side gate drive outputs for N-channel MOSFET drivers. External series gate resistors can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of Sx outputs. CA/CB/CC. High-side connections for bootstrap capacitors, providing positive supply for high-side gate drivers. The bootstrap capacitors are charged to approximately VREG when the output Sx terminals go low. When the outputs swing high, the voltages on these pins rise with the outputs to provide the boosted gate voltages needed for the N-channel power MOSFETs. the motor depending on stored setting for BRKSEL). • Thermal shutdown (coasts the motor). • Motor lead (SA/SB/SC) connected to ground (turns off only the high-side power MOSFETs). Only the “short-to-ground” fault is latched, but it is cleared at each commutation. If the motor has stalled due to a shortto-ground being detected, toggling the RESET pin or repeating a power-up sequence clears the fault. BRAKE. Logic input for braking function. Setting BRAKE to 1 turns on low-side MOSFETs, and turns off the high-side MOSFETs. This effectively shorts the BEMF in the windings and brakes the motor. Internal 50 kΩ pull-up to LCAP. Setting RESET to 1 overrides this BRAKE pin. See also BRKSEL. BRKCAP. This pin is for connection of the reservoir capacitor used to provide the positive power supply for the sink drive outputs for a power-down condition. This allows predictable braking, if desired. Using a 4.7 F capacitor will provide 6.5 V gate drive for 300 ms. If the power-down braking option is not needed (i.e., BRKSEL = 0), then this pin should be tied to VREG. BRKSEL. Logic input to enable/disable braking upon power-down condition or RESET = 1. Internal 50 kΩ pull-up to LCAP. Setting BRKSEL to 0 enables Coast mode. Setting BRKSEL to 1 enables Brake mode. MODE. Logic input to set current-decay mode. In response to a PWM Off command, Slow Decay mode (MODE = 1) switches off the high-side FET, and Fast Decay mode (MODE = 0) switches off the high-side and low-side FETs. Has an internal 50 kΩ pull-up to LCAP. PWM. Speed control input. Setting PWM to 1 turns on MOSFETs selected by Hall input logic. Setting PWM to 0 turns off the selected MOSFETs. Keep the PWM input held high to utilize internal current control circuitry. Internal 50 kΩ pull-up to LCAP. H1/H2/H3. Hall sensor inputs with internal, 50 kΩ pull-ups RC. Analog input. Connection for RT and CT to set the fixed off-time. CT also sets the BLANK time (see the section Application Information). It is recommended that the fixed off-time should not be less than 10 μs. The resistor should be in the range between 10 kΩ and 500 kΩ. to LCAP. Configured for 120-degree electrical spacing. DIR. Logic input to reverse rotation (see the table Commutation Truth Table, on the next page). Has internal, 50 kΩ pull-up to LCAP. FAULT. Open-drain output to indicate fault condition. Will be pulled high (usually by 5.1 kΩ external pull-up) for any of the following fault conditions: • Invalid Hall sensor input code (coasts the motor). • Undervoltage condition detected at VREG (coasts or brakes VREG. Regulated 13 V supply for the low-side gate drive and the bootstrap capacitor charge circuit. As a regulator, use a 10 μF decoupling/storage capacitor (ESR < 1 Ω) from this pin to AGND, as close to the device pins as possible. Note: For 12 V applications, the VREG pin should be shorted to VBB. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3938 Three-Phase Power MOSFET Controller VBB. Motor power supply connection for the A3938 and for power MOSFETs. It is good practice to connect a decoupling capacitor from this pin to AGND, as close to the device pins as possible. REF. Analog input to current limit comparator. Voltage applied here sets the peak load current according to the following equation: ITRIP = VREF / RSENSE DEAD. Analog input. A resistor between DEAD and LCAP is selected to adjust turn-off time to turn-on time. This delay is needed to prevent cross-conduction in the external power MOSFETs. See the section Application Information for details on setting dead time. SENSE. Analog input to the current limit comparator. Voltage representing load current appears on this pin. Voltage transients that are seen at this pin when the drivers turn on are ignored for period of time, tBLANK. LCAP. 5 V reference to power internal logic and provide AGND. Analog reference ground. low current for DEAD pin and FAULT pin. Connection for 0.1 μF external capacitor for decoupling. PGND. Return for low-side gate drivers. This should be connected to the PCB power ground. Commutation Truth Table H1 1 1 1 0 0 0 1 1 1 0 0 0 H2 0 0 1 1 1 0 0 0 1 1 1 0 H3 1 0 0 0 1 1 1 0 0 0 1 1 DIR 1 1 1 1 1 1 0 0 0 0 0 0 GLA 0 0 1 1 0 0 1 0 0 0 0 1 GLB 0 0 0 0 1 1 0 1 1 0 0 0 GLC 1 1 0 0 0 0 0 0 0 1 1 0 GHA 1 0 0 0 0 1 0 0 1 1 0 0 GHB 0 1 1 0 0 0 0 0 0 0 1 1 GHC 0 0 0 1 1 0 1 1 0 0 0 0 SA HI Z LO LO Z HI LO Z HI HI Z LO SB Z HI HI Z LO LO Z LO LO Z HI HI SC LO LO Z HI HI Z HI HI Z LO LO Z Input Logic MODE PWM RESET Quadrant Mode of Operation** PWM chop – current decay with opposite of selected low0* 0 0 Fast decay side drivers ON. Selected drivers ON. If current limiting, opposite of selected 0* 1 0 Fast Decay low-side drivers ON. 1 0 0 Slow decay PWM chop – current decay with both low-side drivers ON. 1 1 0 Slow Decay Selected drivers ON. If current limiting, both low-side drivers ON. All high-side drivers OFF, low-sides see BRKSEL stored. X X 1 X Clears storable faults. * Low-side, only, Synchronous Rectification mode. **See Commutation Truth Table for meaning of “both” and "selected." Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3938 Three-Phase Power MOSFET Controller Application Information Synchronous Rectification. To reduce power consumption in the external MOSFETs, during the load current recirculation PWM-off cycle, the A3938 control logic turns on the appropriate low-side driver only. The reverse body diode of the power MOSFET conducts only during the dead time required at each PWM transition, as usual. However, unlike full synchronous rectification, the opposite high-side FET’s body diode (not the RDSON) will carry the re-circulating current, be self-extinguishing, and not force the motor to reverse direction. Dead Time. To prevent cross-conduction, it is required to have a delay between a high-side or low-side turn-off, and the next turn-on event. The potential for cross-conduction occurs with synchronous rectification, direction changes, PWM, or after a bootstrap capacitor charging cycle. This dead-time is set via a resistor from the DEAD pin to LCAP and can be varied from 100 ns to 5.5 μs. For a nominal case, given: • 25°C ambient temperature, and • 5.6 kΩ < Rdead < 470 kΩ, tdead (nom,ns) = 37 + [(11.9 ×10 ) × (R -3 dead + 500)] For predicting worst-case overvoltage and temperature extremes, use the following equations: tdead (min,ns) = 10 + [(6.55 ×10 ) × (R dead + 350)] ×10 ) ×(R dead + 650)] tdead (max,ns) = 63 + [(17.2 -3 -3 For nominal comparison with Idead currents, also at 25°C ambient temperature: Idead = (Vlcap – Vbe) / (Rdead + Rint) Decoupling. The internal reference VREG supplies current for the gate drive circuit. As the gates are driven high, they will require current from an external decoupling capacitor to support the transients. This capacitor should be placed as close as possible to the VREG pin. The value of the capacitor should be at least 20 times larger than the bootstrap capacitor. Additionally, a 1 nF (or larger) ceramic monolithic capacitor should be connected between LCAP and AGND, as close to the device pins as possible. Protection Circuitry. The A3938 has several protection features: • Bootstrap Monitor. The bootstrap capacitor is charged whenever a sink-side MOSFET is on, an Sx output goes low, or load current recirculates. This happens constantly during normal operation. Note: The high side will not be allowed to turn on before the charging has decayed to less than approximately 9 mA. • Undervoltage. VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are at a proper level before enabling any of the outputs. The undervoltage circuit is active during power-up and signals a fault, and also coasts or brakes (depending on the stored BRKSEL setting) the motor during that time period, until VREG is greater than approximately 10 V. On powering down, a fault is signaled and the motor is coasted or braked, depending on the stored setting for BRKSEL. • Hall Invalid. Illegal codes for the Hall sensor inputs (0,0,0 or 1,1,1) force a fault and coast the motor. Noisy Hall lines may cause Hall code errors, and therefore faults. Additional external pull-up loading and filtering may be required in some systems. where Vlcap = 5 V, Vbe = 0.7 V, and Rint = 500 Ω. Hint: Use dividers to the VREG terminal, than to the LCAP terminal, because the VREG terminal has more current capability. Rather than use Rdead values near 470 kΩ, set Vdead = 0 V, which activates an internal (Idead = 10 μA) current source. 165C cause the A3938 to signal a fault and coast the motor. The choice of power MOSFET and external gate resistance determines the selection of the dead-time resistor. The dead time should be made long enough to cover the variation of the MOSFET capacitance and gate resistor tolerances (both external and internal to the A3938). • Motor Lead. The A3938 signals a fault if the motor lead is shorted to ground. A short-to-ground is assumed after a high- side is turned on and greater than 2 V is measured between the drain (VBB) and source (Sx) of the high-side power MOSFET. This fault is cleared at the beginning of • Thermal Shutdown. Junction temperatures greater than Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3938 Three-Phase Power MOSFET Controller each commutation. If a stalled motor results from a fault, the fault can only be cleared by toggling the RESET pin or by a power-up sequence. Current Regulation. Load current can be regulated by an internal fixed off-time, PWM-control circuit. When the outputs of the MOSFETs are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF / RSENSE At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed offtime period. The current path during recirculation is determined by the configuration of the MODE and SR input pins. The fixed off-time is determined by an external resistor, RT, and capacitor, CT, connected in parallel from the RC terminal to AGND. The fixed off-time is approximated by: tOFF = RT ×C T tOFF should be in the range between 10 μs and 50 μs. Larger values for tOFF could result in audible noise problems. For proper circuit operation, 10 kΩ < RT < 500 kΩ. Torque control can be implemented by varying the REF input voltage as long as the PWM input stays high. If direct control of the torque/current is desired by PWM input, a voltage can be applied to the REF pin to set an absolute maximum current limit. PWM Blank. The capacitor CT also serves as the means to set the BLANK time duration. At the end of a PWM off-cycle, a high-side gate selected by the commutation logic turns on. At this time, large current transients can occur during the reverse recovery time, trr, of the intrinsic body diodes of the power MOSFETs. To prevent false tripping of the sense comparator, the BLANK function disables the comparator for a time period defined by: tBLANK = 1.9 ×C T / (1 × 10 -3 – [2 / RT]) The user must ensure that CT is large enough to cover the current spike duration. Braking. The A3938 dynamically brakes the motor by forcing all low-side power MOSFETs on, and all high-side power MOSFETs off. This effectively short-circuits the BEMF and brakes the motor. During braking, the load current can be approximated by: IBRAKEPEAK = VBEMF / RLOAD As the current does not flow through the sense resistor during a dynamic brake, care should be taken to ensure that the maximum ratings of the power MOSFETs are not exceeded. Note: On its rising edge, a RESET setting of 1 overrides the BRAKE input pin and latches the condition selected by the BRKSEL pin. Power Loss Brake. The BRKCAP and BRKSEL pins provide a power-down braking option. A Power-Loss Brake Trigger Event, which is either an undervoltage on VREG or a RESET = 1 rising edge, is sensed by the A3938, which then dynamically brakes or coasts (depending on the stored BRKSEL setting) the motor. The reservoir capacitor on the BRKCAP pin provides the positive voltage that forces the low-side gates of the power MOSFETs high, keeping them on, even after supply voltage is lost. A stored setting of BRKSEL = 1 brakes the motor, but a stored setting of BRKSEL = 0 coasts it. The combined effect of these settings is shown in the table Brake Control. Brake Control BRAKE 0 0 1 1 BRKSEL 0 1 0 1 Before Power Loss Brake Trigger Event Normal run mode Normal run mode Brake mode – All low-side gate drivers ON Brake mode – All low-side gate drivers ON After Power Loss Brake Trigger Event Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON Coast mode – All gate drive outputs OFF Brake mode – All low-side gate drivers ON Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3938 Three-Phase Power MOSFET Controller Terminal List Name Description Number PGND Low-Side Gate Drive Return 36 RESET Control Input 1 GLC Low-Side Gate Drive Output, Phase C 2 Motor Connection, Phase C 3 High-Side Gate Drive Output, Phase C 6 CC Bootstrap Capacitor, Phase C 7 GLB Low-Side Gate Drive Output, Phase B 8 SC GHC SB Motor Connection, Phase B 9 High-Side Gate Drive Output, Phase B 10 CB Bootstrap Capacitor, Phase B 11 GLA Low-Side Gate Drive Output, Phase A 12 Motor Connection, Phase A 13 GHB SA GHA High-Side Gate Drive Output, Phase A 14 Bootstrap Capacitor, Phase A 15 VREG Gate Drive Supply 16 LCAP 5 V Output 17 FAULT Diagnostic Output 19 MODE Control Input 20 VBB Load Supply 21 H1 Hall Control Input 22 H3 Hall Control Input 24 H2 Hall Control Input 25 DIR Control Input 26 BRAKE Control Input 27 BRKCAP Power Loss Brake Reservoir Capacitor 28 BRKSEL Control Input 29 PWM Control Input 30 Connection for Fixed Off-Time R and C 31 Sense Resistor 32 Current Limit Adjust 33 DEAD Dead Time Adjust 34 AGND Ground 35 CA RC SENSE REF N/C Not Connected 4, 5, 18, 23, 37, 38 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A3938 Three-Phase Power MOSFET Controller LD Package, 38-pin TSSOP 1.60 9.70 ±0.10 4º 0.50 38 0.30 38 +0.06 0.15 –0.05 4.40 ±0.10 6.40 ±0.20 6.00 A 1 2 1 2 0.25 38X SEATING PLANE 0.10 C 0.22 ±0.05 0.50 C 1.20 MAX 0.10 ±0.05 B SEATING PLANE GAUGE PLANE PCB Layout Reference View All dimensions nominal, not for tooling use (reference JEDEC MO-153 BD-1) Dimensions in millimeters A Terminal #1 mark area B Reference pad layout (reference IPC SOP50P640X110-38M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©2003-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11