HA13568AT CD-ROM Combo Driver ADE-207-261A (Z) 2nd Edition December 1998 Description The HA13568AT is combination of Spindle, Forcus, Tracking, Slide, Tray designed for CD-ROM and have following functions and features. Features • • • • • • • 1.5 A sensorless spindle driver 0.5 A BTL focus driver 0.5 A BTL tracking driver 1.5 A H bridge slide motor driver 0.5 A H bridge tray motor driver Over temperature shut down (OTSD) Voltage regulator control circuit Functions • • • • • Sensorless driver with self start Soft switching drive Snubberless Low output saturation voltage Direct PWM slide driver HA13568AT Pin Arrangement GND FCSREF FCSIN FCSRS TRRRS VFCS FCSP FCGND FCSN TRRP TRRN TRYP TRYN VSLD SLGND SLDN SLDP VBST B1 B2 RNF U V W VSPN WFIL VFIL GND 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Top view) 2 GND TRRREF TRRIN NC NC NC TRYLIM TRYR TRYF SLDIN SLDLIM RT CT2 VSS CT3 CT1 CE VREGF VREGS BRKSEL PHASE PC CT AGC VCTL REFIN UFIL GND HA13568AT Pin Description Pin No. Pin Name Function 2 FCSREF FCS driver block reference voltage 3 FCSIN FCS control input pin 4 FCSRS FCS sense pin 5 TRRRS TRR sense pin 6 VFCS FCS driver and TRR driver power supply 7 FCSP FCS driver P output 8 FCGND FCS driver and TRR driver GND 9 FCSN FCS driver N output 10 TRRP TRR driver P output 11 TRRN TRR driver N output 12 TRYP TRY driver P output 13 TRYN TRY driver N output 14 VSLD SLD driver and TRY driver power supply 15 SLGND SLD driver and TRY driver GND 16 SLDN SLD driver N output 17 SLDP SLD driver P output 18 VBST Booster output pin. This circuit generates a voltage about 1.5 V above that of the VSPN pin. 19 B1 Booster pumping capacitor connection 20 B2 21 RNF Spindle driver current detection 22 U U phase output 23 V V phase output 24 W W phase output 25 VSPN Spindle and booster power supply 26 WFIL W phase low pass filter. Connect a filter C to this pin during GND. 27 VFIL V phase low pass filter. Connect a filter C to this pin during GND. 30 UFIL U phase low pass filter. Connect a filter C to this pin during GND. 31 REFIN Reference voltage of spindle and slide 32 VCTL Spindle control input. Generates forward torque when a DC voltage higher than REFIN is applied, and brake when a DC voltage lower than REF is applied. 33 AGC For AGC. Holds the level used for IC internal processing fixed even if the B-EMF level fluctuates due to the rotation speed. 34 CT Spindle center tap 35 PC Spindle driver phase compensation 3 HA13568AT Pin Description (cont) Pin No. Pin Name Function 36 PHASE Outputs the B-EMF zero cross phase. Open corrector. (See the timing chart) 37 BRKSEL To select the brake mode. Lo: Short brake, Hi: Reverse full brake (when forward torque input: BRKSEL = H) 38 VREGS Voltage regulator sense pin (VREGS ≈ 3.3 V output) 39 VREGF Voltage regulator force pin 40 CE Chip enable. Input Hi: active 41 CT1 Time constant for clock oscillator circuit. The clock oscillator frequency is determined by the external capacitor and resistor Ct1 and Rt. 42 CT3 Time constant for PWM carrier oscillator. The carrier frequency is determined by the external capacitor and resistor Ct3 and Rt. 43 VSS Control block power supply. 5 V 44 CT2 Time constant for start-up oscillator. The start-up oscillator frequency is determined by the external capacitor and resistor Ct2 and Rt. 45 RT Reference voltage (3.3 V). The IC’s internal reference current is determined by this voltage and the external resistor Rt. 46 SLDLIM SLD output maximum duty setting 47 SLDIN SLD control input pin 48 TRYF TRY driver forward input 49 TRYR TRY driver reverese input 50 TRYLIM TRY output voltage setting pin 51 NC No connection 52 NC 53 NC 54 TRRIN TRR control input pin 55 TRRREF TRR driver block reference voltage 1, 28, 29, 56, TAB 4 GND HA13568AT Block Diagram C102 VSS 43 UFIL VFIL WFIL AGC 33 U V W 34 CT 30 27 B-EMF detection 26 PHASE 36 Vspn Commutation Tmask 44 Ct2 1.5A SPN output Drive mode Mask time CT2 VSPN 25 Vref V 23 W 24 21 VCTL 32 CE 40 Rt RT 45 CT1 41 Ct1 22 Vbst Start-up circuit U V SPN W RNF Rnf Current control REFIN 31 BRKSEL 37 U 35 OTSD Brake 19 CLK Bias CLK OSC 20 Vbst 18 FCSIN 3 B2 VBST N P 10 0.5A BTL Vfcs 2 B1 6 VFCS FCSP 7 FCSRS 4 FCSN 9 P FCSREF 2 PC FCS Vbst TRRIN 54 TRRREF 55 0.5A BTL Vfcs 2 5 TRRP TRRRS TRR TRRN N 11 P 14 VSLD SLDP 17 N 16 P 12 N 13 8 FCGND Vbst SLDIN 47 1.5AH bridge SLD control SLDLIM 46 M SLD M TRY SLDN Vbst VREGS 38 VREGF 39 0.5AH bridge Vreg TRYP TRYN 15 SLGND TAB CT3 42 Ct3 49 50 48 TRYLIM TRYF TRYR 51 , 52 , 53 : NC pin 5 HA13568AT Timing Chart 1. Start-up CE 0 Tc2 Vhct2 Vlct2 16Tc2 14Tc2 12Tc2 10Tc2 8Tc2 6Tc2 0 2Tc2 4Tc2 4Tc2 4Tc2 4Tc2 4Tc2 CT2 + Output current 0 (U phase) − + Output current 0 (V phase) − + Output current 0 (W phase) − PHASE 0 B-EMF Mask period Synchronous mode Note: Tc2 is as follows. Tc2 = Where, 6 8 (Vhct2 − Vlct2) Rt Ct2 Vrt Vhct2 : CT2 pin high voltage (See electrical characteristics) Vlct2 : CT2 pin low voltage (See electrical characteristics) B-EMF mode HA13568AT 2. Acceleration (switching mode) U V W V W Reverse + start-up voltage 0 B-EMF − PHASE 0 + Output current 0 (U phase) − + Output current 0 (V phase) − + Output current 0 (W phase) − 3. Running (soft switching mode) U Reverse start-up voltage B-EMF + PHASE 0 Output voltage (U phase) 0 − 0 + Output current 0 (U phase) − 7 HA13568AT Truth Table Table 1 Overall CE OTSD SPN Driver FCS Driver TRR Driver SLD Driver TRY Driver L X Z Z Z Z Z H ON Z Z Z Z Z OFF ON ON ON ON ON Note: X: Option, Z: Hi impedance Table 2 SPN Driver BRKSEL VCTL SPN Driver X > REFIN Forward torque REFIN Z L < REFIN Short brake H REFIN – 0.6 V Reverse brake Note: X: Option, Z: Hi impedance Table 3 TRY Driver TRYF TRYR P Output N Output L L Z Z L H L H H L H L H H H H Note: Z: Hi impedance 8 HA13568AT Application 1. FCS, TRR voltage drive +5V +12V C101 VSS C102 VSPN AGC CT UFIL U VFIL V WFIL W C103 C104 SPN C105 Ct2 5V CT2 R105 Rnf Q1 Cpc VREGF 3.3V VREGS Vcc MPU RNF C108 PHASE PC BRKSEL B1 C106 CE R101 VCTL C109 B2 Rt1 C107 RT Rt2 VBST Ct1 CT1 REFIN VREF VFCS FCSP FCSRS FCSN TRRP TRRRS TRRN FCGND VSLD SLDP DMO R110 FOO FCSIN R111 FCSREF R112 TRO TRRIN R113 TRRREF R102 FMO SLDIN C110 +5V R103 C111 R104 C112 FCS TRR R106 M SLD Ct3 SLDLIM SLDN CT3 TRYP TRYF TRYR TRYLIM R107 M TRY TRYN SLGND TAB 9 HA13568AT 2. FCS, TRR voltage drive FCSP R110 FO R111 FCSIN (Zin ≈ 12kΩ) C111 RSFCS FCSREF (Zin ≈ 12kΩ) DSP FCSN R108 C113 R112 TO R113 REF R103 FCS FCSRS TRRIN (Zin ≈ 12kΩ) TRRP R104 TRR C112 TRRRS TRREF (Zin ≈ 12kΩ) RSTRR TRRN R109 C114 Note: Other pins have the same connections as those used in application 1. 3. When used at a voltage other than 3.3 V with a voltage regulator (Vout = 3.3 to Vcc – 1 V) Vcc (5V or 12V) R105 Q1 VREGF + − Vout C115 Rr1 3.3V VREGS 3.3V Rr2 Note: Other pins have the same connections as those used in application 1. 10 HA13568AT External Components Parts No. Reccomended Value Reccomended Range Purpose R101 47 kΩ ≤ 47 kΩ Filter for SPN driver control input R102 47 kΩ ≤ 47 kΩ Filter for SLD driver control input R103 6.8 Ω — To stop FCS block oscillation R104 6.8 Ω — To stop TRR block oscillation R105 500 Ω ≥ 100 Ω for Q1 bias R106 20 kΩ — for TRY driver output voltage setting R107 27 kΩ — R108 6.8 Ω — To stop FCS block oscillation R109 6.8 Ω — To stop TRR block oscillation R110 to R113 20 kΩ — for BTL gain setting 7 Rnf 0.25 Ω ≥ 0.25 Ω SPN driver current detection resistor 1 Rt1 1.8 kΩ Rt1 + Rt2 = 10 kΩ Reference current setting and SLD driver maximum duty setting 2, 5 Rt2 8.2 kΩ RSFCS 1Ω ≥ 0.33 Ω for FCS driver current sense 7 RSTRR 1Ω ≥ 0.33 Ω for TRR driver current sense Rr1 — — Voltage regulator division resistor Rr2 — — C101 0.1 µF ≥ 0.1 µF C102 0.047 µF for B-EMF Amplitude AGC C103 0.01 µF for B-EMF filter Note 8 for Power supply by passing 6 C104 C105 C106 0.22 µF ≥ 0.22 µF for Booster pumping C107 0.47 µF ≥ 0.47 µF for Booster output smoothing C108 0.1 µF for SPN driver phase compensation C109 0.01 µF Filter for SPN control input C110 3300 pF Filter for SLD control input C111 0.01 µF — To stop FCS block oscillation C112 0.01 µF — To stop TRR block oscillation C113 0.01 µF — To stop FCS block oscillation C114 0.01 µF — To stop TRR block oscillation C115 2.2 µF for Voltage regulator smoothing 11 HA13568AT External Components (cont) Parts No. Reccomended Value Reccomended Range Ct1 150 pF ≥ 120 pF Ct2 0.033 µF Ct3 470 pF ≥ 390 pF Q1 Note: Purpose Note Time constant for CLK oscillation. Use a capacitor with good temperature characteristics. 3 Time constant for start-up oscillation. Use a capacitor with good temperature characteristics. 4 PWM carrier oscillation time constant 5 Transistor for voltage regulator 1. The output current maximum value Iospnmax of SPN driver is controlled according to the following equation. However, Vspncl is the current limiter reference voltage. (See the electrical characteristics) Vspncl Iospnmax = Rnf 2. The maximum duty Dmax of SLD driver output is controlled according to the following equation. Dmax = Vrt Vhct3 − Vlct3 Rt2 Vlct3 − × 100 (%) Rt Vrt However, Rt = Rt1 + Rt2, Vlct3 Rt2 ≥ Vrt Rt Where, Vrt : RT pin voltage (See the electrical characteristics) Vlct3 : CT3 pin low voltage (≈ 1.3 V) Vhct3 : CT3 pin high voltage (≈ 3.3 V) Since Vrt ≈ Vhct3, Dmax is not limited at 100% when Rt1 = 0 Ω. 3. The CLK oscillation frequency is determined by the following equation. fclk = Vrt 8 Ct1 Rt ∆Vct1 Where, Vrt : RT pin voltage (See the electrical characteristics) ∆Vct1 : CT1 pin voltage amplitude (≈ 1 V) 4. The Ct2 for start-up oscillation is determined by the following equation. Tc2 = 1 6 Ct2 = Tc2 Vrt 8 Rt (Vhct2 − Vlct2) J P Kt Ispnmax Where, J P Kt Vhct2 Vlct2 12 : Spindle motor inertia (kg · cm · S 2) : Number of spindle motor poles (Total number of S poles and N poles) : Spindle motor torque constant (kg · cm / A) : CT2 pin high voltage (≈ 3.3 V) : CT2 pin low voltage (≈ 1.3 V) HA13568AT 5. The PWM oscillation frequency fpwm is determined by the following equation. Vrt fpwm = 8 Ct3 Rt (Vhct3 − Vlct3) Where, Vhct3 : CT3 pin high voltage (≈ 3.3 V) Vlct3 : CT3 pin low voltage (≈ 1.3 V) 6. The C103 to C105 for B-EMF filter are determined by the following equation. 21 35 ≤ C103 ≤ π ⋅ Rflt ⋅ No ⋅ P π ⋅ Rflt ⋅ No ⋅ P Where, Rfill : B-EMF detection output resistor (See the electrical characteristics) No : Maximum rotation speed (rpm) 7. The FCS and TRR is determined by the following equation. Voltage drive: R1 Gv = Rin + R2 Current drive: R1 Gm = ((Rin + R2) ⋅ Rs) Where, R1 R2 Rin : Resistor of IC inside (≈30kΩ) : Resistor of IC inside (≈7kΩ) : Resistor value inserted in the input (Ω) (R110 to R113) Rs : Current sense resistor (Ω) 8. The output voltage Vout of voltage regulator is determined by the following equation. Vout = 3.3 1 + Rr1 Rr2 13 HA13568AT Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Note Supplu voltage Vss 7 V 1 SPN supply voltage Vspn 15 V 1 FCS & TRR supply voltage Vfcs 15 V 1 SLD & TRY supply voltage Vsld 15 V 1 Input voltage Vin 0 to Vss V 2 Vintrylim Vss to Vsld V SPN output current Iospn 1.5 A 3 FCS & TRR & TRY output current Iofcs 0.5 A 3 SLD output current Iosld 1.5 A 3 Power dissipation PT 5 W 4 Junction temperature Tj 160 °C 1 Storage temperature range Tstg –55 to +125 °C Note: 1. Operating voltage range is shown below. Vss = 4.25 to 5.75 V Vspn = 4.25 to 13.8 V Vfcs = 4.25 to 13.8 V (However, the output high voltage is clamped at 7 V.) Vsld = 4.25 to 13.8 V Tjopr = 0 to +135°C 2. Applied to BRKSEL, VCTL, REFIN, CE, FCSIN, FCSREF, TRRIN, TRRREF, SLDIN, SLDLIM, TRYF and TRYR. 3. ASO (Area of Safety Operation) of each output transistor is shown below (TBD). ASO of SLD driver 2.0 1.5 1.5 1.0 t = 0.1ms 0.5 t = 1ms t = 10ms 0.2 0.1 1 2 5 10 15 20 The voltage between Corrector and Emitter Vce (V) Corrector Current Ic (A) Corrector Current Ic (A) ASO of SPN driver 2.0 1.0 t = 0.1ms 0.5 t = 1ms t = 10ms 0.2 0.1 1 2 5 10 15 20 The voltage between Corrector and Emitter Vce (V) 4. Thermal resistance is shown below. θj-tab ≤ 12°C / W (back side tab soldering area is 70% or more) θj-a ≤ 25°C / W (mounted on 4 layer multi glass-epoxy board, back side tab soldering area is 70% or more) 14 HA13568AT Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vspn = 12 V, Vfcs = 5 V, Vsld = 12 V) Item Symbol Min Typ Max Unit Test Conditions Applicable Pins Quiescent current Iss0 — 0.7 0.9 mA CE = L VSS Ispn0 — — 0.2 mA VSPN Ifcs0 — — 0.01 mA VFCS Isld0 — — 0.01 mA VSLD Iss1 14 20 25 mA CE = H, VCTL = VSS Ispn1 11 15 20 mA FCSIN = TRRIN = VSPN Ifcs1 6 10 15 mA SLDIN = REFIN, VFCS Isld1 — — 1.0 mA TRYF = TRYR = L All load open VSLD Iss2 20 33 60 mA CE = H, VCTL = VSS Ispn2 11 30 50 mA FCSIN = TRRIN = VSPN Ifcs2 7 10 15 mA SLDIN = 5 V, VFCS Isld2 –15 –1.0 1.0 mA TRYF, TRYR = H, L, All load open VSLD Iince 0 70 100 µA Vin = 0 to 5 V BRKSEL, Iin — — ±10 µA CE, TRYF, Low level voltage Vil — — 0.8 V TRYR High level voltage Vih 2.0 — — V Logic Low level voltage Vol — — 0.4 V Io = 1 mA output Leak current Icer1 — — ±10 µA Vce = 15 V SPN driver Output saturation voltage Vsatspn — 1.25 1.75 V Iospn = 1.0 A Leak current Icer2 1.3 2.2 3 mA Vce = 15 V Current limiter voltage Vspncl 238 265 292 mV Rnf = 0.25 Ω Input resistance Rinfcs 9.6 12 14.4 kΩ Rinfcsref 9.6 12 14.4 kΩ Vinfcs 0 — 5 V Logic Input current input FCS driver Input voltage range Note PHASE U, V, W 1 RNF 2 FCSIN 15 HA13568AT Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vspn = 12 V, Vfcs = 5 V, Vsld = 12 V) (cont) Symbol Min Typ Max Unit Test Conditions Applicable Pins Output quiescent voltage Vqfcs 2.375 2.5 2.625 V FCSIN=FCSREF= 2.5 V, VFCS=5 V FCSP, FCSN Output offset voltage Vosfcs — — ±20 mV Output saturation voltage Vsatfcs — 1.0 1.4 V Voltage gain Gvfcs 11.6 12.6 13.6 dB Gain band width Bfcs 100 — — kHz Input resistance Rintrr 9.6 12 14.4 kΩ Rintrrref 9.6 12 14.4 kΩ Input voltage range Vintrr 0 — 5 V Output quiescent voltage Vqtrr 2.375 2.5 2.625 V FCSIN=TRRREF= 2.5 V, VFCS=5 V Output offset voltage Vostrr — — ±20 mV FCSIN = REF Output saturation voltage Vsattrr — 1.0 1.4 V Io = 0.33 A Voltage gain Gvtrr 11.6 12.6 13.6 dB Gain band width Btrr 100 — — kHz ∆Gv = –3 dB Output saturation voltage Vsatsld — 1.5 2.0 V Iosld = 0.75 A Leak current Icer3 — — ±100 µA Vce = 15 V Penetration current Iovlap — — 100 Transient response tplh1 — — time tphl1 — Output saturation voltage Vsattry Leak current Item FCS driver TRR driver SLD driver TRY driver 16 Io = 0.33 A Note 3 1 4 ∆Gv = –3 dB TRRIN TRRP, TRRN 3 1 4 SLDP, SLDN 1 mA VSLD 8 5 µs SLDP, — 5 µs SLDN — 1.0 1.4 V Iotry = 0.33 A Icer3 — — ±100 µA Vce = 15 V Penetration current Iovlap — — 100 Transient response tplh1 — — time tphl1 — Input current Iintrylim Output voltage Vlimtry TRYP, TRYN 1 mA VSLD 8 5 µs TRYP, — 5 µs TRYN — — ±5 µA Vtrylim=7 to VSLD 0.1 0.7 1.0 V RL = 16Ω, Vtrylim = 7 V 9 HA13568AT Electrical Characteristics (Ta = 25°C, Vss = 5 V, Vspn = 12 V, Vfcs = 5 V, Vsld = 12 V) (cont) Item Symbol Min Typ Max Unit Test Conditions Applicable Pins Note Vctl = 0 to Vss–1V VCTL, 2 SPN Input current Iinspn — — ±5.0 µA current REF voltage range Vref 1.6 — 3.0 V control Dead zone voltage Vdzspn ±50 — ±120 mV Current control gain Gctl — –12 ±1.5 dB Drive Change threshold Vctl — 0.5 ±0.1 V Vref reference VCTL 5 mode voltage fPHASE — ≥f CT2 ±50% Hz SOFT SW mode U, V, W 5 — <fCT2 –20% Hz SW mode SW ↔ SOFT SW B-EMF REFIN Vref reference RNF Output resistance Rflt — 10 ±20% kΩ Threshold voltage of PHASE occurrence Viemf — 40 ±50% mVpp VSPN ≥ Vss + 3VF — 28 ±50% mVpp VSPN ≤ Vss + 3VF UFIL, VFIL, WFIL detection U, V, W CLK RT voltage Vrt 3.135 3.30 3.465 V OSC CLK oscillation frequency fclk 210 240 270 kHz Rt = 10 kΩ, Ct1 = 82 pF CT1 Start-up circuit Start-up oscillation frequency fct2 437 485 534 Hz Rt = 10 kΩ, Ct2 = 0.033 µF CT2 SLD Input current I insld — — ±5.0 µA Vsld = 0 to Vss–1V SLDIN control Input voltage range Vinsld 0 — 4.0 V Limiter input current Isldlim — — ±5.0 µA PWM oscillation frequency fpwm 33 38 42.35 kHz Control gain D/V 80 90 100 %/V Offset voltage Vossld — — 20 mV SLDIN = REFIN Output sink current Isinkreg 8.5 12.2 — mA VREGS = 4 V, VREGF = 4 V Output voltage Voutreg 3.135 3.30 3.465 V Operating temperature Tsd 135 160 — °C Hysteresis Thys — 50 — °C Voltage regulator OTSD 6 RT SLDLIM Rt = 10 kΩ, Ct3 = 470 pF 7 8 17 HA13568AT 1. The output saturation voltage is the sum of the upper and lower saturation voltages. 2. See figure 1. Where, ∆Vrnf Gctl = 20 log Forward Reverse ∆Vctl torque torque Vspncl Vdzspn Vrnf (V) Note: ∆Vrnf ∆Vctl Vref 0 Figure 1 Vctl (V) Reverse brake Short brake 3. Where, Vfcsp + Vfcsn 2 Vtrrp + Vtrrn Vqtrr = 2 Vqfcs = 4. See figure 2. Where, Vfcsp (Vtrrp) & Vfcsn (Vtrrn) ∆Vfcsp (∆Vtrrp) (V trr p) n) trr cs p ∆Vfcsin (∆Vtrrin) Vf ∆Vtrrn ∆Vtrrin (V ∆Vtrrp ∆Vtrrin n Gvtrr = 20 log cs ∆Vfcsp ∆Vfcsn ∆Vfcsin ∆Vfcsin Vf Gvfcs = 20 log 0 Vref Vfcsin (Vtrrin) Figure 2 , ,, fPHASE (Hz) 5. The circuit operates in soft switching drive mode only when the control input (Vctl) is lower than f CT2 and fPHASE is higher than the threshold voltage. See figure 3. SOFT SW mode SW mode fCT2 SW mode 0 Figure 3 6. PHASE is output only when B-EMF exceeds the threshold voltage. 18 0.5V VCTL − REFIN HA13568AT Duty (%) 7. See figure 4. Where, ∆D D/V = ∆Vin SLDP = PWM SLDN = H SLDP = H SLDN = PWM 100 ∆D Vref ∆Vin 0 Vinsld (V) Figure 4 8. Design guide only. 9. Vlimtry = VTRYP – VTRYLIM, or VTRYN – VTRYLIM 19 HA13568AT 20 rm ra e ow 1 er +L arm p Up rm er a ow m, L r ar 0 0 e Upp 0.5 1.0 Output Current Iospn (A) 1.5 SLD Driver Output Saturation Voltage vs. Output Current 4 3 m r we 2 rm + ar Lo ra e pp U 1 r we , Lo r ppe 0 0 arm arm U 0.5 1.0 Output Current Iosld (A) 1.5 Output Saturation Voltage Vsatfcs (V) 2 Output Saturation Voltage Vsattrr (V) SPN Driver Output Saturation Voltage vs. Output Current 3 TRY Driver Output Saturation Voltage vs. Output Current 3 2 er 1 rm a er + w Lo p Up 0 0 ower m, L er ar arm FCS Driver Output Saturation Voltage vs. Output Current 3 2 rm ra e ow 1 rm ra +L pe Up 0 0 r arm Lowe arm, r e p Up 0.2 0.4 Output Current Iofcs (A) 0.6 TRR Driver Output Saturation Voltage vs. Output Current 3 2 arm er 1 r ppe arm + Low U 0 0 er arm , Low r arm Uppe 0.2 0.4 Output Current Iotrr (A) 0.6 RT Voltage vs. Junction Temperature 3.6 RT Voltage Vrt (V) Output Saturation Voltage Vsattry (V) Output Saturation Voltage Vsatsld (V) Output Saturation Voltage Vsatspn (V) Reference Data 3.4 3.2 arm Upp 0.2 0.4 Output Current Iotry (A) 0.6 3.0 0 25 50 75 100 135 Junction Temperature Tj (°C) HA13568AT Package Dimensions Preliminary Unit: mm 14.0 14.2 Max 29 6.10 56 Top view 1 0.50 0.21 +0.04 −0.05 0.19 +0.03 −0.05 28 0.08 M 1.0 8.10 ± 0.15 0.08 0.05 ± 0.05 0° − 8° 0.17 ± 0.05 0.15 ± 0.04 1.20 Max 0.65 Max 0.50 ± 0.1 (7.5) 28 (2.8) 1 Under view 56 29 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-56DT 0.32 g 21 HA13568AT Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 22