MCP39F511N Dual-Channel, Single-Phase Power-Monitoring IC with Calculation Features Description • Power Monitoring of Two Loads with accuracy of 0.5% across 4000:1 Dynamic Range • Built-in Calculations on Fast 16-Bit Processing Core: - Active, Reactive, Apparent Power - True RMS Current, RMS Voltage - Line Frequency, Power Factor • 64-bit Wide Import and Export Active Energy Accumulation Registers Per Channel • 64-bit Four Quadrant Reactive Energy Accumulation Registers Per Channel • Signed Active and Reactive Power Outputs • Dedicated Zero Crossing Detection (ZCD) Pin Output with Less than 200 µs Latency • Dedicated PWM Output Pin with Programmable Frequency and Duty Cycle • Automatic Event Pin Control through Fast Voltage Surge Detection - Less than 5 ms Delay • Two-Wire Serial Protocol with Selectable Baud Rate up to 115.2 kbps using Universal Asynchronous Receiver/Transmitter (UART) • Fast Calibration Routines and Simplified Command Protocol • 512 Bytes User-Accessible EEPROM through Page Read/Write Commands • Low-Drift Internal Voltage Reference, 10 ppm/°C Typical • 28-lead 5x5 QFN Package • Extended Temperature Range: -40°C to +125°C The MCP39F511N is a highly integrated, complete dual-channel single-phase power-monitoring IC designed for real-time measurement of input power for dual-socket wall outlets, power strips, and consumer and industrial applications. It includes dual-channel 24-bit Delta-Sigma ADCs for dual-current measurements, a 10-bit SAR ADC for voltage measurement, a 16-bit calculation engine, EEPROM and a flexible two-wire interface. An integrated low-drift voltage reference with 10 ppm/°C in addition to 94.5 dB of SINAD performance on each measurement channel allows for better than 0.5% accurate designs across a 4000:1 dynamic range. Package Types 2015 Microchip Technology Inc. ZCD REFIN+/OUT NC 2 20 V+ NC 3 19 I2+ EP 29 UART_RX 4 COMMONA 5 18 I217 I116 I1+ OSCI 6 15 EVENT2 OSCO 7 PWM COMMONB AVDD 9 10 11 12 13 14 RESET 8 UART_TX Wall Socket (Dual Plug) Power Monitoring Power Monitoring for Home Automation Industrial Lighting Power Monitoring Real-Time Measurement of Input Power for AC/DC Supplies • Intelligent Power Distribution Units MCLR 21 AGND NC • • • • DVDD DGND 28 27 26 25 24 23 22 EVENT1 1 NC Applications DGND DR MCP39F511N 5x5 QFN* *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005473A-page 1 MCP39F511N Functional Block Diagram I1+ I1- I2+ I2- + PGA - + PGA - V+ DS20005473A-page 2 AVDD AGND DVDD DGND Internal Oscillator 24-bit Delta-Sigma Multi-level Modulator ADC 24-bit Delta-Sigma Multi-level Modulator ADC 10-bit SAR ADC SINC3 Digital Filter OSCO Timing Generation SINC3 Digital Filter OSCI UART Serial Interface 16-BIT CORE FLASH UART_TX UART_RX PWM EVENT1 Calculation Engine (CE) EVENT2 Digital Outputs ZCD 2015 Microchip Technology Inc. MCP39F511N Typical Application L N 10 1 µF + I1- AVDD DVDD RESET REFIN/OUT+ 33 nF LOAD – 0.1 µF 0.1 µF 1 k 2 m +3.3V 0.1 µF 1 k I1+ to MCU UART 1 k LOAD + 2 m – UART_TX 33 nF I2- UART_RX 33 nF to MCU UART 1 k (OPTIONAL) I2+ MCP39F511N 33 nF NC NC NC NC DR +3.3V 499 k 51 k 47 µ F 499 k 5.1 k 1 k V+ 51 k 33 nF COMMONA,B 33 nF N.C. Leave Floating Connect on PCB EVENT1 L N EVENT2 ZCD OSCO PWM 4 MHz OSCI 22 pF DGND AGND 22 pF (OPTIONAL) +3.3V 0.47 µ F 470 MCP1754 0.01 µF DGND Note: 470 µF AGND The external sensing components shown here, the 2 mΩ shunts, two 499 kΩ and 5.1 kΩ resistor for the 200:1 voltage divider, are specifically chosen to match the default values for the calibration registers defined in Section 6.0 “Register Descriptions”. By choosing low-tolerance components of these values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero calibration. See Section 9.0 “MCP39F511N Calibration” for more information. 2015 Microchip Technology Inc. DS20005473A-page 3 MCP39F511N 1.0 † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † DVDD .................................................................. -0.3 to +4.5V AVDD .................................................................. -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND ............... -0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ............... ....-2V to +2V VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin..............................300 mA Maximum Current into DVDD pin .................................250 mA Maximum Output Current Sunk by Digital IO ................25 mA Maximum Current Sourced by Digital IO.......................25 mA Storage temperature .....................................-65°C to +150°C Ambient temperature with power applied......-40°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V ESD on all other pins (HBM,MM) ........................4.0 kV, 200V 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Active Power (Note 1) P — ±0.5 — % 4000:1 Dynamic Range on Current Channel (Note 2) Reactive Power (Note 1) Q — ±0.5 — % 4000:1 Dynamic Range on Current Channel (Note 2) Apparent Power (Note 1) S — ±1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Current RMS (Note 1) IRMS — ±1 — % 4000:1 Dynamic Range on Current Channel (Note 2) Voltage RMS (Note 1) VRMS — ±1 — % 4000:1 Dynamic Range on Voltage Channel (Note 2) Power Factor (Note 1) — ±1 — % Line Frequency (Note 1) LF — ±1 — % Power Measurement Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only. DS20005473A-page 4 2015 Microchip Technology Inc. MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions 2N x (1/fLINE) — ms Note 3 see — ms Note 4 Calibration, Calculation and Event Detection Times Auto-Calibration Time tCAL — Minimum Time for Voltage Surge/Sag Detection tAC_SASU — Section 7.0 24-Bit Delta-Sigma ADC Performance Analog Input Absolute Voltage VIN -1 — +1 V Analog Input Leakage Current AIN — 1 — nA Differential Input Voltage Range (I1+ – I1-), (I2+ – I2-) -600/GAIN — +600/GAIN mV VOS -1 — +1 mV Offset Error Offset Error Drift Gain Error — 0.5 — µV/°C GE -4 — +4 % — 1 — ppm/°C ZIN 232 — — k 142 — — k G=2 72 — — k G=4 Gain Error Drift Differential Input Impedance Signal-to-Noise and Distortion Ratio VREF = 1.2V, proportional to VREF SINAD Note 5 G=1 38 — — k G=8 36 — — k G = 16 33 — — k G = 32 92 94.5 — dB Note 6 Total Harmonic Distortion THD — -106.5 -103 dBc Note 6 Signal-to-Noise Ratio SNR 92 95 — dB Note 6 SFDR — 111 — dB Note 6 Spurious Free Dynamic Range Crosstalk CTALK — -122 — dB AC Power Supply Rejection Ratio AC PSRR — -73 — dB AVDD and DVDD = 3.3V + 0.6VPP, 100 Hz, 120 Hz, 1 kHz DC Power Supply Rejection Ratio DC PSRR — -73 — dB AVDD and DVDD = 3.0 to 3.6V DC Common Mode Rejection Ratio DC CMRR — -105 — dB VCM varies from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only. 2015 Microchip Technology Inc. DS20005473A-page 5 MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions 10-Bit SAR ADC Performance for Voltage Measurement Resolution NR — 10 — bits Absolute Input Voltage VIN DGND - 0.3 — DVDD + 0.3 V Recommended Impedance of Analog Voltage Source RIN — — 2.5 k Integral Nonlinearity INL — ±1 ±2 LSb Differential Nonlinearity DNL — ±1 ±1.5 LSb Gain Error GERR — ±1 ±3 LSb Offset Error EOFF — ±1 ±2 LSb UART Baud Rate UDB 1.2 — 115.2 kbps Master Clock and Crystal Frequency fMCLK -2% 8 +2% MHz Capacitive Loading on OSCO pin COSC2 — — 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC — 2 — % -40°C to +85°C only (Note 7) VREF -2% 1.2 +2% V TCVREF — 10 — Output Impedance ZOUTVREF — 2 — k Current, VREF AIDDVREF — 40 — µA — — 10 pF VREF+ AGND + 1.1V — AGND + 1.3V V AVDD, DVDD 2.7 — 3.6 V VPOR DGND — 0.7 V Clock and Timings See Section 3.2 for protocol details Internal Voltage Reference Internal Voltage Reference Tolerance Temperature Coefficient ppm/°C TA = -40°C to +85°C, VREFEXT = 0 Voltage Reference Input Input Capacitance Absolute Voltage on VREF+ Pin Power Specifications Operating Voltage DVDD Start Voltage to Ensure Internal Power-On Reset Signal Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only. DS20005473A-page 6 2015 Microchip Technology Inc. MCP39F511N TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions DVDD Rise Rate to Ensure Internal Power-on Reset Signal SDVDD 0.05 — — V/ms 0 – 3.3V in 0.1s, 0 – 2.5V in 60 ms AVDD Start Voltage to Ensure Internal Power-on Reset Signal VPOR AGND — 2.1 V SAVDD 0.042 — — V/ms IDD — 15 — mA Cell Endurance EPS 100,000 — — E/W Self-Timed Write Cycle Time TIWD — 4 — ms Number of Total Write/Erase Cycles Before Refresh RREF — 10,000,000 — E/W TRETDD 40 — — Years IDDPD — 7 — mA AVDD Rise Rate to Ensure Internal Power-on Reset Signal Operating Current 0 – 2.4V in 50 ms Data EEPROM Memory Characteristic Retention Supply Current during Programming Note 1: 2: 3: 4: 5: 6: 7: Provided no other specifications are violated Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 16 line cycles, channel 1 or channel 2. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or TCAL = 320 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical Performance Curves” for typical performance. VIN = 1 VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and UART only. 2015 Microchip Technology Inc. DS20005473A-page 7 MCP39F511N TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6 V, TA = -40°C to +125°C, MCLK = 4 MHz Characteristic Sym. Min. VIH 0.8 DVDD Low-Level Input Voltage VIL 0 High-Level Output Voltage VOH 3 Low-Level Output Voltage VOL ILI High-Level Input Voltage Input Leakage Current TABLE 1-3: Typ. Max. Units Test Conditions — DVDD V — 0.2 DVDD V — — V IOH = -3.0 mA, VDD = 3.6V — — 0.4 V IOL = 4.0 mA, VDD = 3.6V — — 1 µA — 0.050 0.100 µA Digital Output pins only (ZCD, PWM, EVENT1, EVENT2) TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 36.9 — °C/W Conditions Temperature Ranges Thermal Package Resistance Thermal Resistance, 28LD 5x5 QFN DS20005473A-page 8 2015 Microchip Technology Inc. MCP39F511N 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% -0.40% -0.50% 0.01 0.1 1 10 100 Current Channel Input Amplitude (mVPEAK) FIGURE 2-1: 0 fIN = -60 dBFS @ 60 Hz fD = 3.9 ksps 16384 pt FFT OSR = 256 -20 -40 Amplitude (dB) Measurement Error (%) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz, channel 1 or channel 2. -60 -80 -100 -120 -140 -160 -180 -200 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) Active Power, Gain = 1. FIGURE 2-4: Spectral Response. RMS Current, Gain = 1. 10 100 1000 -105.8 -105.9 -106.1 Total Harmonic Distortion (-dBc) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1 -106.2 1000 FIGURE 2-5: Total HDrmonic Distortion(dBc) Energy Accumulation Error (%) FIGURE 2-2: 100 -106.4 1 10 Input Voltage RMS (mVPP) -106.5 0.1 -106.7 -0.100% -106.8 -0.050% -107.0 0.000% -107.1 0.050% -107.3 Frequency of Occurrence RMS Current Error (%) 0.100% 10000 100000 THD Histogram. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 G=1 G=8 -50 -25 0 G=2 G = 16 25 50 75 Temperature (°C) G=4 G = 32 100 125 150 Energy Accumulation (Watt-Hours) FIGURE 2-3: Energy, Gain = 8. 2015 Microchip Technology Inc. FIGURE 2-6: THD vs. Temperature. DS20005473A-page 9 MCP39F511N Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz, channel 1 or channel 2. 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-7: SNR Histogram. 100 90 80 70 60 50 40 30 20 10 0 G=1 G=8 -50 -25 0 FIGURE 2-8: G=2 G = 16 Internal Voltage Reference (V) Frequency of Occurrence 1.2008 1.2007 1.2006 1.2005 1.2004 1.2003 1.2002 1.2001 1.2000 1.1999 -50 FIGURE 2-10: vs. Temperature. 0 50 Temperature (°C) 100 150 Internal Voltage Reference G=4 G = 32 25 50 75 100 125 150 Temperature (°C) SINAD vs. Temperature. 5 4 Gain Error (%) 3 2 1 0 -1 -2 -3 G=1 G=8 -4 -5 -50 -25 0 25 G=2 G = 16 50 75 G=4 G = 32 100 125 150 Temperature (°C) FIGURE 2-9: DS20005473A-page 10 Gain Error vs. Temperature. 2015 Microchip Technology Inc. MCP39F511N 3.0 PIN DESCRIPTION The pin descriptions are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP39F511N 5x5 QFN Symbol 1 EVENT1 2, 3, 8, 9 NC Function Event 1 Output pin No Connect (must be left floating) 4 UART_RX UART Communication RX pin 5 COMMONA Common pin A, to be connected to pin 13 (COMMONB) 6 OSCI Oscillator Crystal Connection pin or External Clock Input pin 7 OSCO Oscillator Crystal Connection pin 10 RESET Reset pin for Delta Sigma ADCs 11 AVDD 12 UART_TX Analog Power Supply pin UART Communication TX pin Common pin B, to be connected to pin 5 (COMMONA) 13 COMMONB 14 PWM 15 EVENT2 16 I1+ Non-Inverting Current Channel 1 Input for 24-bit ADC 17 I1- Inverting Current Channel 1 Input for 24-bit ADC 18 I2- Inverting Voltage Channel 2 Input for 24-bit ADC 19 I2+ Non-Inverting Current Channel 2 Input for 24-bit ADC 20 V+ Non-Inverting Voltage Channel Input for 10-bit SAR ADC 21 AGND Analog Ground pin, return path for internal analog circuitry 22 ZCD Zero Crossing Detection Output 23 REFIN+/OUT Pulse-Width Modulation (PWM) Output pin Event 2 Output pin Non-Inverting Voltage Reference Input and Internal Reference Output pin 24, 27 DGND Digital Ground pin, return path for internal digital circuitry 25 DVDD Digital Power Supply pin 26 MCLR Master Clear for device 28 DR Data Ready (must be left floating) 29 EP Exposed Thermal Pad (to be connected to pins 24 and 27 (DGND)) 2015 Microchip Technology Inc. DS20005473A-page 11 MCP39F511N 3.1 Event Output Pins (EVENTn) These digital output pins can be configured to act as output flags based on various internal raise conditions. Control is modified through the Event Configuration register. 3.2 UART Communication Pins (UART_RX, UART_TX) The MCP39F511N device contains an asynchronous full-duplex UART. The UART communication is eight bits with the Start and Stop bits. See Section 4.3 “UART Settings” for more information. 3.3 Common Pins (COMMON A and B) The COMMONA and COMMONB pins are internal connections for the MCP39F511N. These two pins should be connected together in the application. 3.4 Oscillator Pins (OSCI/OSCO) OSCI and OSCO provide the master clock for the device. Appropriate load capacitance should be connected to these pins for proper operation. An optional 8 MHz crystal can be connected to these pins. If a crystal or external clock source is not detected, the device will clock from the internal 8 MHz oscillator. 3.5 Analog Power Supply Pin (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP39F511N. This pin requires appropriate bypass capacitors and should be maintained to 2.7V and 3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.7 24-Bit Delta Sigma ADC Differential Current Channel Input Pins (I1+/I1-/I2+/I2-) (I1-, I1+), (I2-, I2+) are the two fully-differential current-channel pair inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mVPEAK/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each In+/- input pin is ±1V with no distortion and ±6V with no breaking after continuous voltage. 3.9 Voltage Analog Input (V+) This is the non-inverting input to the SAR ADC for voltage measurement input. This input is used as the voltage measurement for both channel 1 and channel 2. Care should be taken to limit the voltage input here to within 300 mV of DGND. DC offset of DVDD/2 and approximately 1 VRMS AC input signal. 3.10 Analog Ground Pin (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). If an analog ground pin is available on the PCB, it is recommended that this pin be tied to that plane. Reset Pin (RESET) This pin is active-low and places the Delta-Sigma ADCs, PGA, internal VREF and other blocks associated with the analog front-end in a Reset state when pulled low. This input is Schmitt-triggered. 3.6 3.8 Pulse-Width Modulator (PWM) This digital output is a dedicated PWM output that can be controlled through the PWM Frequency and PWM Duty-Cycle Registers. See Section 8.0 “Pulse-Width modulation (PWM)” for more information. DS20005473A-page 12 3.11 Zero Crossing Detection (ZCD) This digital output pin is the output of the zero crossing detection circuit of the IC. The output here will be a logic output with edges that transition at each zero crossing of the voltage channel input. For more information see Section 5.10 “Zero Crossing Detection (ZCD)”. 3.12 Non-Inverting Reference Input/Internal Reference Output Pin (REFIN+/OUT) This pin is the non-inverting side of the differential voltage reference input for the delta sigma ADCs or the internal voltage reference output. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. 2015 Microchip Technology Inc. MCP39F511N 3.13 Digital Ground Connection Pins (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). If a digital ground plane is available, it is recommended to tie this pin to the digital plane of the PCB. This plane should also reference all other digital circuitry components in the system. 3.14 Digital Power Supply Pin (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP39F511N. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. It is recommended to use 0.1 µF ceramic capacitors. 3.15 Data Ready Pin (DR) The Data Ready pin indicates if a new Delta-Sigma A/D conversion result is ready to be processed. This pin is for indication only and should be left floating. After each conversion is finished, a low pulse will take place on the Data Ready pin to indicate the conversion result is ready and an interrupt is generated in the calculation engine (CE). This pulse is synchronous with the line frequency to ensure an integer number of samples for each line cycle. Note: 3.16 This pin is internally connected to the IRQ of the calculation engine and should be left floating. Exposed Thermal Pad (EP) This pin is the exposed thermal pad. It must be connected to DGND. 2015 Microchip Technology Inc. DS20005473A-page 13 MCP39F511N NOTES: DS20005473A-page 14 2015 Microchip Technology Inc. MCP39F511N 4.0 COMMUNICATION PROTOCOL If a custom communication protocol is desired, please contact a Microchip sales office. Note: All communication to the device occurs in frames. Each frame consists of a header byte, the number of bytes in the frame, a command packet (or command packets) and a checksum. It is important to note that the maximum number of bytes in either a Receive or Transmit frame is 35. Frame Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 ...Command Packet n Checksum Command BYTE1 BYTE2 BYTE N BYTE0 BYTE N FIGURE 4-1: MCP39F511N Communication Frame. This approach allows for single, secure transmission from the host processor to the MCP39F511N with either a single command or multiple commands. No command in a frame is processed until the entire frame is complete and the checksum and number of bytes are validated. The number of bytes in an individual command packet depends on the specific command. For example, to set the instruction pointer, three bytes are needed in the packet: the command byte and two bytes for the address you want to set to the pointer. The first byte in a command packet is always the command byte. 4.1 Device Responses After the reception of a communication frame, the MCP39F511N has three possible responses, which are returned with or without data, depending on the frame received. These responses are either: • Acknowledge (ACK, 0x06): Frame received with success, commands understood and commands executed with success. • Negative Acknowledge (NAK, 0x15): Frame received with success, however commands not executed with success, commands not understood or some other error in the command bytes. • Checksum Fail (CSFAIL, 0x51): Frame received with success, however the checksum of the frame did not match the bytes in the frame. Note: There is one unique device ID response which is used to determine which MCP39FXXX device is present: [NAK(0x15) + ID_BYTE]. If the device is interrogated with 0x5A, i.e. it receives 0x5A as the first byte instead of the standard 0xA5 first header byte, a special NAK is returned followed by an ID_BYTE. For the MCP39F511N the ID_BYTE is 0x03. 2015 Microchip Technology Inc. 4.2 Checksum The checksum is generated using simple byte addition and taking the modulus to find the remainder after dividing the sum of the entire frame by 256. This operation is done to obtain an 8-bit checksum. All the bytes of the frame are included in the checksum, including the header byte and the number of bytes. If a frame includes multiple command packets, none of the commands will be issued if the frame checksum fails. In this instance, the MCP39F511N will respond with a CSFAIL response of 0x51. On commands that are requesting data back from the MCP39F511N, the frame and checksum are created in the same way, with the header byte becoming an Acknowledge (0x06). Communication examples are given in Section 4.5 “Example Communication Frames and MCP39F511N Responses”. 4.3 UART Settings The default baud rate is 115.2 kbps and can be changed using the UART bits in the System Configuration Register. Note that the baud rate is changed only at system power-up, so when changing the baud rate, a Save To Flash command followed by a power-on cycle is required. The UART operates in 8-bit mode, plus one start bit and one stop bit, for a total of 10 bits per byte, as shown in Figure 4-1. IDLE START D0 D1 FIGURE 4-1: D2 D3 D4 D5 D6 D7 STOP IDLE UART Transmission, N-8-1. DS20005473A-page 15 MCP39F511N 4.4 Command List The following table is a list of all accepted command bytes for the MCP39F511N. There are 10 possible accepted commands for the MCP39F511N. TABLE 4-1: MCP39F511N INSTRUCTION SET Command # Command Command ID Instruction Parameter Number of bytes Successful Response UART_TX 1 Register Read, N bytes 0x4E Number of bytes 2 ACK, Data, Checksum 2 Register Write, N bytes 0x4D Number of bytes 1+N ACK 3 Set Address Pointer 0x41 ADDRESS 3 ACK 4 Save Registers To Flash 0x53 None 1 ACK 5 Page Read EEPROM 0x42 PAGE 2 ACK, Data, Checksum 6 Page Write EEPROM 0x50 PAGE 18 ACK 7 Bulk Erase EEPROM 0x4F None 1 ACK 8 Auto-Calibrate Gain 0x5A Channel Selection (1) Note 2 9 Auto-Calibrate Reactive Gain 0x7A Channel Selection (1) Note 2 Auto-Calibrate Frequency 0x76 None Note 2 10 Note 1: 2: 4.5 Each bit in the instruction parameter byte refers to the corresponding channel that is being calibrated with the command. For example, if bits 0 and 1 are high, both channels 1 and 2 will be calibrated. A NAK or ACK will be returned. If a NAK is returned, refer to the Calibration Status bits in the Event Configuration Register for more information. See Section 9.0 “MCP39F511N Calibration” for more information on calibration. Example Communication Frames and MCP39F511N Responses Tables 4-2 to 4-11 show exact hexadecimal communication frames as they are recommended to be sent to the MCP39F511N from the system MCU. The values here can be used as direct examples for writing the code to communicate to the MCP39F511N. TABLE 4-2: REGISTER READ, N BYTES COMMAND (Note 1) Byte # Value Description 1 0xA5 Header Byte 2 0x08 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0x4E Command (Register Read, N Bytes) 7 0x20 Number of Bytes to Read (32) 8 0x5E Checksum Response from MCP39F511N ACK + Number of Bytes (35) + 32 bytes + Checksum Note 1: This example Register Read, N bytes frame, as it is written here, can be used to poll a subset of the output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame. DS20005473A-page 16 2015 Microchip Technology Inc. MCP39F511N TABLE 4-3: REGISTER WRITE, N- BYTES COMMAND (Note 1) Byte # Value 1 0xA5 Header Byte 2 0x17 Number of Bytes in Frame (23) 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0xB1 Address Low 6 0x4D Command (Register Write, N Bytes) 7 0x0F Number of Bytes to Write (15) 8-22 *Data* 23 Checksum Description Response from MCP39F511N Data Bytes (15 total data bytes) Checksum ACK Note 1: This Register Write, N Bytes frame, as shown here, is writing channel 1 range and calibration target values, starting at address 0xB1 (the second byte in the Channel 1 Range register) and then writing 15 bytes of data to consecutive addresses to complete the setup of channel 1 registers prior to calibration. Note these are not the calibration registers, but the calibration targets which need to be written prior to issuing the auto-calibration target commands. See Section 9.0 “MCP39F511N Calibration” for more information. TABLE 4-4: SET ADDRESS POINTER COMMAND (Note 1) Byte # Value Description 1 0xA5 Header Byte 2 0x06 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0xEE Checksum Response from MCP39F511N ACK Note 1: The Set Address Pointer command is typically included inside of a frame that includes a read or write command, as shown in Tables 4-2 and 4-3. There is typically no reason for this command to have its own frame, but is shown here as an example. TABLE 4-5: SAVE TO FLASH COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x53 Command (Save To Flash) 4 0xFC Checksum TABLE 4-6: Description Response from MCP39F511N ACK PAGE READ EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x42 Command (Page Read EEPROM) 4 0x01 Page Number (e.g. 1) 5 0xED Checksum 2015 Microchip Technology Inc. Description Response from MCP39F511N ACK + EEPROM Page Data + Checksum DS20005473A-page 17 MCP39F511N TABLE 4-7: PAGE WRITE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x15 Number of Bytes in Frame 3 0x50 Command (Page Write EEPROM) Page Number (e.g. 1) 4 0x01 5-20 *Data* 21 Checksum TABLE 4-8: Description EEPROM Data (16 bytes/Page) Checksum ACK BULK ERASE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x4F Command (Bulk Erase EEPROM) 4 0xF8 Checksum TABLE 4-9: Response from MCP39F511N Description Response from MCP39F511N ACK AUTO-CALIBRATE GAIN COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x5A Command (Auto-Calibrate Gain) 4 0x03 Instruction Parameter (Channel Instruction, calibrate both channels 1 and 2) 5 0x07 Checksum Response from MCP39F511N ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information. TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND Byte # Value Description 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x7A Command (Auto-Calibrate Reactive Gain) 4 0x01 Instruction Parameter (Channel Instruction, calibrate channel 1 only) 5 0x25 Checksum Response from MCP39F511N ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information. DS20005473A-page 18 2015 Microchip Technology Inc. MCP39F511N TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND Byte # Value Description Response from 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x76 Command (Auto-Calibrate Frequency) 4 0x1F Checksum ACK (or NAK if unable to calibrate)(1) Note 1: See Section 9.0 “MCP39F511N Calibration” for more information. 4.6 4.6.1 Command Descriptions REGISTER READ, N BYTES (0x4E) The Register Read, N Bytes command returns the N bytes that follow whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other read commands. An Acknowledge, Data and Checksum is the response for this command. The maximum number of bytes that can be read with this command is 32. If there are other read commands within a frame, the maximum number of bytes that can be read is 32 minus the number of bytes being read in the frame. With this command, the data is returned LSB first. 4.6.2 REGISTER WRITE, N BYTES (0x4D) The Register Write, N Bytes command is followed by N bytes that will be written to whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other write commands. An Acknowledge is the response for this command. The maximum number of bytes that can be written with this command is 32. If there are other write commands within a frame, the maximum number of bytes that can be written is 32 minus the number of bytes being written in the frame. With this command, the data is written LSB first. 4.6.3 SET ADDRESS POINTER (0x41) This command is used to set the address pointer for all read and write commands. This command is expecting the address pointer as the command parameter in the following two bytes: Address High Byte followed by Address Low Byte. The address pointer is two bytes in length. If the address pointer is within the acceptable addresses of the device, an Acknowledge will be returned. 4.6.4 4.6.5 PAGE READ EEPROM (0x42) The Page Read EEPROM command returns 16 bytes of data that are stored in an individual page on the MCP39F511N. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. This command is expecting the EEPROM page as the command parameter or the following byte. The response to this command is an Acknowledge, 16-bytes of data and CRC Checksum. 4.6.6 PAGE WRITE EEPROM (0x50) The Page Write EEPROM command is expecting 17 additional bytes in the command parameters, which are the EEPROM page plus 16 bytes of data. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. The response to this command is an Acknowledge. 4.6.7 BULK ERASE EEPROM (0x4F) The Bulk Erase EEPROM command will erase the entire EEPROM array and return it to a state of 0xFFFF for each memory location of EEPROM. A more complete description of the memory organization of the EEPROM can be found in Section 10.0 “EEPROM”. The response to this command is Acknowledge. 4.6.8 AUTO-CALIBRATE GAIN (0x5A) The Auto-Calibrate Gain command initiates the single-point calibration that is all that is typically required for the system. This command calibrates the RMS current, RMS voltage and Active power based on the target values written in the corresponding registers. The instruction parameter for this command selects if you are calibrating channel 1, 2 or both. Bit 0 corresponds to channel 1 and bit 1 corresponds to channel 2. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. The response to this command is Acknowledge. SAVE REGISTERS TO FLASH (0x53) The Save Registers To Flash command makes a copy of all the calibration and configuration registers to flash. This includes all R/W registers in the register set. The response to this command is an Acknowledge. 2015 Microchip Technology Inc. DS20005473A-page 19 MCP39F511N 4.6.9 AUTO-CALIBRATE REACTIVE POWER GAIN (0x7A) The Auto-Calibrate Reactive Gain command initiates a single-point calibration to match the measured Reactive power to the target Reactive power. The instruction parameter for this command selects if you are calibrating channel 1, 2, or both. Bit 0 corresponds to channel 1 and bit 1 corresponds to channel 2. This is typically done at PF = 0.5. See section Section 9.0 “MCP39F511N Calibration” for more information on device calibration. 4.6.10 AUTO-CALIBRATE FREQUENCY (0x76) For applications not using an external crystal and running the MCP39F511N off the internal oscillator, a gain calibration to the line frequency indication is required. The Gain Line Frequency register is set such that the frequency indication matches what is set in the Line Frequency Reference register. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. 4.7 Notation for Register Types The following notation has been adopted for describing the various registers used in the MCP39F511N: TABLE 4-12: SHORT-HAND NOTATION FOR REGISTER TYPES Notation Description u64 Unsigned, 64-bit register u32 Unsigned, 32-bit register s32 Signed, 32-bit register u16 Unsigned, 16-bit register s16 Signed, 16-bit register b32 32-bit register containing discrete Boolean bit settings DS20005473A-page 20 2015 Microchip Technology Inc. MCP39F511N 5.0 CALCULATION ENGINE (CE) DESCRIPTION 5.1 Computation Cycle Overview The MCP39F511N uses a coherent sampling algorithm to phase lock the sampling rate to the line frequency on the voltage channel input with an integer number of samples per line cycle, and reports all power output quantities at a 2N number of line cycles. This is defined as a computation cycle and is dependent on the line frequency, so any change in the line frequency will change the update rate of the power outputs. There are two separate computation paths, using two currents from two separate channels (channel 1 and channel 2) referenced below as IN and V. Therefore each current, power, and energy output is duplicated, one for each calculation channel. In addition, there are duplicate calibration registers (offset, gain, phase, etc.) for each calculation channel. 5.1.1 LINE FREQUENCY IN+ 24-bit ADC Multi-Level Modulator + PGA - IN- CHANNEL IN SINC3 Digital Filter The coherent sampling algorithm is also used to calculate the Line Frequency Output register, which is updated every computation cycle. The correction factor for line frequency measurement is the Gain Line Frequency register which is used during the line frequency calibration (see section Section 9.6.1 “Using the Auto-Calibrate Frequency Command”. Note that the resolution of the Line Frequency Output register is fixed, and the resolution is 1 mHz. 5.2 Accumulation Interval Parameter The accumulation interval is defined as a 2N number of line cycles, where N is the value in the Accumulation Interval Parameter register. This is identical for both calculation channels. 5.3 Raw Voltage and Currents Signal Conditioning The first set of signal conditioning that occurs inside the MCP39F511N is shown in Figure 5-1. All conditions set in this diagram affect all of the output registers (RMS current, RMS voltage, Active power, Reactive power, apparent power, etc.). The gain of the PGA, the Shutdown and Reset status of the 24-bit ADCs are all controlled through the System Configuration Register. To compensate for any external phase error between the current and voltage channels, the Phase Compensation register can be used. See Section 9.0 “MCP39F511N Calibration” for more information on device calibration. + HPF (1) i1,2 + SystemConfiguration:b32 PhaseCompensation1:s16 V+ 10-bit SAR ADC HPF (1) v CHANNEL V Note 1: FIGURE 5-1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel. Channels 1 or 2 (IN and V) Input-Signal Flow. 2015 Microchip Technology Inc. DS20005473A-page 21 MCP39F511N 5.4 RMS Current, RMS Voltage and Apparent Power (S) The MCP39F511N device provides true RMS measurements. The MCP39F511N device has two simultaneous sampling 24-bit A/D converters for the current measurements. The root mean square calculations are performed on 2N current and voltage samples, where N is defined by the register Accumulation Interval Parameter. EQUATION 5-1: RMS CURRENT AND VOLTAGE N 2 –1 I RMS = N 2 –1 in 2 n=0 ----------------------------N 2 vn 2 n=0 -----------------------------N 2 V RMS = Range:b32 2N-1 0 ÷ 2 X iN N + ACCU X ÷2RANGE CurrentRMS1,2:u32 + GainCurrentRMS1,2:u16 OffsetCurrentRMS1,2:s32 ApparentPower1,2:u32 GainVoltageRMS:u16 X v 2N-1 0 ÷ 2 N ACCU X ÷2RANGE X VoltageRMS:u16 Range:b32 FIGURE 5-2: RMS Current (Channel 1 or 2), Apparent Power (Channel 1 and 2) and Voltage Calculation Signal Flow. 5.4.1 APPARENT POWER (S) This 32-bit register is the output register for the final apparent power indication. It is the product of RMS current and RMS voltage as shown in Equation 5-2. EQUATION 5-2: APPARENT POWER (S) S = I RMS V RMS 5.4.2 APPARENT POWER DIVISOR DIGITS Because AppPowerDivisorDigits registers can be higher than 4, it may result in a 32-bit divisor. To improve the speed of this part of the calculation engine, a method that uses only multiplications and right-bit shifts was implemented. Therefore the following equation applies: EQUATION 5-3: APPARENT POWER (S) I RMS V RMS ApparentPower = --------------------------------------------------------------------10AppPowerDivisorDigits The registers AppPowerDivisorDigits1 and AppPowerDivisorDigits2 are configurable by the user depending on the precision of the RMS indications and the desired precision for ApparentPower1 or ApparentPower2. DS20005473A-page 22 2015 Microchip Technology Inc. MCP39F511N 5.5 Power and Energy The MCP39F511N offers signed power numbers for Active and Reactive power, import and export registers for active energy, and four-quadrant Reactive power measurement. For this device, import power or energy is considered positive (power or energy being consumed by the load), and export power or energy is considered negative (power or energy being delivered by the load). The following figure represents the measurements obtained by the MCP39F511N. Import Reactive Power Generate, Inductive -P, +Q Quadrant II Consume, Inductive +P, +Q Quadrant I S Q P Import Active Power Export Active Power Quadrant III Generate, Capacitive -P, -Q Quadrant IV Consume, Capacitive +P, -Q Export Reactive Power FIGURE 5-3: The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive). 2015 Microchip Technology Inc. DS20005473A-page 23 MCP39F511N 5.6 Energy Accumulation 5.7 Energy accumulation for all four energy registers (import/export, active/reactive) occurs at the end of each computation cycle if the energy accumulation has been turned on. See Section 6.5 “System Configuration Register” for the energy-control bits. The accumulation of energy occurs in one of eight 64-bit energy counters, four for each channel (import and export counters for both Active and Reactive power). 5.6.1 Active Power (P) The MCP39F511N has three simultaneous sampling A/D converters monitoring two individual currents and two individual active powers. For the Active Power calculations, the instantaneous currents and voltage are multiplied together to create instantaneous power. This instantaneous power is then converted to Active Power by averaging or calculating the DC component. Equation 5-5 controls the number of samples used in this accumulation prior to updating the Active Power output register. NO-LOAD THRESHOLD Please note that although this register is unsigned, the direction of the Active power (import or export) can be determined by the Active Power Sign bit located in the System Status Register. The no-load threshold is set by modifying the value in the No-Load Threshold register. The unit for this register is power with a default resolution of 0.01W. The default value is 100 or 1.00W. Any power that is below 1W will not be accumulated into any of the energy registers. EQUATION 5-5: For scaling of the Apparent power indication, the calculation engine uses the Apparent Power Divisor register. This is described in the following register operations, per Equation 5-4. EQUATION 5-4: ACTIVE POWER 1 P = ------N 2 N k=2 –1 Vk Ik k=0 APPARENT POWER (S) CurrentRMS VoltageRMS S = --------------------------------------------------------------------ApparentPowerDivisor 10 GainActivePower1,2:u16 iN Range1,2:b32 X v FIGURE 5-4: DS20005473A-page 24 2N-1 0 ÷ 2 ACCU N + X ÷2RANGE ActivePower1,2:u32 + OffsetActivePower1,2:s32 Channel 1 or Channel 2 Active Power Calculation Signal Flow. 2015 Microchip Technology Inc. MCP39F511N 5.8 Power Factor (PF) Power factor is calculated by the ratio of P to S, or Active power divided by Apparent power. EQUATION 5-6: POWER FACTOR P PF = --S The Power Factor Reading is stored in two signed 16-bit registers (Power Factor), one for each channel. This register is a signed, two's complement register with the MSB representing the polarity of the power factor. Positive power factor means import power, negative power factor means export power. The sign of the Reactive power component can be used to determine if the load is inductive (positive) or capacitive (negative). Each LSB is then equivalent to a weight of 2-15. A maximum register value of 0x7FFF corresponds to a power factor of 1. The minimum register value of 0x8000 corresponds to a power factor of -1. 5.9 Reactive Power (Q) In the MCP39F511N, Reactive Power is calculated using a 90 degree phase shift in the voltage channel. The same accumulation principles apply as with Active power where ACCU acts as the accumulator. Any light load or residual power can be removed by using the Offset Reactive Power register. Gain is corrected by the Gain Reactive Power register. The final output is an unsigned 32-bit value located in the Reactive Power register. Please note that although this register is unsigned, the direction of the power can be determined by the Reactive Power Sign bit in the System Status Register. GainReactivePower1,2:u16 iN HPF Range1,2:b32 X v FIGURE 5-5: 2N-1 0 ÷ 2 N ACCU1 + - X ÷2RANGE ReactivePower1,2:u32 OffsetReactivePower1,2:s32 HPF (+90deg.) Channel 1 or Channel 2 Reactive Power Calculation Signal Flow. 2015 Microchip Technology Inc. DS20005473A-page 25 MCP39F511N 5.10 Zero Crossing Detection (ZCD) The zero crossing detection block generates a logic pulse output on the ZCD pin that is coherent with the zero crossing of the input AC signal present on voltage input pin (V+). The ZCD pin can be enabled and disabled by the corresponding bit in the System Configuration Register. When enabled, this produces a square wave with a frequency that is the same as the AC signal present on the voltage input. Figure 5-6 represents the signal on the ZCD pin superimposed with the AC signal present on the voltage input in this mode. <200 µs FIGURE 5-6: Zero Crossing Detection Operation (Non-Inverted, Non-Pulse). A second mode is available that produces a 100 µs pulse, the frequency here is twice that of the AC signal on the voltage channel input, at each zero crossing, as shown in Figure 5-7. <200 µs FIGURE 5-7: Zero Crossing Detection Operation (Non-Inverted, Pulsed). Switching modes is done by setting the corresponding bit in the System Configuration Register. In addition, either the toggling of this pin, or the pulse, can be inverted. The ZCD Inversion bit is also in the System Configuration register. There are two bits in the System Configuration register that can be used to modify the zero crossing. The zero crossing output can be inverted by setting the inversion bit, or the zero crossing can be a 100 µs pulse at each zero crossing by setting the pulse bit. Note that a low-pass filter is included in the signal path that allows the zero crossing detection circuit to filter out the fundamental frequency. An internal compensation circuit is then used to gain back the phase delay introduced by the low-pass filter resulting in a latency of less than ±200 µs. DS20005473A-page 26 2015 Microchip Technology Inc. MCP39F511N 6.0 REGISTER DESCRIPTIONS 6.1 Complete Register Map The following table describes the registers for the MCP39F511N device. TABLE 6-1: MCP39F511N REGISTER MAP Address Register Name Section Number Read/ Write Data type Description Output Registers 0x0000 Instruction Pointer 6.2 R u16 Address pointer for read or write commands 0x0002 System Status 6.3 R b16 System Status Register 0x0004 System Version 6.4 R u16 System version date code information for MCP39F511N, set at the Microchip factory; format YMDD 0x0006 Voltage RMS 5.4 R u16 RMS Voltage output 0x0008 Line Frequency 5.1.1 R u16 Line Frequency output 0x000A Power Factor1 5.8 R s16 Power Factor output from channel 1 0x000C Power Factor2 5.8 R s16 Power Factor output from channel 2 0x000E Current RMS1 5.4 R u32 RMS Current output from channel 1 0x0012 Current RMS2 5.4 R u32 RMS Current output from channel 2 0x0016 Active Power1 5.7 R u32 Active Power output from channel 1 0x001A Active Power2 5.7 R u32 Active Power output from channel 2 0x001E Reactive Power1 5.9 R u32 Reactive Power output from channel 1 0x0022 Reactive Power2 5.9 R u32 Reactive Power output from channel 2 0x0026 Apparent Power1 5.4 R u32 Apparent Power output from channel 1 0x002A Apparent Power2 5.4 R u32 Apparent Power output from channel 2 0x002E Import Energy Active Counter 1 5.6 R u64 Accumulator for Active Energy, Import, channel 1 0x0036 Import Energy Active Counter 2 5.6 R u64 Accumulator for Active Energy, Import, channel 2 0x003E Export Energy Active Counter 1 5.6 R u64 Accumulator for Active Energy, Export, channel 1 0x0046 Export Energy Active Counter 2 5.6 R u64 Accumulator for Active Energy, Export, channel 2 0x004E Import Energy Reactive Counter 1 5.6 R u64 Accumulator for Reactive Energy, Import, channel 1 0x0056 Import Energy Reactive Counter 2 5.6 R u64 Accumulator for Reactive Energy, Import, channel 2 0x005E Export Energy Reactive Counter 1 5.6 R u64 Accumulator for Reactive Energy, Export channel 1 0x0066 Export Energy Reactive Counter 2 5.6 R u64 Accumulator for Reactive Energy, Export, channel 2 Calibration Registers 0x006E Calibration Registers Delimiter 9.7 R/W u16 May be used to initiate loading of the default factory calibration coefficients at start-up 0x0070 Gain Current RMS1 5.4 R/W u16 Gain Calibration Factor for RMS Current channel 1 0x0072 Gain Current RMS2 5.4 R/W u16 Gain Calibration Factor for RMS Current channel 2 0x0074 Gain Voltage RMS 5.4 R/W u16 Gain Calibration Factor for RMS Voltage 2015 Microchip Technology Inc. DS20005473A-page 27 MCP39F511N TABLE 6-1: Address MCP39F511N REGISTER MAP (CONTINUED) Register Name Section Number Read/ Write Data type Description 0x0076 Gain Active Power1 5.7 R/W u16 Gain Calibration Factor for Active Power, channel 1 0x0078 Gain Active Power2 5.7 R/W u16 Gain Calibration Factor for Active Power, channel 2 0x007A Gain Reactive Power1 5.9 R/W u16 Gain Calibration Factor for Reactive Power, channel 1 0x007C Gain Reactive Power2 5.9 R/W u16 Gain Calibration Factor for Reactive Power, channel 2 0x007E Gain Line Frequency 5.1.1 R/W u16 Gain Calibration Factor for the Line Frequency 0x0080 Offset Current RMS1 5.4 R/W s32 Offset Calibration Factor for RMS Current, channel 1 0x0084 Offset Current RMS2 5.4 R/W s32 Offset Calibration Factor for RMS Current, channel 2 0x0088 Offset Active Power1 5.7 R/W s32 Offset Calibration Factor for Active Power, channel 1 0x008C Offset Active Power2 5.7 R/W s32 Offset Calibration Factor for Active Power, channel 2 0x0090 Offset Reactive Power1 5.9 R/W s32 Offset Calibration Factor for Reactive Power, channel 1 0x0094 Offset Reactive Power2 5.9 R/W s32 Offset Calibration Factor for Reactive Power, channel 2 0x0098 Phase Compensation1 5.3 R/W s16 Phase Compensation, channel 1 0x009A Phase Compensation2 5.3 R/W s16 Phase Compensation, channel 2 0x009C Apparent Power Divisor1 5.4.2 R/W u16 Number of Digits for apparent power divisor to match IRMS and VRMS resolution, channel 1 0x009E 5.4.2 R/W u16 Number of Digits for apparent power divisor to match IRMS and VRMS resolution, channel 2 Apparent Power Divisor2 Design Configuration Registers 0x00A0 System Configuration 6.5 R/W b32 Control for device configuration, including ADC configuration 0x00A4 Event Configuration 7.5 R/W b32 Settings for the Event pins including Relay Control 0x00A8 Accumulation Interval Parameter 5.2 R/W u16 N for 2N number of line cycles to be used during a single computation cycle 0x00AA Calibration Voltage 9.3.1 R/W u16 Target Voltage to be used during single-point calibration 0x00AC Calibration Line Frequency 9.6.1 R/W u16 Reference Value for the nominal line frequency 0x00AE Range1 6.6 R/W b32 Scaling factor for Outputs, channel 1 0x00B2 Calibration Current1 9.3.1 R/W u32 Target Current to be used during single-point calibration, channel 1 0x00B6 Calibration Power Active1 9.3.1 R/W u32 Target Active Power to be used during single-point calibration, channel 1 9.3.1 R/W u32 Target Active Power to be used during single-point calibration, channel 1 6.6 R/W b32 Scaling factor for Outputs, channel 2 0x00BA Calibration Power Reactive1 0x00BE Range2 DS20005473A-page 28 2015 Microchip Technology Inc. MCP39F511N TABLE 6-1: MCP39F511N REGISTER MAP (CONTINUED) Section Number Read/ Write Data type Description 0x00C2 Calibration Current2 9.3.1 R/W u32 Target Current to be used during single-point calibration, channel 2 0x00C6 Calibration Power Active2 9.3.1 R/W u32 Target Active Power to be used during single-point calibration Channel 2 0x00CA Calibration Power Reactive2 9.3.1 R/W u32 Target Active Power to be used during single-point calibration, channel 2 0x00CE Voltage Sag Limit 7.2 R/W u16 RMS Voltage Sag threshold at which an event flag is recorded 0x00D0 Voltage Surge Limit 7.2 R/W u16 RMS Voltage Surge threshold at which an event flag is recorded 0x00D2 Over Current1 Limit 7.2 R/W u32 RMS Over Current threshold for channel 1 at which an event flag is recorded 0x00D6 Over Current2 Limit 7.2 R/W u32 RMS Over Current threshold for channel 2 at which an event flag is recorded 0x00DA OverPower1 Limit 7.2 R/W u32 Over Power threshold for channel 1 at which an event flag is recorded 0x00DE OverPower2 Limit 7.2 R/W u32 Over Power threshold for channel 2 at which an event flag is recorded Address Register Name Control Registers for Peripherals 0x00E2 PWM Period 8.2 R/W u16 Input register controlling PWM Frequency 0x00E4 PWM Duty Cycle 8.3 R/W u16 Input register controlling PWM Duty Cycle 0x00E6 Reserved — — u16 Reserved 0x00E8 Reserved — — u16 Reserved 0x00EA VoltagePhaseCompFreqCoef — — u16 Phase Compensation Frequency Coefficient 0x00EC RangeVoltageChPhaseCompFreq — — u16 Voltage Channel Phase Frequency Compensation Range 0x00EE GainActivePowerCompFreqCoef — — u16 Active Power Gain Frequency Compensation Coefficient 0x00F0 RangeGainActivePowerCompFreq — — u16 Active Power Gain Frequency Compensation Range 0x00F2 GainReactivePowerCompFreq — — u16 Reactive Power Gain Frequency Compensation Coefficient 0x00F4 RangeGainReactivePowerCompFreq — — u16 Reactive Power Gain Frequency Compensation Range 0x00F6 GainVoltageRMSCompFreqCoef — — u16 RMS Voltage Gain Frequency Compensation Coefficient 0x00F8 RangeGainVoltageRMSCompFreq — — u16 RMS Voltage Gain Frequency Compensation Range 0x00FA GainCurrentRMSCompFreqCoef — — u16 RMS Current Gain Frequency Compensation Coefficient — — u16 RMS Current Gain Frequency Compensation Range 5.6.1 R/W u16 No Load Threshold for Energy Counting (both channels, all registers) 0x00FC RangeGainCurrentRMSCompFreq 0x00FE No Load Threshold 2015 Microchip Technology Inc. DS20005473A-page 29 MCP39F511N 6.2 Address Pointer Register This unsigned 16-bit register contains the address to which all read and write instructions occur. This register is only written through the Set Address Pointer command and is otherwise outside the writable range of register addresses. 6.3 System Status Register The System Status register is a read-only register and can be used to detect the various states of pin levels as defined in Register 6-1. REGISTER 6-1: SYSTEM STATUS REGISTER U-0 U-0 U-0 R-x R-n R-n R-x R-n — — — AC_STATUS EVENT2 EVENT1 OVERPOW2 OVERCURR2 bit 15 bit 8 R-n R-n R-n R-n R-n R-n R-n R-n SIGN_PR _CH2 SIGN_PA_ CH2 SIGN_PR_C H1 SIGN_PA_C H1 OVERPOW1 OVERCURR1 VSURGE VSAG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 AC_STATUS: AC Detection Status 1 = AC Detection failed. 0 = AC Detection successful. bit 11 EVENT2: State of Event2 Detection algorithm. This bit is latched and must be cleared. 1 = Event 2 has occurred. 0 = Event 2 has not occurred. bit 10 EVENT1: State of Event1 Detection algorithm. This bit is latched and must be cleared. 1 = Event 1 has occurred. 0 = Event 1 has not occurred. bit 9 OVERPOW2: Over Power, channel 2. An over power event has occurred on channel 2. 1 = Over Power threshold has been broken 0 = Over Power threshold has not been broken bit 8 OVERCURR2: Over Current, channel 2. An over current event has occurred on channel 2. 1 = Over current threshold has been broken 0 = Over current threshold has not been broken bit 7 SIGN_PR_CH2: Sign of Reactive Power Channel 2 (inductive/capacitive state of the reactive power) 1 = Reactive Power is inductive and is in quadrants 1,2 0 = Reactive Power is capacitive and is in quadrants 3,4 bit 6 SIGN_PA_CH2: Sign of Active Power Channel 2 (import/export sign of active power) 1 = Active Power is positive (import) and is in quadrants 1,4 0 = Active Power is negative (export) and is in quadrants 2,3 DS20005473A-page 30 2015 Microchip Technology Inc. MCP39F511N REGISTER 6-1: SYSTEM STATUS REGISTER (CONTINUED) bit 5 SIGN_PR_CH1: Sign of Reactive Power Channel 1 (inductive/capacitive state of the reactive power) 1 = Reactive Power is inductive and is in quadrants 1,2 0 = Reactive Power is capacitive and is in quadrants 3,4 bit 4 SIGN_PA_CH1: Sign of Active Power Channel 1 (import/export sign of active power) 1 = Active Power is positive (import) and is in quadrants 1,4 0 = Active Power is negative (export) and is in quadrants 2,3 bit 3 OVERPOW1: Over Power, channel 1. An over power event has occurred on channel 1. 1 = Over Power threshold has been broken 0 = Over Power threshold has not been broken bit 2 OVERCURR1: Over Current, channel 1. An over current event has occurred on channel 1. 1 = Over current threshold has been broken 0 = Over current threshold has not been broken bit 1 VSURGE: Voltage Surge. State of Voltage Surge Detection algorithm. This bit is latched and must be cleared 1 = Surge threshold has been broken 0 = Surge threshold has not been broken bit 0 VSAG: Voltage Sag.State of Voltage Sag Detection algorithm. This bit is latched and must be cleared 1 = Sag threshold has been broken 0 = Sag threshold has not been broken 6.4 System Version Register The System Version register is hard-coded by Microchip Technology Incorporated and contains calculation-engine date-code information. The System Version register is a date code in the YMDD format, with year and month in hex, day in decimal (e.g. 0xFB20 = 2015, Nov. 20th). 6.5 System Configuration Register The System Configuration register contains bits for the following control: • • • • • PGA setting ADC Reset State ADC Shutdown State Voltage Reference Trim Single Wire Auto-Transmission These options are described in the following sections. 6.5.1 PROGRAMMABLE GAIN AMPLIFIERS (PGA) The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn<2:0> bits in Register 6-2: the System Configuration register. Table 6-2 represents the gain settings for the PGAs. TABLE 6-2: PGA CONFIGURATION SETTING (Note 1) Gain PGA_CHn<2:0> Gain (V/V) Gain (dB) VIN Range (V) 0 0 0 1 0 ±0.6 0 0 1 2 6 ±0.3 0 1 0 4 12 ±0.15 0 1 1 8 18 ±0.075 1 0 0 16 24 ±0.0375 1 0 1 32 30 ±0.01875 Note 1: This table is defined with VREF = 1.2V. The two undefined settings, 110 and 111 are G = 1. The two Programmable Gain Amplifiers (PGAs) reside at the front-end of each 24-bit Delta-Sigma ADC. They have two functions: • translate the common mode of the input from AGND to an internal level between AGND and AVDD • amplify the input differential signal The translation of the common mode does not change the differential signal, but enters the common mode so that the input signal can be properly amplified. 2015 Microchip Technology Inc. DS20005473A-page 31 MCP39F511N 6.5.2 24-BIT ADC RESET MODE (SOFT RESET MODE) 24-bit ADC Reset mode (also called Soft Reset) can only be entered by setting high the RESET<1:0> bits in the System Status Register. This mode is defined as the condition where the converters are active but their output is forced to ‘0’. 6.5.3 ADC SHUTDOWN MODE ADC Shutdown mode is defined as a state where the converters and their biases are OFF, consuming only leakage current. When the Shutdown bit is reset to ‘0’, the analog biases will be enabled, as well as the clock and the digital circuitry. Each converter can be placed in Shutdown mode independently. This mode is only available through programming of the SHUTDOWN<1:0> bits in the System Status Register. 6.5.4 VREF TEMPERATURE COMPENSATION The internal voltage reference comprises a proprietary circuit and algorithm to compensate first-order and second-order temperature coefficients. The compensation allows very low temperature coefficients (typically 10 ppm/°C) on the entire range of temperatures from -40°C to +125°C. This temperature coefficient varies from part to part. The default value of this register is set to 0x42. The typical variation of the temperature coefficient of the internal voltage reference, with respect to VREFCAL register code, is shown in Figure 6-1. 60 VREF Drift (ppm) 50 40 30 20 10 0 0 64 128 192 VREFCAL Register Trim Code (decimal) FIGURE 6-1: Trimcode Chart. DS20005473A-page 32 256 VREF Tempco vs. VREFCAL 2015 Microchip Technology Inc. MCP39F511N REGISTER 6-2: SYSTEM CONFIGURATION REGISTER U-0 U-0 — — R/W-0 R/W-1 R/W-1 R/W-0 PGA_CH2<2:0> R/W-1 R/W-1 PGA_CH1<2:0> bit 31 bit 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 bit 23 R/W-0 bit 16 R/W-0 R/W-0 UART<2:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ZCD_INV ZCD_PULS ZCD_OUTPUT_DIS ENERGY2 ENERGY1 bit 15 R/W-0 bit 8 R/W-0 PWM R/W-0 RESET<1:0> R/W-0 R/W-0 SHUTDOWN<1:0> R/W-0 U-0 U-0 VREFEXT — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-30 Unimplemented: Read as ‘0’ bit 29-27 PGA_CH2 <2:0>: PGA Setting for channel 2 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 (Default) 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 26-24 PGA_CH1 <2:0>: PGA Setting for channel 1 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 (Default) 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 23-16 Unimplemented: Read as ‘0’ bit 15-13 UART<2:0>: UART Baud Rate bits 111 = 1200 110 = 2400 101 = 4800 100 = 9600 011 = 19200 010 = 38400 001 = 57600 000 = 115200 (Default) bit 12 ZCD_INV: Zero Crossing Detection Output Inverse 1 = ZCD is inverted 0 = ZCD is not inverted (Default) 2015 Microchip Technology Inc. x = Bit is unknown DS20005473A-page 33 MCP39F511N REGISTER 6-2: SYSTEM CONFIGURATION REGISTER (CONTINUED) bit 11 ZCD_PULS: Zero Crossing Detection Pulse mode 1 = ZCD output is 200 µs pulses on zero crossings 0 = ZCD output changes logic state on zero crossings (Default) bit 10 ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin 1 = ZCD output is disabled 0 = ZCD output is enabled (Default) bit 9 ENERGY2: Energy counting control, channel 2 1 = Energy Counting for channel 2 is enabled 0 = Energy Counting for channel 2 is reset and disabled (Default) bit 8 ENERGY1: Energy counting control, channel 1 1 = Energy Counting for channel 1 is enabled 0 = Energy Counting for channel 1 is reset and disabled (Default) bit 7 PWM: PWM Control 1 = PWM Output is enabled 0 = PWM Output is disabled (Default) bit 6-5 RESET <1:0>: Reset mode setting for current measurement ADCs 11 = Both I1 and I2 are in Reset mode 10 = I2 ADC is in Reset mode 01 = I1 ADC is in Reset mode 00 = Neither ADC is in Reset mode (Default) bit 4-3 SHUTDOWN <1:0>: Shutdown mode setting for current measurement ADCs 11 = Both I1 and I2 are in Shutdown 10 = I2 ADC is in Shutdown 01 = I1 ADC is in Shutdown 00 = Neither ADC is in Shutdown (Default) bit 2 VREFEXT: Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (Default) bit 1-0 Unimplemented: Read as ‘0’ DS20005473A-page 34 2015 Microchip Technology Inc. MCP39F511N 6.6 Range Registers The range registers are 32-bit registers that contain the number of right-bit shifts for the following outputs, divided into separate bytes defined below across the two registers: • • • • • RMS Voltage RMS Current, Channel 1 Power, Channel 1 RMS Current, Channel 2 Power, Channel 2 • high enough to prevent overflow in the output register • low enough to allow for the desired output resolution. It is the user’s responsibility to set this register correctly to ensure proper output operation for a given meter design. Note that the Power Range byte operates across both the active and reactive output registers and sets the same scale. REGISTER 6-3: The purpose of this register is two-fold: the number of right-bit shifting (division by 2RANGE) must be: For further information and example usage, see Section 9.3 “Single-Point Gain Calibrations at Unity Power Factor”. RANGE1 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POWER1[7] POWER1[6] POWER1[5] POWER1[4] POWER1[3] POWER1[2] POWER1[1] POWER1[0] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CURRENT1[7] CURRENT1[6] CURRENT1[5] CURRENT1[4] CURRENT1[3] CURRENT1[2] CURRENT1[1] CURRENT[0] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VOLTAGE[7] VOLTAGE[6] VOLTAGE[5] VOLTAGE[4] VOLTAGE[3] VOLTAGE[2] VOLTAGE[1] VOLTAGE[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0‘ bit 23-16 POWER1[7:0]: Sets the number of right-bit shifts for the Active and Reactive Power output registers, channel 1. bit 15-8 CURRENT1[7:0]: Sets the number of right-bit shifts for the Current RMS output register, channel 1. bit 7-0 VOLTAGE[7:0]: Sets the number of right-bit shifts for the Voltage RMS output register. 2015 Microchip Technology Inc. DS20005473A-page 35 MCP39F511N REGISTER 6-4: RANGE2 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POWER2[7] POWER2[6] POWER2[5] POWER2[4] POWER2[3] POWER2[2] POWER2[1] POWER2[0] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CURRENT2[7] CURRENT2[6] CURRENT2[5] CURRENT2[4] CURRENT2[3] CURRENT2[2] CURRENT2[1] CURRENT2[0] bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0‘ bit 23-16 POWER2[7:0]: Sets the number of right-bit shifts for the Active and Reactive Power output registers, channel 2 bit 15-8 CURRENT2[7:0]: Sets the number of right-bit shifts for the Current RMS output register, channel 2. bit 7-0 Unimplemented: Read as ‘0‘ DS20005473A-page 36 2015 Microchip Technology Inc. MCP39F511N 7.0 EVENT OUTPUT PINS/EVENT CONFIGURATION REGISTER 7.1 Event Pins The MCP39F511N device has two event pins that can be configured in three possible configurations. These configurations are: 1. 2. No event is mapped to the pin Voltage Surge, Voltage Sag, Over Current or Over Power event is mapped to the pin. More than one event can be mapped to the same pin. Manual control of two pins, independently. Possible only when no event is mapped to the pin. 3. These three configurations allow for the control of external interrupts or hardware that is dependent on the measured power, current or voltage. The Event Configuration Register below describes how these events and pins can be configured. 7.2 Limits There are 6 limit registers associated with these events: • • • • • • Voltage Sag Limit Voltage Surge Limit Over Current Limit, channel 1 Over Power Limit, channel 1 Over Current Limit, channel 2 Over Power Limit, channel 2 Each of these limits are compared to the respective output registers of voltage, current and power, and should have the same unit, e.g. 0.1V, 0.01W, etc. 7.3 Therefore, at each data-ready occurrence, the value of VSA is compared to the programmable threshold set in the Voltage Sag Limit register and Voltage Surge Limit register to determine if a flag should be set. If either of these events are masked to either the Event1 or Event2 pin, a logic-high interrupt will be given on these pins. The Sag or Surge events can be used to quickly determine if a power failure has occurred in the system. 7.4 Calibration Status Events The Event register contains eight bits that correspond to the pass/fail of a calibration attempt issued through the Auto-Calibrate Gain commands. These commands can be used to calibrate all single-point calibration outputs for both channels: • • • • • • • • Line Frequency Voltage Channel 1 Current Channel 1 Active Power Channel 1 Reactive Power Channel 2 Current Channel 2 Active Power Channel 2 Reactive Power Bits 31-24 are status bits with a 1 representing a calibration fail. These bits are reset to 0 when a calibration command is successful for whichever channel (or both) is being calibrated. For more information on calibration, see Section 9.3 “Single-Point Gain Calibrations at Unity Power Factor”. Voltage Sag and Voltage Surge Detection The event alarms for Voltage Sag and Voltage Surge work differently compared to the Over Current and Over Power events, which are tested against every computation cycle. These two event alarms are designed to provide a much faster interrupt if the condition occurs. Note that neither of these two events have a respective Hold register associated with them, since the detection time is less than one line cycle. The calculation engine keeps track of a trailing mean square of the input voltage, as defined by Equation 7-1: EQUATION 7-1: 2 2 fLINE V SA = -------------------------- f SAMPLE 0 Vn f SAMPLE n = – -------------------------- – 1 2 f LINE 2015 Microchip Technology Inc. DS20005473A-page 37 MCP39F511N 7.5 Event Configuration Register The Event Configuration register is used to control the event operations and the event pins and to give event and calibration status. REGISTER 7-1: EVENT CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL_PR2 CAL_PR1 CAL_PA2 CAL_PA1 CAL_CURR 2 CAL_CURR 1 CAL_VOLT CAL_LF bit 31 bit 24 R/W-0 R/W-0 OVERPOW_PIN2 OVERCUR_PIN2 R/W-0 R/W-0 VSURGE_PI VSAG_PIN2 N2 R/W-0 R/W-0 OVERPOW_PIN1 OVERCUR_PIN1 R/W-0 R/W-0 VSURGE_PI VSAG_PIN1 N1 bit 23 bit 16 R/W-0 R/W-0 EVENT2_MA EVENT1_MA NU NU U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OVERCUR_CL OVERPOW_CL VSURGE_C L VSAG_CL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VSUR_LA VSAG_LA OVERPOW_LA OVERCUR_LA VSUR_TST VSAG_TST OVERPOW_TST OVERCUR_TST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 CAL_PR2: Single-Point Calibration Result for Reactive Power, channel 2 1 = Calibration Failed 0 = Calibration Successful bit 30 CAL_PR1: Single-Point Calibration Result for Reactive Power, channel 1 1 = Calibration Failed 0 = Calibration Successful bit 29 CAL_PA2: Single-Point Calibration Result for Active Power, channel 2 1 = Calibration Failed 0 = Calibration Successful bit 28 CAL_PA1: Single-Point Calibration Result for Active Power, channel 1 1 = Calibration Failed 0 = Calibration Successful bit 27 CAL_CURR2: Single-Point Calibration Result for RMS Current, channel 2 1 = Calibration Failed 0 = Calibration Successful bit 26 CAL_CURR1: Single-Point Calibration Result for RMS Current, channel 1 1 = Calibration Failed 0 = Calibration Successful bit 25 CAL_VOLT: Single-Point Calibration Result for RMS Voltage 1 = Calibration Failed 0 = Calibration Successful DS20005473A-page 38 2015 Microchip Technology Inc. MCP39F511N REGISTER 7-1: EVENT CONFIGURATION REGISTER (CONTINUED) bit 24 CAL_LF: Single-Point Calibration Result for Line Frequency 1 = Calibration Failed 0 = Calibration Successful bit 23 OVERPOW_PIN2: Event pin 2 operation for the Over Power event 1 = Event mapped to Event pin 2 only 0 = Event not mapped to a pin (Default) bit 22 OVERCUR_PIN2: Event pin 2 operation for the Over Current event 1 = Event mapped to Event pin 2 only 0 = Event not mapped to a pin (Default) bit 21 VSURGE_PIN2: Event pin 2 operation for the Voltage Surge event 1 = Event mapped to Event pin 2 only 0 = Event not mapped to a pin (Default) bit 20 VSAG_PIN2: Event pin 2 operation for the Voltage Sag event 1 = Event mapped to Event pin 2 only 0 = Event not mapped to a pin (Default) bit 19 OVERPOW_PIN1: Event pin 1 operation for the Over Power event 1 = Event mapped to Event pin 1 only 0 = Event not mapped to a pin (Default) bit 18 OVERCUR_PIN1: Event pin 1 operation for the Over Current event 1 = Event mapped to Event pin 1 only 0 = Event not mapped to a pin (Default) bit 17 VSURGE_PIN1: Event pin 1 operation for the Voltage Surge event 1 = Event mapped to Event pin 1 only 0 = Event not mapped to a pin (Default) bit 16 VSAG_PIN1: Event pin 1 operation for the Voltage Sag event 1 = Event mapped to Event pin 1 only 0 = Event not mapped to a pin (Default) bit 15 EVENT2_MANU Manual control of the Event2 pin 1 = Pin is logic high 0 = Pin is logic low (Default) bit 14 EVENT1_MANU Manual control of the Event1 pin 1 = Pin is logic high 0 = Pin is logic low (Default) bit 13-12 Unimplemented: Read as ‘0‘ bit 11 OVERCUR_CL: Reset or clear bit for the Over Current event 1 = Event is cleared 0 = Event is not cleared (Default) bit 10 OVERPOW_CL: Reset or clear bit for the Over Power event 1 = Event is cleared 0 = Event is not cleared (Default) bit 9 VSURGE_CL: Reset or clear bit for the Voltage Surge event 1 = Event is cleared 0 = Event is not cleared (Default) bit 8 VSAG_CL: Reset or clear bit for the Voltage Sag event 1 = Event is cleared 0 = Event is not cleared (Default) bit 7 VSUR_LA: Latching control of the Voltage Surge event 1 = Event is latched and needs to be cleared 0 = Event is not latched (Default) bit 6 VSAG_LA: Latching control of the Voltage Sag event 1 = Event is latched and needs to be cleared 0 = Event is not latched (Default) 2015 Microchip Technology Inc. DS20005473A-page 39 MCP39F511N REGISTER 7-1: EVENT CONFIGURATION REGISTER (CONTINUED) bit 5 OVERPOW_LA: Latching control of the Over Power event 1 = Event is latched and needs to be cleared 0 = Event is not latched (Default) bit 4 OVERCUR_LA: Latching control of the Over Current event 1 = Event is latched and needs to be cleared 0 = Event is not latched (Default) bit 3 VSUR_TST: Test control of the Voltage Surge event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 2 VSAG_TST: Test control of the Voltage Sag event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 1 OVERPOW_TST: Test control of the Over Power event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) bit 0 OVERCUR_TST: Test control of the Over Current event 1 = Simulated event is turned on 0 = Simulated event is turned off (Default) DS20005473A-page 40 2015 Microchip Technology Inc. MCP39F511N 8.0 PULSE-WIDTH MODULATION (PWM) 8.1 Overview The PWM output pin gives up to a 10-bit resolution of a pulse-width modulated signal. The PWM output is controlled by an internal timer inside the MCP39F511N, FTIMER described in this section, with a base frequency of 32 MHz. The output of the PWM is active only when the PWM Control register has a value of 0x0001. The PWM output is turned off when the register has a value of 0x0000. The PWM output (see Figure 8-1) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). The base period is defined as PTIMER and is 1/[32 MHz]. This 32 MHz time base is fixed due to the 8 MHz internal oscillator or 8 MHz external crystal. Period Duty Cycle FIGURE 8-1: PWM Output. There are two registers that control the PWM output, PWM Period and PWM Duty Cycle. The 8-bit PWM Period is controlled by a 16-bit register that contains the period bits and also the prescaler bits. The PWM period bits are the most significant eight bits in the register, and the prescaler value is represented by the two least significant bits. These two values together create the PWM Period (see Figure 8-2). Period Prescaler 255 PWM PERIOD 11 1 1 1 1 1 1 0 0 0 0 00 1 0 (8-bit) PWM Period Register MSB 1023 PWM DUTY (10-bit) LSB 1 1 1 1 1 1 11 0 0 00 0 0 1 0 PWM duty-cycle Register FIGURE 8-2: PWM Period and Duty-Cycle Registers. The 10-bit PWM Duty Cycle is controlled by a 16-bit register where the eight most significant bits are the 8 MSB and the 2 LSB, corresponding to the 2 LSBs of the 10-bit value. An example of the register’s values are shown in Figure 8-2 with 255 for PWM Frequency (8-bit value) and 1023 for the Duty cycle (10-bit value), with the prescaler set to divide by 16 (1:0). 2015 Microchip Technology Inc. DS20005473A-page 41 MCP39F511N 8.2 PWM Period The PWM period is specified by writing the PWM Period bits of the PWM Period register. The PWM period can be calculated using the following formula: Equation 8-1: PWM Period = [(PWM_Frequency) + 1] × 2 × PTIMER × (Prescale Value) The PWM Period is defined as 1/[PWM frequency]. When PTIMER is equal to PWM Period, the following two events occur on the next increment cycle: • the PWM timer is cleared • the PWM pin is set. Exception: If the PWM Duty Cycle equals 0%, the PWM pin will not be set. 8.3 PWM Duty Cycle The PWM duty cycle is specified by writing to the PWM Duty-Cycle register. Up to 10-bit resolution is available. The PWM Duty-Cycle register contains the eight MSbs and the two LSbs. The following equations are used to calculate the PWM duty cycle as a percentage or as time: EQUATION 8-1: PWM Duty Cycle (%) = (PWM_DUTY CYCLE>)/(4 × PWM_FREQUENCY) PWM Duty Cycle (time in s) = (PWM_DUTY_CYCLE) × PWM_TIMER_PERIOD/2 × (Prescale Value) The PWM Duty-Cycle register can be written to at any time, but the duty-cycle value is not latched until after a period is complete. The PWM registers and a two-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitch-less PWM operation. The maximum PWM resolution (bits) for a given PWM frequency is shown in Equation 8-2. EQUATION 8-2: MAXIMUM PWM RESOLUTION BASED ON A FUNCTION OF PWM FREQUENCY 2 F TIMER log -------------------------- F PWM PWM Resolution (max)= --------------------------------------- bits log 2 Note: If the PWM duty-cycle value is longer than the PWM period, the PWM pin will not be cleared. DS20005473A-page 42 2015 Microchip Technology Inc. MCP39F511N TABLE 8-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH PWM_TIMER_FREQ = 32 MHz (DEFAULT) PWM Frequency Timer Prescaler PWM Frequency Value Maximum Resolution (bits) REGISTER 8-1: R/W-0 1.95 kHz 31.25 kHz 62.5 kHz 125 kHz 2.67 MHz 4 MHz 16 1 1 1 1 1 FFh FFh 7Fh 3Fh 02h 01h 10 10 9 4 3 2 R/W-1 R/W-1 PWM PERIOD REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 PWM_P<7:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 PRE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 PWM_P<7:0>: 8-bit PWM period value bit 7-2 Unimplemented: Read as ‘0‘ bit 1-0 PRE<1:0>: PWM Prescaler 11 = Unused 10 = 1:16 01 = 1:4 00 = 1:1 (Default) REGISTER 8-2: R/W-0 x = Bit is unknown PWM DUTY-CYCLE REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DUTY<9:2> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 DUTY<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 DUTY<9:2>: Upper 8 bits of 10-bit duty-cycle value bit 7-2 Unimplemented: Read as ‘0‘ bit 1-0 DUTY<1:0>: Lower 2 bits of 10-bit duty-cycle value 2015 Microchip Technology Inc. x = Bit is unknown DS20005473A-page 43 MCP39F511N NOTES: DS20005473A-page 44 2015 Microchip Technology Inc. MCP39F511N 9.0 MCP39F511N CALIBRATION 9.3.1 9.1 Overview By applying stable reference voltages and currents that are equivalent to the values that reside in the target Calibration Current, Calibration Voltage and Calibration Active Power registers, the Auto-Calibration Gain command can then be issued to the device. Calibration compensates for ADC gain error, component tolerances and overall noise in the system. The device provides an on-chip calibration algorithm that allows simple system calibration to be performed quickly. The excellent analog performance of the A/D converters on the MCP39F511N allows for a single-point calibration and a single calibration command to achieve accurate measurements. USING THE AUTO-CALIBRATION GAIN COMMAND After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. Calibration can be done by either using the predefined auto-calibration commands, or by writing directly to the calibration registers. If additional calibration points are required (AC offset, Phase Compensation, DC offset), the corresponding calibration registers are available to the user and will be described separately in this section. The following registers are set when the Auto-Calibration Gain command is issued: 9.2 The channels can be calibrated individually or simultaneously depending on the instruction parameter byte following the command byte. Calibration Order The proper steps for calibration need to be maintained. If the device runs on the internal oscillator, the line frequency should be calibrated first using the Auto-Calibrate Frequency command. The single-point Gain Calibration at Unity Power Factor should be performed next. This can be done for an individual channel or for both channels at the same time, depending on the user’s calibration setup. If non-unity displacement power factor measurements are a concern, then the next step should be Phase calibration followed by Reactive power gain calibration. Here is a summary on the order of calibration steps: 1. 2. 3. 4. Line Frequency Calibration Gain Calibration at PF = 1 for a single channel or both Phase Calibration at PF 1 for a single channel or both (optional) Reactive Gain Calibration at PF 1 for a single channel or both (optional) If calibrating a single channel at a time, repeat steps 2-4 for the second channel. 9.3 Single-Point Gain Calibrations at Unity Power Factor • • • • • Gain Current RMS Channel 1 Gain Current RMS Channel 2 Gain Voltage RMS Gain Active Power Channel 1 Gain Active Power Channel 2 When this command is issued, the MCP39F511N attempts to match the expected values to the measured values for all three output quantities by changing the gain register based on the following formula: EQUATION 9-1: GAIN NEW = GAIN Expected -------------------------OLD Measured The same formula applies for Voltage RMS, Current RMS and Active power. Since the gain registers for all three quantities are 16-bit numbers, the ratio of the expected value to the measured value (which can be modified by changing the Range register) and the previous gain must be such that the equation yields a valid number. Here the limits are set to be from 25,000 to 65,535. A new gain within this range for all three limits will return an ACK for a successful calibration, otherwise the command returns a NAK for a failed calibration attempt. It is the user’s responsibility to ensure that the proper range settings, PGA settings and hardware design settings are correct to allow for successful calibration using this command. When using the device in AC mode with the high-pass filters turned on, most offset errors are removed and only a single-point gain calibration is required. Setting the gain registers to properly produce the desired outputs can be done manually by writing to the appropriate register. The alternative method is to use the auto-calibration commands described in this section. 2015 Microchip Technology Inc. DS20005473A-page 45 MCP39F511N 9.3.2 EXAMPLE OF RANGE SELECTION FOR VALID CALIBRATION In this example, the user applies a calibration current of 1A to an uncalibrated system. The indicated value in the Current RMS register is 2300 with the system's specific shunt value, PGA gain, etc. The user expects to see a value of 1000 in the Current RMS register when 1A current is applied, meaning 1.000A with 1 mA resolution. Other given values are: • the existing value for Gain Current RMS is 33480 • the existing value for Range is 12 By using Equation 9-1, the calculation for GainNEW yields: EQUATION 9-2: GAIN NEW = GAIN OLD Expected Measured 1000 2300 --------------------------- = 33480 ------------ = 14556 14556 25 000 issue. The best approach is to choose a range value that places the new gain in the middle of the bounds of the gain registers described above. In a second example, when applying 1A, the user expects an output of 1.0000A with 0.1 mA resolution. The example is starting with the same initial values: EQUATION 9-4: Expected 10000 GAIN NEW = GAIN OLD --------------------------- = 33480 --------------- = 145565 Measured 2300 145565 65535 The GainNEW is much larger than the 16-bit limit of 65535, so fewer right-bit shifts must be introduced to get the measured value closer to the expected value. The user needs to compute the number of bit shifts that will give a value lower than 65535. To estimate this number: EQUATION 9-5: When using the Auto-Calibration Gain command, the result is a failed calibration or a NAK returned form the MCP39F511N, because the resulting GainNEW is less than 25,000. The solution is to use the Range register to bring the measured value closer to the expected value, such that a new gain value can be calculated within the limits specified above. The Range register specifies the number of right-bit shifts (equivalent to divisions by 2) after the multiplication with the Gain Current RMS register. Refer to Section 5.0 “Calculation Engine (CE) Description” for information on the Range register. Incrementing the Range register by 1 unit, performing an additional right-bit shift or dividing in half is included in the calculation. Increasing the current range from 12 to 13 yields the new measured Current RMS register value of 2300/2 = 1150. The expected (1000) and measured (1150) values are much closer now, so the expected new gain should be within the limits: 145565 ------------------ = 2.2 65535 2.2 rounds to the closest integer value of 2. The range value changes to 12 – 2 = 10; there are two less right-bit shifts. The new measured value will be 2300 x 22 = 9200. EQUATION 9-6: Expected 10000 GAIN NEW = GAIN OLD --------------------------- = 33480 --------------- = 36391 Measured 9200 25 000 36391 65535 The resulting new gain is within the limits, and the device successfully calibrates Current RMS and returns an ACK. EQUATION 9-3: GAIN NEW = GAIN OLD Expected Measured 1000 1150 --------------------------- = 33480 ------------ = 29113 25 000 29113 65535 The resulting new gain is within the limits and the device successfully calibrates Current RMS and returns an ACK. Notice that the range can be set to 14 and the resulting new gain will still be within limits (GainNEW = 58226). However, since this gain value is close to the limit of the 16-bit Gain register, variations from system to system (component tolerances, etc.) might create a scenario where the calibration is not successful on some units and there would be a yield DS20005473A-page 46 2015 Microchip Technology Inc. MCP39F511N 9.4 Calibrating the Phase Compensation Register Phase compensation is provided to adjust for any phase delay between the current and voltage paths. Channel 1 and channel 2 both have independent phase compensation registers. This procedure requires sinusoidal current and voltage waveforms with a significant phase shift between them, and significant amplitudes. The recommended displacement power factor for calibration is 0.5. The procedure for calculating the phase compensation register is as follows: 1. Determine what the difference is between the angle corresponding to the measured power factor (PFMEAS) and the angle corresponding to the expected power factor (PFEXP), in degrees. EQUATION 9-7: Value in PowerFactor Register PF MEAS = --------------------------------------------------------------------------32768 180 ANGLEMEAS = acos PF MEAS --------- 180 ANGLE EXP = acos PF EXP --------- 2. Convert this from degrees to the resolution provided in Equation 9-8: EQUATION 9-8: = ANGLE MEAS – ANGLE EXP 40 3. 9.5 Offset/No-Load Calibrations During offset calibrations, it is recommended that no line voltage or current be applied to the system. The system should be in a no-load condition. 9.5.1 AC OFFSET CALIBRATION There are three registers associated with the AC Offset Calibration: • • • • • • Offset Current RMS Channel 1 Offset Current RMS Channel 2 Offset Active Power Channel 1 Offset Active Power Channel 2 Offset Reactive Power Channel 1 Offset Reactive Power Channel 2 When computing the AC offset values, the respective gain and range registers should be taken into consideration according to the block diagrams in Figures 5-2 and 5-4. After a successful offset calibration, a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. 9.5.2 DC OFFSET CALIBRATION In DC applications, the high-pass filter on the current and voltage channels is turned off. To remove any residual DC value on the current, the DCOffsetCurrent Channel 1 and Channel 2 registers add to the A/D conversion immediately after the ADC and prior to any other function. Combine this additional phase compensation to whatever value is currently in the phase compensation and update the register. It is recommended that Equation 9-9 be computed in terms of an 8-bit two's complement-signed value. The 8-bit result is placed in the least significant byte of the 16-bit Phase Compensation register. EQUATION 9-9: PhaseCompensation NEW = PhaseCompensation OLD + Based on Equation 9-9, the maximum angle in degrees that can be compensated is ±3.2 degrees. If a larger phase shift is required, contact your local Microchip sales office. 2015 Microchip Technology Inc. DS20005473A-page 47 MCP39F511N 9.6 Calibrating the Line Frequency Register The Line Frequency register contains a 16-bit number with a value equivalent to the input-line frequency as it is measured on the voltage channel. When in DC mode, this calculation is turned off and the register will be equal to zero. The measurement of the line frequency is only valid from 45 to 65 Hz. 9.6.1 USING THE AUTO-CALIBRATE FREQUENCY COMMAND By applying a stable reference voltage with a constant line frequency that is equivalent to the value that resides in the LineFrequencyRef register, the Auto-Calibrate Frequency command can then be issued to the device. After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. The following register is set when the Auto-Calibrate Frequency command is issued: • Gain Line Frequency The formula used to calculate the new gain is shown in Equation 9-1. 9.7 Retrieving Factory-Default Calibration Values After user calibration and a Save to Flash command has been issued, it is possible to retrieve the factory-default calibration values. This can be done by writing 0xA5A5 to the Calibration Delimiter register, issuing a Save to Flash, and then resetting the part. This procedure will retrieve all factory default-calibration values and will remain in this state until calibration has been performed again, and a Save to Flash command has been issued. DS20005473A-page 48 2015 Microchip Technology Inc. MCP39F511N 10.0 There are three commands that support access to the EEPROM array. EEPROM The data EEPROM is organized as 16-bit wide memory. Each word is directly addressable, and is readable and writable across the entire VDD range. The MCP39F511N has 256 16-bit words of EEPROM that is organized in 32 pages for a total of 512 bytes. TABLE 10-1: • EEPROM Page Read (0x42) • EEPROM Page Write (0x50) • EEPROM Bulk Erase (0x4F) EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE Command Command ID BYTE 0 BYTE 1-N # Bytes Successful Response 0x42 PAGE 2 ACK, Data, Checksum Page Write EEPROM 0x50 PAGE + 16 BYTES OF DATA 18 ACK Bulk Erase EEPROM 0x4F None 1 ACK Page Read EEPROM TABLE 10-2: Page MCP39F511N EEPROM ORGANIZATION 00 02 04 06 08 0A 0C 0E 0 0000 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 1 0010 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 2 0020 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 3 0030 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4 0040 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 5 0050 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 6 0060 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 7 0070 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 8 0080 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 9 0090 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 10 00A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 11 00B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 12 00C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 13 00D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 14 00E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 15 00F0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 16 0100 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 17 0110 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 18 0120 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 19 0130 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 20 0140 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 21 0150 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 22 0160 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 23 0170 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 24 0180 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 25 0190 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 26 01A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 27 01B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 28 01C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 29 01D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 30 01E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 31 01F0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 2015 Microchip Technology Inc. DS20005473A-page 49 MCP39F511N NOTES: DS20005473A-page 50 2015 Microchip Technology Inc. MCP39F511N 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 28-Lead QFN (5x5x0.9 mm) PIN 1 XXXXXXX XXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example PIN 1 39F511N 39F511N -E/MQ ^^ -E/MQ e e^^33 1549256 1549256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2015 Microchip Technology Inc. DS20005473A-page 51 MCP39F511N 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.10 C C SEATING PLANE A1 A 28X A3 SIDE VIEW 0.08 C 0.10 C A B D2 0.10 C A B E2 28X K 2 1 NOTE 1 N 28X L e BOTTOM VIEW 28X b 0.10 0.05 C A B C Microchip Technology Drawing C04-140C Sheet 1 of 2 DS20005473A-page 52 2015 Microchip Technology Inc. MCP39F511N 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Standoff A1 Contact Thickness A3 E Overall Width Exposed Pad Width E2 Overall Length D D2 Exposed Pad Length b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.80 0.00 3.15 3.15 0.18 0.35 0.20 MILLIMETERS NOM 28 0.50 BSC 0.90 0.02 0.20 REF 5.00 BSC 3.25 5.00 BSC 3.25 0.25 0.40 - MAX 1.00 0.05 3.35 3.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-140C Sheet 2 of 2 2015 Microchip Technology Inc. DS20005473A-page 53 MCP39F511N 28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-2140A DS20005473A-page 54 2015 Microchip Technology Inc. MCP39F511N APPENDIX A: REVISION HISTORY Revision A (December 2015) • Original release of this document. 2015 Microchip Technology Inc. DS20005473A-page 55 MCP39F511N NOTES: DS20005473A-page 56 2015 Microchip Technology Inc. MCP39F511N PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) X Tape and Temperature Reel Range Device: /XX Package MCP39F511N: Dual-Channel Single-Phase Power-Monitoring IC with Calculation Examples: a) MCP39F511N-E/MQ: Extended temperature, 28LD 5x5 QFN package b) MCP39F511NT-E/MQ: Tape and Reel, Extended temperature, 28LD 5x5 QFN package Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel (1) Temperature Range: E = -40°C to +125°C Package: MQ = Plastic Quad Flat, No Lead Package 5x5x0.9 mm body (QFN), 28-lead 2015 Microchip Technology Inc. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability for the Tape and Reel option. DS20005473A-page 57 MCP39F511N NOTES: 2015 Microchip Technology Inc. DS20005473A-page 58 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0103-2 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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