X40020, X40021
®
Data Sheet
May 17, 2006
FN8112.1
APPLICATIONS
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery switch backup
• VOUT: 5mA to 50mA from VCC; 250µA from VBATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA battery current in backup mode
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• Monitor voltages: 5V to 1.6V
• Memory security
• Pb-free plus anneal available (RoHS compliant)
X40020, X40021
Standard VTRIP1 Level Standard VTRIP2, Level Suffix
4.6V (±1%)
2.9V(±1.7%)
-A
4.6V (±1%)
2.6V (±2%)
-B
2.9V(±1.7%)
1.6V (±3%)
-C
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
The X40020 combines power-on reset control, watchdog timer, supply voltage supervision, and secondary
supervision, and manual reset, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator to stabilize before the processor can execute code.
BLOCK DIAGRAM
+
V2MON
SDA
WP
SCL
V2 Monitor
Logic
Fault Detection
Register
Data
Register
+
VBATT
System
Battery
Switch
1
Watchdog
and
Reset Logic
WDO
VOUT
MR
VCC
(V1MON)
V2FAIL
VTRIP2
Status
Register
Command
Decode Test
& Control
Logic
VOUT
BATT-ON
VOUT
-
VOUT
VCC Monitor
Logic
-
VTRIP1
Power-on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40020
RESET
X40021
LOWLINE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40020, 40021
Ordering Information
PART
NUMBER*
WITH RESET
X40020S14-C
PART
MARKING
X40020S C
PART
NUMBER*
WITH RESET
X40021S14-C
PART
MARKING
X40021S C
MONITORED
VCC
SUPPLIES
VTRIP1
RANGE
(mV)
VTRIP2
RANGE
(mV)
TEMP.
RANGE (°C)
1.6 to 3.6
2.9 ±50
1.6 ±50
0 to 70
X40020S14I-C X40020S IC X40021S14I-C X40021S IC
X40020V14-C
X4002 0VC
X40021V14-C
X40020S B
X40021S14-B
X4002 1VC
X40021S B
0 to 70
2.6 to 5.5
4.6 ±50
2.6 ±50
X40020S14Z-B X40020S ZB X40021S14Z-B X40021S ZB
(Note)
(Note)
X40020S14I-B
X40020S IB
X40021S14I-B
X40021S IB
X4002 0VB
X40021V14-B
X4002 0VIB
X40021V14I-B
X4002 1VB
X4002 1VIB
X40020V14IZ-B X4002 0VZIB X40021V14IZ-B X4002 1VZIB
(Note)
(Note)
X40020S14-A
X40020S A
X40021S14-A
X40021S A
X40020S14Z-A X40020S ZA X40021S14Z-A X40021S ZA
(Note)
(Note)
X40020S14I-A
X40020S IA
X40021S14I-A
X40021S IA
X40020S14IZ-A X40020S ZIA X40021S14IZ-A X40021S ZIA
(Note)
(Note)
X40020V14-A
X4002 0VA
X40021V14-A
X4002 1VA
X40020V14Z-A X4002 0VZA X40021V14Z-A X4002 1VZA
(Note)
(Note)
X40020V14I-A
X4002 0VIA
X40021V14I-A
X4002 1VIA
X40020V14IZ-A X4002 0VZIA X40021V14IZ-A X4002 1VZIA
(Note)
(Note)
14 Ld TSSOP
(4.4mm)
M14.173
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
0 to 70
14 Ld SOIC (150 mil) MDP0027
0 to 70
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
X40020V14Z-B X4002 0VZB X40021V14Z-B X4002 1VZB
(Note)
(Note)
X40020V14I-B
14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40020S14IZ-B X40020S ZIB X40021S14IZ-B X40021S ZIB
(Note)
(Note)
X40020V14-B
PKG.
DWG. #
-40 to +85 14 Ld SOIC (150 mil) MDP0027
X40020V14I-C X4002 0VIC X40021V14I-C X4002 1VIC
X40020S14-B
PACKAGE
2.9 to 5.5
2.9 ±50
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
0 to 70
14 Ld SOIC (150 mil) MDP0027
0 to 70
14 Ld SOIC (150 mil) MDP0027
(Pb-free)
-40 to +85 14 Ld SOIC (150 mil) MDP0027
-40 to +85 14 Ld SOIC (150 mil) MDP0027
(Pb-free)
0 to 70
14 Ld TSSOP
(4.4mm)
M14.173
0 to 70
14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
-40 to +85 14 Ld TSSOP
(4.4mm)
M14.173
-40 to +85 14 Ld TSSOP
(4.4mm) (Pb-free)
M14.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8112.1
May 17, 2006
X40020, 40021
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second voltage monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be reprogrammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares VCC with VBATT input
and connects VOUT to whichever is higher. This provides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
50mA from VCC to 250µA from VBATT. The device only
switches to VBATT when VCC drops below the low VCC
voltage threshold and VBATT.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
X40021
14-Pin SOIC, TSSOP
X40020
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
14
13
12
11
5
6
7
10
9
8
VCC
BATT-ON
VOUT
VBATT
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
BATT-ON
VOUT
VBATT
WP
SCL
SDA
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used.
3
LOWLINE
4
WDO
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
5
MR
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up
resistor.
6
RESET/
RESET
RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the programmed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1.
When VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor.
3
FN8112.1
May 17, 2006
X40020, 40021
PIN DESCRIPTION (Continued)
Pin
Name
Function
7
VSS
Ground
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
WP
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10MΩ typical)
11
VBATT
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not
used, connect VBATT to ground.
12
VOUT
Output Voltage. (V)
VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1
then VOUT = VCC if VCC > VBATT + 0.03V
else VOUT = VBATT (ie if VCC < VBATT – 0.03V)
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to VOUT to ensure stability.
13
BATT-ON
Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when
VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
14
VCC
Supply Voltage
4
FN8112.1
May 17, 2006
X40020, 40021
PRINCIPLES OF OPERATION
Low Voltage V2 Monitoring
Power-on Reset
Applying power to the X40020/21 activates a Poweron Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to stabilization of the oscillator.
– It allows time for an FPGA to download its configuration prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40021) and RESET (X40020) pin allowing the system
to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
The X40020/21 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V2FAIL signal remains active until the VCC
drops below 1V (VCC falling). It also remains active until
V2MON returns and exceeds VTRIP2.
V2MON voltage monitor is powered by VOUT. If VCC
and VBATT go away, V2MON cannot be monitored.
Figure 2. Two Uses of Multiple Voltage Monitoring
VOUT
X40020
VCC
RESET
System
Reset
V2MON
V2FAIL
R
X40020
System
Reset
5V
Reg
Unreg.
Supply
R
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
RESET
VOUT
MR
Manual
Reset
X40021
Unreg.
Supply
5V
Reg
VCC
3V
Reg
V2MON
RESET
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capability. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains LOW for
tPURST or till the push-button is released and for tPURST
thereafter. A weak pull up resistor is connected to the
MR pin.
Low Voltage V1 Monitoring
During operation, the X40020/21 monitors the VCC
level and asserts RESET if supply voltage falls below
a preset minimum VTRIP1. The RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The V1FAIL signal remains active
until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP1 for tPURST.
5
System
Reset
V2FAIL
Notice: No external components required to monitor two voltages.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. A standard
read or write sequence to any slave address byte
restarts the watchdog timer and prevents the WDO signal to go active. A minimum sequence to reset the
watchdog timer requires four microprocessor instructions
namely, a Start, Clock Low, Clock High and Stop. The
state of two nonvolatile control bits in the Status Register
determine the watchdog timer period. The microprocessor can change these watchdog bits by writing to the
X40020/21 control register (also refer to page 21).
FN8112.1
May 17, 2006
X40020, 40021
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
VCC/V2MON
VP
WDO
7
0
SCL
0
7
0
7
SDA
00h
A0h
The STOP bit following a valid write operation initiates
the programming sequence. Pin WDO must then be
brought LOW to complete the operation.
Figure 4. Watchdog Restart
.6µs
SCL
1.3µs
SDA
Start
WDT Reset
Stop
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40020/21 is shipped with standard V1 and V2
threshold (VTRIP1, VTRIP2) voltages. These values will not
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in
the threshold value, the X40020 trip points may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.
Setting a VTRIPx Voltage (x = 1, 2)
There are two procedures used to set the threshold voltages (VTRIPx), depending if the threshold voltage to be
stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x = 1, 2)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the
corresponding input pin (Vcc(V1MON) or V2MON).
Then, a program-ming voltage (Vp) must be applied to
the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for VTRIP1, and 09h for
VTRIP2, and a 00h Data Byte in order to program VTRIPx.
6
tWC
To check if the VTRIPX has been set, set VXMON to a
value slightly greater than VTRIPX (that was previously
set). Slowly ramp down VXMON and observe when the
corresponding outputs (LOWLINE and V2FAIL) switch.
The voltage at which this occurs is the VTRIPX (actual).
CASE A
Now if the desired VTRIPX is greater than the VTRIPX
(actual), then add the difference between VTRIPX
(desired) - VTRIPX (actual) to the original VTRIPX desired.
This is your new VTRIPX that should be applied to
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
Now if the VTRIPX (actual), is higher than the VTRIPX
(desired), perform the reset sequence as described in
the next section. The new VTRIPX voltage to be applied
to VXMON will now be: VTRIPX (desired) - (VTRIPX
(actual) - VTRIPX (desired)).
Note: 1. This operation does not corrupt the memory
array.
2. Set VCC = 5V, when VTRIP2 is being programmed
Setting a Lower VTRIPx Voltage (x = 1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” according to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
FN8112.1
May 17, 2006
X40020, 40021
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1 and 0Bh for VTRIP2, followed by 00h for the Data
Byte in order to reset VTRIPx. The STOP bit following a
valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of VTRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the registers.
System Battery Switch
As long as VCC exceeds the low voltage detect threshold VTRIP, VOUT is connected to VCC through a 5Ω (typical) switch. When the VCC has fallen below V1TRIP,
then VCC is applied to VOUT if VCC is or equal to or
greater than VBATT - 0.03V. When VCC drops to less
than VBATT - 0.03V, then VOUT is connected to VBATT
through an 80Ω (typical) switch. VOUT typically supplies
the system static RAM voltage, so the switchover circuit
operates to protect the contents of the static RAM during a power failure. Typically, when VCC has failed, the
SRAMs go into a lower power state and draw much less
current than in their active mode. When VCC returns,
VOUT switches back to VCC when VCC exceeds VBATT +
0.03V. There is a 60mV hysteresis around this battery
switch threshold to prevent oscillations between supplies.
While VCC is connected to VOUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP transistor to provide additional current to the external circuits
during normal operation.
Condition
Mode of Operation
VCC > VTRIP1
Normal Operation
VCC > VTRIP1 &
VBATT = 0
Normal Operation without battery
backup capability
0 ≤ VCC ≤ VTRIP1
and VCC < VBATT
Battery Backup mode; RESET
signal is asserted. No communication to the device is allowed.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, and PUP0. The X40020 will not acknowledge any data bytes written after the first byte is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condition to be consistent with the bus protocol, but a stop is
not required to end this operation.
7
6
PUP1 WD1
5
4
3
WD0
0
0
2
1
0
RWEL WEL PUP0
Operation
RWEL: Register Write Enable Latch (Volatile)
The device is in normal operation with VCC as long as
VCC > VTRIP1. It switches to the battery backup mode
when VCC goes away.
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample VTRIP Reset Circuit
VP
V2FAIL
RESET
VTRIP1
Adj.
Adjust
1
6
13
X40020
2
9
7
VTRIP2
Adj.
4.7K
7
µC
14
8
Run
SCL
SDA
FN8112.1
May 17, 2006
X40020, 40021
Figure 6. VTRIPX Set/Reset Sequence (X = 1, 2)
Vx = VCC, VxMON
Note: X = 1, 2
Let: MDE = Maximum Desired Error
VTRIPX Programming
No
Desired
VTRIPX<
Present Value
MDE+
Acceptable
Desired Value
YES
Error Range
Execute
VTRIPX Reset Sequence
MDE–
Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
> Desired VTRIPX to VX
Execute Reset VTRIPX
Sequence
NO
Decrease VX
Output Switches?
YES
Error < MDE–
Error > MDE+
Actual VTRIPX Desired VTRIPX
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
8
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high voltage write cycle, so the device is ready for the next
operation immediately after the stop condition.
FN8112.1
May 17, 2006
X40020, 40021
BP: Block Protect Bit (Nonvolatile)
BP
The Block Protect Bits BP determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half the array segment.
Protected Addresses
(Size)
Memory
Array Lock
0
None
None
1
100h - 1FFh (256 bytes)
Upper Half of
Memory Array
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power-up times are
shown in the following table.
PUP1
PUP0
Power-on Reset Delay (tPURST)
0
0
50ms
0
1
200ms (default)
1
0
400ms
1
1
800ms
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
WD0
Watchdog Time Out Period
0
0
1.4 seconds
0
1
200 milliseconds
1
0
25 milliseconds
1
1
disabled (factory default)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
9
– Write a one byte value to the Control Register that
has all the control bits set to the desired state. The
Control register can be represented as qxy0 001r in
binary, where xy are the WD bits, and qr are the
power-up bits. This operation proceeded by a start
and ended with a stop bit. Since this is a nonvolatile
write cycle it will take up to 10ms to complete. The
RWEL bit is reset by this cycle and the sequence
must be repeated to change the nonvolatile bits
again. If bit 2 is set to ‘1’ in this third step (qxy0 011r)
then the RWEL bit is set, but the WD1, WD0, PUP1,
and PUP0, bits remain unchanged. Writing a second
byte to the control register is not allowed. Doing so
aborts the write operation and returns a NACK.
– A read operation occurring between any of the previous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Note: 1. tPURST is set to 200ms as factory default.
2. Watchdog timer bits are shipped disabled.
Fault Detection Register (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile.
7
6
5
4
3
2
1
0
LV1F
LV2F
0
WDF
MRF
0
0
0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write operation directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the control register to access this fault detection register.
FN8112.1
May 17, 2006
X40020, 40021
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading the register
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will set to “0” when Manual Reset input
goes active.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when WDO goes active.
LV1F, Low VCC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when VCC (V1MON)
falls below VTRIP1.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below VTRIP2.
10
Data Stable
Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
FN8112.1
May 17, 2006
X40020, 40021
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 9.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
Stop
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance.
Figure 9. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
11
Acknowledge
FN8112.1
May 17, 2006
X40020, 40021
Figure 10. Byte Write Sequence
Signals from
the Master
SDA Bus
S
t
a
r
t
Byte
Address
Slave
Address
S
t
o
p
Data
0
Signals from
the Slave
Stops and Write Modes
A
C
K
A
C
K
A
C
K
Figure 11. Acknowledge Polling Sequence
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 11.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one.
12
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
Returned?
Issue STOP
NO
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
FN8112.1
May 17, 2006
X40020, 40021
Read Operation
Slave Address Byte
Prior to issuing the Slave Address Byte with the R/W bit
set to one, the master must first perform a “dummy” write
operation. The master issues the start condition and the
Slave Address Byte, receives an acknowledge, then
issues the Word Address Bytes. After acknowledging
receipts of the Word Address Bytes, the master immediately issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the eight
bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 12 for the address, acknowledge, and data transfer sequence.
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
SERIAL DEVICE ADDRESSING
– a device type identifier that is always “1011” when
accessing the control register and fault detection
register.
– two bits of “0”.
– one bit that becomes the MSB of the memory
address X4.
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. See Figure 13.
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FFhex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FFhex
Figure 12. Read Sequence
S
t
a
r
t
Signals from
the Master
SDA Bus
1 01 1 0 0
0
13
S
t
o
p
Slave
Address
1
1 111 1 1 11
A
C
K
Signals from
the Slave
S
t
a
r
t
Byte
Address
Slave
Address
A
C
K
A
C
K
Data
FN8112.1
May 17, 2006
X40020, 40021
Figure 13. Slave Address, Word Address, and Data Bytes
Slave Byte
General Purpose Memory
Control Register
1
1
0
0
1
1
0
1
0
0
0
0
Fault Detection Register
1
0
1
1
0
0
A8 R/W
1 R/W
0
Word Address
General Purpose Memory A7 A6 A5 A4 A3 A2 A1
Control Register
1
1
1
1
1
1
1
Fault Detection Register
1
1
1
1
1
1
1
R/W
A0
1
1
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter.
The following circuitry has been included to prevent
inadvertent writes:
Operational Notes
– The WEL bit must be set to allow write operations.
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST.
14
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
FN8112.1
May 17, 2006
X40020, 40021
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
respect to VSS ...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10s) .................... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0°C
Industrial
-40°C
70°C
Version Chip Supply Voltage
Monitored
Voltages*
+85°C
-A or -B
2.7V to 5.5V
2.6 to 5.5V
-C
2.7V to 5.5V
1.6V to 3.6V
*See Ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Min.
Typ.(5)
Max.
Unit
ICC1(1)
Active Supply Current (VCC) Read
(Excludes IOUT)
1.5
mA
ICC2(1)
Active Supply Current (VCC) Write Non
Volatile Memory (Excludes IOUT)
3.0
mA
Test Conditions
VIL = VCC x 0.1
VIH = VCC x 0.9,
fSCL = 400kHz
ISB1(1)(7)
Standby Current (VCC) AC (WDT off)
6
10
µA
VIL = VCC x 0.1
VIH = VCC x 0.9
fSCL, fSDA = 400kHz
ISB2(2)(7)
Standby Current (VCC) DC (WDT on)
25
30
µA
VSDA = VSCL = VCC
Others = GND or VCC
0.2
1
µA
VOUT = VCC
0.2
6
µA
VBATT = 2.8V
VOUT = Open
IBATT1(3)(7 VBATT Current (Excludes IOUT)
)
IBATT2(7)
VBATT Current (Excludes IOUT)
(Battery Backup Mode)
VOUT1(7) Output Voltage (VCC > VBATT + 0.03V
or VCC > VTRIP1)
VCC-0.05V
VCC-0.5V
V
IOUT = 5mA VCC = (4.5-5.5V)
IOUT = 50mA VCC = (4.5-5.5V)
VOUT2(7) Output Voltage (VCC < VBATT- 0.03V
and VCC < VTRIP1) {Battery Backup}
VBATT-0.2
V
IOUT = 250µA
V
IOL = 3.0mA (4.5-5.5V)
V
IOH = -0.4mA (4.5-5.5V)
VOLB
Output (BATT-ON) LOW Voltage
VOHB
Output (BATT-ON) HIGH Voltage
VBSH
(7)
0.4
VOUT-0.8
30
-30
Battery Switch Hysteresis
(VCC < VTRIP1)
mV
Power-up
Power-down
ILI
Input Leakage Current (SCL, MR,WP)
10
µA
VIL = GND to VCC
ILO
Output Leakage Current (SDA, V2FAIL,
WDO, RESET)
10
µA
VSDA = GND to VCC
Device is in Standby(2)
VIL(3)
Input LOW Voltage (SDA, SCL, MR,WP)
VCC x 0.3
V
VCC + 0.5
V
VIH
(3)
-0.5
Input HIGH Voltage (SDA, SCL, MR,WP) VCC x 0.7
15
FN8112.1
May 17, 2006
X40020, 40021
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
VHYS
(7)
VOL
Parameter
Typ.(5)
Min.
Schmitt Trigger Input Hysteresis
• Fixed input level
• VCC related level
Max.
0.2
.05 x VCC
Unit
Test Conditions
V
V
Output LOW Voltage (SDA, RESET/RESET, LOWLINE, V2FAIL, WDO)
0.4
V
4.75
V
IOL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.4-3.6V)
VCC Supply
VTRIP1(6) VCC Reset Trip Point Voltage Range
tRPDL(7)
2.0
4.55
4.6
4.65
2.85
2.9
2.95
VTRIP1 to LOWLINE
A, B Version
C Version
5
µS
3.5
V
Second Supply Monitor
VTRIP2(6) V2MON Reset Trip Point Voltage Range
tRPD2(7)
0.9
2.85
2.9
2.95
A Version
2.55
2.6
2.65
B Version
1.55
1.6
1.65
C Version
VTRIP2 to V2FAIL
5
µS
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) Negative numbers indicate charging current, positive numbers indicate discharge current.
(4) VIL Min. and VIH Max. are for reference only and are not tested.
(5) At 25°C, VCC = 3V.
(6) See ordering information for standard programming levels. For custom programming levels, contact factory.
(7) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
∆V
VREF
∆V = 100mV
R
VxMON
+
C
VREF
Output
–
tRPDX = 5µs worst case
16
FN8112.1
May 17, 2006
X40020, 40021
CAPACITANCE
Symbol
COUT(1)
CIN(1)
Note:
Parameter
Max.
Unit
Test Conditions
Output Capacitance (SDA, RESET, RESET/LOWLINE,
V2FAIL, WDO)
8
pF
VOUT = 0V
Input Capacitance (SCL, WP)
6
pF
VIN = 0V
(1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
VCC = 5V
VOUT
5V
V2MON
4.6kΩ
2.06kΩ
RESET
WDO/LOWLINE
SDA
30pF
4.6kΩ
V2FAIL
30pF
30pF
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing levels
VCC x 0.5
Output load
Standard output load
17
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8112.1
May 17, 2006
X40020, 40021
A.C. CHARACTERISTICS
400kHz
Symbol
fSCL
Parameter
Min.
SCL Clock Frequency
Max.
Unit
400
kHz
tIN
Pulse width Suppression Time at inputs
50
tAA
SCL LOW to SDA Data Out Valid
0.1
tBUF
Time the bus free before start of new transmission
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
Data Output Hold Time
50
ns
tDH
ns
0.9
µs
+.1Cb(1)
300
ns
300
ns
tR
SDA and SCL Rise Time
20
tF
SDA and SCL Fall Time
20 +.1Cb(1)
tSU:WP
WP Setup Time
0.6
µs
tHD:WP
WP Hold Time
0
µs
Cb
Note:
Capacitive load for each bus line
400
pF
(1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tHIGH
tF
SCL
tR
tSU:DAT
tSU:STA
SDA IN
tLOW
tHD:STA
tHD:DAT
tSU:STO
tAA
tDH
tBUF
SDA OUT
18
FN8112.1
May 17, 2006
X40020, 40021
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
tSU:WP
tHD:WP
WP
Write Cycle Timing
SCL
SDA
ACK
8th Bit of Last Byte
tWC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
tWC
Note:
Parameter
(1)
Min.
Write Cycle Time
Typ.(1)
Max.
Unit
5
10
ms
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
VTRIPX
tRPDL
VCC or
tRPDX
V2MON
tRPDL
tRPDX
tRPDX
tF
tR
LOWLINE or
tRPDL
VRVALID
V2FAIL
X = 1, 2
19
FN8112.1
May 17, 2006
X40020, 40021
RESET/RESET/MR Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
VRVALID
RESET
MR
tMD
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Symbol
tRPD1(1)
tRPDL
tLR (1)
Parameters
Min.
Typ.
VTRIP1 to RESET/RESET (Power-down only)
VTRIP1 to LOWLINE
LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL]
tRPD2(1)
VTRIP2 to V2FAIL
tPURST
Power-on Reset delay:
PUP1 = 0, PUP0 = 0
PUP1 = 0, PUP0 = 1 (Factory default)
PUP1 = 1, PUP0 = 0
PUP1 = 1, PUP0 = 1
Max.
Unit
5
µs
500
ns
5
50(1)
200
400(1)
800(1)
µs
ms
ms
ms
ms
tF
VCC, V2MON Fall Time
20
mV/µs
tR
VCC, V2MON Rise Time
20
mV/µs
Reset Valid VCC
1
V
MR to RESET/ RESET delay (activation only)
500
ns
Pulse width Suppression Time for MR
50
ns
VRVALID
tMD
(1)
tin1
tWDO
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
WD1 = 1, WD0 = 1 (factory default)
tRST1
Watchdog Reset Time Out Delay
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
100
200
300
ms
tRST2
Watchdog Reset Time Out Delay WD1=1, WD0=0
12.5
25
37.5
ms
tRSP
Watchdog timer restart pulse width
Note:
1.4(1)
200(1)
25
OFF
1
s
ms
ms
µs
(1) Based on characterization data.
20
FN8112.1
May 17, 2006
X40020, 40021
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
WDO
tWDO
tRST
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
VTRIPX Set/Reset Conditions
VCC/V2MON
(VTRIPX)
tTHD
VP
tTSU
WDO
tVPS
tVPH
SCL
7
0
0
7
0
tVPO
7
*
SDA
00h
A0h
tWC
Start
*01h sets VTRIP1
*09h sets VTRIP2
*03h resets VTRIP1
*0Bh resets VTRIP2
* all others reserved
21
FN8112.1
May 17, 2006
X40020, 40021
VTRIP1, VTRIP2 Programming Specifications: VCC = 2.0-5.5V; Temperature = 25°C
Parameter
Description
Min.
Max.
Unit
tVPS
WDO Program Voltage Setup time
10
µs
tVPH
WDO Program Voltage Hold time
10
µs
tTSU
VTRIPX Level Setup time
10
µs
tTHD
VTRIPX Level Hold (stable) time
10
µs
tWC
VTRIPX Program Cycle
10
ms
tVPO
Program Voltage Off time before next cycle
1
ms
Programming Voltage
15
18
V
VTRAN1
VTRIP1 Set Voltage Range
2.0
4.75
V
VTRAN2
VP
VTRIP2 Set Voltage Range
0.9
3.5
V
Vtv
VTRIPX Set Voltage variation after programming (0-75°C).
-25
+25
mV
tVPS
WDO Program Voltage Setup time
10
µs
VTRIPX programming parameters are periodically sampled and are not 100% tested.
22
FN8112.1
May 17, 2006
X40020, 40021
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
SO-8
SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
N
8
14
16
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
23
FN8112.1
May 17, 2006
X40020, 40021
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
α
e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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24
FN8112.1
May 17, 2006