INTERSIL X4163S8

X4163, X4165
®
16K, 2K x 8 Bit
Data Sheet
April 13, 2005
CPU Supervisor with 16K EEPROM
FN8120.0
DESCRIPTION
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 16Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
—8-lead SOIC
—8-lead TSSOP
The X4163/5 combines four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the set minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Four industry
standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
S0
Data
Register
Command
Decode &
Control
Logic
S1
VCC Threshold
Reset logic
VCC
Status
Register
EEPROM Array
+
VTRIP
1
RESET (X4163)
RESET (X4165)
Reset &
Watchdog
Timebase
2Kb
SCL
Protect Logic
Block Lock Control
SDA
Watchdog
Timer Reset
-
Power on and
Low Voltage
Reset
Generation
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4163, X4165
PIN CONFIGURATION
8-Pin JEDEC SOIC
S0
S1
RESET/RESET
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8 Pin TSSOP
WP
VCC
S0
S1
1
2
3
4
8
7
6
5
SCL
SDA
VSS
RESET/RESET
PIN FUNCTION
Pin
(SOIC)
Pin
(TSSOP)
Name
1
3
S0
Device Select Input
2
4
S1
Device Select Input
3
5
RESET/
RESET
4
6
VSS
Ground
5
7
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
6
8
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
7
1
WP
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
8
2
VCC
Supply Voltage
2
Function
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 250ms.
RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET
goes active on power up and remains active for 250ms after the power supply stabilizes.
FN8120.0
April 13, 2005
X4163, X4165
PRINCIPLES OF OPERATION
WATCHDOG TIMER
– It prevents the processor from operating prior to stabilization of the oscillator.
The Watchdog Timer circuit monitors the microprocessor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two nonvolatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
– It allows time for an FPGA to download its configuration prior to initialization of the circuit.
EEPROM INADVERTENT WRITE PROTECTION
Power On Reset
Application of power to the X4163/5 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP threshold value
for
200ms
(nominal)
the
circuit
releases
RESET/RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4163/5 monitors the VCC level
and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any inprogress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC THRESHOLD RESET PROCEDURE
The X4163/5 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X4163/5 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvolatile control signal.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
00h
3
01h
00h
FN8120.0
April 13, 2005
X4163, X4165
Setting the VTRIP Voltage
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher or
lower voltage value. It is necessary to reset the trip
point before setting the new value.
This procedure is used to set the VTRIP to a “native”
voltage level. For example, if the current VTRIP is 4.4V
and the new VTRIP must be 4.0V, then the VTRIP must
be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To set the new VTRIP voltage, start by setting the WEL
bit in the control register, then apply the desired VTRIP
threshold voltage to the VCC pin and the programming
voltage, VP, to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
To reset the new VTRIP voltage start by setting the
WEL bit in the control register, apply VCC and the programming voltage, VP , to the WP pin and 2 byte
address and 1 byte of “00” data. The stop bit of a valid
write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Figure 2. Reset VTRIP Level Sequence (VCC > 3V. WP = 12–15V, WEL bit set)
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
03h
00h
00h
Figure 3. Sample VTRIP Reset Circuit
VP
SOIC
Adjust
4.7K
RESET
1
2
3
VTRIP
Adj.
4
µC
8
X4163
7
6
5
Run
SCL
SDA
4
FN8120.0
April 13, 2005
X4163, X4165
Figure 4. VTRIP Programming Sequence
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
New VCC Applied =
Old VCC Applied - Error
Execute
Set VTRIP
Sequence
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error ≤ –Emax
Error ≥ Emax
Measured VTRIP Desired VTRIP
–Emax < Error < Emax
Emax = Maximum Allowed VTRIP Error
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write operation directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
5
DONE
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, and WD0. The X4163/5 will not acknowledge
any data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4163/5 resets itself after the first byte is read.
The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required
to end this operation.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
FN8120.0
April 13, 2005
X4163, X4165
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next operation immediately after the stop condition.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block protect bits will prevent write operations to the following
segments of the array.
WD1, WD0: Watchdog Timer Bits
BP2
BP1
BP0
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Protected Addresses
(Size)
0
0
0
None (factory setting)
None
0
0
1.4 seconds
0
0
1
None
None
0
1
600 milliseconds
0
1
0
None
None
1
0
200 milliseconds
0
1
1
0000h - 7FFh (2K bytes)
Full Array (All)
1
1
disabled (factory setting)
Array Lock
WD1
WD0
Watchdog Time Out Period
1
0
0
000h - 03Fh (64 bytes)
First Page (P1)
1
0
1
000h - 07Fh (128 bytes)
First 2 pgs (P2)
1
1
0
000h - 0FFh (256 bytes)
First 4 pgs (P4)
1
1
1
000h - 1FFh (512 bytes)
First 8 pgs (P8)
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of five blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes to the
block protected sections in the memory array cannot be
written and the block protect bits cannot be changed.
Only the sections of the memory array that are not
block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed
back to a LOW state; so write protection is enabled as
long as the WP pin is held HIGH.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
Table 1. Write Protect Enable Bit and WP Pin Function
WP
WPEN
Memory Array not
Block Protected
Memory Array Block
Protected
WPEN Bit
Protection
LOW
X
Writes OK
Writes Blocked
Writes OK
Software
HIGH
0
Writes OK
Writes Blocked
Writes OK
Software
HIGH
1
Writes OK
Writes Blocked
Writes Blocked
Hardware
6
FN8120.0
April 13, 2005
X4163, X4165
Writing to the Control Register
Changing any of the nonvolatile bits of the control register requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be represented as 0xys t01r in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop). Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xys t11r) then the
RWEL bit is set, but the BP2, BP1, BP0, WD1 and
WD0 bits remain unchanged. Writing a second byte
to the control register is not allowed. Doing so aborts
the write operation and returns a NACK.
– A read operation occurring between any of the previous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
7
Data Change
Data Stable
FN8120.0
April 13, 2005
X4163, X4165
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
Stop
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from Receiver
Start
8
Acknowledge
FN8120.0
April 13, 2005
X4163, X4165
Figure 8. Byte Write Sequence
S
t
a
r
t
Signals from
the Master
SDA Bus
Slave
Address
10 1 0
S
t
o
p
Data
0
A
C
K
Signals from
the Slave
Word Address
Byte 0
Word Address
Byte 1
A
C
K
A
C
K
A
C
K
Page Write
Serial Write Operations
The device is capable of a page write operation. It is
initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowledge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12-bytes, then the first 4bytes are written to locations 60 through 63, and the
last 8-bytes are written to locations 0 through 7. Afterwards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64-bytes of data, then new data over-writes
the previous data, one byte at a time.
BYTE WRITE
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits
the next eight bits of data. After receiving the 8 bits of
the Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA
output is at high impedance. See Figure 8.
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 9. Page Write Operation
Signals from
the Master
S
t
a
r
t
(1 < n < 64)
Word Address
Byte 1
Slave
Address
S
t
o
p
Data
(n)
Data
(1)
Word Address
Byte 0
SDA Bus
1 0 1 0
0
A
C
K
Signals from
the Slave
9
A
C
K
A
C
K
A
C
K
A
C
K
FN8120.0
April 13, 2005
X4163, X4165
Figure 10. Writing 12-bytes to a 64-byte page starting at location 60.
8 Bytes
Address
=7
4 Bytes
Address Pointer
Ends Here
Addr = 8
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Address
60
Address
n-1
Figure 11. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
YES
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal nonvolatile cycle. Acknowledge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.
10
Nonvolatile Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
FN8120.0
April 13, 2005
X4163, X4165
Figure 12. Current Address Read Sequence
Signals from
the Master
S
t
a
r
t
SDA Bus
S
t
o
p
Slave
Address
1 0 1 0
1
A
C
K
Signals from
the Slave
Data
Serial Read Operations
Random Read
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12
for the address, acknowledge, and data transfer
sequence.
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Figure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 13. Random Address Read Sequence
Signals from
the Master
SDA Bus
S
t
a
r
t
Word Address
Byte 1
Slave
Address
1 0 1 0
11
Word Address
Byte 0
0
S
t
o
p
Slave
Address
1
A
C
K
Signals from
the Slave
S
t
a
r
t
A
C
K
A
C
K
A
C
K
Data
FN8120.0
April 13, 2005
X4163, X4165
Figure 14. Sequential Read Sequence
Signals from
the Master
Slave
Address
SDA Bus
A
C
K
S
t
o
p
A
C
K
A
C
K
1
A
C
K
Signals from
the Slave
Data
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
X4163/5 Addressing
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000H and the device continues
to output data for each acknowledge received. Refer
to Figure 14 for the acknowledge and data transfer
sequence.
SLAVE ADDRESS BYTE
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array.
– one bits of ‘0’.
– next two bits are the device address.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the operation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
12
FN8120.0
April 13, 2005
X4163, X4165
Figure 15. X4163/5 Addressing
Device Identifier
1
0
1
Device Select
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
0
0
0
0
0
A10
(X4)
A9
(X3)
A8
(X2)
A1
(Y1)
A0
(Y0)
D1
D0
Word Address Byte 0–16K
Low Order Word Address
A7
(X1)
A6
(X0)
A5
(Y5)
A4
(Y4)
A3
(Y3)
A2
(Y2)
Word Address Byte 0 for all options
D7
D6
D5
D4
D3
D2
Data Byte for all options
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible to write to the device.
– SDA pin is the input mode.
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress communication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
– RESET/RESET Signal is active for tPURST.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
– The WEL bit must be set to allow write operations.
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
13
FN8120.0
April 13, 2005
X4163, X4165
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Option
Supply Voltage Limits
Commercial
0°C
70°C
-2.7 and -2.7A
2.7V to 5.5V
Industrial
-40°C
+85°C
Blank and -4.5A
4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
VCC = 2.7 to 5.5V
Max
Unit
Test Conditions
Active Supply Current Read
1.0
mA
Active Supply Current Write
3.0
mA
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Commands
Standby Current DC (WDT off)
1
µA
VSDA = VSCL = VSB
Others = GND or VSB
Standby Current DC (WDT on)
20
µA
VSDA=VSCL=VSB
Others = GND or VSB
ILI
Input Leakage Current
10
µA
VIN = GND to VCC
ILO
Output Leakage Current
10
µA
VSDA = GND to VCC
Device is in Standby(2)
-0.5
VCC x 0.3
V
Input nonvolatile
VCC x 0.7
VCC + 0.5
V
Schmitt Trigger Input Hysteresis
Fixed input level
VCC related level
0.2
.05 x VCC
Symbol
ICC1(1)
ICC2(1)
ISB(2)
ISB(2)
VIL(3)
VIH
(3)
VHYS
VOL
Parameter
Input LOW Voltage
Output LOW Voltage
Min
V
V
0.4
V
IOL = 3.0mA (2.7- 5.5V)
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
14
FN8120.0
April 13, 2005
X4163, X4165
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol
COUT
CIN
(4)
(4)
Parameter
Max.
Unit
Test Conditions
Output Capacitance (SDA, RST/RST)
8
pF
VOUT = 0V
Input Capacitance (SCL, WP)
6
pF
VIN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
5V
1533Ω
SDA
or
RESET
For VOL= 0.4V
and IOL = 3 mA
Input pulse levels
0.1VCC to 0.9VCC
Input rise and fall times
10ns
Input and output timing levels
0.5VCC
Output load
Standard output load
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
Parameter
Min.
Max.
Unit
400
kHz
SCL Clock Frequency
0
tIN
Pulse width Suppression Time at inputs
50
tAA
SCL LOW to SDA Data Out Valid
0.1
tBUF
Time the bus free before start of new transmission
1.3
µs
tLOW
Clock LOW Time
1.3
µs
tHIGH
Clock HIGH Time
0.6
µs
tSU:STA
Start Condition Setup Time
0.6
µs
tHD:STA
Start Condition Hold Time
0.6
µs
ns
0.9
µs
tSU:DAT
Data In Setup Time
100
ns
tHD:DAT
Data In Hold Time
0
µs
tSU:STO
Stop Condition Setup Time
0.6
µs
tDH
Data Output Hold Time
50
ns
tR
SDA and SCL Rise Time
20 + .1Cb
300
ns
tF
SDA and SCL Fall Time
20 + .1Cb
300
ns
tSU:WP
WP Setup Time
0.6
µs
tHD:WP
WP Hold Time
0
µs
Cb
Capacitive load for each bus line
400
pF
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
15
FN8120.0
April 13, 2005
X4163, X4165
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
SCL
tR
tLOW
tSU:DAT
tSU:STA
SDA IN
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
tSU:WP
WP
tHD:WP
Write Cycle Timing
SCL
SDA
8th bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
tWC
Parameter
(1)
Write Cycle Time
Min.
Typ.(1)
Max.
Unit
5
10
ms
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
16
FN8120.0
April 13, 2005
X4163, X4165
Power-Up and Power-Down Timing
VTRIP
VCC
tPURST
0 Volts
tR
tPURST
tF
tRPD
VRVALID
RESET
(X4165)
VRVALID
RESET
(X4163)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset Trip Point Voltage, X4163/5-4.5A
Reset Trip Point Voltage, X4163/5
Reset Trip Point Voltage, X4163/5-2.7A
Reset Trip Point Voltage, X4163/5-2.7
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
tPURST
Power-up Reset Time Out
100
250
400
ms
500
ns
tRPD
tF
(8)
VCC Detect to Reset/Output
(8)
VCC Fall Time
100
µs
(8)
VCC Rise Time
100
µs
1
V
tR
VRVALID
Reset Valid VCC
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
tRSP
tRSP<tWDO
tRSP>tWDO
tRSP>tWDO
tRST
tRST
SCL
SDA
RESET
Note: All inputs are ignored during the active reset period (tRST).
17
FN8120.0
April 13, 2005
X4163, X4165
RESET Output Timing
Symbol
tWDO
tRST
Parameter
Min.
Typ.
Max.
Units
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
250
650
1.5
400
850
2
ms
ms
sec
Reset Time Out
100
250
400
ms
VTRIP Programming Timing Diagram (WEL = 1)
VCC
(VTRIP)
VTRIP
tTSU
tTHD
VP
WP
tVPH
tVPS
tVPO
SCL
tRP
SDA
01h or 03h
00h
A0h
00h
VTRIP Programming Parameters
Parameter
Description
Min.
Max.
Unit
tVPS
VTRIP Program Enable Voltage Setup time
1
µs
tVPH
VTRIP Program Enable Voltage Hold time
1
µs
tTSU
VTRIP Setup time
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
0
µs
tRP
VTRIP Program Recovery Period (Between successive adjustments)
10
ms
VP
Programming Voltage
15
18
V
VTRIP Programmed Voltage Range
2.55
4.75
V
Vta1
Initial VTRIP Program Voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.)
-0.1
+0.4
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied - Vta1) - VTRIP.
Programmed at 25°C.]
-25
+25
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations. Programmed
at 25°C.)
-25
+25
mV
Vtv
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
VTRAN
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
18
FN8120.0
April 13, 2005
X4163, X4165
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030"
Typical
8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
FN8120.0
April 13, 2005
X4163, X4165
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
(4.16) (7.72)
Detail A (20X)
(1.78)
.031 (.80)
.041 (1.05)
(0.42)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
20
FN8120.0
April 13, 2005
X4163, X4165
Ordering Information
VCC
Range
VTRIP
Range
Package
Operating
Temperature Range
Part Number RESET
(Active LOW)
Part Number RESET
(Active HIGH)
4.5-5.5V
4.5-4.75
8L SOIC
0°C - 70°C
X4163S8–4.5A
X4165S8–4.5A
-40°C - 85°C
X4163S8I–4.5A
X4165S8I–4.5A
0°C - 70°C
X4163V8–4.5A
X4165V8–4.5A
-40°C - 85°C
X4163V8I–4.5A
X4165V8I–4.5A
0°C - 70°C
X4163S8
X4165S8
-40°C - 85°C
X4163S8I
X4165S8I
8L TSSOP
4.5-5.5V
4.25-4.5
8L SOIC
8L TSSOP
2.7-5.5V
2.85-3.0
8L SOIC
8LTSSOP
2.7-5.5V
2.55-2.7
8L SOIC
8L TSSOP
0°C - 70°C
X4163V8
X4165V8
-40°C - 85°C
X4163V8I
X4165V8I
0°C - 70°C
X4163S8–2.7A
X4165S8–2.7A
-40°C - 85°C
X4163S8I–2.7A
X4165S8I–2.7A
0°C - 70°C
X4163V8–2.7A
X4165V8–2.7A
-40°C - 85°C
X4163V8I–2.7A
X4165V8I–2.7A
0°C - 70°C
X4163S8–2.7
X4165S8–2.7
-40°C - 85°C
X4163S8I–2.7
X4165S8I–2.7
0°C - 70°C
X4163V8–2.7
X4165V8–2.7
-40°C - 85°C
X4163V8I–2.7
X4165V8I–2.7
Part Mark Information
8-Lead TSSOP
EYWW
XXXXX
8-Lead SOIC
X4163/5 X
XX
ADB/ADK = -4.5A (0 to +70°C)
ADD/ADM = No Suffix (0 to +70°C)
ADF/ADO = -2.7A (0 to +70°C)
ADH/ADQ= -2.7 (0 to +70°C)
4163/4165
Blank = 8-Lead SOIC
AL = -4.5A (0 to +70°C)
AM = -4.5A (-40 to +85°C)
Blank = No Suffix (0 to +70°C)
I = No Suffix (-40 to +85°C)
AN = -2.7A (0 to +70°C)
AP = -2.7A (-40 to +85°C)
F = -2.7 (0 to +70°C)
G = -2.7 (-40 to +85°C)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8120.0
April 13, 2005