ISL59831 ® Data Sheet March 29, 2007 Single Supply Video Driver with Reconstruction Filter and Charge Pump The ISL59831 is a single supply video driver with reconstruction filter and charge pump. It is designed to drive SDTV displays with luma (Y) or composite video (CV) signals. It operates on a single supply (3.0V to 3.6V) and generates its own negative supply (-1.9V) using a regulated charge pump. Input signal can be AC or DC coupled. When AC coupled, the sync tip clamp sets the blank level to ground at the output, ensuring that the sync-tip voltage level is set to approximately -300mV at the back-termination resistor of a standard video load. The ISL59831 is capable of driving two AC or DC coupled standard video loads. The device also features a 4th order Butterworth reconstruction filter with nominal -3dB frequency set to 9.1MHz, providing 44dB of attenuation at 27MHz. When powered down, the device draws 2µA supply current. Nominal operational current is 15mA. The ISL59831 is available in 12 Ld TDFN package and operates from the -40°C to +85°C temperature range. Pinout FN6266.0 Features • 3.3V Nominal Supply, Operates Down to 3.0V • DC-Coupled or AC-Coupled Input or Output • Eliminates Need for Large Output Coupling Capacitor • Internal Sync Tip Clamp Puts the Backporch to Ground at the Output • Drives Two Standard Video Loads • Response Flat to 5MHz and 44dB Attenuation at 27MHz • Pb-free Plus Anneal Available (RoHs Compliant) Applications • Set-Top Box Receiver • Televisions • DVD Players • Digital Displays • Cell Phones ISL59831 (12 LD TDFN) TOP VIEW • Digital Cameras Simplified Block Diagram IN 1 12 OUT GND 2 11 VEEIN GND 3 10 CPVEEOUT VCC 4 9 ISL59831 CP ENABLE 5 8 CN GCP 6 7 VCP LOWPASS FILTER VIDEO IN CLAMP x2 VIDEO OUT CHARGE PUMP Ordering Information PART NUMBER ISL59831IRTZ PART TAPE & MARKING REEL PACKAGE PKG. DWG. # 83IZ - 12 Ld 4x3 TDFN L12.4x3A ISL59831IRTZ-T7 83IZ 7” 12 Ld 4x3 TDFN L12.4x3A NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL59831 Pin Descriptions NUMBER NAME FUNCTION 1 IN 2, 3 GND Ground 4 VCC Positive Power Supply. Bypass to GND with a 0.1µF capacitor. 5 ENABLE 6 GCP Charge Pump Ground 7 VCP Charge Pump Power Supply. Bypass with a 0.1µF capacitor to GCP. 8 CN Charge-Pump Flying Capacitor Negative Terminal. Connect a 56nF capacitor from CP to CN. 9 CP Charge-Pump Flying Capacitor Positive Terminal. Connect a 56nF capacitor from CP to CN. 10 CPVEEOUT 11 VEEIN 12 OUT Video Input. AC-couple (0.1µF) or DC-couple Enable. Connect to VCC to enable device. Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GCP. Negative Supply. Connect an RC filter between VEEIN and CPVEEOUT. See “Block Diagram/Typical Application Circuit” on page 2. Video Output. Can be AC-coupled (220µF) or DC-coupled EP Open or connect to VEEIN Block Diagram/Typical Application Circuit 3.0V TO 3.6V 4.7μF VCC ENABLE LPF IN LEVEL SHIFT 9MHz OUT 75Ω X2 75Ω VEEIN CLAMP + LUMA OR CV VIDEO SOURCE 0.1μF -593mV CPVEEOUT 20Ω 3.0V TO 3.6V RFIL VCP ISL59831 CCP CHARGE PUMP 0.1μF 4.7μF 0.1μF CS CFIL 0.22μF GCP GND GND CP CN 56nF CF 2 FN6266.0 March 29, 2007 ISL59831 Absolute Maximum Ratings (TA = +25°C) Thermal Information VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±50mA Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .350V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 4x3 TDFN Package . . . . . . . . . . . . . . . 41 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications SYMBOL VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20%, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, TA = +27°C, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNIT Supply Range 3.0 3.3 3.6 V Charge Pump Output -1.1 -1.9 -2.4 V DC CHARACTERISTICS VCC, VCP CPVEE ICC Supply Current No load 4 6 8.5 mA ICP Charge Pump Supply Current No load 5 9 20 mA IPD Power Down Current ENABLE = 0.4V 2 5 µA IIN Input Pulldown Current VIN = 0.5V 0.5 2 4.5 µA AV DC Gain 1.9 2 2.06 V/V VIN_MAX Max DC Input Range DC-Coupled Input, guaranteed by output linearity VCLAMPOUT Output Sync Tip Clamp Sync height = 293mV, VIN ≤ 0, AC-coupled input Level VCLAMPIN Input Clamp Level VOS ICLAMP PSRRDC Input floating Output Level Shift Sync height = 293mV, VIN > 0, output shifted relative to input, DC-coupled input Clamp Restore Current Force VIN = -0.3V Power Supply Rejection VCC = +3.0 to +3.6 1.4 V -500 -550 -600 mV 0 40 80 mV -530 -592 -650 mV 2 3.9 mA 35 50 dB AC CHARACTERISTICS APB Passband Flatness f = 100kHz to 5MHz relative to 100kHz 0 ASB Stopband Attenuation f ≥ 27MHz relative to 100kHz 25 dG Differential Gain dP SNR 2 dB 44 dB 5-step modulated staircase 0.4 % Differential Phase 5-step modulated staircase 0.35 ° Signal to Noise Ratio Peak signal (1.4VP-P) to RMS noise, f = 10Hz to 50MHz 59 dB 3 FN6266.0 March 29, 2007 ISL59831 Electrical Specifications SYMBOL tg VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20%, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, TA = +27°C, unless otherwise specified. (Continued) PARAMETER CONDITIONS MIN TYP MAX UNIT DC Group Delay Group delay at 100kHz 56 ns Group Delay Deviation Deviation from 100kHz to 3.58MHz 10 ns HDIST Line Time Distortion 18µs, 100 IRE 0.1 % VDIST Field Time Distortion 130 Lines, 18µs, 100 IRE 0.1 % tCLAMP Clamp Settling Time Back porch to ±1% of final value 50 Lines 32 dB Δtg PSRR Power Supply Rejection VCC + 100mVP-P sine, f = 100kHz to 5MHz LOGIC VIL Logic Low Input Voltage VIH Logic High Input Voltage II Logic Input Current 0.8 2.0 Source V V -10 10 µA CHARGE PUMP fCP Charge Pump Clock Frequency VOUTCP Charge Pump Noise Coupling 4 RFIL = 20Ω, CFIL = 0.22µF, measured at output 15 MHz 10.8 mVP-P FN6266.0 March 29, 2007 ISL59831 Typical Performance Curves VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, unless otherwise noted. 2 10 0 0 -10 CL = 220pF -20 GAIN (dB) GAIN (dB) -2 RL = 500Ω -30 RL = 1000Ω -40 CL = 150pF -4 -6 CL = 10pF -50 RL = 150Ω -60 VOUT = 2VP-P CL = 0pF -70 0.1M -8 RL = 75Ω -10 1M 10M 100M 0.1M 1M FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD 100M FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD 2.0 9.16 VOUT = 2VP-P 1.5 CL = 11pF RL = 150Ω 1.0 9.15 3dB ROLL-OFF (MHz) GAIN (dB) 10M FREQUENCY (Hz) FREQUENCY (Hz) 0.5 0.0 -0.5 -1.0 9.14 9.13 9.12 9.11 -1.5 9.10 -2.0 0.1M 1M 10M 3.0 FREQUENCY (Hz) FIGURE 3. GAIN FLATNESS vs FREQUENCY 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 FIGURE 4. 3dB ROLL-OFF vs SUPPLY VOLTAGE 1.6 0 CL = 220pF RL = 150Ω 1.5 -10 ISOLATION (dB) PEAKING (dB) -20 1.4 1.3 1.2 -30 -40 -50 -60 -70 1.1 -80 1.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) FIGURE 5. PEAKING vs SUPPLY VOLTAGE (CL = 220pF) 5 -90 0.1M 1M 10M FREQUENCY (Hz) 100M FIGURE 6. INPUT TO OUTPUT ISOLATION vs FREQUENCY FN6266.0 March 29, 2007 ISL59831 Typical Performance Curves VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, unless otherwise noted. (Continued) 18 9.4 NO LOAD 9.3 INPUT FLOATING 14 12 3dB POINT (MHz) SUPPLY CURRENT (mA) 16 10 8 6 9.2 9.1 9.0 4 8.9 2 0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 8.8 -40 3.6 -15 10 SUPPLY VOTLAGE (V) 60 85 FIGURE 8. BANDWIDTH vs TEMPERATURE 15.3 50 15.2 45 15.1 40 15.0 35 IMPEDANCE (Ω) SUPPLY CURRENT (mA) FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE 14.9 14.8 14.7 14.6 30 25 20 15 10 14.5 NO LOAD INPUT FLOATING 14.4 5 0 0.01M 14.3 -40 -15 10 35 60 85 0.1M FIGURE 9. SUPPLY CURRENT vs TEMPERATURE 10M 100M FIGURE 10. OUTPUT IMPEDANCE vs FREQUENCY 4000 INPUT VOLTAGE NOISE ( nV Hz ) 0 -10 -20 -30 -40 -50 -60 -70 -80 0.01M 1M FREQUENCY (Hz) TEMPERATURE (°C) PSRR (dB) 35 TEMPERATURE (°C) 0.1M 1M FREQUENCY (Hz) FIGURE 11. PSRR vs FREQUENCY 6 10M 3500 3000 2500 2000 1500 1000 500 0 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 12. INPUT VOLTAGE NOISE vs FREQUENCY FN6266.0 March 29, 2007 ISL59831 Typical Performance Curves VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, unless otherwise noted. (Continued) 0 THD -20 VCC = VCP = +3.3V VOUT = 2VP-P, SINE WAVE RL = 150Ω VCC = VCP = +3.3V RL = 150Ω -10 -20 -30 -30 THD (dBc) HARMONIC DISTORTION (dBc) 0 -10 -40 -50 -40 -50 fIN = 5MHz -60 -60 3RD HD -70 -80 2ND HD -90 0.5M 1.0M 1.5M 2.0M -70 -80 fIN = 500kHz -90 2.5M 3.0M 3.5M 4.0M 4.5M 5.0M 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (VP-P) FREQUENCY (Hz) FIGURE 13. HARMONIC DISTORTION vs FREQUENCY FIGURE 14. THD (dBc) vs OUTPUT VOLTAGE (VP-P) 0.02 0.4 WAVEFORM = MODULATED RAMP 0 IRE to 100 IRE 0.01 0.00 0.3 0.2 -0.02 DP (°) DG (%) -0.01 -0.03 0.1 -0.04 -0.05 WAVEFORM = MODULATED RAMP 0 IRE to 100 IRE -0.06 0.0 -0.07 -0.1 -0.08 0 1 2 3 4 5 6 STEP 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 STEP FIGURE 15. DIFFERENTIAL GAIN TIME SCALE = 20ns/DIV CH1 = 1V/DIV CH2 = 1V/DIV FIGURE 16. DIFFERENTIAL PHASE CH1 = ENABLE SIGNAL ΔTIME = 29.5µs CH1 = DISABLE SIGNAL CH2 = OUTPUT SIGNAL TIME SCALE = 5µs/DIV CH1 = 1V/DIV CH2 = 1V/DIV CH2 = OUTPUT SIGNAL FIGURE 17. DISABLE TIME 7 FIGURE 18. ENABLE TIME (WORST CASE) FN6266.0 March 29, 2007 ISL59831 Typical Performance Curves VCP = VCC = 3.3V, CF = 56nF ±20%, CS = 0.1µF ±20%, RFIL = 20Ω ±1%, CFIL = 0.22µF ±20, CIN = 0.1µF ±20%, RL = 150Ω, CL = 0pF, unless otherwise noted. (Continued) TIME SCALE = 500ns/DIV IN = CH1 = 200mV/DIV OUT = CH2 = 500mV/DIV INPUT TIME SCALE = 100ns/DIV IN = CH1 = 200mV/DIV OUT = CH2 = 500mV/DIV INPUT OUTPUT OUTPUT FIGURE 19. 12.5T RESPONSE FIGURE 20. 2T RESPONSE INPUT TIME SCALE = 10µs/DIV IN = CH1 = 500mV/DIV OUT = CH2 = 1V/DIV OUTPUT MAX OUTPUT MAGNITUDE (VP-P) 3.2 3.1 3.0 2.9 2.8 2.7 2.6 0 fIN = 500kHz AC-COUPLED INPUT 100 200 300 400 500 600 700 800 900 1000 LOAD RESISTANCE (Ω) FIGURE 21. NTSC COLORBAR FIGURE 22. MAXIMUM OUTPUT MAGNITUDE vs LOAD RESISTANCE 100 GROUP DELAY (ns) 80 TIME SCALE = 50ns VERTICAL SCALE = 5mV/DIV 60 40 20 0 -20 0.1M 1M 10M 100M FREQUENCY (Hz) FIGURE 23. GROUP DELAY vs FREQUENCY 8 FIGURE 24. AMPLIFIER OUTPUT NOISE (CHARGE PUMP OSCILLATION) FN6266.0 March 29, 2007 ISL59831 Description of Operation and Application Information Video Performance Theory of Operation For good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150Ω because of the change in output current with changing DC levels. Special circuitry has been incorporated into the ISL59831 for the reduction of output impedance variation with the current output. This results in outstanding differential gain and differential phase specifications of 0.04% and 0.35°, while driving 150Ω at a gain of +2V/V. Driving higher impedance loads would result in similar or better differential gain and differential phase performance. The ISL59831 is a single supply video driver with a reconstruction filter and an on-board charge pump. It is designed to drive SDTV displays with luma (Y) or composite video (CV) signals. The input signal can be AC-coupled or DC-coupled. When AC-coupled, the sync tip clamp sets the blank level to ground at the output. The ISL59831 is capable of driving two AC-coupled or DC-coupled standard video loads and has a 4th order Butterworth reconstruction filter with nominal -3dB frequency set to 9.1MHz, providing 44dB of attenuation at 27MHz. The ISL59831 is designed to operate with a single supply voltage range ranging from 3.0V to 3.6V. This eliminates the need for a split supply with the incorporation of a charge pump capable of generating a bottom rail as much as 1.9V below ground; providing a 5.2V range on a single 3.3V supply. This performance is ideal for NTSC video with negative-going sync pulses. Output Amplifier DIFFERENTIAL GAIN/PHASE NTSC The ISL59831, generating a negative rail internally, is ideally suited for NTSC video with its accompanying negative-going sync signals. Driving Capacitive Loads and Cables The ISL59831 output amplifier provides a gain of +6dB. The output amplifier is able to drive a 2.8VP-P video signal into a 150Ω load to ground. The output is a highly-stable, low distortion, low power, high frequency amplifier capable of driving moderate capacitive loads. Input/Output Range The ISL59831 has a recommended dynamic input range of 0VP-P to 1.4VP-P. This allows the device to handle the maximum possible video signal input. As the input signal moves outside the specified range, the output signal will exhibit increasingly higher levels of harmonic distortion. As the load resistance becomes lower, the current drive capability of the device will be challenged and its ability to drive close to each rail is reduced. The ISL59831, internally-compensated to drive 75Ω cables, will drive 220pF loads in parallel with 150Ω with less than 1.5dB of peaking. AC-Coupled Inputs SYNC TIP CLAMP The ISL59831 features a sync tip clamp that sets the black level of the output video signal to ground. This ensures that the sync-tip voltage level is set to approximately -300mV at the back-termination resistor of a standard video load. The clamp is activated whenever the input voltage falls below 0V. The correction voltage required to do this is stored across the input AC-coupling capacitor. Refer to “Block Diagram/Typical Application Circuit” on page 2 for a detailed diagram. DC-Coupled Inputs The Charge Pump The ISL59831 charge pump provides a bottom rail up to 1.9V below ground while operating on a 3.0V to 3.6V power supply. The charge pump is internally regulated and is driven by an internal 15MHz clock. To reduce the noise on the power supply generated by the charge pump, connect a low pass RC-network between CPVEEOUT and VEEIN. See “Block Diagram/Typical Application Circuit” on page 2 for further information. The CPVEEOUT Pin CPVEEOUT is the output pin for the charge pump. Keep in mind that the output of this pin is generated by the internal charge pump and a fully regulated supply that must be properly bypassed. Bypass this pin with a 0.1µF ceramic capacitor placed as close to the pin and connected to the ground plane of the board. 9 When DC-coupling the inputs ensure that the lowest signal level is greater than +50mV to prevent the clamp from turning on and distorting the output. When DC-coupled the ISL59831 shifts the signal by -550mV from input to output. Amplifier Disable The ISL59831 can be disabled and its output placed in a high impedance state. The turn-off time is around 10ns and the turn-on time is around 30µs. The turn-on time is greater in length because extra time is given for the charge pump to settle before the amplifier is enabled. When disabled, the amplifier's supply current is reduced to 2µA typically, reducing power consumption. The amplifier's power-down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to the GND pin. Applying a signal that is less than 0.8V above FN6266.0 March 29, 2007 ISL59831 GND will disable the amplifier. The amplifier will be enabled when the signal at ENABLE pin is 2V above GND. Output Drive Capability The maximum output current for the ISL59831 is set at ±50mA. Maximum reliability is maintained if the output current never exceeds ±50mA, after which the electromigration limit of the process will be exceeded and the part will be damaged. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the ISL59831, it is possible to exceed the +150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout Strip line design techniques are recommended for the input and output signal traces. As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VCC and VCP to GND will suffice. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire-wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is also very important. (EQ. 1) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature ΘJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing: V OUT i PD MAX = V S × I SMAX + ( V S – V OUT i ) × ----------------RL i (EQ. 2) for sinking: PD MAX = V S × I SMAX + ( V OUT i – V S ) × I LOAD i (EQ. 3) Where: VS = Supply voltage ISMAX = Maximum quiescent supply current VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current i = Number of output channels 10 FN6266.0 March 29, 2007 ISL59831 Thin Dual Flat No-Lead Plastic Package (TDFN) L12.4x3A 12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C) 2X 0.15 C A A D MILLIMETERS 2X 0.15 C B SYMBOL 0.70 A1 - A3 E b 6 INDEX AREA D2 B // A SIDE VIEW C SEATING PLANE 0.10 0.08 A3 7 8 - - 0.05 - 0.23 0.30 5,8 4.00 BSC 3.15 3.30 3.40 7,8 3.00 BSC 1.55 e 1.70 1.80 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 12 2 Nd 6 3 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 2 4. All dimensions are in millimeters. Angles are in degrees. NX k 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. (DATUM A) E2/2 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX L N N-1 NX b e 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 5 (Nd-1)Xe REF. BOTTOM VIEW NX (b) C NOTES 0.80 Rev. 0 1/06 D2/2 1 C MAX 0.75 NOTES: D2 (DATUM B) 8 0.18 E E2 NOMINAL 0.20 REF D TOP VIEW 6 INDEX AREA MIN A 0.10 M C A B CL (A1) L 5 e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6266.0 March 29, 2007