ISL5727 ® Data Sheet May 2004 Dual 10-bit, +3.3V, 260+MSPS, High Speed D/A Converter The ISL5727 is a dual 10-bit, 260+MSPS (Mega Samples Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5G or 3G cellular protocols. • +3.3V Power Supply -40 to 85 48 Ld LQFP PKG. DWG. # CLOCK SPEED Q48.7x7A 260MHz Evaluation Platform 260MHz • Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA QD1 NC QD0 (LSB) • Wireless Communication Systems NC NC NC ID9 (MSB) ID6 ID7 ID8 ID5 ID4 • Medical/Test Instrumentation and Equipment ID3 1 48 47 46 45 44 43 42 41 40 39 38 37 36 QD2 ID2 2 35 QD3 ID1 (LSB) ID0 3 34 QD4 4 33 NC 5 32 NC 6 7 31 QD5 QD6 QD7 30 QD8 NC 8 29 SLEEP DVDD 9 28 QD9 (MSB) CLK 10 27 DGND 11 12 26 AGND AVDD NC QOUTB QOUTA AGND FSADJ REFIO 1 REFLO IOUTA IOUTB NC 25 13 14 15 16 17 18 19 20 21 22 23 24 AVDD ICOMP Applications • Quadrature Transmit with IF Range 0–80MHz ISL5727 (LQFP) TOP VIEW AGND • Dual, 3.3V, Lower Power Replacement for AD9763 • BWA Infrastructure Pinout NC • Excellent Spurious Free Dynamic Range (70dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz) • EDGE/GSM SFDR = 83dBc at 11MHz in 20MHz Window PACKAGE 25 • 3V LVCMOS Compatible Inputs • UMTS Adjacent Channel Power = 65dB at 19.2MHz TEMP. RANGE (°C) ISL5727EVAL1 • Low Power . . . . . 233mW with 20mA Output at 130MSPS • Guaranteed Gain Matching < 0.14dB Ordering Information ISL5727IN Features • Adjustable Full Scale Output Current . . . . . 2mA to 20mA This device complements the ISL5x57 and ISL5x27 families of high speed converters, which include 8-, 10-, 12-, and 14-bit devices. PART NUMBER FN6082 QCOMP ISL5727 ID4 ID5 ID6 ID7 ID8 ID9 (MSB) NC NC NC NC QD0 (LSB) QD1 Typical Applications Circuit SLEEP DVPP C1 0.1µF ICOMP C2 0.1µF AVPP 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 30 7 29 8 CLK 28 9 DGND 27 10 DVDD AGND 26 11 AGND 25 12 13 14 15 16 17 18 19 20 21 22 23 24 REFIO REFLO AGND FSADJ ID3 ID2 ID1 (LSB) ID0 NC NC NC NC AVDD AVDD C4 0.1µF QD2 QD3 QD4 QD5 QD6 QD7 QD8 QD9 (MSB) R1 50Ω QCOMP C3 0.1µF AVPP C5 0.1µF C6 0.1µF RSET 1.91kΩ 50Ω 50Ω R3 R2 1:1 TRANSFORMER REPRESENTS ANY 50Ω LOAD (50Ω) (50Ω) QOUT IOUT BEAD FERRITE + C11 10µF L1 10µH DVPP (DIGITAL POWER PLANE) = +3.3V C9 0.1µF C10 1µF C12 0.1µF C13 1µF +3.3V POWER SOURCE FERRITE BEAD + C14 10µF 2 L2 10µH AVPP (ANALOG POWER PLANE) = +3.3V ISL5727 Functional Block Diagram NC QOUTA NC QOUTB NC NC (LSB) QD0 INPUT LATCH CASCODE QD1 36 QD2 SWITCH MATRIX 36 CURRENT SOURCE QD3 QD4 5 LSBs QD5 QD6 QD7 QD8 + 31 MSB SEGMENTS UPPER 5-BIT DECODER (MSB) QD9 QCOMP SLEEP INT/EXT VOLTAGE CLK BIAS GENERATION REFERENCE FSADJ REFIO REFLO ICOMP NC NC IOUTA NC NC (LSB) ID0 IOUTB INPUT LATCH CASCODE ID1 36 ID2 SWITCH MATRIX 36 CURRENT SOURCE ID3 ID4 5 LSBs ID5 ID6 ID7 ID8 (MSB) ID9 3 UPPER 5-BIT DECODER + 31 MSB SEGMENTS ISL5727 Pin Descriptions PIN NO. PIN NAME PIN DESCRIPTION 11, 19, 26 AGND Analog ground. 13, 24 AVDD Analog supply (+2.7V to +3.6V). 28 CLK Clock input. 27 DGND Connect to digital ground. 10 DVDD Digital supply (+2.7V to +3.6V). 20 FSADJ Full scale current adjust. Use a resistor to ground to adjust full scale output current. Full scale output current = 32 x VFSADJ/RSET. 14, 23 NC 12, 25 ICOMP, QCOMP 1-4, 29-38, 43-48 ID9-ID0, QD9-QD0 15, 22 IOUTA, QOUTA Current outputs of the device. Full scale output current is achieved when all input bits are set to binary 1. 16, 21 IOUTB, QOUTB Complementary current outputs of the device. Full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. 17 REFIO Reference voltage input if Internal reference is disabled. The internal reference is not intended to drive an external load. Use 0.1µF cap to ground when internal reference is enabled. 18 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 5-8, 39-42 NC No connect (NC). Not internally connected. No termination required, may be used for device migration to higher resolution DACs. 9 SLEEP Not internally connected. Recommend no connect. Compensation pin for internal bias generation. Each pin should be individually decoupled to AGND with a 0.1µF capacitor. Digital data input ports. Bit 9 is most significant bit (MSB) and bit 0 is the least significant bit (LSB). Connect to digital ground or leave floating for normal operation. Connect to DVDD for sleep mode. 4 ISL5727 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +3.6V Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +3.6V Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DVDD + 0.3V Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Resistance (Typical, Note 1) θJA(°C/W) LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values TA = -40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 10 - - Bits -0.5 ±0.1 +0.5 LSB -0.5 ±0.1 SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL “Best Fit” Straight Line (Note 8) Differential Linearity Error, DNL (Note 8) Offset Error, IOS IOUTA (Note 8) Offset Drift Coefficient (Note 8) - Full Scale Gain Error, FSE With External Reference (Notes 2, 8) Full Scale Gain Drift Crosstalk Gain Matching Between Channels (DC Measurement) +0.5 LSB +0.006 % FSR 0.1 - ppm FSR/°C -3 ±0.5 +3 % FSR With Internal Reference (Notes 2, 8) -3 ±0.5 +3 % FSR With External Reference (Note 8) - ±50 - ppm FSR/°C With Internal Reference (Note 8) - ±100 - ppm FSR/°C fCLK = 100MSPS, fOUT = 10MHz - 83 - dB fCLK = 100MSPS, fOUT = 40MHz - 74 - dB fCLK = 260MSPS, fOUT = 40.4MHz - 73 - dB As a percentage of Full Scale Range -1.6 0.6 +1.6 % FSR In dB Full Scale Range -0.14 0.05 +0.14 dB FSR 2 20 22 mA (Note 3) -1.0 - 1.25 V 260 300 - MHz Full Scale Output Current, IFS Output Voltage Compliance Range -0.006 DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Output Rise Time Full Scale Step - 1 - ns Output Fall Time Full Scale Step - 1 - ns - 5 - pF IOUTFS = 20mA - 50 - pA/√Hz IOUTFS = 2mA - 30 - pA/√Hz Output Capacitance Output Noise 5 ISL5727 Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued) TA = -40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50Ω and RLOAD = 50Ω, Full Scale Output = -2.5dBm) Spurious Free Dynamic Range, SFDR Within a Window fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 8) - 71 - dBc fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 8) - 75 - dBc fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 8) - 77 - dBc Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) fCLK = 260MSPS, fOUT = 80.8MHz (Notes 4, 8) - 52 - dBc fCLK = 260MSPS, fOUT = 40.4MHz (Notes 4, 8) - 62 - dBc fCLK = 260MSPS, fOUT = 20.2MHz (Notes 4, 8) - 64 - dBc fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 8) - 52 - dBc fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 8, 10) - 62 - dBc fCLK = 200MSPS, fOUT = 20.2MHz, T = 25°C (Notes 4, 8) 58 64 - dBc fCLK = 200MSPS, fOUT = 20.2MHz, T = -40°C to 85°C (Notes 4, 8) 56 - - dBc fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 8) - 55 - dBc fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) - 60 - dBc fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 8) - 68 - dBc 65 70 - dBc fCLK = 130MSPS, fOUT = 5.05MHz, (Notes 4, 8) - 75 - dBc fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) - 58 - dBc fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 8) - 61 - dBc fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 8) - 68 - dBc fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 8, 10) - 70 - dBc fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 8) - 74 - dBc fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) - 64 - dBc fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 8) - 72 - dBc fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 8) - 75 - dBc fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing, 50MHz Span (Notes 4, 8, 10) - 63 - dBc fCLK = 130MSPS, fOUT = 17.5MHz to 27.9MHz, 1.3MHz Spacing, 35MHz Span (Notes 4, 8) - 64 - dBc fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing, 15MHz Span (Notes 4, 8) - 70 - dBc fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing, 10MHz Span (Notes 4, 8) - 71 - dBc Spurious Free Dynamic Range, fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW = 30kHz SFDR in a Window with EDGE or GSM (Notes 4, 8, 10) - 83 - dBc fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW = 30kHz (Notes 4, 8, 10) - 65 - dB 1.2 1.23 1.3 V - ±40 - ppm/°C - 0 - µA Reference Input Impedance - 1 - MΩ Reference Input Multiplying Bandwidth (Note 8) - 1.0 - MHz fCLK = 130MSPS, fOUT = 10.1MHz, T = -40°C to 85°C (Notes 4, 8) Spurious Free Dynamic Range, SFDR in a Window with Eight Tones Adjacent Channel Power Ratio, ACPR with UMTS VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Pin 20 Voltage with Internal Reference Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability 6 Reference is not intended to drive an external load ISL5727 Electrical Specifications AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued) TA = -40°C TO 85°C PARAMETER DIGITAL INPUTS TEST CONDITIONS MIN TYP MAX UNITS D9-D0, CLK Input Logic High Voltage with 3.3V Supply, VIH (Note 3) 2.3 3.3 - V Input Logic Low Voltage with 3.3V Supply, VIL (Note 3) - 0 1.0 V Sleep Input Current, IIH -25 - +25 µA Input Logic Current, IIH, IL -20 - +20 µA Clock Input Current, IIH, IL -10 - +10 µA - 3 - pF Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 15 - 1.5 - ns Data Hold Time, tHLD See Figure 15 - 1.5 - ns Propagation Delay Time, tPD See Figure 15 - 1 - Clock Period CLK Pulse Width, tPW1 , tPW2 See Figure 15 (Note 3) 2 - - ns POWER SUPPLY CHARACTERISTICS AVDD Power Supply (Note 9) 2.7 3.3 3.6 V DVDD Power Supply (Note 9) 2.7 3.3 3.6 V Analog Supply Current (IAVDD) 3.3V, IOUTFS = 20mA - 60 62 mA 3.3V, IOUTFS = 2mA - 24 - mA 3.3V (Note 5) - 11 15 mA 3.3V (Note 6) - 17 21 mA Supply Current (IAVDD) Sleep Mode 3.3V, IOUTFS = Don’t Care - 5 - mA Power Dissipation 3.3V, IOUTFS = 20mA (Note 5) - 233 255 mW 3.3V, IOUTFS = 20mA (Note 6) - 253 274 mW 3.3V, IOUTFS = 20mA (Note 7) - 275 - mW - 115 - mW -0.125 - +0.125 %FSR/V Digital Supply Current (IDVDD) 3.3V, IOUTFS = 2mA (Note 5) Power Supply Rejection Single Supply (Note 8) NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 5. Measured with the clock at 130MSPS and the output frequency at 10MHz. 6. Measured with the clock at 200MSPS and the output frequency at 20MHz. 7. Measured with the clock at 260MSPS and the output frequency at 40.4MHz. 8. See Definition of Specifications. 9. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in analog output current may be necessary to maintain spectral performance. 10. See Typical Performance plots. 7 ISL5727 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100Ω and RLOAD = 50Ω) SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK (83+dBc @ ∆f = +6MHz) FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (75dBc -NYQUIST, 6dB PAD) SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK (86+dBc @ ∆f = +6MHz, 3dB PAD) FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK (78dBc - NYQUIST, 9dB PAD) FIGURE 5. FOUR EDGE CARRIERS AT 12.4–15.6MHz, 800kHz SPACING, 78MSPS (67dBc - 20MHz WINDOW) FIGURE 6. FOUR GSM CARRIERS AT 12.4–15.6MHz, 78MSPS (71dBc - 20MHz WINDOW, 6dB PAD) 8 ISL5727 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100Ω and RLOAD = 50Ω) (Continued) SPECTRAL MASK UMTS TDD P>43dBm BTS FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (65dB 1st ACPR, 64dB 2nd ACPR) FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK (61dBc - NYQUIST, 6dB PAD) FIGURE 11. TWO TONES (CF = 6) AT 8.5MHz, 50MSPS CLOCK, 500kHz SPACING (80dBc - 10MHz WINDOW, 6dB PAD) 9 FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK (71dBc - NYQUIST, 6dB PAD) FIGURE 10. EIGHT TONES (CREST FACTOR = 8.9) AT 37MHz, 210MSPS CLOCK, 2.1MHz SPACING (64dBc - NYQUIST) FIGURE 12. FOUR TONES (CF = 8.1) AT 14MHz, 80MSPS CLOCK, 800kHz SPACING (70dBc - NYQUIST, 6dB PAD) ISL5727 Definition of Specifications Adjacent Channel Power Ratio, ACPR, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. Crosstalk, is the measure of the channel isolation from one DAC to the other. It is measured by generating a sinewave in one DAC while the other DAC is clocked with a static input, and comparing the output power of each DAC at the frequency generated. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be one LSB. A DNL specification of one LSB or less guarantees monotonicity. EDGE, Enhanced Data for Global Evolution, a TDMA standard for cellular applications which uses 200kHz BW, 8-PSK modulated carriers. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per °C. through a known resistance. Offset error is defined as the maximum deviation of the IOUTA output current from a value of 0mA. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The nominal supply voltage is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). UMTS, Universal Mobile Telecommunications System, a W-CDMA standard for cellular applications which uses 3.84MHz modulated carriers. Gain Matching, is a measure of the full scale amplitude match between the I and Q channels given the same input pattern. It is typically measured with all 1s at the input to both channels, and the full scale output voltage developed into matching loads is compared for the I and Q outputs. Detailed Description GSM, Global System for Mobile Communication, a TDMA standard for cellular applications which uses 200kHz BW, GMSK modulated carriers. Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per °C. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage at IOUTA through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree °C. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of IOUTA 10 The ISL5727 is a dual 10-bit, current out, CMOS, digital to analog converter. The maximum update rate is at least 260+MSPS and can be powered by a single power supply in the recommended range of +3.0V to +3.6V. It consumes less than 125mW of power per channel when using a +3.3V supply, the maximum 20mA of output current, and the data switching at 210MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at these major transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy. Digital Inputs and Termination The ISL5727 digital inputs are formatted as offset binary and guaranteed to 3V LVCMOS levels. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50Ω ISL5727 lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. For pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50-200Ω) prior to the DAC’s inputs in order to reduce the amount of noise. Power Supply Separate digital and analog power supplies are recommended. The allowable supply range is +2.7V to +3.6V. The recommended supply range is +3.0 to 3.6V (nominally +3.3V) to maintain optimum SFDR. However, operation down to +2.7V is possible with some degradation in SFDR. Reducing the analog output current can help the SFDR at +2.7V. The SFDR values stated in the table of specifications were obtained with a +3.3V supply. Ground Planes Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of +1.23V with a ±40ppm/°C drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin selects the reference. The internal reference can be selected if REFLO is tied low (ground). If an external reference is desired, then REFLO should be tied high (the analog supply voltage) and the external reference driven into REFIO. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 22mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V. If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. 11 If the full scale output current is set to 20mA by using the internal voltage reference (1.23V) and a 1.91kΩ RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL REFERENCE (1.23V TYP) AND RSET = 1.91kΩ INPUT CODE (D9-D0) IOUTA (mA) IOUTB (mA) 11 1111 1111 20.6 0 10 0000 0000 10.3 10.3 00 0000 0000 0 20.6 Analog Output IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -1.0V to 1.25V. ROUT (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X ROUT. The most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. The maximum recommended output current is 20mA. Differential Output IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection. With RDIFF = 50Ω and RLOAD = 50Ω, the circuit in Figure 13 will provide a 500mV (-2.5dBm) signal at the output of the transformer if the full scale output current of the DAC is set to 20mA (used for the electrical specifications table). Values of RDIFF = 100Ω and RLOAD = 50Ω were used for the typical performance curves to increase the output power and the dynamic range. The center tap in Figure 13 must be grounded. In the circuit in Figure 14, the user is left with the option to ground or float the center tap. The DC voltage that will exist at either IOUTA or IOUTB if the center tap is floating is IOUTDC x (RA//RB) V because RDIFF is DC shorted by the transformer. If the center tap is grounded, the DC voltage is 0V. Recommended values for the circuit in Figure 14 are RA = RB = 50Ω, RDIFF = 100Ω, assuming RLOAD = 50Ω. The performance of Figure 13 and Figure 14 is basically the same, however leaving the center tap of Figure 14 floating allows the circuit to find a more balanced virtual ground, ISL5727 theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations. REQ = 0.5 x (RLOAD//RDIFF//RA), WHERE RA = RB AT EACH OUTPUT RA OUTA REQ = 0.5 x (RLOAD//RDIFF) AT EACH OUTPUT RDIFF VOUT = (2 x OUTA x REQ)V 1:1 OUTA RDIFF ISL5727 VOUT = (2 x OUTA x REQ)V OUTB ISL5727 RLOAD RLOAD RB RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER OUTB FIGURE 14. ALTERNATIVE OUTPUT LOADING Propagation Delay RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus <2ns of processing. See Figure 15. FIGURE 13. OUTPUT LOADING FOR DATASHEET MEASUREMENTS Test Service Intersil offers customer-specific testing of converters with a service called Testdrive. To submit a request, fill out the Testdrive form at www.intersil.com/testdrive. Or, send a request to the technical support center. Timing Diagram tPW2 tPW1 50% CLK tSU tSU tHLD D9-D0 W0 tSU tHLD tHLD W1 tPD W2 W3 tPD OUTPUT = W0 IOUT OUTPUT = W-1 OUTPUT = W1 FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 12 ISL5727 Thin Plastic Quad Flatpack Packages (LQFP) D Q48.7x7A (JEDEC MS-026BBC ISSUE B) 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES SYMBOL -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.08 0.003 -C- MIN MAX MILLIMETERS MIN MAX NOTES A - 0.062 - 1.60 - A1 0.002 0.005 0.05 0.15 - A2 0.054 0.057 1.35 1.45 - b 0.007 0.010 0.17 0.27 6 b1 0.007 0.009 0.17 0.23 - D 0.350 0.358 8.90 9.10 3 D1 0.272 0.280 6.90 7.10 4, 5 E 0.350 0.358 8.90 9.10 3 E1 0.272 0.280 6.90 7.10 4, 5 L 0.018 0.029 0.45 0.75 - N 48 48 7 e 0.020 BSC 0.50 BSC Rev. 2 1/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 0.08 0.003 M C A-B S 11o-13o 0.020 0.008 MIN b 4. Dimensions D1 and E1 to be determined at datum plane -H- . 0.09/0.16 A2 A1 0.004/0.006 GAGE PLANE BASE METAL WITH PLATING L 0o-7o 3. Dimensions D and E to be determined at seating plane -C- . b1 0o MIN 0.25 0.010 D S 11o-13o 0.09/0.20 0.004/0.008 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. “N” is the number of terminal positions. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13