iCE40 Hardware Checklist January 2015 Technical Note TN1252 Introduction When designing complex hardware using the iCE40™ device family (iCE40 LP/HX, iCE40LM, iCE40 Ultra™, iCE40 UltraLite™), designers must pay special attention to critical hardware configuration requirements. This technical note steps through these critical hardware requirements related to the iCE40 device. This document does not provide detailed step-by-step instructions but gives a high-level summary checklist to assist in the design process. The iCE40 ultra-low power, non-volatile devices are available in four versions – LP series for low power applications, HX series for high performance applications, LM and Ultra/UltraLite series for ultra-low power for mobile applications. This technical note assumes that the reader is familiar with the iCE40 device features as described in DS1040, iCE40LP/HX Family Data Sheet, DS1045, iCE40LM Family Data Sheet, DS1048, iCE40 Ultra Family Data Sheet and DS1050, iCE40 UltraLite Family Data Sheet. The critical hardware areas covered in this technical note include: • Power supplies as they relate to the supply rails and how to connect them to the PCB and the associated system • Configuration and how to connect the configuration mode selection • Device I/O interface and critical signals Power Supply The VCC (core supply voltage) VCCIO_2, SPI_VCC and VPP_2V5 determine the iCE40 device’s stable condition. These supplies need to be at a valid and stable level before the device can become operational. Refer to the family data sheets for voltage requirements. Table 1. Power Supply Description and Voltage Levels Supply3, 4 Voltage (Nominal Value) Description VCC 1.20 V Core supply voltage VCCIO_X 1.5 V to 3.3 V Power supply for I/O banks VPP_2V5 2.5 V NVCM programming and operating supply voltage VPP_FAST Leave unconnected Optional fast NVCM programming supply SPI_VCC 1.8 V to 3.3 V SPI interface supply voltage VCCPLL1, 2 1.2 V Analog voltage supply to Phase Locked Loop (PLL) 1. 2. 3. 4. VCCPLL must be tied to VCC when PLL is not used. External power supply filter required for VCCPLL and GNDPLL. iCE40LM family devices do not have VPP_2V5 and VPP_FAST supplies. iCE40 Ultra/iCE40 UltraLite family devices do not have VPP_FAST. Analog Power Supply Filter for PLL The iCE40 sysCLOCK™ PLL contains analog blocks, so the PLL requires a separate power and ground that is quiet and stable to reduce the output clock jitter of the PLL on device with external VCCPLL supply pins (PLL is not offered in some device/package combinations without the VCCPLL ball. Please refer to the data sheet and the device family Pin List to check the availability of VCCPLL ball.) The sysCLOCK PLL has the DC ground connection made on the FPGA, so the external PLL ground connection (GNDPLL) must NOT be connected to the board’s ground. Figure 1 also includes sample values for the components that make up the PLL power supply filter. © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 TN1252_1.5 iCE40 Hardware Checklist Figure 1. Isolating PLL Supplies RS VCCPLL 100W 10µF 100nF iCE40 FPGA CLF CHF GNDPLL1 1. Note that GNDPLL should not be connected to the board’s ground. Configuration Considerations The iCE40 LP/HX/Ultra/UltraLite devices contain two types of memory, CRAM (Configuration RAM) and NVCM (Non-volatile Configuration Memory). The iCE40LM device contains only the CRAM. CRAM memory contains the active configuration. The NVCM provides on-chip storage of configuration data. It is one-time programmable and is recommended for mass-production. For more information, refer to TN1248, iCE40 Programming and Configuration. The configuration and programming of the iCE40 LP/HX/LM/Ultra/UltraLite devices from external memory is using the SPI port, both in Master and Slave modes. In Master SPI mode, the device configures its CRAM from an external SPI Flash connected to it. In Slave mode, the device can be configured or programmed using the Lattice Diamond® Programmer or embedded processor. On the iCE40LP/HX and iCE40 Ultra/UltraLite family devices, the SPI_SS_B determines if the iCE40 CRAM is configured from an external SPI (SPI_SS_B=0) or from the NVCM (SPI_SS_B=1). This pin is sampled after Power-onReset (POR) is released or CRESET_B is held low or toggled (High-Low-High). Table 2. Configuration Pins Pin Name Function CRESET_B Configuration Reset input, active low. Input CDONE Configuration Done output from iCE40. Output SPI_VCC SPI interface supply voltage. Supply SPI_SI SPI serial input to the iCE40, in both Master and Slave modes. SPI_SO SPI serial output from the iCE40, in both Master and Slave modes. SPI_SCK SPI_SS_B External Termination Direction 10 KOhm pull-up to VCCIO_2. Notes A low on CRESET_B delay’s configuration. Pull-up to VCCIO_2. The maximum Rpullup value is calculated as follows: Rpullup=1/(2*ConfigFrequency*CDONETraceCap) Input Released to user I/O after configuration. Output Released to user I/O after configuration. SPI clock Direction based on Master or Slave modes. Input/Output 10 KOhm pull-up to VCC_SPI recommended. Released to user I/O after configuration. Chip select Input (Slave 10 KOhm pull-up to VCC_SPI in Master mode)/ mode and a 10 KOhm pull-down in Slave Output (Masmode. ter mode) 2 Refer to TN1248, iCE40 Programming and Configuration, for more details. iCE40 Hardware Checklist SPI Flash Requirement in Master SPI Mode Users are free to select any industry standard SPI Flash. The SPI Flash must support the 0x0B Fast Read command, using a 24-bit start address with eight dummy bits before the PROM provides first data. Refer to TN1248, iCE40 Programming and Configuration, for additional information. LVDS Pin Assignments (For iCE40LP/HX Devices Only) The differential inputs are supported only by Bank 3; however, differential outputs are supported in all banks. Checklist Table 3. iCE40 Hardware Checklist iCE40 Hardware Checklist Item 1 1.1 Power Supply Core supply VCC at 1.2 V 1.2 I/O power supply VCCIO 0-3 at 1.5 V to 3.3 V 1.3 SPI_VCC at 1.8 V to 3.3 V 1.4 VCCPLL pulled to VCC even if PLL not used 1.5 Power supply filter for VCCPLL and GNDPLL 1.6 2 GNDPLL must NOT be connected to the board Power-on-Reset (POR) inputs 2.1 VCC 2.2 SPI_VCC 2.3 VCCIO_0-3 2.4 VPP_2V5 3 Configuration VPP_FAST 3.1 Configuration mode based on SPI_SS_B 3.2 Pull-up on CRESET_B,CDONE pin 3.3 4 4.1 TRST_B is kept low for normal operation I/O pin assignment LVDS pin assignment considerations 3 OK N/A iCE40 Hardware Checklist Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version January 2015 1.5 Added support for iCE40 UltraLite. Change Summary June 2014 1.4 Added support for iCE40 Ultra. Updated Analog Power Supply Filter for PLL section. Updated Table 2, Configuration Pins. Changed VCCIO_2 to VCC_SPI in SPI_SCK and SPI_SS_B. October 2013 01.3 Updated the Configuration Pins table. Updated Technical Support Assistance information. December 2012 01.2 Power Supply Description and Voltage Levels table – corrected VCC nominal voltage. September 2012 01.1 LVDS Pin Assignments text section – corrected description of differential input and output support. 01.0 Initial release. 4