HI-301 thru HI-307 TM Data Sheet March 2000 File Number 3125.4 CMOS Analog Switches Features The HI-301 thru HI-307 series of switches are monolithic devices fabricated using CMOS technology and the Intersil dielectric isolation process. These switches feature break before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation, (a few mW for the Hl-301 and HI-303, a few hundred mW for the HI-307). • Analog Signal Range (±15V Supplies) . . . . . . . . . . ±15V The HI-301 and HI-303 are TTL compatible and have a logic “0” condition with an input less than 0.8V and a logic “1” condition with an input greater than 4V. The HI-307 switches are CMOS compatible and have a low state with an input less than 3.5V and a high state with an input greater than 11V. (See pinouts for switch conditions with a logic “1” input.) TEMP. RANGE (oC) • Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA • Low On Resistance at 25oC . . . . . . . . . . . . . . . . . . . 35Ω • Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns • Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC • TTL, CMOS Compatible • Symmetrical Switch Elements • Low Operating Power (Typ for Hl-301 and HI-303) . . 1.0mW Applications Ordering Information PART NUMBER • Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA • Sample and Hold (i.e., Low Leakage Switching) PACKAGE PKG. NO. • Op Amp Gain Switching (i.e., Low On Resistance) 14 Ld SOIC M14.15 • Portable, Battery Operated Circuits -55 to 125 14 Ld CERDIP F14.3 • Low Level Switching Circuits HI1-0303-5 0 to 75 14 Ld CERDIP F14.3 • Dual or Single Supply Systems HI9P0303-5 0 to 75 14 Ld SOIC M14.15 Functional Diagram HI9P0303-9 -40 to 85 14 Ld SOIC M14.15 HI1-0307-5 0 to 75 14 Ld CERDIP F14.3 HI9P0301-5 0 to 75 HI1-0303-2 S IN N P D Pinouts Switch States Shown For A Logic “1” Input SPST HI-301 (SOIC) TOP VIEW DUAL SPDT HI-303 (CERDIP, SOIC) HI-307 (CERDIP) TOP VIEW NC 1 14 V+ NC 1 14 V+ D1 2 13 D2 S3 2 13 S4 NC 3 12 NC D3 3 12 D4 S1 4 11 S2 D1 4 11 D2 NC 5 10 NC S1 5 10 S2 IN 6 9 NC IN1 6 8 V- GND 7 9 IN2 8 V- GND 7 LOGIC SW1 SW2 LOGIC SW1, SW2 SW3, SW4 0 OFF ON 0 OFF ON 1 ON OFF 1 ON OFF 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI-301 thru HI-307 Schematic Diagrams SWITCH CELL A V+ MN1B MN2B MN3B MP5B MP4B IN OUT MN4B MN6B MP3B MP2B MP1B V- A DIGITAL INPUT BUFFER AND LEVEL SHIFTER V+ D2A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A 200Ω A A LOGIC IN D1A MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) 2 HI-301 thru HI-307 Absolute Maximum Ratings Thermal Information Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . .44V (±22V) Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 95 40 SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HI-3XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-3XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-3XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. HI-301 and HI-303: VIN - for Logic “1” = 4V, for Logic “0” = 0.8V. HI-307: VIN - for Logic “1” = 11V, for Logic “0” = 3.5V, Unless Otherwise Specified -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Switch ON Time, tON (Note 13) 25 - 210 300 - 210 300 ns Switch OFF Time, tOFF (Note 13) 25 - 160 250 - 160 250 ns Switch ON Time, tON (Note 14) 25 - 160 250 - 160 250 ns Switch OFF Time, tOFF (Note 14) 25 - 100 150 - 100 150 ns Break-Before-Make Delay, tOPEN 25 - 60 - - 60 - ns Charge Injection Voltage, ∆V (Note 7) 25 - 3 - - 3 - mV OFF Isolation (Note 6) 25 - 60 - - 60 - dB Input Switch Capacitance, CS(OFF) 25 - 16 - - 16 - pF Output Switch Capacitance, CD(OFF) 25 - 14 - - 14 - pF Output Switch Capacitance, CD(ON) 25 - 35 - - 35 - pF Digital Input Capacitance, CIN 25 - 5 - - 5 - pF Input Low Level, VINL (Note 13) Full - - 0.8 - - 0.8 V Input High Level, VINH (Note 13) Full 4 - - 4 - - V Input Low Level, VINL (Note 14) Full - - 3.5 - - 3.5 V Input High Level, VINH (Note 14) Full 11 - - 11 - - V Input Leakage Current (Low), IINL (Note 5) Full - - 1 - - 1 µA Input Leakage Current (High), IINH (Note 5) Full - - 1 - - 1 µA Analog Signal Range Full -15 - +15 -15 - +15 V ON Resistance, rON (Note 2) 25 - 35 50 - 35 50 Ω Full - 40 75 - 40 75 Ω 25 - 0.04 1 - 0.04 5 nA Full - 1 100 - 0.2 100 nA PARAMETER DYNAMIC CHARACTERISTICS DIGITAL INPUT CHARACTERISTICS ANALOG SWITCH CHARACTERISTICS OFF Input Leakage Current, IS(OFF) (Note 3) 3 HI-301 thru HI-307 Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. HI-301 and HI-303: VIN - for Logic “1” = 4V, for Logic “0” = 0.8V. HI-307: VIN - for Logic “1” = 11V, for Logic “0” = 3.5V, Unless Otherwise Specified (Continued) PARAMETER OFF Output Leakage Current, ID(OFF) (Note 3) ON Leakage Current, ID(ON) (Note 4) -2 -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.04 1 - 0.04 5 nA Full - 1 100 - 0.2 100 nA 25 - 0.03 1 - 0.03 5 nA Full - 0.5 100 - 0.2 100 nA 25 - 0.09 0.5 - 0.09 0.5 mA Full - - 1 - - 1 mA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA 25 - 0.01 10 - 0.01 100 µA Full - - 100 - - - µA POWER SUPPLY CHARACTERISTICS Current, I+ (Notes 8, 13) Current, I- (Notes 8, 13) Current, I+ (Notes 9, 13) Current, I- (Notes 9, 13) Current, I+ (Notes 10, 14) Current, I- (Notes 10, 14) Current, I+ (Notes 11, 14) Current, I- (Notes 11, 14) NOTES: 2. VS = ±10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions. 3. VS = ±14V, VD = 14V. 4. VS = VD = ±14V. 5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K. 7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse (HI-301 - 303), 15V pulse (HI-307). Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x ∆V. 8. VIN = 4V (one input, all other inputs = 0V). 9. VIN = 0.8V (all inputs). 10. VIN = 15V (all inputs). 11. VIN = 0V (all inputs). 12. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended. 13. HI-301 thru HI-303 only. 14. HI-307 only. 4 HI-301 thru HI-307 Test Circuits and Waveforms V+ 15V S VO D VS = +3V RL 300Ω LOGIC “1” = SWITCH ON SWITCH OUTPUT CL 33pF LOGIC INPUT 0V LOGIC INPUT VINH 50% 50% VS V-15V GND 90% SWITCH TYPE VINH HI-301 and HI-303 4V HI-307 15V 0V SWITCH OUTPUT FIGURE 1A. TEST CIRCUIT 10% tOFF tON FIGURE 1B. MEASUREMENT POINTS +15V V+ RGEN = 0 S VGEN D RL 10kΩ IN CL 10pF LOGIC INPUT (V) FIGURE 1. SWITCH tON AND tOFF 6 HI-301 AND HI-303 4 2 0 LOGIC INPUT VGND VLOGIC -15V 0 15 HI-307 10 5 0 LOGIC INPUT 0 0.4 0.8 TIME (µs) 1.2 FIGURE 2C. CMOS LOGIC INPUT 5 0.8 TIME (µs) 1.2 1.6 FIGURE 2B. TTL LOGIC INPUT OUTPUT VOLTAGE (V) LOGIC INPUT (V) FIGURE 2A. TEST CIRCUIT 0.4 1.6 10 (NOTE 16) 5 VGEN = 10V 0 0 0.4 0.8 1.2 TIME (µs) FIGURE 2D. VANALOG = 10V 1.6 HI-301 thru HI-307 (Continued) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Test Circuits and Waveforms 5 0 VGEN = 5V 0 0.4 0.8 TIME (µs) 1.2 5 0 VGEN = 0V -5 1.6 0 0 -5 VGEN = -5V 0 0.4 0.8 0.8 TIME (µs) 1.2 1.6 FIGURE 2F. VANALOG = 0V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) FIGURE 2E. VANALOG = 5V 0.4 1.2 0 -5 -10 VGEN = -10V 0 1.6 0.4 TIME (µs) 0.8 1.2 1.6 TIME (µs) FIGURE 2G. VANALOG = -5V FIGURE 2H. VANALOG = -10V NOTE: 15. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES 15V S1 VS1 = +3V VS2 = +3V V+ D1 OUT 1 D2 S2 OUT 2 RL2 CL2 RL1 CL1 LOGIC INPUT LOGIC “1” = SWITCH ON VINH RL1 = RL2 = 300Ω CL1 = CL2 = 33pF 0V LOGIC INPUT GND V-15V 50% SWITCH TYPE VINH HI-301, HI-303 5V HI-307 15V FIGURE 3A. TEST CIRCUIT OUT 1 50% 0V tOPEN FIGURE 3B. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN) 6 50% 0V SWITCH OUTPUTS OUT 2 50% tOPEN HI-301 thru HI-307 Typical Performance Curves 80 DRAIN TO SOURCE ON RESISTANCE (Ω) DRAIN TO SOURCE ON RESISTANCE (Ω) 80 V+ = +15V, V- = -15V 60 125oC 25oC -55oC 40 20 0 -15 -10 -5 0 5 10 TA = 25oC 60 C B 40 A 20 A B C D 0 -15 15 D V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 FIGURE 4. rDS(ON) vs VD 10 15 FIGURE 5. rDS(ON) vs VD 100 100 V+ = +15V, V- = -15V CLOAD = 30pF, VS = 1VRMS V+ = +15V, V- = -15V TA = 25oC, VS = 15V, RL = 2K 80 OFF ISOLATION (dB) POWER DISSIPATION (mW) 5 DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) 10 HI-301 AND HI-303 1.0 RL = 100Ω 60 RL = 1kΩ 40 20 HI-307 0 105 0.1 1 10 100 1K 10K 100K 1M FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) 107 108 FIGURE 7. OFF ISOLATION vs FREQUENCY 10.0 10.0 V+ = +15V, V- = -15V V+ = +15V, V- = -15V | VD | = | VS | = 14V 1.0 1.0 ID(ON) (nA) SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA) 106 FREQUENCY (Hz) LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) 0.1 0.1 0.01 25 75 125 TEMPERATURE (oC) FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE † † 0.01 25 75 125 TEMPERATURE (oC) FIGURE 9. ID(ON) vs TEMPERATURE † The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 7 HI-301 thru HI-307 Typical Performance Curves (Continued) 16 INPUT CAPACITANCE (pF) OUTPUT ON CAPACITANCE (pF) 60 50 40 30 12 8 TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) HI-301 AND HI-303 4 HI-307 TRANSITION 20 0 2 4 6 8 10 12 14 16 0 2 4 DRAIN VOLTAGE (V) FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE 8 10 12 14 16 FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE 300 300 V+ = +15V, V- = -15V VINH = 15V, VINL = 0V V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V tON SWITCHING TIME (ns) SWITCHING TIME (ns) 6 INPUT VOLTAGE (V) 200 tOFF 100 -55 -35 -15 5 25 45 65 85 105 200 tON 100 tOFF -55 125 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 12. SWITCHING TIME vs TEMPERATURE, HI-301 AND HI-303 FIGURE 13. SWITCHING TIME vs TEMPERATURE, HI-307 300 tON tON SWITCHING TIME (ns) SWITCHING TIME (ns) 300 V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V tOFF 200 100 0 5 10 NEGATIVE SUPPLY (V) FIGURE 14. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE, HI-301 AND HI-303 8 15 V+ = +15V, TA = 25oC VINH = 15V, VINL = 0V 200 tOFF 100 0 5 10 NEGATIVE SUPPLY (V) FIGURE 15. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE, HI-307 15 HI-301 thru HI-307 1.8 (Continued) 1.8 V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V 1.6 V- = -15V, TA = 25oC VINH = 15V, VINL = 0V 1.6 1.4 1.4 SWITCHING TIME (µs) SWITCHING TIME/BREAK-BEFORE-MAKE TIME (µs) Typical Performance Curves 1.2 1.0 0.8 0.6 tON 0.4 1.0 0.8 0.6 0.4 tOFF tOPEN HI-301/303 ONLY 0.2 1.2 tOFF tON 0.2 0 0 0 5 10 0 15 5 FIGURE 16. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE, HI-301 AND HI-303 FIGURE 17. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE, HI-307 INPUT SWITCHING THRESHOLD (V) 7 V- = -15V, TA = 25oC 6 HI-307 5 4 3 2 HI-301 AND 303 1 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 18. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE 9 10 POSITIVE SUPPLY VOLTAGE (V) POSITIVE SUPPLY VOLTAGE (V) 15 HI-301 thru HI-307 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) LEAD FINISH c1 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E M -Bbbb S C A-B S -C- S1 0.200 - 5.08 - 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - eA ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 10 NOTES - b2 b MAX 0.014 α A A MIN b A L MILLIMETERS MAX A Q SEATING PLANE MIN M (b) D BASE PLANE SYMBOL b1 SECTION A-A D S INCHES (c) b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 14 14 8 Rev. 0 4/94 HI-301 thru HI-307 Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA H 0.25(0.010) M 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- α e B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e A1 B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 14 0o 14 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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