MAXIM DG406DN

DG406, DG407
®
Data Sheet
March 13, 2006
Single 16-Channel/Differential 8-Channel,
CMOS Analog Multiplexers
The DG406 and DG407 monolithic CMOS analog
multiplexers are drop-in replacements for the popular
DG506A and DG507A series devices. They each include an
array of sixteen analog switches, a TTL and CMOS
compatible digital decode circuit for channel selection, a
voltage reference for logic thresholds, and an ENABLE input
for device selection when several multiplexers are present.
These multiplexers feature lower signal ON resistance
(<100Ω) and faster transition time (tTRANS < 300ns)
compared to the DG506A and DG507A. Charge injection
has been reduced, simplifying sample and hold applications.
The improvements in the DG406 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30VP-P signals when operating with ±15V power
supplies.
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.
Pinouts
DG406 (PDIP, SOIC)
TOP VIEW
V+ 1
28 D
NC 2
NC 3
DG407 (PDIP, SOIC)
TOP VIEW
V+ 1
28 DA
27 V-
DB 2
27 V-
26 S8
NC 3
26 S8A
S16 4
25 S7
S8B 4
25 S7A
S15 5
24 S6
S7B 5
24 S6A
S14 6
23 S5
S6B 6
23 S5A
S13 7
22 S4
S5B 7
22 S4A
S12 8
21 S3
S4B 8
21 S3A
S11 9
20 S2
S3B 9
20 S2A
S10 10
19 S1
S2B 10
19 S1A
S9 11
18 EN
S1B 11
18 EN
GND 12
17 A0
GND 12
17 A0
NC 13
16 A1
NC 13
16 A1
A3 14
15 A2
NC 14
15 A2
FN3116.9
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . 100Ω
• Low Power Consumption (PD) . . . . . . . . . . . . . . . <1.2mW
• Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . 300ns
• Low Charge Injection
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Battery Operated Systems
• Data Acquisition
• Medical Instrumentation
• Hi-Rel Systems
• Communication Systems
• Automatic Test Equipment
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
DG406DJ
DG406DJ
-40 to 85
28 Ld PDIP
DG406DJZ
(See Note)
DG406DJZ
-40 to 85
28 Ld PDIP* E28.6
(Pb-free)
E28.6
DG406DY
DG406DY
-40 to 85
28 Ld SOIC
M28.3
DG406DY-T
DG406DY
DG406DYZ
(See Note)
DG406DYZ
28 Ld SOIC Tape and Reel M28.3
DG406DYZ-T
(See Note)
DG406DYZ
DG407DJ
DG407DJ
-40 to 85
28 Ld PDIP
DG407DJZ
(Note)
DG407DJZ
-40 to 85
28 Ld PDIP* E28.6
(Pb-free)
-40 to 85
28 Ld SOIC
(Pb-free)
M28.3
28 Ld SOIC Tape and Reel M28.3
(Pb-free)
E28.6
DG407DY
DG407DY
-40 to 85
28 Ld SOIC
M28.3
DG407DYZ
(Note)
DG407DYZ
-40 to 85
28 Ld SOIC
(Pb-free)
M28.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are
not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2000, 2003, 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
DG406, DG407
Schematic Diagram (Typical Channel)
V+
VREF
GND
D
A0
V+
LEVEL
SHIFT
AX
V-
DECODE/
DRIVE
S1
V+
EN
SN
V-
Functional Diagrams
DG406
DG407
S1A
S1
S2A
S2
S3A
S3
S4A
S4
S6A
S6
S7A
S7
S8A
S8
D
S9
S1B
S10
S2B
S11
S3B
S12
S4B
S13
S6B
S15
S7B
S16
S8B
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16
A1
DB
S5B
S14
A0
DA
S5A
S5
A2
A3
2
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ENABLE
EN
ADDRESS DECODER
1 OF 8
A0
A1
A2
ENABLE
EN
FN3116.9
March 13, 2006
DG406, DG407
DG406 TRUTH TABLE
DG407 TRUTH TABLE
A3
A2
A1
A0
EN
ON SWITCH
A2
A1
A0
EN
ON SWITCH PAIR
X
X
X
X
0
None
X
X
X
0
None
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
2
0
0
1
1
2
0
0
1
0
1
3
0
1
0
1
3
0
0
1
1
1
4
0
1
1
1
4
0
1
0
0
1
5
1
0
0
1
5
0
1
0
1
1
6
1
0
1
1
6
0
1
1
0
1
7
1
1
0
1
7
0
1
1
1
1
8
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
1
10
1
0
1
0
1
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
16
3
Logic “0” = VAL < 0.8V.
Logic “1” = VAH > 2.4V.
X = Don’t Care.
FN3116.9
March 13, 2006
DG406, DG407
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS , VD (Note 1). . . . . . (V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . 100mA
Thermal Resistance (Typical, Note1)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
θJA (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Signals on SX , DX , EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP (oC)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
DYNAMIC CHARACTERISTICS
(See Figure 1)
Transition Time, tTRANS
Break-Before-Make Interval, tOPEN
(See Figure 3)
(See Figure 2)
Enable Turn-ON Time, tON(EN)
Enable Turn-OFF Time, tOFF(EN)
25
-
200
300
ns
Full
-
-
400
ns
25
25
50
-
ns
Full
10
-
-
ns
25
-
150
200
ns
Full
-
-
400
ns
25
-
70
150
ns
Full
-
-
300
ns
Charge Injection, Q
CL = 1nF, VS = 0V, RS = 0Ω
25
-
40
-
pC
OFF Isolation, OIRR
VEN = 0V, RL = 1kΩ,
f = 100kHz (Note 7)
25
-
-69
-
dB
Logic Input Capacitance, CIN
f = 1MHz
25
-
7
-
pF
Source OFF Capacitance, CS(OFF)
VEN = 0V, VS = 0V,
f = 1MHz
25
-
8
-
pF
Drain OFF Capacitance, CD(OFF)
VEN = 0V, VD = 0V,
f = 1MHz
25
-
160
-
pF
25
-
80
-
pF
25
-
180
-
pF
25
-
90
-
pF
Full
2.4
-
-
V
DG406
DG407
Drain ON Capacitance, CD(ON)
VEN = 5V, VD = 0V,
f = 1MHz
DG406
DG407
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, VINH
Full
-
-
0.8
V
Logic High Input Current, IAH
VA = 2.4V, 15V
Full
-1
-
1
µA
Logic Low Input Current, IAL
VEN = 0V, 2.4V, VA = 0V
Full
-1
-
1
µA
Logic Low Input Voltage, VINL
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON Resistance, rDS(ON)
rDS(ON) Matching Between Channels,
∆rDS(ON)
4
VD = ±10V, IS = +10mA (Note 5)
VD = 10V, -10V (Note 6)
25
-
50
100
Ω
Full
-
-
125
Ω
25
-
5
-
%
FN3116.9
March 13, 2006
DG406, DG407
Electrical Specifications
Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
Source OFF Leakage Current, IS(OFF)
(Continued)
TEMP (oC)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
25
-0.5
0.01
0.5
nA
Full
-5
-
5
nA
25
-1
0.04
1
nA
Full
-40
-
40
nA
25
-1
0.04
1
nA
Full
-20
-
20
nA
25
-1
0.04
1
nA
Full
-40
-
40
nA
25
-1
0.04
1
nA
Full
-20
-
20
nA
25
-
13
30
µA
Full
-
-
75
µA
VEN = 0V, VS = ±10V,
VD = +10V
Drain OFF Leakage Current, ID(OFF)
DG406
DG407
VS = VD = ±10V (Note 5)
Drain ON Leakage Current, ID(ON)
DG406
DG407
POWER SUPPLY CHARACTERISTICS
VEN = VA = 0V or 5V
(Standby)
Positive Supply Current, I+
Negative Supply Current, I-
VEN = 2.4V, VA = 0V
(Enabled)
Positive Supply Current, I+
Negative Supply Current, I-
Electrical Specifications
25
-1
-0.01
-
µA
Full
-10
-
-
µA
25
-
80
100
µA
Full
-
-
200
µA
25
-1
-0.01
-
µA
Full
-10
-
-
µA
Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified
TEST
CONDITIONS
PARAMETER
TEMP (oC)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
DYNAMIC CHARACTERISTICS
Switching Time of
Multiplexer, tTRANS
VS1 = 8V, VS8 = 0V,
VIN = 2.4V
25
-
300
450
ns
Enable Turn-ON Time, tON(EN)
VINH = 2.4V, VINL = 0V,
VS1 = 5V
25
-
250
600
ns
25
-
150
300
ns
CL = 1nF, VS = 6V,
RS = 0Ω
25
-
20
-
pC
Enable Turn-OFF Time,
tOFF(EN)
Charge Injection, Q
5
FN3116.9
March 13, 2006
DG406, DG407
Electrical Specifications
Single Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified (Continued)
TEST
CONDITIONS
TEMP (oC)
(NOTE 3)
MIN
(NOTE 4)
TYP
(NOTE 3)
MAX
UNITS
Full
0
-
12
V
25
-
90
120
Ω
25
-
5
-
%
25
-
0.01
-
nA
DG406
25
-
0.04
-
nA
DG407
25
-
0.04
-
nA
DG406
25
-
0.04
-
nA
DG407
25
-
0.04
-
nA
25
-
13
30
µA
Full
-
13
75
µA
25
-1
-0.01
-
µA
Full
-5
-0.01
-
µA
PARAMETER
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
VD = 3V, 10V, IS = -1mA
(Note 5)
Drain-Source ON-Resistance,
rDS(ON)
rDS(ON) Matching Between
Channels (Note 6), ∆rDS(ON)
Source Off Leakage Current, IS(OFF)
VEN = 0V, VD = 10V or 0.5V,
VS = 0.5V or 10V
Drain Off Leakage Current, ID(OFF)
VS = VD = ±10V (Note 5)
Drain On Leakage Current, ID(ON)
POWER SUPPLY CHARACTERISTICS
VEN = 0V or 5V,
VA = 0V or 5V
Positive Supply Current (I+)
(Standby)
Negative Supply Current (I-)
(Enabled)
NOTES:
3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
4. Typical values are for Design Aid Only, not guaranteed nor production tested.
5. Sequence each switch ON.
6. ∆rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) ÷ rDS(ON) average.
7. Worst case isolation occurs on channel 8B due to proximity to the drain pin.
Test Circuits and Waveforms
+15V
+15V
A2
LOGIC
INPUT
V+
+2.4V
±10V
S1
S2 - S15
A1
A0 GND
V-
50Ω
LOGIC
INPUT
10V
A1
-15V
FIGURE 1A. DG406 TEST CIRCUIT
35pF
V+
S1B
±10V
†
DG407
A0 GND
VO
D
300Ω
6
EN
A2
DG406 S
16
±
EN
A3
S8B
V-
50Ω
10V
±
+2.4V
DB
VO
300Ω
35pF
-15V
† = S1A - S8A , S2B - S7B , DA
FIGURE 1B. DG407 TEST CIRCUIT
FN3116.9
March 13, 2006
DG406, DG407
Test Circuits and Waveforms
(Continued)
tr < 20ns
tf < 20ns
3V
LOGIC
INPUT
50%
50%
0V
VS1B
SWITCH
OUTPUT
VO
S1 ON
80% VS1
0V
80%
VS8
VS8B
tTRANS
tTRANS
S8 ON
FIGURE 1C. MEASUREMENT POINTS
FIGURE 1. TRANSITION TIME
+15V
+15V
A3
A2
LOGIC
INPUT VIN
A1
V+
A2
-5V
S1
A1
S2 - S16
LOGIC
INPUT VIN
DG406
A0
EN GND
V-
VO
D
50Ω
300Ω
A0
EN
V+
-5V
S1B
†
DG407
DA AND DB
GND V-
50Ω
VO
300Ω
35pF
35pF
-15V
-15V
† = S1A - S8A , S2B - S8B , DA
FIGURE 2A. DG406 TEST CIRCUIT
LOGIC
INPUT
VIN
FIGURE 2B. DG407 TEST CIRCUIT
tr < 20ns
tf < 20ns
3V
50%
50%
0V
tON(EN)
tOFF(EN)
0V
SWITCH
OUTPUT
VO
VO
90% VO
FIGURE 2C. MEASUREMENT POINTS
FIGURE 2. ENABLE SWITCHING TIMES
+15V
tr < 20ns
tf < 20ns
3V
+2.4V
EN
A3
LOGIC
INPUT
V+
ALL S
AND DA
+5V (VS)
0V
A2 DG406
DG407
A1
D,
A0 GND V- DB
LOGIC
INPUT
50Ω
VO
300Ω
35pF
SWITCH
OUTPUT
VO
VS
80%
0V
tOPEN
-15V
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
7
FN3116.9
March 13, 2006
DG406, DG407
160
80
140
70
rDS(ON) , ON-RESISTANCE (Ω)
rDS(ON) , ON RESISTANCE (Ω)
Typical Performance Curves
120
±5V
100
80
60
40
±8V
±10V
±12V
±15V
±20V
-16
60
-12
-8
-4
0
4
8
VD , DRAIN VOLTAGE (V)
12
16
30
-40oC
20
-55oC
ID , IS , CURRENT (pA)
160
10V
120
12V
15V
0
5
10
15
120
V+ = 15V, V- = -15V
VS = -VD FOR ID(OFF)
VD = VS(OPEN) FOR ID(ON)
80
80
-5
FIGURE 5. rDS(ON) vs VD AND TEMPERATURE
V+ = 7.5V
200
-10
VD , DRAIN VOLTAGE (V)
20V
22V
40
IS(OFF)
0
-40
DG406 ID(ON) , ID(OFF)
DG407 ID(ON) , ID(OFF)
-80
40
0
4
8
12
16
20
-120
-15
FIGURE 6. rDS(ON) vs VD AND SUPPLY
100nA
0
5
10
15
350
300
10nA
250
tTRANS
TIME (ns)
1nA
ID(ON) , ID(OFF)
10pA
IS(OFF)
200
tON(EN)
150
100
tOFF(EN)
1pA
0.1pA
-55
-5
FIGURE 7. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE
V+ = 15V, V- = -15V
VS OR VD = ±10V
100pA
-10
VS , VD , SOURCE DRAIN VOLTAGE (V)
VD , DRAIN VOLTAGE (V)
ID , IS , CURRENT (A)
0oC
V+ = 15V
V- = -15V
0
-15
20
V- = 0V
240
rDS(ON) , ON-RESISTANCE (Ω)
25oC
40
FIGURE 4. rDS(ON) vs VD AND SUPPLY
0
85oC
50
10
20
0
-20
125oC
50
-35
-15
5
25
45
65
85
105
TEMPERATURE (oC)
FIGURE 8. ID , IS LEAKAGE vs TEMPERATURE
8
125
0
5
10
15
20
VSUPPLY , SUPPLY VOLTAGE (±V)
FIGURE 9. SWITCHING TIMES vs BIPOLAR SUPPLIES
FN3116.9
March 13, 2006
DG406, DG407
Typical Performance Curves
(Continued)
-140
700
600
-120
500
-100
ISOL (dB)
TIME (ns)
V- = 0V
tTRANS
400
300
tON(EN)
-80
-60
-40
200
tOFF(EN)
-20
100
0
5
10
15
0
100
20
1K
10K
V+, SUPPLY VOLTAGE (V)
FIGURE 10. SWITCHING TIMES vs SINGLE SUPPLY
280
V+ = 15V, V- = -15V
260
240
I+
4
220
2
TIME (ns)
I, CURRENT (mA)
10M
300
EN = 5V, AX = 0V OR 5V
6
0
IGND
-2
tTRANS
200
180
tON(EN)
160
140
-4
120
I-
-6
100
-8
-10
10
1M
FIGURE 11. OFF ISOLATION vs FREQUENCY
10
8
100K
f, FREQUENCY (Hz)
tOFF(EN)
80
100
1K
10K
100K
1M
60
-55
10M
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (oC)
f, FREQUENCY (Hz)
FIGURE 12. SUPPLY CURRENTS vs SWITCHING FREQUENCY
FIGURE 13. tON /tOFF vs TEMPERATURE
3
VA , (V)
2
1
0
0
5
10
15
20
VSUPPLY, SUPPLY VOLTAGE (±V)
FIGURE 14. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
9
FN3116.9
March 13, 2006
DG406, DG407
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
2490µm x 4560µm x 485µm
Type: Nitride
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: SiAl
Thickness: 12kÅ ±1kÅ
9.1 x 104 A/cm2
Metallization Mask Layout
DG406
NC
D
V-
S16
S5
S15
S7
S14
S6
S13
S5
S12
S4
S11
S3
S10
S2
S9
S1
GND A3
10
V+
A2
A1
A0
EN
FN3116.9
March 13, 2006
DG406, DG407
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
2490µm x 4560µm x 485µm
Type: Nitride
Thickness: 8kÅ ±1kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: SiAl
Thickness: 12kÅ ±1kÅ
9.1 x 104 A/cm2
Metallization Mask Layout
DG407
DB
V+
DA
V-
S8A
S8B
S7A
S7B
S6A
S6B
S5A
S5B
S4A
S4B
S3A
S3B
S2A
S2B
S1A
S1B
GND
11
NC
A2
A1
A0
EN
FN3116.9
March 13, 2006
DG406, DG407
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-BD
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
-
0.250
-
6.35
4
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.380
1.565
D1
0.005
-
0.13
A
L
D1
MIN
A
E
-C-
MAX
A1
-ABASE
PLANE
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
35.1
39.7
5
-
5
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
28
28
9
Rev. 1 12/00
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12
FN3116.9
March 13, 2006
DG406, DG407
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MILLIMETERS
MAX
A1
e
µα
MIN
28
0o
28
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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13
FN3116.9
March 13, 2006