INTERSIL HIP6200

HIP6200, HIP6201
Data Sheet
Transient Voltage Regulator
DeCAPitator™
February 1998
File Number
4423.2
Features
The Intersil DeCAPitator helps to stabilize a power system
voltage during severe transients. It accomplishes this by
supplying current when the voltage is more than 1% low or
sinking current when the voltage is higher than 1.5% from
the average load voltage. The fast transient response of the
DeCAPitator can make up for the slow response time of
many switching DC-DC converters.
Although the HIP6200 serves as a simple replacement for
large output capacitors for any dynamic load, it is especially
useful in stabilizing the CPU core voltage in portable
computer applications, where size and efficiency are major
concerns. The DeCAPitator enables power supply designs
for more powerful microprocessors without increasing
converter size or decreasing converter efficiency.
The DeCAPitator acts independently of the PWM control
circuitry. This simplifies converter layout because the
DeCAPitator and the load may be located separately from
the DC-DC converter. The DeCAPitator should be located
near the load for optimum performance.
• Saves Power System Size and Cost
- Replaces Expensive Bulk Capacitors
- Small 8 Lead SOIC Package
• Linear Regulator Response
- Greater than 5MHz Bandwidth
• Very Low Static Power Dissipation
- Shutdown Current . . . . . . . . . . . . . . . . . . . . . . . . . < 5µA
- Power Dissipated Only During Load Transients
• Over Temperature Shutdown/Signal
• Simplifies Power Supply Layout
- Allows for Remotely Located CPU DC-DC Converter
Applications
• Notebook Computers
• Pentium®, Pentium Pro, and Pentium II Power Supplies
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
HIP6200CB
0 to 70
8 Ld SOIC
M8.15
HIP6201CB
0 to 70
8 Ld SOIC
M8.15
Pinouts
HIP6200 (SOIC)
TOP VIEW
HIP6201 (SOIC)
TOP VIEW
PVCC
1
8 EN/OT
PVCC
1
8 EN
PGND
2
7 OUT
PGND
2
7 OUT
GND
3
6 SNS
GND
3
6 SNS
VCC
4
5 CAP
VCC
4
5 CAP
Pentium® is a registered trademark of Intel Corporation.
DeCAPitator™ is a trademark of Intersil Corporation.
2-441
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HIP6200, HIP6201
Typical Application - Portable CPU Dynamic Regulator
PWM
CONTROLLER
BATTERY
POWER
+5V
VCC
4
EN/OT
8
HIP6200
POR
1
PVCC
7
OUT
6
SNS
+
-
X 0.99
R
CAP
5
20R
CPU
LOAD
+
X 1.015
-
2
3
PGND
GND
Block Diagram
VCC
PVCC
RVCC
EN/OT
(HIP6200)
THERMAL
MONITOR
(TMON)
POWER-ON
RESET (POR)
EN
(HIP6201)
99%
UPPER
COMPARATOR
+
-
ENABLE
+
UPPER
AMPLIFIER
-
OUT
RT1
SNS
CAP
RT2
LOWER
AMPLIFIER
ROUT
+
+
101.5%
ENABLE
RGND
LOWER
COMPARATOR
GND
2-442
PGND
HIP6200, HIP6201
Functional Pin Description
PVCC (Pin 1)
PVCC is the power source for the npn transistor output
device. PVCC is connected internally to VCC through a
resistor. Bulk capacitance should be placed between this pin
and PGND to minimize voltage deviations.
PGND (Pin 2)
PGND is power ground for the N-Channel MOSFET output
device. Tie this pin to the ground plane of the circuit board.
GND (Pin 3)
GND is signal ground for the IC. Tie this pin to the ground
plane of the circuit board.
VCC (Pin 4)
VCC provides bias power to the chip. It should be tied to
system 5V. Provide local decoupling to this pin.
CAP (Pin 5)
Connect a capacitor to GND to set the internal amplifiers’
on-time response to a rapid voltage change at the SNS pin.
SNS (Pin 6)
SNS is the remote sense of the output voltage to be
regulated. If the output voltage increases rapidly by greater
than 1.5%, the lower amplifier responds by turning on the NChannel MOSFET to sink current through the OUT pin to
PGND. If the output voltage decreases rapidly by greater
than 1%, the upper amplifier responds by turning on the npn
transistor to source current from PVCC to OUT.
OUT (Pin 7)
This pin is the output pin of the IC. Tie this pin directly to the
voltage to be regulated.
EN/OT or EN (Pin 8)
This pin is the only differentiation between the HIP6200 and
the HIP6201.
On the HIP6200, this pin is multiplexed. It is chip enable and
also an overtemperature indicator. When this pin is low, the
chip is disabled. If an overtemperature occurs, this pin will be
pulled low internally. Tie EN/OT to a pull-up resistor and
drive with an open collector signal.
On the HIP6201, this pin is chip enable only. Pulling it low
disables the IC. EN should be driven with a logic signal.
2-443
HIP6200, HIP6201
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
EN, CAP, OUT, SNS. . . . . . . . . . . . . . . . . . . . . . . .GND-0.3V to +7V
GND - PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +0.5V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145oC/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Output Device Supply Voltage, PVCC . . . . . . . . . . . . +4.5V to +5.5V
Output Voltage, OUT = SNS = CAP. . . . . . . . . . . . . . +1.3V to +2.0V
Load Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8A
Ambient Operating Temperature Range . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
300
-
µA
-
1
-
µA
0.8
1.5
2.0
V
VCC SUPPLY CURRENT
Nominal Supply
IVCC
Shutdown Supply
IVCC_SD
EN = GND
PROTECTION CIRCUITRY
EN Threshold
VTH_EN
Overtemperature (OT) Threshold
On-Resistance of OT NMOS
OT
130
150
170
oC
Rds_TFN
-
250
600
Ω
POWER-ON RESET (POR)
VCC Rising Threshold
VTHH_VCC
EN = VCC
-
4.1
4.5
V
VCC Falling Threshold
VTHL_VCC
EN = VCC
3.6
4.0
-
V
CAP Rising Threshold
VTH_CAP
EN = VCC
-
1.10
1.20
V
EN = VCC
0.95
1.05
-
V
CAP Falling Threshold
POR Turn-Off Delay to EN Falling
-
2
-
µs
POR Turn-On Delay to EN Rising
-
1
-
ms
POR Turn-Off Delay to VCC UV
EN = VCC, VCC Falling
-
15
-
µs
POR Turn-On Delay after VCC UV
EN = VCC, VCC Rising
-
15
-
µs
POR Turn-Off Delay to CAP UV
EN = VCC, CAP Falling
-
2
-
µs
POR Turn-On Delay after CAP UV
EN = VCC, CAP Rising
-
15
-
µs
REFERENCE VOLTAGE
VSNS - VCAP
VHIGH
CAP = 2V, SNS Increased Until Amplifier Turns On
-
30
-
mV
VCAP - VSNS
VLOW
CAP = 2V, SNS Decreased Until Amplifier Turns On
-
20
-
mV
-
500
-
A/V
AMPLIFIERS
Transconductance
Response Time (Rising)
60mV Step on OUT, Time for IOUT < -4A
50
100
175
ns
Response Time (Falling)
-60mV Step on OUT, Time for IOUT > 4A
50
100
175
ns
RESISTOR VALUES
Small Time Constant Resistor
RT1
120
200
250
Ω
Large Time Constant Resistor
RT2
3000
4000
5500
Ω
VCC to PVCC Resistor
RVCC
6
10
16
Ω
OUT to SNS Resistor
ROUT
1000
1500
2100
Ω
GND to PGND Resistors
RGND
-
140
-
Ω
2-444
HIP6200, HIP6201
Application Information
maintain a small difference between the desired and actual
output voltage.
Theory of Operation
The HIP6200 is used in conjunction with a switching DC-DC
converter to provide a regulated DC voltage. The output
voltage of a DC-DC converter changes instantly with sudden
load changes characteristic of today’s microprocessors. This
change occurs because the bulk capacitors are imperfect;
they have parasitic resistances (ESR) and inductances (ESL)
which translate into voltage drops as the load is initially
supplied by the bulk capacitance. Also, due to its output
inductor, the DC-DC converter takes about 10-20µs (typical)
before it provides the load current required by the CPU. The
HIP6200 contains two high-speed linear regulators which are
inactive except during the converter response time after high
di/dt load transients. When active, the linear regulators
The Typical Application Diagrams below illustrate how the
DeCAPitator functions. The left side shows a common DCDC converter response to a fast ‘low-to-high’ load transient.
The right side shows a similar response with a HIP6200
circuit employed. The HIP6200 allows the use of fewer bulk
capacitors to handle the regulation requirements of the high
edge-rate load transients. The response time of the
HIP6200’s linear regulators (100ns typical) are fast enough
to help with the leading edge spike. Output voltage
deviations during the converter response time are reduced
with the HIP6200 since it helps supply the load while the
inductor current slews.
Typical Application Diagrams
PWM
CONTROLLER
BATTERY
POWER
IL
+5V
BATTERY
POWER
PVCC
VCC
VOUT
EN 8
ICPU
PWM
CONTROLLER
7
HIP6201
VCAP
IL
CBULK
CAP 5
CBULK: (11) 220µF, 10V, 0.1Ω Tantalums
CCAP
GND
2
OUT
VOUT
IOUT
6
3
CPU
LOAD
CPVCC
1
4
SNS
ICPU
PGND
CPU
LOAD
CBULK
CBULK: (5) 100µF, 10V, 0.1Ω Tantalums
CCAP: small Ceramic (0805)
CVCC: small Ceramic (0805)
CPVCC: (1) 100µF, 10V, 0.1Ω Tantalum
ICPU
ICPU
IL
IL
VCAP
VOUT
VOUT
IOUT
CONVERTER
RESPONSE TIME (TR)
FIGURE 1. PORTABLE CPU WITHOUT HIP6200, HIP6201
2-445
FIGURE 2. PORTABLE CPU WITH HIP6200, HIP6201
HIP6200, HIP6201
Detailed Functional Description
As shown in the Block Diagram, the HIP6200 has two
comparators which compare the voltage on the CAP pin to
the voltage on the SNS pin. The CAP voltage follows the
SNS voltage with an R-C delay which is user programmable
and also variable depending upon the state of the amplifiers.
Normally, resistor RT1 is in parallel with RT2 when the
amplifiers are not active. RT1 is small and the CAP voltage
(VCAP) follows the SNS voltage (VSNS) closely. During a
transient, when either amplifier is active, the switch in series
with RT1 opens and RT2 alone (with the capacitor on CAP)
sets the time constant. Since RT2 is 20 times larger than
RT1, the DeCAPitator has time to source or sink current as
the inductor current slews. The CAP voltage waveform is
depicted in the Typical Application Diagrams.
Prior to the load transient, VCAP follows VOUT (and
likewise VSNS) closely. This is important in many portable
applications because the DC-DC converter will be in an
energy-saving skip-cycle mode at light load currents. In this
mode, the output voltage ripple may be in excess of ±2%
and could trip the HIP6200’s comparators if VCAP did not
track VSNS. This would turn on the amplifiers and waste
power. When a fast load transient occurs, VCAP no longer
follows VOUT and the DeCAPitator becomes active when
VOUT exceeds +1% or -1.5% of VCAP.
When the DeCAPitator is active, it either supplies current
from the PVCC pin or sources current to PGND. Because of
this, a high-quality capacitor must be placed locally from
PVCC to GND. The system 5V bus typically has a good
deal of bulk capacitance as well as high frequency
decoupling sprinkled across the application board. PVCC is
tied to the system 5V bus through an on-chip 10Ω resistor.
This resistor helps isolate the system 5V from the
disturbances on PVCC.
The HIP6200 has a power-on reset function which ensures
that both VCC and CAP are at some minimum levels before
allowing amplifier operation. There is also an EN(ABLE) pin,
allowing users to disable the HIP6200 if desired. An
overtemperature (OT) shutdown feature ensures that the
HIP6200 will not self-destruct from thermal overload. An OT
event will shutdown the chip until the junction temperature
decreases a few degrees below its trip point.
The DeCAPitator draws very little bias current (300µA
typical) when its amplifiers are inactive. When either
amplifier is active, the chip draws 15-30mA of bias current.
This current is mainly for the active high-speed amplifier and
lasts only for the duration of the on-time of the HIP6200.
Component Selection Guidelines
Bulk Output Capacitors
For a given converter design without the HIP6200 in the
target application, the number of output capacitors is
determined mainly by the output voltage regulation and
2-446
transient specifications. It is estimated that for a load
transient of 0-8A with a di/dt of 20A/µs, eleven 220µF, 0.1Ω
low ESR tantalum capacitors are necessary to maintain
CPU core voltage regulation specifications. For identical
conditions with a HIP6200 employed, only five 100µF, 0.1Ω
low ESR tantalums are required. Similar savings in output
capacitance can be achieved with other capacitor dielectrictypes.
The number of capacitors which can be eliminated on the
output is limited by either of the following:
1. Output voltage ripple - this increases proportional to the
equivalent ESR of the bulk output capacitance. This may
be counteracted by increasing the output inductance. In
many cases the inductor can remain the same because
the output ripple will still be acceptably small.
2. Leading edge voltage spike - this may increase with reduced number of capacitors. The HIP6200 and its very
fast response is very effective in handling this leading
edge spike up to a point. Some additional ceramic decoupling on the OUT pin can also help.
PVCC Capacitor
A 100µF, 0.1Ω tantalum is recommended on the PVCC pin
for an application which has 8A transients (maximum
recommended operation of the HIP6200). RVCC is an
internal 10Ω resistor from VCC to PVCC which decouples the
PVCC transient from the system 5V (VCC).
CAP Capacitor
The capacitor on the CAP pin sets the amount of time that
the HIP6200 has to sink or source current in response to a
load transient. The DeCAPitator on-time should be greater
than the converter response time. When the HIP6200’s
amplifiers are not active, the CAP pin follows the output
voltage closely to prevent false tripping at light loads due to
PWM skip-cycle modes of operation. These two
boundaries are addressed with RT1 and RT2 internal to the
HIP6200 but must also be verified on each design.
The converter response time is the time interval required for
the inductor current to slew to the output load current. This
time is dramatically different for the two edges of the
transient event if there is a large differential between input
and output voltages of the converter. The converter
response times are approximated by v = L*di/dt:
I STEP
T R1 = L OUT • -----------------------------------( V IN – V OUT )
(EQ. 1)
I STEP
T R2 = L OUT • -------------------( V OUT )
(EQ. 2)
where
TR1 = converter response time to low-to-high load transient
TR2 = converter response time to high-to-low load transient
HIP6200, HIP6201
LOUT = output inductor value
and:
ISTEP = transient current step amplitude
Ibias UP • t ACTIVE Ibias DWN • t ACTIVE
I BIAS = I IDLE + --------------------------------------------------- + -------------------------------------------------------T
T
The value of the capacitor at the CAP pin should be sized so
that the HIP6200 can be active in response to a transient for
longer than the greater of TR1 and TR2. For a 12V to 1.7V
DC-DC converter with a 3µH inductor and a 8A maximum
transient step size, TR1 = 2.3µs and TR2 = 14.1µs. Thus, the
CAP capacitor should be chosen for the worst-case TR2
response. Though the HIP6200 will be active for longer than
necessary in response to the low-to-high load transient, the
amount of power wasted will be minimal. The upper amplifier
will be active, drawing about 15mA, but the power npn
darlington will pinch off after the inductor current slews up.
The following section details power dissipation further.
Thermal Considerations
HIP6200 Power Dissipation
The power dissipated by the DeCAPitator is a function of
many variables. The load transient step size (ISTEP), the
frequency of the transient events (1/TTRAN), and the
converter response time (TR1, TR2) have the largest
influence. Figure 3 displays these terms.
TTRAN
ICPU
ISTEP
TRAN
TRAN
(EQ. 7)
IIDLE = nominal supply current when HIP6200 is powered
and amplifiers are not active (300µA typical)
IbiasUP = upper amplifier bias current when active (15mA
typical)
IbiasDWN = lower amplifier bias current when active (30mA
typical)
tACTIVE = time amplifiers are active. This time is set by CAP
capacitor and should be at least as long as TR2.
The bias power is a very small percentage of the total chip
power dissipation, but is included for completeness.
Based on these equations, the two figures below show how
the power dissipation varies with the transient frequency
(1/TTRAN), step load change (ISTEP), and converter
response time (TR1, TR2). Both figures assume VIN = 12V
and VOUT = 1.7V. Figure 4 assumes a 3µH output inductor
and varies the step size (as well as the transient frequency).
As mentioned in the previous section, these conditions give
TR1 = 2.3µs and TR2 = 14.1µs for ISTEP = 8A. Figure 5
holds ISTEP constant at 8A and varies the response time.
The converter response time often differs from the ideal
(Equations 1 and 2) substantially and therefore should be
verified experimentally.
IOUT
0.6
POWER DISSIPATION (W)
TR2
TR1
FIGURE 3. IDEALIZED WAVEFORMS OF DeCAPitator
OPERATION
Based on some simplifying assumptions, the DeCAPitator
power dissipation can be approximated as follows:
P DISS = P BIAS + P UP + P DWN
(EQ. 3)
0.5
ISTEP = 8A
0.4
ISTEP = 4A
ISTEP = 6A
0.3
0.2
0.1
102
103
104
105
TRANSIENT FREQUENCY (Hz)
where:
T R1 
 I STEP
P UP = ( V CC – V OUT ) •  ---------------- • -------------------
T TRAN
 2
(EQ. 4)
T R2 
 I STEP
P DWN = ( V OUT ) •  ---------------- • -------------------
T TRAN
 2
(EQ. 5)
P BIAS = V CC • ( I BIAS )
(EQ. 6)
2-447
FIGURE 4. ESTIMATED HIP6200, HIP6201 POWER
DISSIPATION vs ISTEP
Figures 4 and 5 show the relationships between the
DeCAPitator power dissipation and the load transient
frequency, load transient step size and the converter
response time. The power dissipation is linear with the
transient frequency but is shown on the log scale to
emphasize the fact that the HIP6200/1 power is minimal at
frequencies below a few hundred Hertz.
HIP6200, HIP6201
In actual systems, the load transient will most likely be of
varying frequency and step size. The power dissipation
of the HIP6200/1 becomes even more difficult to estimate
analytically.
Example: HIP6200/1 Junction Temperature Calculation
TAMBIENT = 70oC
PDISS = 0.2W
POWER DISSIPATION (W)
ΘJA = 100oC/W
0.6
TR1 = 15µs, TR2 = 40µs
TR1 = 10µs, TR2 = 30µs
0.5
TR1 = 2µs, TR2 = 10µs
THIP6200 = 70oC + (0.2 x 100) = 90oC
TR1 = 5µs, TR2 = 20µs
In a similar fashion, one could estimate the maximum
allowable power dissipation for given maximum ambient and
transient loading and determine the boundary of maximum
transient frequency.
0.4
0.3
Example
0.2
Maximum Transient Frequency Calculation
0.1
TAMBIENT = 70oC
102
103
104
TRANSIENT FREQUENCY (Hz)
FIGURE 5. ESTIMATED HIP6200, HIP6201 POWER
DISSIPATION vs CONVERTER RESPONSE TIME
HIP6200 Temperature Rise
The HIP6200/1 junction temperature can be estimated
simply by:
T HIP6200 = T AMBIENT + ( P DISS • Θ JA )
(EQ. 8)
where:
ΘJA is the thermal resistance from junction to ambient.
2-448
THIP6200 = 110oC max
ΘJA = 80oC/W (this number is dependent upon airflow and
the amount of pc board trace connected to HIP6200
Max PDISS = (110oC - 70oC)/(80oC/W) = 0.5W
From Figures 4 and 5, the estimated maximum transient
frequency is obtained for any of the seven cases shown. For
instance, from Figure 4, the maximum transient frequency is
about 4kHz for the 8A transient step and the conditions
stipulated.
HIP6200, HIP6201
Layout Considerations
P5V
4
VCC
C37 +
100µ
10V
FROM µP CORE
+
C19-23
5x
100µ
10V
6
C24-26
3x
1µ
16V
PVCC
EN
8
U3
HIP6201
7
VOUT
OUTPUT OF DC-DC
(OUTPUT INDUCTOR)
1
OUT
CAP
C38
0.1µ
5
SNS
PGND
2
RTN
GND
C39
8200p
3
RTN
CERAMIC DECOUPLING
FOR HIGH di/dt LOAD
(MAY NOT BE REQUIRED)
BULK OUTPUT CAPACITANCE
OF DC-DC CONVERTER
FIGURE 6. TYPICAL SCHEMATIC
Example Layout
• HIP6200 located near bulk output capacitance (not shown is the microprocessor load itself - for best performance, the
HIP6200 and bulk output capacitance should be located close to the µP)
• C37 (+5V bulk cap) located near the HIP6200
• Solid ground and VOUT planes with numerous via interconnects
TOP - SILK SCREEN
TOP - COMPONENT SIDE
SOLDER SIDE
INTERNAL ONE
GND
NOTE: Internal layers are shown as negatives
(white is copper):
via connection to copper plane
no connection
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2-449