Ei ceDR I V ER™ Tips & Tri cks for R C I N and I TR I P 6EDL family - 2nd generation Application Note AN2015-09 About this document Scope and purpose The RCIN and ITRIP functions strongly help to reduce the system cost. However, the functions as they are available do have limitations in some applications. This application note helps to understand the function more in detail and give application support how to overcome these limitations. Intended audience The application note addresses experienced hardware engineers who have already basic knowledge of the 6EDL family – 2nd generation. Table of Contents 1 Introduction ............................................................................................................... 2 2 Overcoming the large tolerance of the RCIN timing ........................................................ 3 3 Overcome the high trigger level of the ITRIP function ..................................................... 7 Application Note AN2015-09 1 <Revision 2>, <2015-07-13> AN2015-09 Tips & Tricks for RCIN and ITRIP Introduction 1 Introduction The 6EDL family – 2nd generation is a family of versatile and robust driver ICs. This application note is related to the family’s members given in Table 1 Table 1 Members of 6ED family – 2nd generation control input UVLO Bootstrap HIN1,2,3 and LIN1,2,3 threshold diode 6EDL04I06NT negative logic 12.1V/10.2V 6EDL04I06PT positive logic 6EDL04N06PT / 6EDL04N02PR 6ED003L06-F2 / 6ED003L02-F2 Sales code Package Optimal for Yes DSO28 IGBT 12.1V/10.2V Yes DSO28 IGBT positive logic 8.9V/8.0V Yes negative logic 12.1V/10.2V No MOSFET DSO28 / TSSOP28 DSO28 / IGBT, TSSOP28 replacement of 1st generation The RCIN and ITRIP functions strongly help to reduce the system cost. However, the functions as they are available do have limitations in some applications. This application note helps to understand the functions in deep detail and gives application support on how to overcome the limitations. It is mandatory for the understanding of this document to carefully read the datasheet [1] and the 6EDL technical description [2]. Application Note AN2015-09 2 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcoming the large tolerance of the RCIN timing 2 Overcoming the large tolerance of the RCIN timing This section describes how the rather large tolerance of the RCIN timing can be overcome. 2.1 Application problem The RCIN function ([1], [2]) of the 6EDL family – 2nd generation provides an integrated current source as depicted in a) of Figure 1. It usually allows skipping an external pull-up resistor. The tolerance of this current source can be derived from a specific datasheet parameter according to b) in Figure 1. a) COM RF ITRIP RSH 6ED family – 2nd generation CF VSS VIT,HYS= 70mV VIT,TH+= 0.445V VZ=10.5V Comp. INPUT NOISE FILTER VDD2 8V Q SET DOMINANT LATCH R current source VCC RCIN CRCin S to input signal logic IRCIN VRCIN,TH= 5.2V VRCIN,HYS = 2.0V NMOS RON,RCIN to /FAULT VSS b) Figure 1 a) RCIN circuit b) Datasheet excerpt of the fault clear time tFLTCLR The fault clear time tFLTCLR specifies the charging time of the RCIN capacitor CRCIN in the datasheet. The RCIN capacitor is charged from the internal current source for this parameter. Therefore, the tolerance of the current source can be derived from the parameter tolerances. This means that the tolerance of the current source is approx. –52 % and + 58 %. Such tolerances may be not acceptable especially for fault clear times tFLTCLR which are longer than 5 ms. For simplification, it is assumed in the following sections that the internal current source has a tolerance of ± 50%. 2.2 Application solution The situation which is described in section 2.1 can be solved by applying an additional, highly accurate current source to charge the capacitor CRCIN according to Figure 2. This can be implemented by a pull-up resistor RRCIN to a voltage Vpu. The pull-up resistor must have a tolerance of 1%. The pull-up current needs to be large enough to tune the overall charging current into a suitable design window. Application Note AN2015-09 3 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcoming the large tolerance of the RCIN timing Two assumptions are made: The pull-up current IRRCIN and the value IRCIN of the integrated current source according to Figure 2 are small with respect to the initial current amplitude during discharge of the capacitor CRCIN. Therefore, only the capacitor CRCIN dominates the discharge process 6ED family – 2nd generation COM RF RSH VCC ITRIP CF VZ=10.5V VSS VIT,TH+= 0.445V Comp. INPUT NOISE FILTER VDD2 8V IRRCIN RRCin VCC RCIN Q SET DOMINANT LATCH R current source VRCIN,TH= 5.2V VRCIN,HYS = 2.0V NMOS RON,RCIN CRCin to /FAULT VSS Figure 2 S IRCIN Vpu DZ to input signal logic VIT,HYS= 70mV Improved RCIN circuit Target power transistor is a IKD06N60RF It is described in [2] that the pull-up resistor bears the risk that the capacitor CRCIN is not discharged fast enough, so that the IC also does not reach the ITRIP latch state. This is shown in the right part of Figure 3. It leads to an occurrence of multiple short circuit or overcurrent shut-down events without getting into the fault clear state. Therefore, the maximum discharge time must remain smaller than the minimum shut down propagation delay 𝑡discharge = −𝑅on,RCIN ∙ 𝐶RCIN 𝑙𝑛 𝑉th,RCIN− < 𝑇ITRIP,min + 𝑡d(off),min 𝑉pu (1) The evaluation of this equation shows that it can easily get critical to use the IC´s supply voltage VVCC as the pull-up voltage: 𝑡discharge (𝐶RCIN = 10 nF, 𝑉pu = 15 V) = 0.62 µs < 400 ns + 106 ns = 506 ns (2) This means that the shut down occurs earlier than the discharge reaches the latching level of 3.2 V. Thus, the IC does not reach the safe fault clear state and activates its outputs again. This is shown in the right part of Figure 3. vRCIN ISC vge, iT Figure 3 vIT,TH+ tdischarge 3.2V t PWM vITRIP VVDD t ≈ vITRIP VVDD t 5.2V tFLTCLR 3.2V vRCIN ISC tITRIP+td(off) t vge, iT t t ¨¨ ¨¨ left: suitable RCIN timing with safe fault clear state right: bad RCIN timing without reaching fault clear state Application Note AN2015-09 4 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcoming the large tolerance of the RCIN timing So both, charging and discharging of the capacitor CRCIN must be carefully evaluated in order to achieve a suitable and precise RCIN timing according to the left part of Figure 3. A lower pull-up voltage can be necessary and can be achieved by implementing a stabilized voltage source by means of a biased zener diode according to the red parts in Figure 2. It is assumed that the current through RRCIN is constant during the charging and discharging until the relevant thresholds are reached. The pull-up current through resistor RRCIN is superposed onto the current IRCIN of the integrated current source. The integrated current source delivers IRCIN = 2.8 µA with a tolerance of TolintCS. The total target tolerance of the charging current is Tol. The charging current through RRCIN can be calculated to be 𝑇𝑜𝑙intCS 𝐼RRCIN,charge = ( − 1) ∙ 𝐼RCIN 𝑇𝑜𝑙 (3) The charging current through RRCIN leads to the corresponding resistance value of 𝑅RCIN = 𝑉pu (4) 𝐼RRCIN,charge The calculated fault clear time including a pull-up resistor RRCIN is depicted in Figure 4. The target capacitor value C*RCIN can be calculated by scaling with the ratio of a given fault clear time and the target fault clear time tFLTCLR,target using the calculated value of RRCIN in equation (4). The application example in section 2.3 explains this procedure in detail. The scaling calculation is ∗ 𝐶RCIN = 𝑡FLTCLR,target ∙𝐶 𝑡RRCIN,CRCIN RCIN (5) Now, equation (1) can be executed and verified by using C*RCIN . 2.3 Application example 100 ms 10 C_RCin=1nF @15V C_RCin=2.2nF @15V C_RCin=4.7nF @15V C_RCin=6.8nF @15V C_RCin=10nF @15V C_RCin=1nF @8.2V C_RCin=2.2nF @8.2V C_RCin=4.7nF @8.2V C_RCin=6.8nF @8.2V C_RCin=10nF @8.2V 1 0.1 tFLTCLR 0.01 100 1000 10000 100000 kW 1000000 OPEN RRCIN Figure 4 Resulting fault clear time of CRCIN in combination with RRCIN. The shadowed area shows the fault clear time without RRCIN Application Note AN2015-09 5 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcoming the large tolerance of the RCIN timing The application example should achieve the target behavior including: Overall tolerance Tol < 20 % Fault clear time tFLTCLR = 10 ms The pull-up voltage is Vpu = 8.2 V Executing equation (3) with the target conditions results in 𝑇𝑜𝑙intCS 50% 𝐼charge,RRCIN = ( − 1) ∙ 𝐼RCIN = ( − 1) ∙ 2.8 µA = 4.2 µA 𝑇𝑜𝑙 20% (6) The related pull-up resistance is 𝑅RCIN = 𝑉pu 𝐼charge,RRCIN = 8.2 V = 1.95 MΩ 4.2 µA (7) The closest match of the E24 series of resistors is a value of 2.0 MW. The scaling of the read out value in Figure 4 is now the next procedure step. The readout value of the dashed purple line at RRCIN = 2.0 MW and CRCIN = 10 nF is tFLTCLR = 8.5 ms. The calculated capacitance C*RCIN is ∗ 𝐶RCIN = 𝑡FLTCLR,target 10 ms ∙ 𝐶RCIN = ∙ 10 nF = 11.8 nF 𝑡RRCIN,CRCIN 8.5 ms (8) A close value is CRCIN = 12nF. The last step in the design procedure is to verify the proper discharge of CRCIN with the selected values for RRCIN and CRCIN 𝑡discharge = −𝑅on,RCIN ∙ 𝐶RCIN 𝑙𝑛 𝑉th,RCIN− 3.2 V = 40 Ω ∙ 12 nF ∙ 𝑙𝑛 = 0.452 µs 𝑉pu 8.2 V (9) The discharge time is short enough to ensure a safe shut down of the power transistor and a latch of the ITRIP event. Nevertheless, a practical verification by measurements in the system is required. 2.4 Limitations of the proposed solution The limitation of this approach is the discharge condition according to equation (1). The concept of the proposed solution is based on the assumption that the discharge of capacitor CRCIN is faster than the minimum total shut down delay time. This time includes the IC´s minimum shutdown propagation delay tITRIP,min and the power transistor´s minimum turn-off propagation delay t(off),min. This is difficult to achieve for power transistors with a very small current rating. Further limitations are especially other component tolerances, such as the capacitance CRCIN, the temperature influence on resistance RRCIN or the zener voltage tolerances. Application Note AN2015-09 6 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcome the high trigger level of the ITRIP function 3 Overcome the high trigger level of the ITRIP function This section describes how the high trigger level of the overcurrent shut down function can be adapted towards lower levels. 3.1 Application problem The shunt, which is located in the emitter path of a low side IGBT, generates a voltage according to its bias point. This voltage is filtered by means of a RF / CF –combination according to Figure 5. 6ED family – 2nd generation ITRIP COM RF RSH Figure 5 vITRIP CF VIT,HYS= 70mV VIT,TH+= 0.445V VZ=10.5V INPUT NOISE FILTER Comp. To RS-latch ITRIP function The ITRIP trigger level of VIT,th+ = 0.445 V is fixed for the 6EDL family – 2nd generation. The adjustment of the triggering current level is done by adjusting the shunt value, so that the shunt’s voltage will trigger the ITRIP event. However, applications with high load currents will dissipate a considerable power in the shunt. For example, a current trigger level of 50 A would dissipate a power of 50 A ∙ 0.445 V = 22.25 W. Therefore, the current trigger level should result in a low shunt voltage in the area of 100 mV to 200 mV in order to reduce the power dissipated in the shunt. 3.2 Application solution The application solution is implemented by an additional voltage drop over the filter resistor RF. The voltage drop is generated by a current added by a pull up-resistor Rpu according to Figure 6. COM +5V Rpu RF RSH Figure 6 6ED family – 2nd generation ITRIP vITRIP CF VZ=10.5V VIT,HYS= 70mV VIT,TH+= 0.445V Comp. INPUT NOISE FILTER To RS-latch ITRIP function with pre-bias circuit The required voltage drop of the resistor RF is calculated with 𝑉IT,th = 𝑉RF + 𝑉SH,max ⟹ 𝑉RF = 𝑉IT,th − 𝑉SH,max (10) This results in a required pull-up current of 𝐼RF = Application Note AN2015-09 𝑉RF 𝑅F (11) 7 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcome the high trigger level of the ITRIP function Now the pull-up resistor value which provides the current IRF can be calculated 𝑅pu = 3.3 𝑉pu − 𝑉IT,th 𝐼RF (12) Application example The example in this document is based on these conditions and assumptions: The triggering current of an ITRIP event should result in a shunt voltage of 200 mV The pull-up voltage is 5 V RF = 1 kW ( RSH ) The execution of equations (10) - (12) is 𝑉RF = 𝑉IT,th − 𝑉SH,max = 0.445 V − 0.2 V = 0.245 V (13) The pull-up current will be 𝐼RF = 𝑉RF 0.245 V = = 0.245 mA 𝑅F 1 kΩ (14) Now the pull-up resistor value which provides the current IRF can be calculated 𝑅pu = 𝑉pu − 𝑉IT,th 5 V − 0.445 V = ≈ 18.6 kΩ 𝐼RF 0.245 mA (15) A selection of Rpu = 18 kW is possible. The design verification step executes the reworked equations (12) - (10) using the selected component values. 𝐼RF = 𝑉pu − 𝑉IT,th 5 V − 0.445 V = = 0.253 mA 𝑅pu 18 kΩ (16) This results in a voltage drop at the resistor RF of 𝑉RF = 𝐼RF ∙ 𝑅F = 0.253 mA ∙ 1 kΩ = 0.253 V (17) The typical error is smaller than 5% and therefore acceptable with respect to the overall tolerance of the ITRIP function. 3.4 Limitations of the proposed solution The most dominant limitation is the overall tolerance of the ITRIP function. It is of course possible to reduce the triggering shunt voltage of this function. However, the absolute tolerance of ± 65 mV remains. A very precise overcurrent shut down function can´t be achieved with this proposal. Nevertheless, the secure shut down of short circuit events is not jeopardized. Additionally, the ITRIP hysteresis must be considered, so that the largest usable voltage drop over the resistor RF is VIT,th+,min – VIT,hys,typ = 380 mV – 70mV = 310 mV. Therefore, the resulting smallest shunt voltage is 65 mV + 70 mV = 135 mV. An additional margin of approximately 50 mV is recommended in order to ensure a proper power up. Application Note AN2015-09 8 <Revision 2>, <2015-07-13> Tips & Tricks for RCIN and ITRIP Overcome the high trigger level of the ITRIP function References [1] Infineon Technologies: 6EDL family – 2nd generation; Datasheet; Infineon Technologies, Neubiberg, Germany. [2] Infineon Technologies: 6EDL family – 2nd generation Technical description; Application Note ANEICEDRIVER-6EDL04-1; Infineon Technologies, Neubiberg, Germany. [3] Infineon Technologies: IKD06N60RF; Datasheet; Infineon Technologies, Neubiberg, Germany. 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