ICE3AXX65ELJ design guide

Application Note, V1.1, November 2009
I C E 3 A xx 6 5 EL J
CoolSET®-F3 Latch & Jitter version
Design Guide
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
Edition 2009-11-01
Published by Infineon Technologies Asia Pacific,
8 Kallang Sector,
349282 Singapore, Singapore
© Infineon Technologies AP 2008.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee
of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types
in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be expected to
cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or
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and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
ICE3Axx65ELJ
Revision History:
2009-11
Previous Version:
V1.0
Page
Subjects (major changes since last revision)
9
Add precaution for the start up sequence.
V1.1
®
ICE3Axx65ELJ CoolSET -F3 Latch & Jitter version Design Guide:
License to Infineon Technologies Asia Pacific Pte Ltd
Kyaw Zin Min
Kok Siu Kam Eric
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AN-PS0030
ICE3Axx65ELJ
Table of Contents
Page
1
Introduction ...................................................................................................................................5
2
List of Features .............................................................................................................................5
3
Package & pin assignment...........................................................................................................6
4
Block Diagram ...............................................................................................................................7
5
Typical Application Circuit...........................................................................................................8
6
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
Function Description ....................................................................................................................9
Startup Cell......................................................................................................................................9
Soft Start and Normal Operation.....................................................................................................9
Active Burst Mode .........................................................................................................................10
Entering Active Burst Mode...........................................................................................................10
Working in Active Burst Mode .......................................................................................................11
Leaving Active Burst Mode ...........................................................................................................12
VCC supply during burst mode .......................................................................................................13
Switching frequency modulation ...................................................................................................13
Propagation delay compensation..................................................................................................14
Protection Features .......................................................................................................................14
Auto Restart Mode ........................................................................................................................15
Latched Off Mode..........................................................................................................................15
Blanking Time for over load protection .........................................................................................16
7
Layout Consideration .................................................................................................................17
8
CoolSET -F3 ICE3Axx65ELJ product list .................................................................................17
9
Useful formula & external component design .........................................................................17
10
References ...................................................................................................................................18
®
Application Note
4
2009-11-01
ICE3Axx65ELJ
1
Introduction
rd
®
The ICE3Axx65ELJ is the further development of the 3 generation CoolSET . It is a PWM controller with
power MOSFET together in a DIP-8 package. The switching frequency is running at 100 KHz and it targets
for DVD player, set-top box, portable game console, auxiliary power supply, etc.
The ICE3Axx65ELJ adopts the BiCMOS technology and provides a wider Vcc operating range up to 26V. It
®
inherits the proven good features of CoolSET -F3 such as the active burst mode achieving the lowest
standby power, the propagation delay compensation making the most precise current limit control in wide
input voltage range, etc. In addition, it also adds on some useful features such as built-in soft start time, builtin basic with extendable blanking time for over load protection and built-in switching frequency modulation (
frequency jittering ), external latch enable, etc. Furthermore, it has implemented with enhanced noise
immunity feature such that it can pass 20KV ESD test (contact discharge) and 8KV lightning surge test.
In this application note, functions of the device are described in detail with formula and its performance is
shown with test waveforms. The description of other related information such as DCM/CCM mode operating
principles and slope compensation and the detailed design procedure are shown in the application note “ANSMPS-ICE2xXXX-1”.
2
List of Features
®
650V avalanche rugged CoolMOS with built in switchable Startup Cell
Active Burst Mode for lowest Standby Power
BiCMOS technology provide wide Vcc voltage range
Fast load jump response in Active Burst Mode
100kHz fixed switching frequency with frequency modulation
Latched Off mode for over temperature, Vcc over voltage and short winding protection
Auto Restart Mode for over load protection, Open Loop protection and Vcc under voltage protection
Built-in soft start time
Built-in and extendable blanking window for short duration peak power
External latch enable feature
Propagation delay compensation tighten the maximum power control between high line and low line
Switching frequency modulation and soft gate driving for low EMI
Robustness to system noise such as ESD, lightning surge, etc.
Application Note
5
2009-11-01
ICE3Axx65ELJ
3
Package & pin assignment
®
The package for CoolSET -F3 Latch and Jitter mode product is DIP-8.
BL
1
8
GND
FB
2
7
VCC
CS
3
6
n.c.
Drain
4
5
Drain
Pin
Symbol
1
BL
extended Blanking & Latch enable
2
FB
FeedBack
3
CS
Current Sense / 650V CoolMOS Source
4
Drain
650V CoolMOS Drain
5
Drain
650V CoolMOS Drain
6
n.c.
not connected
7
VCC
controller supply Voltage
8
GND
controller GrouND
Figure 1
Function
1
1
®
1
®
®
DIP-8 package
1
Tj=110°C
Application Note
6
2009-11-01
ICE3Axx65ELJ
4
Block Diagram
Figure 2
Block Diagram of CoolSET -F3 ICE3Axx65ELJ
Application Note
®
7
2009-11-01
ICE3Axx65ELJ
5
Typical Application Circuit
Figure 3
Typical application circuit with CoolSET -F3, ICE3A1065ELJ 15W 5V
Application Note
®
8
2009-11-01
ICE3Axx65ELJ
6
Function Description
6.1
Startup Cell
The Startup Cell delivers a constant charge current of IVCCcharge3=0.7mA to charge up the VCC capacitor CVcc
at VCC pin. When VCC exceeds the on-threshold VCCon=18V, the bias circuit is switched on. The Startup Cell is
switched off to reduce the power loss. The startup delay time, tDELAY, is independent from the AC line input
voltage. It can be estimated by the Equation(1).
t DELAY =
VVCCon ⋅ CVcc
IVCCch arg e3
(1)
Figure 4 shows the startup time delay at 85VAC input. ( Pls refer to the datasheet for the symbol used in the
equation )
Vds
0.6s
Vcc
Vfb
Figure 4
The startup delay time at AC line input voltage of 85VAC
Precaution : For a typical application, start up should be VCC ramps up first, other pin (such as FB pin)
voltage will follow VCC voltage to ramp up. It is recommended not to have any voltage on other
pins (such as FB; BA and CS) before VCC ramps up.
6.2
Soft Start and Normal Operation
When the IC is turned on after the Startup Delay time, a digital soft start circuit is activated. A gradually
increased soft start voltage is released by the digital soft start circuit, which in turn increases the duty cycle
accordingly. The soft start control voltage is increased with the increasing of count number in the digital
counter of the soft start circuit. The soft start time is set at 20ms. When the soft start time ends, IC goes into
normal mode and the duty cycle is dependent on the FB signal. Figure 5 shows the soft start behaviour at
85VAC input. It can be seen that the primary peak current slowly increase to the maximum in the soft start
period. After soft start stage, IC goes into normal operation with the conventional primary peak current
control scheme. Please refer to “AN-SMPS-ICE2xXXXX-1” for the details of normal operation.
Application Note
9
2009-11-01
ICE3Axx65ELJ
Vout
Vcc
Vfb
1V
20ms
Vcs
Figure 5
Soft start at AC line input voltage of 85VAC
6.3
Active Burst Mode
The IC provides an Active Burst Mode function at no load or low load conditions to enable the system to
achieve the lowest standby power requirement of less than 100mW. Active Burst Mode means the IC is
always in the active state and can therefore immediately response to any changes on the FB signal, VFB.
6.3.1
Entering Active Burst Mode
Because of the current mode control scheme, the feedback voltage VFB actually controls the power delivery
to output. When the output load is getting lower, the feedback voltage VFB drops. If it stays below 1.35V for a
period of 20ms, the IC enters the burst mode operation. The threshold power to enter burst mode can be
estimated in Equation(2).
PBURST _ enter = 0.5 ⋅ LP ⋅ (
VFBC 5 − VOffset − Ramp
Rsense ⋅ AV
) 2 ⋅ f SW
(2)
where, LP is the transformer primary inductance, VFBC5=1.35V is the feedback voltage at which the system
starts to burst, VOffset-Ramp=0.6V is the maximum level of the internal Voltage Ramp on which the amplified
current ramp signal of the PWM-OP is superimposed, AV=3.2 is the internal PWM-OP gain, Rsense is the
current sense resistor, fSW is the switching frequency. Figure 6 shows the test waveform with the load drop
from full load to light load. After blanking time IC goes into burst mode.
Application Note
10
2009-11-01
ICE3Axx65ELJ
Vds
Vout
19.3ms
Vfb
Figure 6
Entering Burst Mode
6.3.2
Working in Active Burst Mode
During active burst mode, the IC is constantly monitoring the output voltage by feedback pin, VFB, which
controls burst duty cycle and burst frequency. The burst “on” starts when VFB reaches 3.61V and stops when
VFB is down to 3.0V. During burst “on”, the primary current limit is set to only 31% of maximum peak current
(VCS=0.31V) to reduce the conduction losses and to avoid audible noise. The FB voltage is changing like a
saw-tooth between 3.0V and 3.61V.The corresponding secondary output ripple (peak to peak) is regulated in
Equation(3).
Vout _ ripple _ pp =
Ropto
RFB ⋅ Gopto ⋅ GTL 431
⋅ ∆VFB
(3)
where, Ropto is the resistor in series with opto-coupler at the secondary side to limit the opto-coupler current,
RFB is the IC internal pull up resistor connected to FB Pin (refer to Figure 2), Gopto is the current transfer gain
of opto-coupler, GTL431 is the voltage transfer gain between the comparator TL431 output and Vout,
∆VFB=3.61-3.0=0.61V is the saw-tooth voltage on the VFB during burst operation.
The leaving burst power threshold, i.e. maximum power to be handled during burst operation is showed in
Equation(4).
Pburst _ max = 0.5 ⋅ LP ⋅ (0.31 ⋅ i peak _ max ) 2 ⋅ f SW = 0.5 ⋅ LP ⋅ (0.31 ⋅
VCS _ max
Rsense
) 2 ⋅ f SW = 0.0961 ⋅ Pmax
(4)
Where, ipeak_max is the maximum primary peak current, VCS_max is the cycle by cycle current limit threshold at
CS pin, Pmax is the maximum output power of the power supply. It can be seen that the maximum power in
burst mode is around 9.61% of Pmax. Figure 7 shows the waveform of burst mode at light load. It can be seen
that the burst ripple is well regulated to be 40mV and it is independent on the output power.
Application Note
11
2009-11-01
ICE3Axx65ELJ
Vds
Vout
40mV
Vfb
Figure 7
In Burst Mode at light load
6.3.3
Leaving Active Burst Mode
When the output load is increasing to be higher than Pburst_max, Vout will drop a little bit and VFB will rise up fast
to 4.5V. The system leaves burst mode immediately when VFB reaches 4.5V. Once system leaves burst
mode, the current sense voltage limit, VCS_MAX, is released to 1V, the feedback voltage VFB swings back to
the required level. The timing diagram of leaving burst mode is shown in Figure 8.
4.5V
3.61V
VFB
3.0V
Vout
Vout_AV
Vout_drop_max
1V
VCS
0.31V
Figure 8
the timing diagram of leaving burst mode
The maximum Vout drop during the mode transition is estimated in Equation(5).
Vout _ drop _ max =
Ropto
RFB ⋅ Gopto ⋅ GTL 431
Application Note
⋅ ( 4 .5 −
1.195 ⋅ Ropto
3.0 + 3.61
)=
2
RFB ⋅ Gopto ⋅ GTL 431
12
(5)
2009-11-01
ICE3Axx65ELJ
Figure 9 shows the waveform to leave burst mode with load jump from light load to full load. The output
voltage drop during the transition is about 140mV.
Vout
140mV
Vfb
Vcs
Figure 9
Scope waveform of leaving burst mode
6.3.4
VCC supply during burst mode
The supply voltage for VCC has to be designed so that it always stays above VVCCoff limit during burst mode,
especially at no load. If there is a substantial high voltage at VCC pin during maximum load operation, it
should add a voltage clamp circuit to absorb the high surge voltage. The circuit configuration for VCC in
Figure 3, which consists of C5, R3, R5, R6, ZD1 and C6, is to ensure the VCC will not exceed 26V under any
operation conditions.
6.4
Switching frequency modulation
The IC is running at fixed frequency of 100KHz with jittering frequency at +/-4KHz in a switching modulation
period of 4ms. This kind of frequency modulation can effectively help to obtain a low EMI level. The
measured jittering frequency is 94.5KHz ~ 102.06KHz ( Figure 10 ).
Vds
102.06KH
94.5KHz
Figure 10
Switching frequency jittering
Application Note
13
2009-11-01
ICE3Axx65ELJ
6.5
Propagation delay compensation
It is observed that the maximum input power will change with input voltage. This is due to the propagation
delay of the controller in different dI/dt of the input voltage. The power difference can be as high as >14%
nd
between high line and low line. Starting from our 2 generation, a propagation delay compensation network
is implemented so that the power difference is greatly reduced to best around 2%. A measured result for this
15W demo boards shows an output power difference of around +/-3.25% between 85Vac and 269
Vac input. Figure 11 shows the propagation delay compensation curve implemented to the IC. This function
applies to discontinuous conduction mode flyback converter only.
without compensation
with compensation
V
1,3
1,25
VSense
1,2
1,15
1,1
1,05
1
0,95
0,9
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
V
µs
dVSense
dt
Figure 11
Propagation delay compensation curve
6.6
Protection Features
The IC provides several protection features which lead to the Auto Restart Mode or Latched off mode. The
following table lists the conditions of the system faults and the associate protection mode.
Protection functions
Failure condition
Protection Mode
VCC Over voltage
VCC > 24V and VFB > 4.5V
Latched off
Over temperature
( controller )
Short Winding/
Short Diode
External latch enable
Output Overload /
Output Short Circuit
Open Loop
−> Output Over Load
Auto Restart
VCC Undervoltage / short
Opto-coupler
VCC < 10.5V
Auto Restart
Application Note
O
TJ > 130 C
Latched off
VCS > 1.66V
Latched off
VBL < 0.1V
VFB > 4.5V and VBL > 4.0V
( after built-in / extended blanking time )
Latched off
14
Auto Restart
2009-11-01
ICE3Axx65ELJ
6.6.1
Auto Restart Mode
There is always a startup phase with switching pulses in the Auto Restart Mode. After this startup phase the
fault conditions are checked. If the fault persists, it would continue the auto-restart mode. Otherwise, it would
resume to normal mode.
Figure 12 shows the switching waveform of the VCC and the feedback voltage VFB when the output is shorted
to ground. The IC turns on when the VCC reaches 18V. It then start the startup phase. However, the IC is off
again due to the fault still persists. The VCC is discharged until 10.5V. Then, the Startup Cell is activated
again to charge up capacitor at VCC to 18V. Then it initiates another restart cycle.
Vds
Vcc
Vfb
Vbl
Figure 12
Auto Restart Mode ( without extended blanking time )
6.6.2
Latched Off Mode
In case of Latched Off Mode, there is no new startup phase any more. Once Latched Off Mode is entered,
the internal Voltage Reference is switched off in order to reduce the current consumption of the IC. In this
stage only the UVLO circuit is working which switches on/off the startup cell at VCCon/VCCoff. Latched Off Mode
can only be reset when AC line input is removed and the VCC is discharged to lower than 6.23V.
Vds
Vcc
Vfb
Vbl
Figure 13
Latch off Mode ( VBL < 0.1V )
Application Note
15
2009-11-01
ICE3Axx65ELJ
6.6.3
Blanking Time for over load protection
The IC controller provides a blanking window before entering into the auto restart mode due to output
overload/short circuit. The purpose is to ensure that the system will not enter protection mode unintentionally.
There are 2 kinds of the blanking time; basic and the extendable. The basic one is a built-in feature which is
set at 20ms. The extendable one is to extend the basic one with a user defined additional blanking time. The
extendable blanking time can be achieved by adding a capacitor, CBK to the BL pin. When there is over load
occurred (VFB > 4.5V), the CBK capacitor will be charged up by an constant current source, IBK ( 8.4uA ) from
0.9V to 4.0V. Then the auto restart protection will be activated. The charging time from 0.9V to 4.0V to the
CBK capacitor is the extended blanking time. The total blanking time can be calculated by the Equation(6).
Tblanking = Basic + Extended = 20ms +
(4.0 − 0.9) * CBK
= 20ms + 369047.6 * CBK
IBK
(6)
The measured total blanking time showing in figure 14 is 125ms using CBK=0.22uF.
In case of output overload or short circuit, the transferred power during the blanking period is limited to the
maximum power defined by the value of the current sense resistor Rsense.
Vout
20ms
Vfb
Vbl
Iout
Figure 14
Blanking window for over load protection ( basic blanking time )
Vout
Vfb
20ms
105ms
Vbl
Iout
Figure 15
Blanking window for overload protection ( with extended blanking time, CBK=0.22uF )
Application Note
16
2009-11-01
ICE3Axx65ELJ
7
Layout Consideration
®
In order to get the optimized performance of the CoolSET -F3, the grounding of the PCB layout must be
®
connected carefully. From the circuit diagram in Figure 3, it indicates that the grounding for the CoolSET -F3
can be split into several groups; signal ground, Vcc ground, Current sense resistor ground and EMI return
ground. All the split grounds should be “star” connected to the bulk capacitor ground directly. The split
grounds are described as below.
®
•
Signal ground includes all small signal grounds connecting to the CoolSET GND pin such as filter
capacitor ground, C6, C7, C8 and opto-coupler ground.
•
Vcc ground includes the Vcc capacitor ground, C5 and the auxiliary winding ground, pin 2 of the power
transformer.
•
Current Sense resistor ground includes current sense resistor R4 and R4A.
•
EMI return ground includes Y capacitor, C4.
CoolSET®-F3 ICE3Axx65ELJ product list
8
Device
Package
VDS
Current /A
Rdson /Ω1
Frequency /
KHz
Pout
Pout
2
Vin=230Vac±15%
Vin=85-265Vac 2
ICE3A1065ELJ
PG-DIP-8
650V
1.0
2.95
100
32W
16W
ICE3A2065ELJ
PG-DIP-8
650V
2.0
0.92
100
57W
28W
9
Useful formula & external component design
Transformer calculation ( DCM flyback)
Vin_min = 90Vdc, Vin_max = 380Vdc,
Input data
Vds_max = 470V for 600V MOSFET,
Dmax ≤ 50%
Turn ratio
N ratio =
Maximum Duty ratio
Dmax =
Vds _ max − Vin _ max
Vout + Vdiode
(Vout + Vdiode ) ⋅ N ratio
Vin _ min + (Vout + Vdiode ) ⋅ N ratio
(Vin _ min ⋅ Dmax ) 2
Primary Inductance
Lp
Primary peak current
I p _ max =
Primary turns
Np ≥
≤
2 ⋅ Pin ⋅ f sw
Vin _ min ⋅ Dmax
L p ⋅ f sw
I p _ max ⋅ L p
Bmax ⋅ Amin
1
Typ @ 25°C
2
Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink.
Application Note
17
2009-11-01
ICE3Axx65ELJ
Np
Secondary turns
Ns =
Auxiliary turns
N aux =
N ratio
Vcc + Vdiode
⋅ Ns
Vout + Vdiode
ICE3AXX65ELJ external component design
Vcsth _ max
Current sense resistor
Rsense ≤
Soft start time
t soft = 20ms
Vcc capacitor
CVCC =
Startup time
t STARTUP =
Enter burst mode power
Pburst _ enter =
Leave burst mode power
Pburst _ max = 0.0961 ⋅ Pin _ max
Output ripple during burst mode
Vout _ ripple _ pp =
Voltage drop when leave burst mode
Vout _ drop _ max =
Total blanking time for over load
protection
tblanking = 20ms + 369047.6 ⋅ C BK
10
I p _ max
I VCC sup 2 ⋅ t soft 2
⋅
VCCHY
3
VVCCon ⋅ CVcc
I CCch arg e3
VFB _ enter − VOffset − Ramp 2
1
⋅ LP ⋅ (
) ⋅ f SW
2
Rsense ⋅ AV
Ropto
RFB ⋅ Gopto ⋅ GTL 431
⋅ ∆VFB
1.195 ⋅ Ropto
RFB ⋅ Gopto ⋅ GTL 431
References
®
[1]
Infineon Technologies, Datasheet “CoolSET -F3 ICE3A1065ELJ Off-Line SMPS Current Mode
®
Controller with Integrated 650V CoolMOS and Startup Cell (Latched and Frequency Jitter Mode)”
[2]
Kyaw Zin Min, Eric Kok Siu Kam, Infineon Technologies, Application Note “AN-EVALSF3®
ICE3A1065ELJ, 15W 5.0V SMPS Evaluation Board with CoolSET -F3 ICE3A1065ELJ “
[3]
Harald Zoellinger, Rainer Kling, Infineon Technologies, Application Note “AN-SMPS-ICE2xXXX-1,
TM
CoolSET ICE2xXXXX for Off-Line Switching Mode Power Supply (SMPS )”
Application Note
18
2009-11-01