A8501
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
Features and Benefits
Description
▪ 600 kHz to 2.2 MHz switching frequency—ability to
operate above the AM band
▪ Internal bias supply for single-supply operation (VIN = 6.8 to 21 V)
▪ Boost converter with integrated 40 V DMOS switch and
OVP–load-dump protection
▪ 3.5 μA shutdown current—limits battery drain
▪ Active current sharing between LED strings for
0.8% current matching and 0.7% accuracy
▪ Drive up to 9 series LEDs in 4 parallel strings, 36 LEDs
maximum (Vf = 3.5 V, If = 100 mA)
▪ LED sinks rated for 100 mA each (400 mA total)
▪ PWM dimming with LED PWM duty cycle control
▪ 4000:1 dimming range
▪ Extensive fault mode protection schemes:
▫ Shorted LED protection against misconnected loads—
with true output disconnect
▫ Open LED disconnect protects against LED failures
▫ External thermistor sensing to limit LED temperature
▫ Output overvoltage protection (OVP): 19.5 V default can
be adjusted as high as 38 V
▫ Open Schottky and open OVP resistor protection against
external component failure
▫ Input under- and overvoltage protection (UVLO and
OVLO) against VIN variation
▫ Boost current limit, output short circuit limit,
overtemperature protection (OTP), and soft start
The A8501 is a multioutput WLED/RGB driver for backlighting
medium-size displays. The A8501 integrates a boost converter
and four 100 mA current sinks. LED channels can be tied
together for up to 400 mA sink capability. It can work from a
single power supply of 6.8 to 21 V and withstand up to 40 V.
The boost converter is a constant frequency, current-mode
converter.
Operating frequency can be set to 2 MHz in order to avoid
interference with the AM radio band. The integrated boost
DMOS switch is rated for 40 V at 3.6 A. PWM dimming allows
LED currents to be controlled at up to a 1000:1 ratio. Additional
4:1 dimming can be achieved by using the DIM pin.
The A8501 provides protection against output connector shorts
through an integrated output disconnect switch. An optional
external thermistor can be used to limit LED current based on
panel temperature.
The device is supplied in a surface mount, 28-pin TSSOP
package (suffix LP), with exposed thermal pad for enhanced
thermal dissipation. It is lead (Pb) free, with a leadframe
plating choice of 100% matte-tin (suffix T) or tin-bismuth
(suffix B).
Applications include:
▪ GPS navigation systems
▪ Automotive infotainment
▪ Back-up camera displays
▪ Cluster backlighting
▪ Portable DVD players
▪ Industrial LCD displays
Package:
28-pin TSSOP with
exposed thermal pad
(package LP)
Not to scale
Typical Application
D1
VBAT
CBAT
4.7 μF
35 V
Figure 1. LCD monitor backlight driving
4 LED strings. On/off and dimming
control using ENABLE pin.
• Current = 50 mA per string
• OVP = 35 V nominal
• Switching frequency = 2 MHz
VIN
CCOMP
1 μF
10 V
COUT
4.7 μF
50 V
ROVP
78.7 kΩ
SW SW SW
OVP CAP
OUT
COMP
DIM
FSET
A8501
CBIAS
0.1 μF
10 V
VTO
RVC
VTI
–t°
Optional Configuration
for Thermal Derating
8501-DS, Rev.4
CIN
EN
A8501
NTC
L1
10 μH
RISET
24.3 kΩ
BIAS
SEL2
PAD
NC
SEL1
LED1
VTO
LED2
VTI
LED3
LED4
ISET
AGND PGND PGND PGND LGND DGND
RFSET
25.5 kΩ
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Selection Guide
Part Number
Operating
Temperature, TA
A8501ELPTR-T
A8501GLPTR-T
A8501KLPTR-B
A8501KLPTR-T
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
–40°C to 125°C
Packing
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
Package
Leadframe Plating
28-pin TSSOP with exposed thermal pad
28-pin TSSOP with exposed thermal pad
28-pin TSSOP with exposed thermal pad
28-pin TSSOP with exposed thermal pad
100% matte tin
100% matte tin
Tin-Bismuth
100% matte tin
Absolute Maximum Ratings*
Characteristic
Symbol
Rating
Units
SW, OVP, CAP, OUT Pins
–0.3 to 40
V
LED1 through LED4 Pins
–0.3 to 21
V
–0.3 to 34
V
40
V
–0.3 to 6
V
–0.3 to 7
V
VIN Pin
VIN
DIM Pin
VDIM
Notes
Steady state
Transient < 1 s
Remaining Pins
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
Tstg
Storage Temperature
Range E
–40 to 85
ºC
Range G
–40 to 105
ºC
Range K
–40 to 125
ºC
150
ºC
–55 to 150
ºC
*Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
4-layer PCB based on JEDEC standard
Value
Units
28
ºC/W
*Additional thermal information available on Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Functional Block Diagram
SW SW SW
VIN
BIAS
Regulator
Bias Supply
CAP
Overvoltage
Comparators
Internal
Supply
FSET
OVP
Charge
Pump
Boost
OUT
Overcurrent
Comparators
OSC
+
–
PGND
Feedback
Control
COMP
SEL1
Device
Control
SEL2
EN
Current Sinks
Open LED Detect
and Disconnect
OVP Fault
2.46 V
LED2
Shorted LED Detect
100 kΩ
VTO
LED1
÷2
VTI
1.23 V
Minimum
Select
LED Current
Reference
LED3
÷4
LED4
References
+
–
100 kΩ
ISET
AGND
PGND
PGND
PGND
LGND
DGND
DIM
PAD
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Pin-out Diagram
28 EN
BIAS 1
DGND 2
27 SEL2
DIM 3
26 SEL1
SW 4
25 PGND
SW 5
24 PGND
SW 6
OVP 7
CAP 8
AGND 9
ISET 10
PAD
23 PGND
22 NC
21 VIN
20 COMP
19 FSET
VTI 11
18 OUT
VTO 12
17 LED4
LED1 13
16 LED3
LED2 14
15 LGND
Terminal List Table
Number
Name
Function
1
BIAS
2
DGND
Output of internal 6 V bias supply. Decouple with a 0.1 μF ceramic capacitor to DGND.
3
DIM
4, 5, 6
SW
DMOS switch drain node. Tie these three pins together on the PCB.
7
OVP
To enable overvoltage protection, connect this pin through a resistor to the CAP pin. The default OVP level, with 0 Ω resistor,
is 19.5 V. External resistor can set OVP up to 38 V.
8
CAP
Input connection for output disconnect switch.
Digital signal ground. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.
Sets ILED by adjusting the ISET to ILEDx current gain, AISET . When DIM = VIL , AISET = 960 and when DIM=VIH , AISET = 240.
9
AGND
10
ISET
Analog signal ground. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.
11
VTI
ISET voltage override. Sets the ISET voltage when VTI < 1.23 V. Tie directly to VTO pin to disable this feature. This pin can
be used for LED current thermal derating or external analog LED current control. See the Typical Application Circuits section
for additional information.
12
VTO
2.46 V output voltage. Use this voltage to bias an external NTC resistor or as a DAC reference. This pin can be used as a
logic high signal for the SEL and DIM pins.
13,14,16,17
LEDX
LED current sinks.
15
LGND
Power ground for LED current sinks. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.
Sets the 100% current level through LED strings. Set by value of RISET connected between ISET and AGND.
18
OUT
Output connection for output disconnect switch. Connect LED common connection to this pin.
19
FSET
Connect RFSET between FSET and AGND to set boost switching frequency.
20
COMP Sets boost loop compensation. Connect external compensation capacitor between COMP and AGND for boost converter stability.
21
VIN
Input supply for the device. Decouple with a 0.1 μF ceramic capacitor.
Not connected internally. It is recommended to connect this pin to external ground.
22
NC
23, 24, 25
PGND
26
SEL1
27
SEL2
28
EN
Enable and PWM LED current control. Apply logic-level PWM for PWM-controlled dimming mode.
–
PAD
Exposed thermal pad. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection. Connect to PCB
copper layer for enhanced heat dissipation.
Power ground. Connect AGND, DGND, LGND, PGND, and PAD using star ground connection.
SEL1 and SEL2 together select which LED strings are enabled. See Functional Description section.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
ELECTRICAL CHARACTERISTICS Valid using circuit shown in figure 1; VIN = 12 V, EN = SEL1 = SEL2 =5 V, RISET = 12.4 kΩ,
RFSET = 24.3 kΩ, VTO shorted to VTI guaranteed over the full operating temperature range with TA =TJ , typical specifications are at
TA = 25ºC; unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
8
–
21
V
V
General
Input Voltage Range
VIN
Undervoltage Lockout Threshold
VUVLO(th)
UVLO Hysteresis Window
VUVLO(hys)
Overvoltage Lockout Threshold
VOVLO(th)
Supply Current
IS
VIN falling
5.7
6.5
6.8
0.21
0.55
0.81
V
VIN rising
29
32
34
V
2 MHz switching at no load
4
11
15
mA
EN = VIL, in shutdown, TA = 25°C,
CAP = VIN = SW = OVP = 16 V
IS = IVIN + ISW + ICAP + IOVP
–
3.5
6
μA
EN = VIL, in shutdown, TA = –40°C to 125°C,
CAP = VIN = SW = OVP = 16 V,
IS = IVIN + ISW + ICAP + IOVP
–
3.5
10
μA
EN = VIL, not in shutdown, IS = IVIN
–
2
4
mA
Logic Input levels (DIM, EN, SELx Pins)
Input Voltage Level-Low
VIL
–
–
0.4
V
Input Voltage Level-High
VIH
1.5
–
–
V
Input Leakage Current (EN, DIM pins)
Ilkg1
VDIM, VEN = 5 V
30
50
70
μA
Input Leakage Current (SELx pins)
Ilkg2
VSELx = 5 V
–
–
1
μA
OVP pin connected to OUT pin
18
19.5
21
V
Overvoltage Protection
Output Overvoltage Threshold
OVP Sense Current
OVP Leakage Current
VOVP(th)
183
200
217
μA
VOVP = 18 V, EN = VIL, in shutdown
–
0.1
1
μA
ISW = 2 A
40
100
300
mΩ
VSW = 21 V
–
0.1
10
μA
3
3.6
5.3
A
IOVPH
IOVP(lkg)
Boost Switch
Switch On Resistance
RSWDS(on)
Switch Leakage Current
ISW(lkg)
Switch Current Limit
ISW(lim)
LED Current Sinks
LEDx Regulation Voltage
VLED
IISET to ILEDx Current Gain
AISET
ISET Pin Voltage
VISET
VTO Pin Voltage
VTO Pin Current Maximum
VTO
IISET = 100 μA, DIM = VIL
IISET = 100 μA, DIM= VIH
–
750
1100
mV
914
960
1008
A/A
228
240
252
A/A
1.13
1.235
1.34
V
IVTO = 1 mA
2.00
2.46
2.65
V
ITO(max)
IVTO increased until VTO drops by 1%
1.5
2.4
5
mA
VTI(falling)
VTI start >1.34 V, VTI pin voltage decreasing
before control changes to VTI pin
1.00
1.12
1.23
V
VTI(rising)
VTI start <1 V VTI pin increasing before
changing to internal reference
1.13
1.235
1.34
V
20
–
100
μA
VTI Pin Voltage
ISET Pin Allowable Current Range
VLED1 = VLED2 = VLED3 = VLED4
IISET
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
ELECTRICAL CHARACTERISTICS (continued) Valid using circuit shown in figure 1; VIN = 12 V, EN = SEL1 = SEL2 =5 V, RISET = 12.4 kΩ,
RFSET = 24.3 kΩ, VTO shorted to VTI, guaranteed over the full operating temperature range with TA =TJ , typical specifications are at
TA = 25ºC; unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
LEDx Accuracy1
ErrLED
RISET = 12.4 kΩ. 100% current ratio, measured
as the average of VLEDx , for LED1 through
LED4, with VLEDx = 0.75 V, TA =TJ = 0 to 125°C
–
0.7
3
%
LEDx Matching2
∆LEDx
IISET = 100 μA, 100% current ratio, with
VLEDx = 0.75 V
–
0.8
3
%
IS(lkg)
LED Switch Leakage Current
VLEDx = 17.5 V, EN = VIL = 0 V
4.8
8.75
12.8
μA
LEDx Short Detect Voltage Threshold
VLEDSC
On any LEDx pin, forces latched shutdown
17.5
19
21
V
Output Disconnect Switch
On-Resistance
RODS(on)
VIN = 8 V, IOUT = 400 mA, TJ = 125°C
–
2
4
Ω
RFSET = 24.3 kΩ
1.14
1.235
1.33
V
RFSET = 24.3 kΩ
1.8
2.1
2.4
MHz
RFSET = 51.1 kΩ
0.850
1
1.285
MHz
RFSET = 84.5 kΩ
0.5
0.6
0.8
MHz
Oscillator
FSET Pin Voltage
VFSET
Frequency
fOSC
Minimum Switch Off-Time
toff(min)
–
60
110
ns
Minimum Switch On-Time
ton(min)
–
60
110
ns
0.4
0.6
0.75
A
Soft Start
Soft Start Boost Current Limit
ISWSS(lim)
Initial soft start current for boost switch
ILEDSS
Current through each enabled LEDx pin during
soft start, RISET =12.4 kΩ
3
5
10
mA
Maximum PWM Dimming Off-Time
tPWML
Measured while EN = low, during dimming
control, and internal references are powered on
(exceeding tPWML results in shutdown)
–
131,072
–
fSW cycles
Minimum PWM On-Time
tPWMH
–
–
6
μs
Soft Start LEDx Current
PWM Timing on EN pin
PWM High to LED On Delay
tdPWM(on)
Time between PWM enable and when LED
current reaches 90% of maximum, with internal
references enabled and tPWML not exceeded
–
3
–
μs
PWM Low to LED Off Delay
tdPWM(off)
Time between EN going low and when LED
current reaches 10% of maximum, with internal
references enabled and tPWML not exceeded
–
0.5
–
μs
150
172
195
°C
15
20
25
°C
Thermal Shutdown Threshold3
Thermal Shutdown
Hysteresis3
TTSD
TTSD(hys)
Device temperature rising
1LED
accuracy is defined as (IISET × 960 – ILED(av)) / (IISET × 960), ILED(av) measured as the average of ILED1 through ILED4.
2LED current matching is defined as (I
LEDx – ILED(av)) / ILED(av), with ILED(av) as defined in footnote 1.
3Guaranteed by design and characterization, functional tested in production.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
Electrostatic Discharge Structures
Equivalent ESD on Pins
VIN / VBIAS
VIN
DIM
CAP / OUT
DIM
CAP
60 V
6V
VBIAS
100 kΩ
40 V
7V
OUT
DGND
DGND
SW
VIN / FSET
SW
VIN
40 V
DGND
AGND, LGND, PGND, and DGND
xGND
35 V
FSET
40 to 60 V
10 V
DGND
PGND
DGND
ISET, VTO, and VTI
VTI
LEDx
LEDx
OVP
OVP
VTO
ISET
12 V
23 V
12 V
12 V
44 V
6V
DGND
DGND
DGND
SEL1, SEL2, and EN
COMP
EN
COMP
SEL2
7V
SEL1
12 V
12 V
12 V
DGND
6V
DGND
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
PWM Waveforms
VBAT = 12 V, IOUT = 400 mA, fPWM = 200 Hz
4 channels enabled, 6 LEDs each channel
50% PWM Duty Cycle (Startup)
C1
C2
C3
VPWM
VOUT
IOUT
IBAT
C4
t
Symbol
C1
C2
C3
C4
t
Parameter
VBAT
VOUT
IOUT
IBAT
time
Units/Division
5V
20 V
500 mA
500 mA
20 ms
1% PWM Duty Cycle (Startup)
C1
C2
C3
VPWM
VOUT
IOUT
IBAT
C4
t
Symbol
C1
C2
C3
C4
t
Parameter
VPWM
VOUT
IOUT
IBAT
time
Units/Division
5V
20 V
500 mA
500 mA
100 ms
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
Startup Waveforms
Soft Start Turn On Using Rising VBAT
VBAT = 12 V, IOUT = 400 mA
4 channels enabled, 6 series LEDs each
A
C1
C2
BC
D
E
F
VBAT
Symbol
C1
C2
C3
C4
t
IBAT
VOUT
Parameter
VBAT
IBAT
VOUT
IOUT
time
Units/Division
10 V
500 mA
20 V
500 mA
5 ms
Parameter
VBAT
VOUT
IOUT
IBAT
time
Units/Division
5V
20 V
500 mA
500 mA
2 ms
C3
C4
IOUT
A
BC
D
t
E
F
A.
VBAT voltage slowly increased with EN held high.
A–B. Input bulk capacitor CBAT and boost output capacitor COUT are charged to
VUVLO .
B.
VBAT reaches VUVLO, and enables A8501 through soft start.
B–C. During soft start period, boost switch peak current is limited to 600 mA and
LED current to 1/20 of desired level. Narrow current spike at B is due to
parasitic capacitance from OUT to ground and CBIAS. COMP pin is help low
during soft start.
D.
After VOUT reaches a level such that all LED pins > 0.75 V, the A8501
comes out of soft start.
C–E. After initial rise of VOUT , the capacitor CCOMP starts charging slowly (CCOMP
not shown).
E.
VCOMP reaches desired level for stable operation.
F.
A8501 and LEDs reach thermal steady state.
Turn On Using EN Pin
VBAT = 8 V, IOUT = 400 mA
4 channels enabled, 6 series LEDs each
C1
C2
C3
VEN
Symbol
C1
C2
C3
C4
t
VOUT
IOUT
IBAT
C4
t
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
LED Current Error at 200 Hz PWM
0
-1
Error (%)
Error (%)
LED Current Error at 100 Hz PWM
Error (%)
Corrected Error (%)
with 2.5 μs turn-on delay
0
10
20
30
40
50
60
70
PWM Duty Cycle (%)
80
90
-2
-3
Error (%)
-4
Corrected Error (%)
with 2.5 μs turn-on delay
-5
-6
100
0
10
20
30
40
50
60
70
PWM Duty Cycle (%)
80
90
100
The LED Current Error graph shows the effect of PWM duty cycles on LED current error, according to the relationship:
Error (%) = (IISET × 960 x PWM Duty cycle – ILED(av)) / (IISET × 960 x PWM Duty cycle) .
At lower PWM duty cycles, turn-on delay adversely affects LED current accuracy. This accuracy can be improved by extending the applied PWM signal
by 2.5 μs. For example, at 100 Hz PWM and 1% PWM duty cycle, the on-time would be 100 μs. The effects of that turn-on delay could be offset by
applying a 102.5 μs PWM pulse.
Efficiency versus PWM Duty Cycle
100
90
90
89
80
88
70
87
Efficiency (%)
ILED (mA)
LED Current versus PWM Duty Cycle
60
50
40
30
PWM
100 Hz
200 Hz
20
10
20
40
60
PWM Duty Cycle (%)
80
85
84
PWM
100 Hz
200 Hz
83
82
81
0
0
86
100
80
0
10
20
30
40
50
60
70
PWM Duty Cycle (%)
80
90
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
100
10
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
Output LED Open Protection
VBAT = 12 V, ILED = 100 mA per LED string, EN = high
LED string #1 disconnected. VOUT increases to OVP level, and LED string #1 is
removed from regulation. The rest of the LED strings continue to function normally.
VBAT
C1
VOUT
C2
VLED1
Symbol
C1
C2
C3
C4
t
Parameter
VBAT
VOUT
VLED1
IOUT
time
Units/Division
10 V
20 V
1V
500 mA
100 μs
Symbol
C1
C2
C3
C4
t
Parameter
VBAT
VOUT
VLED1
IOUT
time
Units/Division
10 V
20 V
1V
500 mA
100 μs
C3
IOUT
C4
t
All four LED strings disconnected simultaneously. VOUT increases to OVP
level, and all LED strings are removed from regulation.
VBAT
C1
VOUT
C2
VLED1
C3
IOUT
C4
t
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
ISET Characterization
LED Current versus RISET
100
90
80
ILED (mA)
70
60
50
40
30
20
10
0
0
20
10
30
50
40
60
70
RISET (kΩ)
LED Current versus 1/ RISET
100
90
80
ILED (mA)
70
60
50
40
30
20
10
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
1/RISET (RISET in kΩ)
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12
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
Disconnect Switch Overcurrent Fault Timing Diagram
VCAP
VOUT
30 V
A
B
C
D
E
F
G
t
5V
VCOMP
t
1A
IOUT
t
30 V
VSW
t
5V
VEN
t
A
B
C
A. Overcurrent on disconnect switch is detected and disconnect
switch latches off. Boost is turned off when >3 V is detected
across the disconnect switch. LEDs stop sinking current
because there is insufficient voltage across them.
B. COMP pin reaches lockout level. LEDs are internally turned
off and the COMP pin is discharged.
C. COMP pin reaches ground voltage, LEDs are internally turned
on, in soft start mode, and boost is put into soft start mode.
Boost and LEDs remain off because VOUT is still at ground
D
E
F
G
potential due to the disconnect switch being latched off.
D. User turns off EN.
E. The A8501 shuts down when EN is off for more than 131,072
clock cycles. If any other fault conditions were present prior
to shutdown, such as: open LED, TSD, shorted LED, or
secondary OVP, these are now cleared and the part is ready
to be re-enabled.
F. User re-enables operation. A8501 enters soft start mode.
G. Soft start mode finished.
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13
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Performance Characteristics
Fault Protection
VBAT = 12 V, ILED = 100 mA per string
4 channels enabled, 8 series LEDs each
VOUT to LED1 Short
(LED Short Detect activated, causing a latched shutdown)
VCAP
VOUT
IOUT
Symbol
C1
C2
C3
t
Parameter
IOUT
VCAP
VOUT
time
Units/Division
200 mA
5V
5V
1 μs
Symbol
C1
C2
C3
t
Parameter
IOUT
VCAP
VOUT
time
Units/Division
1A
5V
5V
2 μs
Symbol
C1
C2
C3
t
Parameter
IOUT
VSW
VOUT
time
Units/Division
200 mA
10 V
5V
20 μs
C1
C2
C3
t
VOUT to Ground Short
(Output Disconnect Switch opens to prevent any damage)
VCAP
VOUT
IOUT
C1
C2
C3
t
Open Schottky Diode Disconnect
(Secondary OVP activated, causing a latched shutdown)
VOUT
IOUT
VSW
C1
C2
C3
t
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14
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Functional Description
Description
The A8501 is a multioutput WLED/RGB driver for display backlighting. It uses a boost converter architecture to generate output
voltage to drive 4 channels with up to 9 LEDs per channel
(Vf = 3.5 V, If = 100 mA). The current-mode boost converter
operates at constant frequency. The boost switching frequency
can be set from 600 kHz to 2.2 MHz by an external resistor connected across FSET and AGND. The integrated boost DMOS
switch is rated for 40 V at 3.6 A. This switch is protected against
overvoltage, and provides pulse-by-pulse current limiting independently of boost converter duty cycle.
The A8501 has 4 well-matched current sinks, which provide
regulated current through the load LEDs for uniform display
brightness. All LEDx sinks are rated for 21 V to allow PWM
dimming control.
Frequency Selection The switching frequency on the SW
pin, fSW , can be set by applying the following equation:
fSW = 51 / RFSET ,
(1)
where fSW is in MHz, and RFSET is in kΩ.
by the combined settings of the SEL1 and SEL2 pins, according
to the following table:
LED Channel Selection
SEL2 Pin
Use matched forward voltage LEDs for better efficiency.
The application circuit shown in figure 1 is a boost converter
and the output voltage is always higher than the battery voltage. Therefore, the quantity of LEDs per string should be such
that the required output voltage is higher than the maximum
battery voltage. If the battery voltage is higher than the output
voltage, the A8501 will switch with minimum pulse width, and
the actual output voltage will be higher than the required voltage. The excess voltage will be dropped across the LED strings.
This lowers efficiency and increases power dissipation, resulting
in higher device temperature. If battery voltage must be higher
than required output voltage, use a SEPIC converter, as shown in
figure 10.
Soft-Start and Compensation
LED Selection Which LED strings are enabled is determined
SEL1 Pin
LED strings that are connected to the A8501, but are not enabled
through the SELx pins, may cause a shutdown if the voltage on
the corresponding LEDx pins exceeds VLEDSC . Refer to the LED
Short Detect section for further details. Unused LEDx pins can be
left open or connected to ground.
Enabled LEDx Outputs
Low
Low
Only LED1
High
Low
LED1 and LED2
Low
High
LED1, LED2, and LED3
High
High
All channels
At startup, the output capacitor is discharged and the A8501
enters soft start. The boost current is limited to 0.6 A and all
active LEDx pins sink 1/20 of the set current until all the enabled
LEDx pins reach 0.75 V. When the A8501 comes out of soft
start, the boost current and the LEDx pin currents are set to
normal. The output capacitor charges to voltage required to supply full LEDx currents within a few cycles. Once VOUT reaches
the required level, LEDx current toggles between 0 and 100%
in response to PWM signals. Soft start behavior on evaluation
boards is shown in the Performance Characteristics section.
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15
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
LED Open Detect When any LED string opens, the boost
LED Current Setting
The maximum LED current can be up to 100 mA per channel, and is set through the ISET pin. Connect a resistor, RISET,
between this pin and AGND to set the reference current level,
IISET , according to the following formula:
IISET = 1.235 / RISET ,
(2)
where IISET is in mA and RISET is in kΩ.
This current is multiplied internally with a gain of 960, and mirrored on all enabled LED pins. This sets the maximum current
through the LEDs, referred as the 100% current.
Dimming The LED current can be reduced from the 100% current level by three alternative dimming methods:
• PWM dimming using the EN pin. PWM dimming is performed
by applying an external PWM signal on the EN pin. When
the EN pin is pulled high, the A8501 turns on and all enabled
LEDs sink 100% current. The sequence is shown in figure 2.
For optimal accuracy, the external PWM signal should be in the
range 100 to 300 Hz. The slight delay between PWM signal and
the LED current causes an error. To compensate for the error,
a small turn-on delay should be added to the PWM signal as
shown on page 10 of the Performance Characteristics section.
When EN is pulled low, the boost converter and LED sinks are
turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. If EN is pulled low for more
than tPWML , the device enters shutdown mode and clears all
internal fault registers. As an example, for a 2 MHz clock, the
maximum PWM low period while avoiding shutdown is 65 ms.
circuit increases the output voltage until it reaches the overvoltage protection level. The OVP event causes any LED string that
is not in regulation to be locked-out from regulating the loop. By
removing the open LED from controlling the boost, the output
voltage returns to normal operating voltage. Every OVP event
retests all LED strings. An EN low signal does not reset the LED
string regulation lock unless it shuts down the device (exceeds
tPWML). The locked-out LED pins always attempt to sink desired
current regardless of lock-out state.
LED Short Detect Any LED pin that has a voltage exceeding VLEDSC will force the device to disable the boost circuit and
LEDx outputs until EN shuts down the A8501 (EN low exceeds
tPWML). This protects the LEDx pins from potentially hazardous
voltages when multiple LEDs are shorted in one string.
Overvoltage Protection The A8501 has overvoltage protection (OVP) and open Schottky diode protection.
The OVP has a default level of 19.5 V and can be increased up to
38 V by the selection of an external resistor, as shown in figure 3.
When the current though OVP pin exceeds 200 μA, the OVP
comparator goes low. When VOUT falls and current through the
OVP pin drops below 165 μA, the OVP is released.
D1
VBATT
VOUT
SW SW SW
COUT
A8501
• Analog dimming using the DIM pin. When the DIM pin is
pulled low, the LED sinks draw 100 % current; when the pin is
pulled high, the LED current level drops to 25%.
ROVP
Latch
• Analog dimming using the VTI pin. External DC voltage can be
applied to the VTI pin to control LED current. LED current varies as a function of voltage on the VTI pin. This configuration is
shown in figure 5.
–
+
1.23 V
OVP
18 V
–
+
EN
External PWM Signal
Turn-on delay
ILEDX
OVP
Disable
1.23 V
100% Current
0 mA
Figure 2. Timing diagram of external PWM signal and LED current
Figure 3. Overvoltage protection (OVP) circuit
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16
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
The following equation can be used to determine the resistance
for setting the OVP level:
ROVP = (VOVP – 19.5) / 200 μA ,
(3)
where VOVP is the target typical OVP level, and ROVP is the value
of the external resistor, in Ω.
A8501 has secondary overvoltage protection to protect internal
switches in the event of an open diode condition. Open Schottky
diode detection is implemented by detecting overvoltage on the
SW pin. If voltage on the SW pin exceeds the device safe operating voltage rating, the A8501 disables and remains latched. The
IC must shut down before it can be reenabled.
Overcurrent Protection The boost switch is protected with
pulse-by-pulse current limiting at 3.6 A. The output disconnect
switch protects against output overcurrent. At 1 A typical, the
A8501 disables. This process is detailed in the Disconnect Switch
Overcurrent Fault Timing diagram in the Performance Characteristics section, page 13.
In some instances, when the LEDs are connected by long wires
and also some output capacitance (such as ESD capacitors) is
present, a clamping diode on the output must be used. This diode
will prevent the output from momentarily going negative during
a short circuit condition. The diode must be chosen such that its
reverse breakdown voltage is higher than normal operating voltage and its reverse current leakage is small. Please refer to the
application note Output Diode Clamping for the A8501 for more
details.
Input UVLO When VIN rises above the UVLO enable hyster-
esis (VUVLO(th) + VUVLO(hys) ), the A8501 is enabled. It is disabled
when VIN falls below VUVLO(th) for more than 50 μs. This lag
is to avoid shutting down because of momentary glitches in the
power supply.
Input OVLO When VIN rises above VOVLO(th) for more than
50 μs, the A8501 is disabled, the boost converter shuts down
instantly, and LED current falls gradually with the CAP pin
capacitor. When VIN falls below VOVLO(th) and EN is high, the
device is reenabled.
Thermal Derating Thermal derating can be achieved by connecting an NTC thermistor between VTI and ground, as shown in
figure 5. When the A8501 is enabled and VTI > 1.1 V, 100% current for the LEDs is controlled by the ISET and DIM pins. This
is represented by the solid blue curves in figure 6. When VTI falls
below 1.1 V, VISET starts to follow VTI , resulting in ILEDX varying
proportionately with VTI represented by the overlap of the dotted
and solid curves. The proportion of ILED to VTI , when LED current is controlled through the VTI pin, is calculated as:
IILEDx = 960 × VTI / RISET ,
(4)
where ILEDx is the LEDx pin current in mA, and RISET is in kΩ.
There is a hysteresis built into the VTI pin circuit, so while VTI
is decreasing, there is a delay before proportional change begins
if VTI pin voltage starts above 1.1 V, as shown by the solid blue
curves in figure 6. When VTI starts below 1.1 V, or falls below
1.1 V during operation and then starts increasing again VISET will
follow VTI until the voltage reaches 1.23 V as shown by the redand-white dotted curves in figure 6.
VOVP
ILED
VTO
C2
RVC
C1
NTC
VTI
2.46 V
÷2
1.23 V
Minimum
Select
–t°
+
LED Current
Reference
–
ISET
RISET
A8501
t
Symbol
C1
C2
t
Parameter
VOVP
ILED
time
Units/Division
10 V
50 mA
100 μs
Figure 4. Output overvoltage protection (OVP) operation
Figure 5. Thermal derating reference circuit
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17
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
ILED versus VTI
at TA = 125°C
100
90
80
(A)
ILED (mA)
70
60
VTI Decreasing
50
VTI Increasing
40
30
20
10
0
0
0.2
0.4
0.6
0.8
V TI (V)
1
1.2
1.4
I LED versus VTI
at TA = 25°C
100
90
80
(B)
ILED (mA)
70
60
VTI Decreasing
50
VTI Increasing
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V TI (V)
I LED versus VTI
at TA = –40°C
100
90
80
(C)
ILED (mA)
70
60
VTI Decreasing
50
VTI Increasing
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V TI (V)
Figure 6. LEDx current versus VTI
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A8501
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
Bias Supply
The BIAS pin provides regulated 6 V for internal circuits. Connect a CBIAS capacitor with a value in the range of 0.1 to 1 μF.
Efficiency Considerations
For better efficiency, use a high quality inductor with relatively
low DCR and core loss.
Use a low forward voltage Schottky diode with relatively low
junction capacitance.
Use matched forward voltage LEDs for better efficiency.
The A8501 provides an output disconnect function through a load
switch that is connected from the boost converter output (CAP) to
LED connection (OUT). This function protects the system against
short circuit conditions from common anode LED connection to
ground, for both boost and SEPIC configurations.
When comparing the efficiency of the A8501 with an alternate
implementation requiring an external input/output disconnect
function, the additional power dissipation in this disconnect
switch must be considered for a proper comparison. To bypass
the disconnect switch, short the CAP pin to the OUT pin to
have a direct connection from the boost regulator to the common anode LED node. When the disconnect switch is bypassed,
both the boost and the SEPIC implementations are not protected
against output short circuit conditions.
Audible Noise Considerations
Multilayer ceramic capacitors cause audible noise when subjected to voltage ripple in the audio frequency range, due to the
piezoelectric effect. Ceramic capacitors connected across boost
converters can also cause audible noise due to voltage ripple
at dimming frequencies. During the PWM dimming off-time,
the voltage across the capacitors drops due to leakage through
the output disconnect switch and the OVP pin. This voltage is
regulated to the desired output level during the PWM dimming
on-time. This voltage ripple may cause audible noise.
Audible noise can be minimized with higher dimming frequency,
but at higher dimming frequencies accuracy may be affected, as
shown in the Performance Characteristics section. It is recommended to use 200 Hz for optimum performance.
Selecting a sufficiently large capacitor across the boost output can
reduce voltage ripple and noise. It is observed that the audible
noise below 250 mV ripple is negligible.
The value to select for a boost capacitor can be calculated using
the following formula:
C ≥
Ilk
(1 – DFPWMmin)
fPWM
.
(5)
0.25
where
Ilk is the leakage current; select Ilk = 165 μA at a 30 V output and
175 μA at a 40 V output,
DFPWMmin is the minimum dimming PWM duty cycle, and
fPWM is the dimming frequency; typically 200 Hz.
For example, if the dimming frequency is 200 Hz, the minimum
dimming PWM duty cycle = 10%, and VOUT = 30 V, then select
the boost capacitor as:
C =
165 μA (1 – 0.1)
200 0.25
= 3 μF
.
The capacitance of ceramic capacitors drops with DC bias. Use
an appropriate capacitor to get at least 3 μF at 30 V.
The selection of a ripple voltage of 0.25 V is based on a typical
MLCC. This ripple level depends on the type and construction of
the MLCC. Increase the boost capacitor if noise exists at 0.25 V.
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2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Application Information
Design Example
This section provides a method for selecting component values
when designing an application using the A8501.
Select a common value: 14.7 kΩ, 1%.
4. Select resistor RFSET (connected between pin FSET and
AGND). Given:
Assumptions For the purposes of this example, the following are
given as the application requirements:
RFSET = 51 /fSW ,
(7)
for a 2 MHz switching frequency, select:
• VBAT: 8 to 18 V
RFSET = 51 / 2 = 25.5 kΩ , 1%.
• Quantity of LED channels, #CHANNELS : 3
5. Select resistor ROVP (connect to the OVP pin to set the
OVP level, VOUT(max)). Given Vf (max) = 3.4 V, 0.75 V as
the VLED regulation level, and worst case output disconnect
switch voltage drop, then:
• Quantity of series LEDs per channel, #SERIESLEDS : 8
• LED current per channel, ILED: 80 mA
• Total current all channels, IOUT = ILED × #CHANNELS
• Vf at 80 mA: 3 to 3.4 V
VOUT(max) = (Vf (max) × #SERIESLEDS )
+ VLED + (RODS(on) × ILED × #CHANNELS ) .
• fSW: 2 MHz
(8)
• TA(max): 65°C
Substituting:
Dimming The A8501 can work with wide range of PWM fre-
VOUT(max) = (3.4 × 8 + 0.75) + (4 × 0.08 × 3) = 28.91 V .
quencies. A small delay between the PWM signal and the LED
current may have a noticeable effect at high PWM frequencies
combined with low PWM duty cycles. For example, at 100 Hz
and 10% PWM duty cycle, the PWM on-period is 1 ms. In that
period, the delay causes only a 0.6% error. If the PWM frequency
is 1 kHz, this error is 6%. However, the error caused by the turnon delay can be decreased by increasing the applied PWM duty
cycle as shown on page 10 in the Performance Characteristics
section.
Procedure The procedure consists of selecting the appropriate
configuration and then the individual component values, in an
ordered sequence.
2. Connect LEDs to pins LED1 through LED3 (leave pin LED4
open).
3. Select resistor RISET (connected between pin ISET and
AGND). Given ILED = 80 mA and AISET = 960, then:
RISET = 1.235 / (0.080 / 960) = 14.82 kΩ .
(9)
Substituting:
ROVP = (33 – 19.5) / 200 × 10-6 = 68 kΩ .
(10)
6. Select inductor L1. This should assume a maximum boost
converter duty cycle, D(max), at VBAT(min) and 90% efficiency, η.
(11)
D(max) = 1– (8 × 0.9) / 28.91 = 75% .
• connect pin SEL1 to ground
Substituting:
ROVP = (VOVP – VOVP(th) ) / IOVPH .
D(max) = 1– (VBAT(min) × η) / VOUT(max)
1. Identify the SELx pins to use. For 3 channels:
• connect pin SEL2 to VTO
RISET = 1.235 / (ILED / AISET ) .
The switch resistance RODS(on) can be found in the electrical table and is listed as worst case at 4 Ω at high temperatures. To set the output OVP level to 33 V, given an IOVPH of
200 μA, and VOVP(th) = 19.5 V:
(6)
Then calculate maximum switch on-time:
ton(max) = D(max) / fSW
(12)
= 0.75 / 2 × 106 = 375 ns .
Maximum input current can be calculated as:
IBAT = (VOUT(max) × IOUT) / (VBAT(min) × η)
(13)
IBAT(max) = [28.91 × (0.080 × 3)] / (8 × 0.9) = 963 mA.
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20
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
8. Select input capacitor CIN, given:
Set inductor ripple at 30% of IBAT(max):
IL = IBAT(max) × ILripple(Ideal) .
(14)
Substituting:
CIN = 0.3 / (8 × 2 × 106 × 0.01 × 8) = 0.23 μF .
VBAT(min) = L × ∆IL × fSW / D ,
8 = L × 0.289 × 2
(15)
/ 0.75, and
Select a common value: L(used) = 10 μH.
It is recommended to select an inductor that can handle a DC
current level that is greater than 963 mA, at the peak current
level (saturation) of 963 mA + 289 mA / 2 = 1.11 A. This is
to ensure that the inductor does not saturate at any steady
state or transient condition, within specified temperature and
tolerance ranges. Inductor saturation level decreases with
increasing temperature. It is advisable to use a inductor with a
saturation level of 2.0 A. The inductor should have a low DC
resistance (DCR) and core loss for better efficiency.
7. Select output capacitor COUT, given:
fPWM = 100 Hz ,
(16)
assuming 20% minimum dimming PWM duty cycle,
DPWM(min) , and the maximum leakage current through the
output disconnect switch at VOUT = 28 V is 165 μA and
VCOUTripple = 0.25 V.
Select the output capacitor as:
COUT = Ilk × (1 – DPWM(min)) / (fPWM × VCOUTripple ) .
Select a 2.2 μF or higher, 35 or 50 V, ceramic capacitor, X5R
or X7R grade.
The RMS current through CIN is given by:
L = 10.4 μH .
(17)
Substituting:
IINRMS = (IOUT × r) / [(1 – D) × 121/2 ],
(23)
= [(80 mA × 3 )× 0.3]
/ [(1 – 0.75) × 3.46] = 83 mA .
Select a capacitor with an RMS current rating greater
than 83 mA.
9. Select the boost diode D1 (connect between the SW pins and
the output). D1 should be a Schottky diode with low forward
drop and junction capacitance.
The diode reverse voltage rating should be greater than VOUT.
A 40 to 50 V diode rating is recommended.
The diode DC current rating should be greater than IOUT and
the peak repetitive current rating should be > IBAT(max)
+ ∆IL / 2.
10. Select the compensation capacitor CCOMP (connect between
the COMP pin and ground). Typically, use a 1 μF capacitor to
reduce audio hum during PWM dimming.
11. Calculate Power Loss. Calculate power loss at various operating conditions to estimate worst-case power dissipation.
a) Loss in LED drive:
COUT = 165 μA× (1 – 0.2) / (100 × 0.25) = 5.3 μF .
(18)
Select 6.8 μF.
The RMS current through COUT is given by:
D(max) + (r / 12) 1/2
,
Crms = IOUT ×
1– D
r = ΔIL / IBAT(max)
, and
.
ILEDx × VLEDx for one string
+ (ILEDx × VLEDx(av) +0.75
× quantity of remaining enabled LED strings),
(19)
where:
VBAT(min) × D
∆IL =
L(used) × fSW
(22)
where ∆VINripple is the input ripple voltage, which can be assumed to be 1% of VBAT. Then:
∆IL = 0.3 × 963 = 289 mA .
Given, during switch on-time:
×106
CIN = ∆IL / (8 × fSW × ∆VINripple ) ,
(20)
(21)
Substituting:
(80 mA × 3 )× {[0.75 + (0.3 / 12)]/(1–0.75)}1/2 = 0.422 A .
Select a capacitor with an RMS current rating greater than 0.422 A.
(24)
where VLEDx is the regulation voltage of the LEDx pins, 0.75 V
typical, and worst-case drop is mismatch due to LED Vf.
A good approximation for VLEDx(av) is 0.8 V. This assumes
that some of the remaining strings will regulate below, and
some above, a value of 1.55 V. If the predicted LED matching is tighter, then a lower value can be used. If the predicted
LED mismatch is large, then a higher value should be used.
To get the complete and accurate power dissipation, the user
will need to measure each individual LED pin to get the exact
VLED voltage:
(80 mA × 0.75) + [80 mA × 2 × (0.8 + 0.75)] = 0.308 W .
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21
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
b) Loss in low drop-out regulator (LDO) + bias:
PLDO = VBAT(max) × IBIAS ,
e) Diode loss:
(25)
c) Boost switch conduction loss:
(26)
where:
r =ΔIL / IBAT(max) .
(27)
d) Boost switch switching loss:
VOUT × IBAT(max) × (trise + tfall) × fSW .
(29)
where Cd is the average junction capacitance of the Schottky
diode. Then:
with bias current during switching 17 mA typical.
I 2BAT(max) × D × RDS(on) × (1+ r2 /12) ,
Diode switching loss = 0.2 × Cd × V 2OUT × fSW ,
(28)
Switch loss calculations assume negligible input gate charge
on internal boost MOSFET until VG(th) (gate threshold), compared to the Miller charge; trise and tfall are measured in the
lab under full load conditions. To approximate this value, use
5 ns for rise and fall times.
Diode conduction loss = Vf × IBAT(max) × (1–D)
(30)
f) Inductor DCR loss:
I 2IN × RDC × (1+ r2 /12) .
(31)
g) Inductor core loss:
This value is an estimate. The default value would be 50 mW
at 1 A ripple current, and then scaled based on ripple current.
h) Power loss in output disconnect switch:
PSWDISC(on) = RODS(on) × IOUT2 ,
(32)
If the Output Disconnect Switch On-Resistance, RODS(on) , is
2 Ω, then:
PSWDISC(on) = 2 × 0.242 = 0.11 W .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
22
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Typical Application Circuits
D1
VBAT
CBAT
4.7 μF
50 V
L1
10 μH
CIN
VIN
ROVP
SW SW SW
FSET
A8501
BIAS
VIN
SEL1
VTO
CCOMP
1 μF
10 V
VTI
L1
10 μH
CBIAS
0.1 μF
10 V
SW SW SW
OVP CAP
OUT
RVC
VTI
LED1
LED2
LED3
LED4
VTI
ISET
AGND PGND PGND PGND LGND DGND
Figure 8. Typical circuit for analog dimming with external DC voltage
CC
1 μF
50 V
VBAT
CBAT
4.7 μF
50 V
L1
10 μH
CIN
VIN
A8501
PAD
FSET
RFSET
25.5 kΩ
NC
LED1
LED2
LED3
LED4
CCOMP
1 μF
10 V
CBIAS
0.1 μF
10 V
SW SW SW
RISET
24.3 kΩ
Figure 9. Typical circuit with ESD capacitors across LEDs (CPx ≤10 nF),
with thermal derating
ROVP
OVP
CAP
OUT
COMP
DIM
BIAS
SEL2
A8501
PAD
COUT
4.7 μF
50 V
FSET
RFSET
25.5 kΩ
NC
SEL1
CP1 CP2 CP3 CP4
ISET
AGND PGND PGND PGND LGND DGND
D1
L2
10 μH
EN
DIM
SEL2
RFSET
25.5 kΩ
NC
PAD
SEL2
COMP
SEL1
VTO
RNTC
–t°
COUT
4.7 μF
50 V
ROVP
EN
BIAS
FSET
A8501
BIAS
RISET
24.3 kΩ
D1
VBAT
CCOMP
1 μF
10 V
OVP CAP
OUT
VTO
Figure 7. Typical circuit for driving 2 LED strings at up to 35 V at 200 mA
per LED string, with thermal derating
VIN
DIM
DAC
ISET
AGND PGND PGND PGND LGND DGND
CIN
SW SW SW
SEL1
RISET
12.4 kΩ
CBAT
4.7 μF
50 V
COUT
4.7 μF
50 V
ROVP
COMP
CBIAS
0.1 μF
10 V
LED1
LED2
LED3
LED4
RVC
RNTC
–t°
RFSET
25.5 kΩ
NC
PAD
SEL2
L1
10 μH
CIN
EN
COMP
DIM
CBIAS
0.1 μF
10 V
CBAT
4.7 μF
50 V
OVP CAP
OUT
EN
CCOMP
1 μF
10 V
D1
VBAT
COUT
4.7 μF
50 V
VTO
VTI
RISET
24.3 kΩ
LED1
LED2
LED3
LED4
ISET
AGND PGND PGND PGND LGND DGND
Figure 10. Typical circuit as SEPIC converter (SEPIC converters can
provide output voltage higher or lower than the input voltage; this topology
can be used if the required output voltage level is within application input
voltage range)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
23
2 MHz, 4 Channel×100 mA WLED/RGB Driver
with Output Disconnect
A8501
Package LP, 28-Pin TSSOP with Exposed Thermal Pad
0.45
9.70±0.10
28
0.65
28
8º
0º
0.20
0.09
1.65
B
3 NOM
4.40±0.10
3.00
6.40±0.20
0.60 ±0.15
A
1
2
1.00 REF
5.08 NOM
0.25 BSC
Branded Face
28X
SEATING
PLANE
0.10 C
0.30
0.19
0.65 BSC
1 2
SEATING PLANE
GAUGE PLANE
C
5.00
C
PCB Layout Reference View
For Reference Only; not for tooling use (reference MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.20 MAX
0.15
0.00
A Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351
SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
Copyright ©2008-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
24
6.10