XMC4000 System Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 2 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 3 XMC4000 Block Diagram XMC4000 is based on a Cortex-M4 architecture with a rich peripheral set for communication and sensor/actuator applications. 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 4 Architecture of Cortex-M4 Highlights Cortex-M4 is a high efficiency processor core with 1.25 DMIPS/MHz. Due to the Thumb-2 instruction set it reaches excellent code density. Its optimised interrupt controller allows use in hard real-time applications. Widespread standard core offers a broad variety of software tools and components. Key Feature Customer Benefits Standard core Availability of third party tools, software libraries and engineering force DSP instruction set Offers computing performance for realtime applications Single precision floating point unit Avoids complex scaling and allows direct programming in C-language 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 5 Architecture of Cortex-M4 Standard Core (1/2) Central Core (including DSP) 1.25 DMIPS/MHz Thumb-2 / Thumb ISA Single Cycle MAC Integrated Nested Vectored Interrupt Controller and SYSTICK Timer Floating Point Unit Single precision Memory Protection Unit (MPU) 8-Region Embedded Trace Macrocell (ETM) for Instruction Trace Debug Access Port: JTAG or Serial Wire Instrumentation Trace Macrocell (ITM ) for Data Trace via Single Wire Output Data Watch Point and Trace Unit (DWT) 4x Data Watchpoints & Event Monitors Flash Patch & Breakpoint Unit 8x Hardware Breakpoints 2x AHB-Lite Buses I_CODE (Instruction Code Bus) D_CODE (Data/Coefficients Code Bus) 1x AHB-Lite Bus SYSTEM (SRAM & Fast Peripherals) 1x APB Bus ARM Peripheral Bus (Internal & Slow Peripherals) Source: http://www.arm.com 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 6 Architecture of Cortex-M4 Standard Core (2/2) Cortex-M Architecture Comparison ARM Cortex-M Thumb Thumb-2 ARM architecture Core architecture Cortex-M0 Most Subset ARMv6-M Von Neumann Cortex-M3 Entire Entire ARMv7-M Harvard Cortex-M4 Entire Entire ARMv7E-M Harvard ARM Cortex-M Hardware multiply Hardware divide Saturated math DSP extensi ons Floatingpoint Cortex-M0 1 or 32 cycle No No No No Cortex-M3 1 cycle Yes Yes No No Cortex-M4 1 cycle Yes Yes Yes Optional Source: Wikipedia 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 7 Architecture of Cortex-M4 DSP Instruction Set (1/2) Cortex-M4F is an ARMv7E-M architecture. It has a full Thumb and Thumb-2 instruction set. Cortex-M4F has a single precision floating point unit. Source: http://www.arm.com 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 8 Architecture of Cortex-M4 DSP Instruction Set (2/2) Single Cycle MAC Instructions Source: http://www.arm.com 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 9 Architecture of Cortex-M4 Single Precision Floating Point Unit Cortex-M4 SIMD + FPU Fix point: ~2x faster Floating point: ~10x faster FIR q15 PID q15 IIR q31 Matrix Mul fixed point fixed point fixed point fixed point - 91% 13,619 158,878 - 70% 2,462 8,310 - 69% 2,462 8,596 - 35% 27 41 2,244 8,819 - 75% CMSIS DSP Library Benchmark: Cortex-M3 vs. Cortex-M4 Correlation floating point Cycles: smaller numbers are better Source: http://www.arm.com 2015-01-23 Cortex-M3 Cortex-M4 Copyright © Infineon Technologies AG 2015. All rights reserved. Memory Access Cycles Page 10 Architecture of Cortex-M4 CPU Performance Benchmark Coremark CRC Routine (The higher the better) 400 (The lower the better) 7759 clock cycles millisec 5681 3681 3100 119 47.3 65 XMC4000 Flash cached XMC4 @120 MHz, 3 WS 2015-01-23 XMC4000 Flash uncached XMC1000 Flash XMC1 @32 MHz, 1.3 WS XMC4000 Flash uncached 31 XMC4000 Flash cached XMC4 @120 MHz, 3 WS Copyright © Infineon Technologies AG 2015. All rights reserved. 178 XMC1000 Flash 97 XMC1000 RAM XMC1 @32 MHz, 1.3 WS Page 11 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 12 Memories Highlights Memories BootROM DSRAM1 Flash PSRAM DSRAM2 Cache The memory map is based on standard ARM Cortex-M4 system memory map. The peripherals are memory mapped into the linear address space. The on-chip memories provide zero wait state accesses to code and data. Flash module has very high performance with low latency. With the external bus interface (EBU), memory can be extended to 65 MBytes. Key Feature Customer Benefits Flash acceleration with cache Integrated cache reduces code execution time and saves power Parity protected RAM and ECC protected Flash High code/data integrity due to hardware error detection and correction mechanism. Flash IP protection Protect against unauthorized read-out of memory content 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 13 Memories Flash acceleration with cache (1/2) 256 bit data buffer Single line Critical word first, streaming 4 KByte instruction buffer 2 way set associative, 256 bit line Bypass and invalidation supported LRU replacement policy Critical word first, streaming 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 14 Memories Flash acceleration with cache (2/2) Performance for Cortex-M4 @ 120 MHz, 3 wait states: Execution with cache: ~2.5 – 3.4x faster Note: compiler play a big role in benchmark results 500 400 EEMBC with IAR 400 EEMBC with Keil 300 300 100 200 400 402 200 260 253 100 61 142 150 119 0 Coremark Flash Dhrystone Flash cached PSRAM 95 208 253 91 0 Coremark Flash Flash cached Dhrystone PSRAM Numbers in clock cycles: higher numbers are better 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 15 Memories Parity protected RAM and ECC protected Flash RAM supports parity bit generation and error detection Parity bit can be inverted to force an error for test purposes Hardware support for ClassB Library saves CPU load for volatile memory test Flash supports ECC with: Single bit error detection and correction Double bit error detection Flash supports margin checks for preventive maintenance All memories with zero wait state: 8-bit, 16-bit and 32-bit write access 32-bit read access 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 16 Memories Flash IP protection For software IP protection there are several modes available which allow both flexibility and safe protection against unauthorized read or manipulation Hierarchical write protection control with 3 levels Password based read protection for temporary disabling protection Global read and sector-specific write granularity Read protection blocks debug accesses and is globally for the whole flash area. Write protection blocks flash write and erase accesses and is sector-specific OTP protection one-time set, never change Granularity: sector-specific, e. g. for a user-specific bootloader 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 17 Memories External memory interface with external Bus Unit (EBU) External Bus Interface (EBU) enables communication with external memories and on-chip peripherals Supports memory access types: Synchronous Asynchronous Burst Protocol Multiple memory types can be accessed in time-multiplex 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 18 Memories Flash Memory Characteristics When Flash is busy, any access to the Flash memory or write access to Flash SFRs will be stalled automatically Parameter Min. Typical Max. 3.1 - 3.6 V - 0.3 0.4 s Sector = 16 Kbytes - 1.2 1.4 s Sector = 64 Kbytes - 5 5.5 s Sector = 256 Kbytes Erase all - - 22 s At 1 Mbyte Write time per page - 5.5 11 ms Page = 256 bytes Data retention 20 - - years Ta = 125°C, 1k cycles Flash Wait States 2 - - cycles fMCLK = 80 MHz 3 - - cycles fMCLK = 120 MHz Erase cycles per sector - - 10k cycles Sector = 64 Kbytes Total erase cycles - - 20k cycles Cycling @ 2 x 64 Kbytes Voltage range Erase time per sector 2015-01-23 Unit Copyright © Infineon Technologies AG 2015. All rights reserved. Note Page 19 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 20 Bus System Highlights Access parallelism through multilayer bus, multi-masters and multi-slaves. Zero wait state data accesses between masters and slaves. Simultaneous access can be handled by arbitration priority scheme. Key Feature Customer Benefits Access parallelism High throughput and real-time access of the system Zero wait state access to memories Fast memory access Arbitration priority scheme Optimize system performance 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 21 Bus System Prioritization Scheme Access Priorities per Slave Masters Examples of simultaneous accesses: 1) Ethernet-DMA to DSRAM2 while 2) CPU to PSRAM while 3) DMA0 to DSRAM1 Slaves 2015-01-23 CPU GPD MA0 GPD MA1 ETH USB FLASH 1 2 3 - - PSRAM 1 2 3 - - DSRAM1 1 2 3 4 5 DSRAM2 1 4 5 2 3 EBU 1 2 3 - - PBA0-2 1 2 3 - - Copyright © Infineon Technologies AG 2015. All rights reserved. Page 22 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 23 Interrupt System Highlights The interrupt system consists of the Nested Vectored Interrupt Controller (NVIC) and the interrupt generation blocks in the individual modules. Events from peripherals can be routed via the connection matrix directly to other peripherals and can trigger interrupt requests. Key Feature Customer Benefits 64 programmable priority level Flexible priority control Interrupt Tail-chaining Speed up interrupt servicing Automatic State Saving and Restoring Low latency exception handling 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 24 Interrupt System 64 Programmable Priority Level NVIC supports 112 interrupt nodes Each interrupt node has an 8-bit priority field in IPRn register One of 64 priority levels is assigned to an interrupt node by writing to its corresponding priority field The lower the value written to the priority field, the higher the priority A higher priority interrupt can interrupt an existing lower priority interrupt, resulting in nested interrupts When multiple interrupts have the same priority level, the pending interrupt with the lower node ID takes precedence 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 25 Interrupt System Interrupt Tail-chaining When a current ISR is completed and there is a pending interrupt, stack pop is skipped and control is transferred to the new ISR Allows interrupt servicing to speed up Tail-chaining Reference: http://www.arm.com 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 26 Interrupt System Automatic State Saving and Restoring Automatic state saving and restoring are done without any instruction overhead: State registers are pushed onto the stack before entering the ISR Reading of vector table entry is done after the state saving State registers are popped after exiting the ISR 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 27 Interrupt System Interrupt Latency Defined as the time from detection of interrupt pulse and latching of interrupt by NVIC, to execution of first instruction in ISR Typically 12 Cycles CLK 1 2 11 12 12-cycle latency due to core Interrupt request active/sampled 1st instruction at ISR Note: Flash wait states are not considered 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 28 Interrupt System General Module Interrupt Structure Generates interrupt levels to NVIC Status flag is a sticky bit – has to be cleared by SW 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 29 Interrupt System Connection Matrix Peripheral outputs can trigger events which are routed to peripheral inputs or to the NVIC Additional event routing is possible via the Event Request Unit ERU which can store events and logically combine two events This allows very flexible and powerful system design 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 30 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 31 Clock Highlights Clock 4-40 MHz Main Clock Generation 32.768 kHz Standby Clock Generation Clock Select -ion Unit The main function of the clock system is to generate clock for the CPU and on-chip peripherals. The clock can be generated internally, by an external crystal or via direct input. The clock selection is flexible, and clocking system prevents against invalid clock configuration. A clock supervisory ensures always a safe clock for operation. Peripheral clock can run at twice the speed of CPU clock. Key Feature Customer Benefits Separate clock sources Wide choice of clock frequency for peripherals and system Internal backup clock Emergency clock if external clock fails (fail safe feature) Optional automatic clock calibration Reduce bill of material 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 32 Clock Separate Clock Sources Two separate PLLs available for the system clock, ETH and USB 1:n 1:n 1:n 1:n System clock (32 kHz to 120 MHz) ETH (>100 MHz) USB/SDMMC (48 MHz) Due to individual prescaler a very flexible configuration for the CPU system and peripherals is possible fPLL fPLLUSB fOFI fSTDBY Clock source (e.g. fOFI) for WDT can be independent from CPU (fCPU) clock 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Clock Selection Unit 1:n 1:n 1:n 1:n fCPU fDMA fPERIPH fCCU fUSB fSDMMC fETH fEBU fWDT fEXT Page 33 Clock Internal Backup Clock A clock malfunction e.g. no clock, clock too slow, clock too fast and spikes in the clock is detected via a hardware oscillator watchdog A backup clock (OFI or OSI) is available in case of a clock malfunction; the backup clock is automatically selected in emergency case Main Clock Generation OFI 4-40 MHz 2015-01-23 PLL USB PLL Clock Select. Unit Standby Clock Generation OSI fSTDBY fRTC 32.768 kHz Copyright © Infineon Technologies AG 2015. All rights reserved. Page 34 Clock Optional Automatic Clock Calibration The two backup clocks can be used as clock source for cost sensitive applications Automatic Clock Calibration OFI and OSI can be calibrated Factory calibration via one-time setting from flash config sector Automatic calibration – on-the fly ¬ In case of using an accurate 32.678 kHz crystal for the RTC, one can use this clock to calibrate the OFI OFI PLL +/-0.5% cal 32.768 kHz RTC ¬ OFI can be used as PLL input clock OFI OSI 36.5 MHz +/- 25% 32 kHz +/- 10% Factory calibrated 24 MHz +/-15% 32 kHz +/- 4-10% Automatic calibrated 24 MHz +/-0.5% - Uncalibrated 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 35 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 36 Reset Highlights Reset Types Poweron Reset Debug Reset System Reset Standby Reset Always ensure safe application state via on-chip reset generation. Full user control via reset event signalizing and software control. Two domains core and hibernate with independent power supply and reset generation. Key Feature Customer Benefits Power-on reset Ensure safe operating conditions and defined system state Fail safe reset mechanisms Reset will bring the system into safe operation Hibernate domain with separate reset Hibernate domain can save information safely when using a backup supply 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 37 Reset Reset Types and Reset Sources 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 38 Reset Power-on Reset Power-on reset Supply voltage (3.3V) and core voltage (internally generated 1.3V) monitoring inside EVR Hysteresis on threshold of poweron reset for supply voltage ¬ Immunity to noise (>250 mV) in the supply voltage Pad control ensures defined pad state in undefined voltage range (VDDP < VDDPmin) 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 39 Reset Fail safe reset mechanisms Brown-out detection pre-warning Prepare system for reset, or, perform software corrective actions avoiding reset Parity error detection Optional system reset in case of parity error Lockup reset Standard ARM CPU feature Optional reset in case of unrecoverable CPU states Watchdog Timer reset Watchdog reset generated if CPU is not responsive Watchdog reset can be avoided with optional pre-warning Software can trigger a System Reset 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 40 Reset Hibernate domain with separate reset Hibernate state will be preserved in case of system reset System context memory retention Hibernate configuration preserved No impact on real-time clock Hibernate domain can be reset with a software reset Explicit reset triggered in user’s software Note: the Hibernate Domain has a separate Power-on mechanism (via Vbat supply) independent to the core system 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 41 Agenda XMC4000 and ARM Cortex-M4 Memories Bus System Interrupt System Clock Reset Power 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 42 Power Highlights Power 3.3V Battery EVR Pads Hibernate CPU clocks memories logic The single 3.3V supply concept allows a wide range of use cases. There are several power saving modes to tailor the current consumption to the application requirements. The power system is optimized for robustness and fail safe behavior for usage in a rugged industrial environment. A battery backed hibernate domain with realtime clock is good for current critical application. Key Feature Customer Benefits Different power saving modes Scalable power consumption according to application use case Hibernate domain with RTC Time and context keeping at low current consumption Power monitoring and validation Fail safe functionality 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 43 Power Different power saving modes (1/2) Simple transition scheme All power saving states entered from Active state ¬ Active – Sleep ¬ Active – Deep Sleep ¬ Active – Hibernate Power saving states entered with a single request ¬ Sleep and Deep Sleep entered via CPU instruction ¬ Hibernate request with single register access Flexible Wake-up trigger ¬ One wake-up trigger source can serve different power saving modes Prevention of wrong clock configuration in hardware 2015-01-23 Mode Power Saving Recovery Active - Clock scaling - Disable selected peripherals - Flash on/off - Fully SW control Sleep - Stop CPU - Disable ETH, USB, CCU, WDT - Wake via interrupt - Automatic restore Deep Sleep - Stop CPU - Disable ETH, USB, CCU, WDT - Disable PLLs, flash - Wake via interrupt - Automatic restore Hibernate - Core power supply off - Wake via event Copyright © Infineon Technologies AG 2015. All rights reserved. Page 44 Power Different power saving modes (2/2) Robust supply concept can be adapted to a wide range of power consumption to the user‘s need Supports enough headroom for worst case current consumption XMC Family Typical [mA] Worst case [mA] XMC4500 ~122 ~180 XMC4400 ~113 ~170 XMC4200 ~80 ~140 Load step due to frequency change*) Max negative load step is ~150mA Max positve load step is ~50mA Typical current consumption [mA] XMC4400 150 113 100 113 MHz. 2015-01-23 61 51 53 50 80 8 0 Active @ 120MHz - from flash - from RAM Freq scale Combined Saving @ 120 MHz CPU off @ 120MHz @ 24MHz Peri. off @ 120MHz @ 1MHz All off @ 24MHz Major current contributors [mA] XMC4400 80 60 60 62 31 40 *) Increasing the frequency has to be done in steps, e. g. 24 MHz - 68 MHz - 120 104 9 20 0 Flash on/off Freq scale Peripherals CPU on/off @ 120 120 to 1 on/off @ 120 @ 120 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 45 Power Hibernate with RTC Hibernate state will be preserved in case of system power off System context memory retention (16 x 32 bit register) Hibernate configuration preserved Hibernate with RTC Battery 2.1–3.6V RTC Standby clock LPAC HIB_IO RAM No impact on real-time clock Very low current consumption in Hibernate Domain Battery supply 15 Hibernate Current Consumption XMC4400 [µA] 10 5 12.8 9 7.7 7 @ 2.4 V @ 2.0 V RTC off @ 2.0 V 0 @ 3.3 V 2015-01-23 Copyright © Infineon Technologies AG 2015. All rights reserved. Page 46 Power Power Monitoring and Validation Pad domain power monitoring Core domain power validation Supply voltage VDDP Core voltage VDDC Threshold level VPOR Threshold level VPV (1.3V) ¬ Upper level of hysteresis is 3.1V ¬ Lower level of hysteresis is 2.85V PORST activated when VDDC < VPV PORST activated when VDDP < VPV Safe power up and down with automatic internal reset handling (release & issue) and external signalization via bi-directional PORST signal. VDDP 2015-01-23 EVR VDDC VDDC VPOR PORST# VDDP VPV t PORST# Copyright © Infineon Technologies AG 2015. All rights reserved. t Page 47