XMC4400 Data Sheet

XMC4400
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex™-M4
32-bit processor core
Data Sheet
V1.1 2014-03
Microcontrollers
Edition 2014-03
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
XMC4400
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex™-M4
32-bit processor core
Data Sheet
V1.1 2014-03
Microcontrollers
XMC4400
XMC4000 Family
XMC4400 Data Sheet
Revision History: V1.1 2014-03
Previous Versions:
V1.0 2013-10
V0.6 2012-11
Page
Subjects
11
Added information on CAN nodes and message objects available in the
devices.
17
Added information on the default configuration of the Port pins.
69
Removed wrong reference to Quality Declarations from footnote on Flash
parameters.
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
Data Sheet
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Table of Contents
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.1
2.2
2.2.1
2.2.2
2.2.2.1
2.3
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
15
17
22
23
27
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.5.1
3.2.5.2
3.2.5.3
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.3
3.3.1
3.3.2
3.3.3
3.3.4
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converters (ADCx) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital to Analog Converters (DACx) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Resolution PWM (HRPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HRC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMP and 10-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Analog Comparator (LPAC) . . . . . . . . . . . . . . . . . . . . . . . .
Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . .
29
29
29
30
31
33
35
36
36
43
48
51
53
53
53
56
57
58
59
61
65
69
70
70
71
72
74
Data Sheet
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XMC4400
XMC4000 Family
Table of Contents
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
3.3.9.1
3.3.9.2
3.3.9.3
3.3.9.4
3.3.10
3.3.11
3.3.11.1
3.3.11.2
3.3.11.3
Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Trace Macro Cell (ETM) Timing . . . . . . . . . . . . . . . . . . . . .
Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Delta-Sigma Demodulator Digital Interface Timing . . . . . . . . . . . . . .
Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . .
Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . .
USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . .
ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . .
ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
77
79
80
81
81
82
85
87
89
90
90
91
92
4
4.1
4.1.1
4.2
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
93
93
94
5
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Data Sheet
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XMC4400
XMC4000 Family
About this Document
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC4400 series devices.
The document describes the characteristics of a superset of the XMC4400 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4400 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
•
•
•
Reference Manual
– decribes the functionality of the superset of devices.
Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Data Sheet
7
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XMC4400
XMC4000 Family
Summary of Features
1
Summary of Features
The XMC4400 devices are members of the XMC4000 Family of microcontrollers based
on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance
and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial
Control, Power Conversion, Sense & Control.
System
Masters
System
Slaves
SCU
RTC
CPU
TM
®
ERU0
ARM Cortex -M4
GPDMA0
System
DCode
Ethernet
WDT
USB
OTG
ICode
FCE
Bus Matrix
Data
Code
PSRAM
PMU
ROM & Flash
USIC0
DSD
PBA0
POSIF1
CCU80
DSRAM1
CCU81
HRPWM
Peripherals 0
ERU1
Figure 1
VADC
POSIF0
DSRAM2
LEDTS0
CCU43
PORTS
DAC
PBA1
Peripherals 1
CCU40
CCU41
CCU42
USIC1
CAN
System Block Diagram
CPU Subsystem
•
•
•
•
•
•
•
CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
Floating Point Unit
Memory Protection Unit
Nested Vectored Interrupt Controller
One General Purpose DMA with up-to 8 channels
Event Request Unit (ERU) for programmable processing of external and internal
service requests
Flexible CRC Engine (FCE) for multiple bit error detection
Data Sheet
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XMC4400
XMC4000 Family
Summary of Features
On-Chip Memories
•
•
•
•
•
16 KB on-chip boot ROM
16 KB on-chip high-speed program memory
32 KB on-chip high speed data memory
32 KB on-chip high-speed communication memory
512 KB on-chip Flash Memory with 4 KB instruction cache
Communication Peripherals
•
•
•
•
•
Ethernet MAC module capable of 10/100 Mbit/s transfer rates
Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY
Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with two nodes,
64 message objects (MO), data rate up to 1MBit/s
Four Universal Serial Interface Channels (USIC), providing four serial channels,
usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
Analog Frontend Peripherals
•
•
•
Four Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
Delta Sigma Demodulator with four channels, digital input stage for A/D signal
conversion
Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
•
•
•
•
•
•
•
•
Two Capture/Compare Units 8 (CCU8) for motor control and power conversion
Four Capture/Compare Units 4 (CCU4) for use as general purpose timers
Four High Resoultion PWM (HRPWM) channels
Two Position Interfaces (POSIF) for servo motor positioning
Window Watchdog Timer (WDT) for safety sensitive applications
Die Temperature Sensor (DTS)
Real Time Clock module with alarm support
System Control Unit (SCU) for system configuration and control
Input/Output Lines
•
•
•
•
•
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Boundary scan test support over JTAG interface
Data Sheet
9
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XMC4400
XMC4000 Family
Summary of Features
On-Chip Debug Support
•
•
Full support for debug features: 8 breakpoints, CoreSight, trace
Various interfaces: ARM-JTAG, SWD, single wire trace
1.1
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
•
•
•
•
•
<DDD> the derivatives function set
<Z> the package variant
– E: LFBGA
– F: LQFP
– Q: VQFN
<PPP> package pin count
<T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
<FFFF> the Flash memory size.
For ordering codes for the XMC4400 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4400 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4400 is used for all derivatives throughout this document.
1.2
Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1
Synopsis of XMC4400 Device Types
1)
Derivative
Package
Flash
Kbytes
SRAM
Kbytes
XMC4400-F100x512
PG-LQFP-100
512
80
XMC4400-F64x512
PG-LQFP-64
512
80
XMC4400-F100x256
PG-LQFP-100
256
80
XMC4400-F64x256
PG-LQFP-64
256
80
XMC4402-F100x256
PG-LQFP-100
256
80
XMC4402-F64x256
PG-LQFP-64
256
80
1) x is a placeholder for the supported temperature range.
Data Sheet
10
V1.1, 2014-03
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XMC4400
XMC4000 Family
Summary of Features
1.3
Device Type Features
The following table lists the available features per device type.
Table 2
Features of XMC4400 Device Types
Derivative1)
LEDTS Intf. ETH
Intf.
USB
Intf.
USIC
Chan.
MultiCAN
Nodes, MO
XMC4400-F100x512
1
RMII
1
2x2
N0, N1
MO[0..63]
XMC4400-F64x512
1
RMII
1
2x2
N0, N1
MO[0..63]
XMC4400-F100x256
1
RMII
1
2x2
N0, N1
MO[0..63]
XMC4400-F64x256
1
RMII
1
2x2
N0, N1
MO[0..63]
XMC4402-F100x256
1
−
1
2x2
N0, N1
MO[0..63]
XMC4402-F64x256
1
−
1
2x2
N0, N1
MO[0..63]
1) x is a placeholder for the supported temperature range.
Table 3
Features of XMC4400 Device Types
Derivative1)
ADC
Chan.
DSD
Chan.
DAC
CCU4
Chan. Slice
CCU8
Slice
POSIF
Intf.
HRPWM
Intf.
XMC4400-F100x512
24
4
2
4x4
2x4
2
1
XMC4400-F64x512
14
4
2
4x4
2x4
2
1
XMC4400-F100x256
24
4
2
4x4
2x4
2
1
XMC4400-F64x256
14
4
2
4x4
2x4
2
1
XMC4402-F100x256
24
4
2
4x4
2x4
2
1
XMC4402-F64x256
14
4
2
4x4
2x4
2
1
1) x is a placeholder for the supported temperature range.
Data Sheet
11
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XMC4400
XMC4000 Family
Summary of Features
1.4
Definition of Feature Variants
The XMC4400 types are offered with several memory sizes and number of available
VADC channels. Table 4 describes the location of the available Flash memory, Table 5
describes the location of the available SRAMs, Table 6 the available VADC channels.
Table 4
Flash Memory Ranges
Total Flash Size
Cached Range
Uncached Range
256 Kbytes
0800 0000H −
0803 FFFFH
0C00 0000H −
0C03 FFFFH
512 Kbytes
0800 0000H −
0807 FFFFH
0C00 0000H −
0C07 FFFFH
Table 5
SRAM Memory Ranges
Total SRAM Size
Program SRAM
System Data SRAM Communication
Data SRAM
80 Kbytes
1FFF C000H −
1FFF FFFFH
2000 0000H −
2000 7FFFH
2000 8000H −
2000 FFFFH
AD Converter Channels1)
Table 6
Package
VADC G0
VADC G1
VADC G2
VADC G3
PG-LQFP-100
CH0..CH7
CH0..CH7
CH0..CH3
CH0..CH3
PG-LQFP-64
CH0,
CH3..CH7
CH0, CH1,
CH3, CH6
CH0, CH1
CH2, CH3
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
1.5
Identification Registers
The identification registers allow software to identify the marking.
Table 7
XMC4400 Identification Registers
Register Name
Value
Marking
SCU_IDCHIP
0004 4001H
EES-AA, ES-AA
SCU_IDCHIP
0004 4002H
ES-AB, AB
JTAG IDCODE
101D C083H
EES-AA, ES-AA
JTAG IDCODE
201D C083H
ES-AB, AB
Data Sheet
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XMC4400
XMC4000 Family
General Device Information
2
General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1
Logic Symbols
VAREF VAGND VDDA VSSA
(1)
(1)
(1) (1)
VDDC VDDP VSS
(4) (4) (1)
Exp. Die Pad
(VSS)
VBAT (1)
RTC_XTAL1
(1) VSSO
RTC_XTAL2
Port 0
13 bit
HIB_IO_0
HIB_IO_1
Port 1
16 bit
XTAL1
Port 2
13 bit
XTAL2
USB_DP
Port 3
7 bit
USB_DM
VBUS
Port 4
2 bit
Port 14
14 bit
Port 5
4 bit
Port 15
4 bit
PORST
TCK
JTAG
3 bit
TMS
Figure 2
Data Sheet
ETM / SWD
5 / 1 bit
via Port Pins
XMC4400 Logic Symbol PG-LQFP-100
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XMC4400
XMC4000 Family
General Device Information
VAREF VAGND
VDDA VSSA
(1)
(1)
VDDC VDDP VSS
(4) (4) (1)
Exp. Die Pad
(VSS)
VBAT (1)
RTC_XTAL1
(1) VSSO
RTC_XTAL2
Port 0
12 bit
HIB_IO_0
Port 1
9 bit
XTAL1
Port 2
10 bit
XTAL2
USB_DP
USB_DM
VBUS
Port 14
9 bit
PORST
TCK
JTAG
3 bit
TMS
Figure 3
Data Sheet
SWD
1 bit
via Port Pins
XMC4400 Logic Symbol PG-LQFP-64
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XMC4400
XMC4000 Family
General Device Information
2.2
Pin Configuration and Definition
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P0.2
P0.3
P0.4
P0.5
P0.6
P0.11
P0.12
P3.3
P3.4
P3.5
P3.6
P0.7
P0.8
VDDP
VDDC
P4.0
P4.1
P1.6
P1.7
P1.8
P1.9
P1.0
P1.1
P1.2
P1.3
The following figures summarize all pins, showing their locations on the different
packages.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XMC4400
(Top View)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1.4
P1.5
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
TCK
TMS
PORST
VDDC
VSSO
XTAL2
XTAL1
VDDP
VSS
P5.0
P5.1
P5.2
P5.7
P2.6
P2.7
P2.0
P2.1
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
VAGND
VAREF
VSSA
VDDA
P14.9
P14.8
P15.9
P15.8
P2.15
P2.14
VDDC
VDDP
P2.10
P2.9
P2.8
P2.5
P2.4
P2.3
P2.2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P0.1
P0.0
P0.10
P0.9
P3.2
P3.1
P3.0
USB_DM
USB_DP
VBUS
VDDP
VDDC
HIB_IO_1
HIB_IO_0
RTC_XTAL1
RTC_XTAL2
VBAT
P15.3
P15.2
P14.15
P14.14
P14.13
P14.12
P14.7
P14.6
Figure 4
Data Sheet
XMC4400 PG-LQFP-100 Pin Configuration (top view)
15
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P0.2
P0.3
P0.4
P0.5
P0.6
P0.11
P0.7
P0.8
VDDP
VDDC
P1.8
P1.9
P1.0
P1.1
P1.2
P1.3
General Device Information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XMC4400
(Top View)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.4
P1.5
P1.15
TCK
TMS
PORST
VDDC
VSSO
XTAL2
XTAL1
VDDP
VSS
P2.6
P2.7
P2.0
P2.1
P14.5
P14.4
P14.3
P14.0
VAGND
VAREF
P14.9
P14.8
VDDC
VDDP
P2.9
P2.8
P2.5
P2.4
P2.3
P2.2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P0.1
P0.0
P0.10
P0.9
USB_DM
USB_DP
VBUS
VDDP
VDDC
HIB_IO_0
RTC_XTAL1
RTC_XTAL2
VBAT
P14.14
P14.7
P14.6
Figure 5
Data Sheet
XMC4400 PG-LQFP-64 Pin Configuration (top view)
16
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
2.2.1
Package Pin Summary
The following general scheme is used to describe each pin:
Table 8
Package Pin Mapping Description
Function
Package A
Package B
...
Pad
Type
Name
N
Ax
...
A2
Notes
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the respective pin/function is given, i.e. deviations
from the default configuration after reset. Per default the regular Port pins are configured
as direct input with no internal pull device active.
Table 9
Package Pin Mapping
Function
LQFP-100
LQFP-64
Pad Type
P0.0
2
2
A1+
P0.1
1
1
A1+
P0.2
100
64
A2
P0.3
99
63
A2
P0.4
98
62
A2
P0.5
97
61
A2
Notes
P0.6
96
60
A2
P0.7
89
58
A2
After a system reset, via
HWSEL this pin selects the
DB.TDI function.
P0.8
88
57
A2
After a system reset, via
HWSEL this pin selects the
DB.TRST function, with a
weak pull-down active.
P0.9
4
4
A2
P0.10
3
3
A1+
P0.11
95
59
A1+
Data Sheet
17
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
Table 9
Function
Package Pin Mapping (cont’d)
LQFP-100
LQFP-64
Pad Type
P0.12
94
-
A1+
P1.0
79
52
A1+
P1.1
78
51
A1+
P1.2
77
50
A2
P1.3
76
49
A2
P1.4
75
48
A1+
P1.5
74
47
A1+
P1.6
83
-
A2
P1.7
82
-
A2
P1.8
81
54
A2
P1.9
80
53
A2
P1.10
73
-
A1+
P1.11
72
-
A1+
P1.12
71
-
A2
P1.13
70
-
A2
P1.14
69
-
A2
A2
P1.15
68
46
P2.0
52
34
A2
P2.1
51
33
A2
P2.2
50
32
A2
P2.3
49
31
A2
P2.4
48
30
A2
P2.5
47
29
A2
P2.6
54
36
A1+
P2.7
53
35
A1+
P2.8
46
28
A2
P2.9
45
27
A2
P2.10
44
-
A2
P2.14
41
-
A2
P2.15
40
-
A2
P3.0
7
-
A2
Data Sheet
18
Notes
After a system reset, via
HWSEL this pin selects the
DB.TDO function.
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
Table 9
Package Pin Mapping (cont’d)
Function
LQFP-100
LQFP-64
Pad Type
P3.1
6
-
A2
P3.2
5
-
A2
P3.3
93
-
A1+
P3.4
92
-
A1+
P3.5
91
-
A2
P3.6
90
-
A2
P4.0
85
-
A2
P4.1
84
-
A2
P5.0
58
-
A1+
P5.1
57
-
A1+
P5.2
56
-
A1+
P5.7
55
-
A1+
P14.0
31
20
AN/DIG_IN
P14.1
30
-
AN/DIG_IN
P14.2
29
-
AN/DIG_IN
P14.3
28
19
AN/DIG_IN
P14.4
27
18
AN/DIG_IN
P14.5
26
17
AN/DIG_IN
P14.6
25
16
AN/DIG_IN
P14.7
24
15
AN/DIG_IN
P14.8
37
24
AN/DAC/DIG_I
N
P14.9
36
23
AN/DAC/DIG_I
N
P14.12
23
-
AN/DIG_IN
P14.13
22
-
AN/DIG_IN
P14.14
21
14
AN/DIG_IN
P14.15
20
-
AN/DIG_IN
P15.2
19
-
AN/DIG_IN
P15.3
18
-
AN/DIG_IN
P15.8
39
-
AN/DIG_IN
P15.9
38
-
AN/DIG_IN
USB_DP
9
6
special
Data Sheet
19
Notes
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
Table 9
Function
Package Pin Mapping (cont’d)
LQFP-100
LQFP-64
Pad Type
Notes
USB_DM
8
5
special
HIB_IO_0
14
10
A1 special
At the first power-up and with
every reset of the hibernate
domain this pin is configured
as open-drain output and
drives "0".
As output the medium driver
mode is active.
HIB_IO_1
13
-
A1 special
At the first power-up and with
every reset of the hibernate
domain this pin is configured
as input with no pull device
active.
As output the medium driver
mode is active.
TCK
67
45
A1
Weak pull-down active.
TMS
66
44
A1+
Weak pull-up active.
As output the strong-soft
driver mode is active.
PORST
65
43
special
Strong pull-down controlled
by EVR.
Weak pull-up active while
strong pull-down is not
active.
XTAL1
61
39
clock_IN
XTAL2
62
40
clock_O
clock_IN
RTC_XTAL1
15
11
RTC_XTAL2
16
12
clock_O
VBAT
17
13
Power
VBUS
10
7
special
VAREF
33
-
AN_Ref
VAGND
32
-
AN_Ref
VDDA
35
-
AN_Power
VSSA
34
-
AN_Power
VDDA/VAREF
-
22
AN_Power/AN
_Ref
Data Sheet
20
When VDDP is supplied
VBAT has to be supplied as
well.
Shared analog supply and
reference voltage pin.
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
Table 9
Package Pin Mapping (cont’d)
Function
LQFP-100
LQFP-64
Pad Type
Notes
VSSA/VAGND
-
21
AN_Power/AN
_Ref
Shared analog supply and
reference ground pin.
Power
VDDC
12
9
VDDC
42
25
Power
VDDC
64
42
Power
VDDC
86
55
Power
VDDP
11
8
Power
VDDP
43
26
Power
VDDP
60
38
Power
VDDP
87
56
Power
VSS
59
37
Power
VSSO
63
41
Power
VSS
Exp. Pad
Exp. Pad
Power
Data Sheet
21
Exposed Die Pad
The exposed die pad is
connected internally to VSS.
For proper operation, it is
mandatory to connect the
exposed pad directly to the
common ground on the
board.
For thermal aspects, please
refer to the Data Sheet.
Board layout examples are
given in an application note.
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
General Device Information
2.2.2
Port I/O Functions
The following general scheme is used to describe each PORT pin:
Table 10
Port I/O Function Description
Function
Outputs
ALT1
ALTn
P0.0
Pn.y
Inputs
HWO0
HWI0
Input
MODA.OUT MODB.OUT MODB.INA
MODA.OUT
Input
MODC.INA
MODA.INA
MODC.INB
Pn.y
XMC4000
Control Logic
PAD
Input 0
MODA.INA
MODA
MODB
VDDP
...
Input n
HWI0
HWI1
Pn.y
SW
MODB.OUT
ALT1
...
ALTn
HWO0
HWO1
Figure 6
GND
Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly driven by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Data Sheet
22
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
Data Sheet
2.2.2.1
Port I/O Function Table
Table 11
Port I/O Functions
Function
Output
ALT1
P0.0
P0.1
USB.
DRIVEVBUS
P0.2
Input
ALT2
ALT3
ALT4
CAN.
N0_TXD
CCU80.
OUT21
LEDTS0.
COL2
U1C1.
DOUT0
CCU80.
OUT11
LEDTS0.
COL3
U1C1.
SELO1
CCU80.
OUT01
HRPWM0.
HROUT01
U1C0.
DOUT3
U1C0.
HWIN3
ETH0.
RXD0B
CCU80.
OUT20
HRPWM0.
HROUT20
U1C0.
DOUT2
U1C0.
HWIN2
ETH0.
RXD1B
P0.3
HWO0
HWI0
Input
Input
Input
Input
U1C1.
DX0D
ETH0.
CLK_RMIIB
ERU0.
0B0
Input
HRPWM0.
C1INB
ETH0.
CLKRXB
ETH0.
CRS_DVB
ERU0.
0A0
HRPWM0.
C2INB
ETH0.
RXDVB
ETH0.
TX_EN
CCU80.
OUT10
HRPWM0.
HROUT21
U1C0.
DOUT1
U1C0.
HWIN1
U1C0.
DX0A
ETH0.
TXD0
U1C0.
DOUT0
CCU80.
OUT00
HRPWM0.
HROUT00
U1C0.
DOUT0
U1C0.
HWIN0
U1C0.
DX0B
CCU80.
OUT30
HRPWM0.
HROUT30
ERU0.
2B3
ERU1.
3A0
23
ETH0.
TXD1
U1C0.
SELO0
U1C0.
DX2A
ERU0.
3B2
WWDT.
SERVICE_OUT
U0C0.
SELO0
HRPWM0.
HROUT11
DB.
TDI
U0C0.
DX2B
DSD.
DIN1A
ERU0.
2B1
CCU80.
IN0A
P0.8
SCU.
EXTCLK
U0C0.
SCLKOUT
HRPWM0.
HROUT10
DB.
TRST
U0C0.
DX1B
DSD.
DIN0A
ERU0.
2A1
CCU80.
IN1B
P0.9
HRPWM0.
HROUT31
U1C1.
SELO0
CCU80.
OUT12
LEDTS0.
COL0
ETH0.
MDIA
U1C1.
DX2A
USB.
ID
ERU0.
1B0
P0.10
ETH0.
MDC
U1C1.
SCLKOUT
CCU80.
OUT02
LEDTS0.
COL1
U1C0.
SCLKOUT
CCU80.
OUT31
U1C1.
SELO0
CCU40.
OUT3
U1C1.
DX1A
ETH0.
RXERB
DSD.
CGPWMN
U0C0.
SELO0
CCU40.
OUT3
ERU1.
PDOUT3
U0C0.
DX2A
DSD.
CGPWMP
U0C0.
SCLKOUT
CCU40.
OUT2
ERU1.
PDOUT2
U0C0.
DX1A
CCU40.
OUT1
ERU1.
PDOUT1
P1.3
P1.4
WWDT.
SERVICE_OUT
P1.5
CAN.
N1_TXD
P1.6
U0C0.
DOUT3
U0C0.
HWIN3
U0C0.
MCLKOUT
CCU40.
OUT0
ERU1.
PDOUT0
U0C0.
DOUT2
U0C0.
HWIN2
CAN.
N0_TXD
CCU80.
OUT33
CCU81.
OUT20
U0C0.
DOUT1
U0C0.
HWIN1
U0C0.
DOUT0
CCU80.
OUT23
CCU81.
OUT10
U0C0.
DOUT0
U0C0.
HWIN0
U0C0.
SCLKOUT
CCU80.
IN1A
CCU80.
IN2A
CCU80.
IN3A
ERU0.
1A0
U1C0.
DX1A
ERU0.
3A2
U1C1.
DX2B
ERU0.
2B2
ERU0.
3B0
CCU40.
IN3A
HRPWM0.
C0INA
POSIF0.
IN2A
ERU0.
3A0
CCU40.
IN2A
HRPWM0.
C1INA
CCU40.
IN1A
HRPWM0.
C2INA
POSIF0.
IN1A
ERU1.
2B0
POSIF0.
IN0A
ERU1.
2A0
U0C0.
DX0B
CAN.
N1_RXDD
ERU0.
2B0
U0C0.
DX0A
CAN.
N0_RXDA
ERU0.
2A0
DSD.
DIN2A
CCU80.
IN2B
ERU1.
0A0
CCU40.
IN0A
HRPWM0.
C0INB
CCU41.
IN0C
HRPWM0.
BL0A
CCU41.
IN1C
DSD.
DIN2B
XMC4400
XMC4000 Family
P1.0
P1.1
P1.2
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
P0.6
P0.7
P0.11
Input
ERU1.
3B0
P0.4
P0.12
Input
ERU0.
3B3
P0.5
ETH0.
MDO
Input
Data Sheet
Table 11
Port I/O Functions
Function
(cont’d)
Output
ALT1
Input
ALT2
ALT3
ALT4
P1.7
U0C0.
DOUT0
DSD.
MCLK2
U1C1.
SELO2
DSD.
MCLK2A
DSD.
MCLK0C
P1.8
U0C0.
SELO1
DSD.
MCLK1
U1C1.
SCLKOUT
DSD.
MCLK1A
DSD.
MCLK0
U1C1.
DOUT0
DSD.
MCLK0A
CCU81.
OUT21
P1.9
U0C0.
SCLKOUT
P1.10
ETH0.
MDC
U0C0.
SCLKOUT
U0C0.
SELO0
CCU81.
OUT11
P1.12
ETH0.
TX_EN
CAN.
N1_TXD
CCU81.
OUT01
P1.13
ETH0.
TXD0
U0C1.
SELO3
CCU81.
OUT20
P1.11
HWO0
Input
Input
Input
Input
Input
Input
Input
DSD.
MCLK0D
DSD.
MCLK2D
DSD.
MCLK3D
DSD.
MCLK1C
DSD.
MCLK2C
DSD.
MCLK3C
ETH0.
MDO
ETH0.
MDIC
CCU41.
IN3C
CAN.
N1_RXDC
24
P1.14
ETH0.
TXD1
U0C1.
SELO2
CCU81.
OUT10
SCU.
EXTCLK
DSD.
MCLK2
CCU81.
OUT00
U1C0.
DOUT0
DB.
ETM_TRACED
ATA3
P2.0
CAN.
N0_TXD
CCU81.
OUT21
DSD.
CGPWMN
LEDTS0.
COL1
ETH0.
MDO
CCU81.
OUT11
DSD.
CGPWMP
LEDTS0.
COL0
DB.TDO/
TRACESWO
DSD.
MCLK2B
ETH0.
MDIB
ERU1.
1A0
ERU0.
0B3
ETH0.
CLK_RMIIA
CCU40.
IN1C
ERU1.
0B0
CCU40.
IN0C
ETH0.
CLKRXA
VADC.
EMUX00
CCU81.
OUT01
CCU41.
OUT3
LEDTS0.
LINE0
LEDTS0.
EXTENDED0
LEDTS0.
TSIN0A
ETH0.
RXD0A
U0C1.
DX0A
ERU0.
1B2
VADC.
EMUX01
U0C1.
SELO0
CCU41.
OUT2
LEDTS0.
LINE1
LEDTS0.
EXTENDED1
LEDTS0.
TSIN1A
ETH0.
RXD1A
U0C1.
DX2A
ERU0.
1A2
POSIF1.
IN2A
CCU41.
IN2A
P2.4
VADC.
EMUX02
U0C1.
SCLKOUT
CCU41.
OUT1
LEDTS0.
LINE2
LEDTS0.
EXTENDED2
LEDTS0.
TSIN2A
ETH0.
RXERA
U0C1.
DX1A
ERU0.
0B2
POSIF1.
IN1A
CCU41.
IN1A
HRPWM0.
BL1A
P2.5
ETH0.
TX_EN
U0C1.
DOUT0
CCU41.
OUT0
LEDTS0.
LINE3
LEDTS0.
EXTENDED3
LEDTS0.
TSIN3A
ETH0.
CRS_DVA
U0C1.
DX0B
ERU0.
0A2
POSIF1.
IN0A
CCU41.
IN0A
HRPWM0.
BL2A
CCU80.
OUT13
LEDTS0.
COL3
DSD.
DIN1B
CAN.
N1_RXDA
ERU0.
1B3
P2.7
ETH0.
MDC
CCU80.
OUT03
LEDTS0.
COL2
ETH0.
TXD0
CCU80.
OUT32
LEDTS0.
LINE4
LEDTS0.
EXTENDED4
LEDTS0.
TSIN4A
DAC.
TRIGGER5
CCU40.
IN0B
CCU40.
IN1B
CCU40.
IN2B
CCU40.
IN3B
CCU80.
OUT22
LEDTS0.
LINE5
LEDTS0.
EXTENDED5
LEDTS0.
TSIN5A
DAC.
TRIGGER4
CCU41.
IN0B
CCU41.
IN1B
CCU41.
IN2B
CCU41.
IN3B
U1C0.
DX0D
CCU43.
IN0B
CCU43.
IN1B
CCU43.
IN2B
CCU43.
IN3B
U1C0.
DX0C
CCU42.
IN0B
CCU42.
IN1B
CCU42.
IN2B
CCU42.
IN3B
P2.9
ETH0.
TXD1
VADC.
EMUX10
P2.14
VADC.
EMUX11
P2.15
VADC.
EMUX12
U1C0.
DOUT0
CCU80.
OUT21
CCU80.
OUT11
DSD.
DIN0B
ETH0.
CRS_DVA
CCU40.
IN3C
P2.8
P2.10
CAN.
N1_TXD
CCU41.
IN3A
DB.
ETM_TRACEC
LK
LEDTS0.
LINE6
LEDTS0.
EXTENDED6
LEDTS0.
TSIN6A
ETH0.
COLA
ERU1.
1B0
CCU40.
IN2C
XMC4400
XMC4000 Family
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
P2.2
P2.3
P2.6
Input
CCU41.
IN2C
P1.15
P2.1
HWI0
Data Sheet
Table 11
Port I/O Functions
Function
ALT1
ALT2
ALT3
P3.0
U0C1.
SCLKOUT
CCU42.
OUT0
P3.1
U0C1.
SELO0
P3.2
(cont’d)
Output
USB.
DRIVEVBUS
P3.3
CCU42.
OUT2
DSD.
MCLK3
CCU42.
OUT1
U0C1.
DOUT0
P3.6
U1C1.
SELO4
CCU42.
OUT0
U0C1.
SCLKOUT
DSD.
MCLK1
25
P4.1
U1C1.
MCLKOUT
DSD.
MCLK0
P5.0
DSD.
CGPWMN
CCU81.
OUT33
Input
Input
ERU0.
0B1
ERU0.
0A1
DB.
ETM_TRACED
ATA1
U0C1.
SELO0
U1C1.
DX1C
DB.
ETM_TRACED
ATA2
DSD.
MCLK1B
CCU42.
IN3A
CCU80.
IN3B
CCU42.
IN2A
CCU80.
IN0B
ERU0.
3B1
CCU42.
IN1A
ERU0.
3A1
CCU42.
IN0A
Input
CCU81.
IN2A
CCU81.
IN3A
DSD.
MCLK1D
U0C0.
DX0D
CCU81.
IN0A
ETH0.
RXD1D
CCU81.
IN0B
CCU81.
OUT23
ETH0.
CRS_DVD
CCU81.
IN1B
P5.7
CCU81.
OUT02
CCU81.
IN1A
ETH0.
RXDVD
LEDTS0.
COLA
P14.0
VADC.
G0CH0
P14.1
VADC.
G0CH1
P14.2
VADC.
G0CH2
VADC.
G1CH2
P14.3
VADC.
G0CH3
VADC.
G1CH3
P14.4
VADC.
G0CH4
VADC.
G2CH0
P14.5
VADC.
G0CH5
VADC.
G2CH1
P14.6
VADC.
G0CH6
P14.7
CAN.
N0_RXDB
POSIF0.
IN2B
VADC.
G0CH7
DAC.
OUT_0
VADC.
G1CH0
VADC.
G3CH2
POSIF0.
IN1B
G0ORC6
POSIF0.
IN0B
G0ORC7
ETH0.
RXD0C
XMC4400
XMC4000 Family
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
CCU81.
OUT32
P5.2
P14.8
Input
U0C1.
DX0E
DSD.
MCLK0B
ETH0.
RXD0D
Input
CCU81.
IN0C
CCU80.
IN0C
DSD.
MCLK3B
DB.
ETM_TRACED
ATA0
Input
CCU80.
IN2C
CCU80.
IN1C
DSD.
DIN3B
U1C1.
SELO2
DSD.
CGPWMP
Input
LEDTS0.
COLA
U1C1.
SELO3
U0C0.
DOUT0
Input
CCU42.
OUT3
P3.4
P5.1
HWI0
U0C1.
DX1B
P3.5
P4.0
HWO0
U0C1.
DX2B
CAN.
N0_TXD
U1C1.
SELO1
Input
ALT4
Data Sheet
Table 11
Port I/O Functions
Function
(cont’d)
Output
ALT1
ALT2
P14.9
ALT3
Input
ALT4
HWO0
HWI0
Input
DAC.
OUT_1
Input
Input
VADC.
G1CH1
P14.12
VADC.
G1CH4
P14.13
VADC.
G1CH5
P14.14
VADC.
G1CH6
P14.15
VADC.
G1CH7
Input
Input
VADC.
G3CH3
ETH0.
RXD1C
Input
Input
Input
G1ORC6
G1ORC7
P15.2
VADC.
G2CH2
P15.3
VADC.
G2CH3
P15.8
VADC.
G3CH0
ETH0.
CLK_RMIIC
ETH0.
CLKRXC
P15.9
VADC.
G3CH1
ETH0.
CRS_DVC
ETH0.
RXDVC
USB_DP
26
USB_DM
HIBOUT
WWDT.
SERVICE_OUT
HIB_IO_1
HIBOUT
WWDT.
SERVICE_OUT
WAKEUPA
WAKEUPB
TCK
TMS
DB.TCK/
SWCLK
DB.TMS/
SWDIO
PORST
XTAL1
U0C0.
DX0F
U0C1.
DX0F
U1C0.
DX0F
U1C1.
DX0F
XTAL2
RTC_XTAL1
ERU0.
1B1
XMC4400
XMC4000 Family
RTC_XTAL2
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
HIB_IO_0
XMC4400
XMC4000 Family
2.3
Power Connection Scheme
Figure 7. shows a reference power connection scheme for the XMC4400.
XMC4000
VBAT
Hibernate domain
2.0...3.6 V
Hibernate
control
Retention
Memory
RTC
32 kHz
Clock
GND
M x VDDC
Core Domain
100 nF x M
Dig.
Peripherals
GPIOs
4.7 µF x 1
CPU
RAMs
Level
shift.
GND
3.3V
N x VDDP
100 nF x N
EVR
FLASH
VSS
10 µF x 1
Exp. Die Pad
PAD Domain
VSS
Analog Domain
GND
Reference
VAREF
100 nF
VAGND
3.3V
AGND
100 nF
ADC
DAC
Out-of-range comparator
VDDA
VSSA
GND
Figure 7
Power Connection Scheme
Every power supply pin needs to be connected. Different pins of the same supply need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and
an additional 4.7uF capacitor to the VDDC nets.
Data Sheet
27
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
The XMC4400 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
VAGND is the low potential to the analog reference VAREF. Depending on the application it
can share the common ground or have a different potential. In devices with shared
VDDA/VAREF and VSSA/VAGND pins the reference is tied to the supply. Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP.
Data Sheet
28
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3
Electrical Parameters
3.1
General Parameters
3.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the XMC4400
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with an two-letter abbreviation in
column “Symbol”:
•
•
CC
Such parameters indicate Controller Characteristics, which are a distinctive feature
of the XMC4400 and must be regarded for system design.
SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4400 is designed in.
Data Sheet
29
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.1.2
Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 12
Absolute Maximum Rating Parameters
Parameter
Symbol
Values
Min. Typ. Max.
–
150
°C
–
−
150
°C
–
–
4.3
V
–
–
VDDP + 1.0
or max. 4.3
V
whichever
is lower
VAIN
-1.0 –
VAREF SR
IIN
SR -10 –
VDDP + 1.0
or max. 4.3
V
whichever
is lower
+10
mA
+25
mA
+100
mA
TST SR -65
Junction temperature
TJ
SR -40
Voltage at 3.3 V power supply VDDP SR –
pins with respect to VSS
Voltage on any Class A and VIN
SR -1.0
Storage temperature
dedicated input pin with
respect to VSS
Voltage on any analog input
pin with respect to VAGND
Input current on any pin
during overload condition
Unit Note /
Test Con
dition
Absolute maximum sum of all ΣIIN
input circuit currents for one
port group during overload
condition1)
SR -25
Absolute maximum sum of all ΣIIN
input circuit currents during
overload condition
SR -100 –
–
1) The port groups are defined in Table 16.
Data Sheet
30
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Figure 8 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
V
V
4.3
VDDP + 1.0
VDDP
A
B
Figure 8
3.1.3
V SS
VSS
-1.0
-1.0
A
Abs. max. input voltage VIN with VDDP > 3.3 V
B
Abs. max. input voltage VIN with VDDP ≤ 3.3 V
Absolute Maximum Input Voltage Ranges
Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 13 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
•
•
full operation life-time is not exceeded
Operating Conditions are met for
– pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
parameters, then the parameters functionality of this pin as stated in the Operating
Conditions can no longer be guaranteed. Operation is still possible in most cases but
with relaxed parameters.
Note: An overload condition on one or more pins does not require a reset.
Data Sheet
31
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
Table 13
Overload Parameters
Parameter
Symbol
Values
Min.
Typ.
Unit Note /
Test Condition
Max.
-5
–
5
mA
Input current on any port pin
during overload condition
IOV SR
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
IOVG SR –
–
20
mA
–
–
20
mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR –
–
80
mA
Σ|IOVx|, for all
IOVx < 0 mA
Σ|IOVx|, for all
IOVx > 0 mA
ΣIOVG
1) The port groups are defined in Table 16.
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
VDDP VDDP
Pn.y
IOVx
GND
ESD
Figure 9
GND
Pad
Input Overload Current via ESD structures
Table 14 and Table 15 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the Absolute Maximum
Ratings must not be exceeded during overload.
Data Sheet
32
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 14
PN-Junction Characterisitics for positive Overload
IOV = 5 mA, TJ = -40 °C
VIN = VDDP + 1.0 V
VIN = VDDP + 0.7 V
VIN = VDDP + 1.0 V
Pad Type
A1 / A1+
A2
AN/DIG_IN
Table 15
PN-Junction Characterisitics for negative Overload
IOV = 5 mA, TJ = -40 °C
VIN = VSS - 1.0 V
VIN = VSS - 0.7 V
VIN = VDDP - 1.0 V
Pad Type
A1 / A1+
A2
AN/DIG_IN
Table 16
IOV = 5 mA, TJ = 150 °C
VIN = VSS - 0.75 V
VIN = VSS - 0.6 V
VIN = VDDP - 0.75 V
Port Groups for Overload and Short-Circuit Current Sum
Parameters
Group
Pins
1
P0.[12:0], P3.[6:0]
2
P14.[15:0], P15.[9:2]
3
P2.[15:0], P5.[7:0]
4
P1.[15:0], P4.[1:0]
3.1.4
IOV = 5 mA, TJ = 150 °C
VIN = VDDP + 0.75 V
VIN = VDDP + 0.6 V
VIN = VDDP + 0.75 V
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic
characteristics. More details (mainly DC parameters) are defined in the Section 3.2.1.
Table 17
Pad Driver and Pad Classes Overview
Class Power Type
Supply
Sub-Class
Speed
Grade
Load
A
A1
(e.g. GPIO)
6 MHz
100 pF No
A1+
(e.g. serial I/Os)
25 MHz
50 pF
Series termination
recommended
A2
(e.g. ext. Bus)
80 MHz
15 pF
Series termination
recommended
3.3 V
Data Sheet
LVTTL
I/O,
LVTTL
outputs
33
Termination
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
V
VDDP
F
E
e
oltag
igh V
ut H
Outp
D
C
B
VOH
A
VOL
w
ut Lo
Outp
ge
Volta
VSS
t
Strong – sharp drive strength
D
B
Strong – medium drive strength
E
Medium drive strength
C
Strong – soft drive strength
F
Weak drive strength
A
A
B
C
C
Figure 10
D
E
F
Class A2 Pads
E
F
Class A1+ Pads
E
F
Class A1 Pads
Strong – slow drive strength
Output Slopes with different Pad Driver Modes
Figure 10 is a qualitative display of the resulting output slope performance with
different output driver modes. The detailed input and output characteristics are listed in
Section 3.2.1.
Data Sheet
34
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.1.5
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4400. All parameters specified in the following tables
refer to these operating conditions, unless noted otherwise.
Table 18
Operating Conditions Parameters
Parameter
Symbol
Values
Min.
Note /
Test Condition
85
°C
Temp. Range F
−
125
°C
Temp. Range K
3.3
3.632)
V
1.3
−
V
−
−
Max.
SR -40
−
-40
Ambient Temperature
TA
Digital supply voltage
VDDP SR 3.131)
VDDC
−1)
Core Supply Voltage
Unit
Typ.
CC
Digital ground voltage
ADC analog supply
voltage
VSS SR 0
VDDA SR 3.0
Analog ground voltage for VSSA SR -0.1
Generated
internally
V
2)
3.3
3.6
V
0
0.1
V
−
3.63
V
−
120
MHz
−
5
mA
VDDA
Battery Supply Voltage for VBAT SR 1.95
Hibernate Domain3)
System Frequency
Short circuit current of
digital outputs
fSYS SR −
ISC SR -5
Absolute sum of short
circuit currents per pin
group4)
ΣISC_PG
SR
−
−
20
mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
SR
−
−
100
mA
When VDDP is
supplied VBAT
has to be
supplied as
well.
1) See also the Supply Monitoring thresholds, Section 3.3.2.
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.
3) Different limits apply for LPAC operation, Section 3.2.6
4) The port groups are defined in Table 16.
Data Sheet
35
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2
DC Parameters
3.2.1
Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19
Standard Pad Parameters
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Max.
−
10
pF
|IPDL|
CC
150
−
μA
1)
−
10
μA
2)
Pull-Up current
|IPUH|
CC
−
10
μA
100
−
μA
Input Hysteresis for
pads of all A classes3)
HYSA
0.1 ×
−
V
CC
VDDP
PORST spike filter
always blocked pulse
duration
tSF1 CC
−
10
ns
PORST spike filter
pass-through pulse
duration
tSF2 CC
100
−
ns
PORST pull-down
current
|IPPD|
CC
13
−
mA
Pin capacitance (digital CIO CC
inputs/outputs)
Pull-down current
VIN ≥ 0.6 × VDDP
VIN ≤ 0.36 × VDDP
2)
VIN ≥ 0.6 × VDDP
1)
VIN ≤ 0.36 × VDDP
VIN = 1.0 V
1) Current required to override the pull device with the opposite logic level (“force current”).
With active pull device, at load currents between force and keep current the input state is undefined.
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
36
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
V
VDDP
XMC4000
IN
IPDL
A
IPDL ≥ 150 μA
B
IPDL ≤ 10 μA
A Valid High
0.6 x VDDP
Invalid digital input
0.36 x VDDP
B Valid Low
GND
VSS
Pull-down active
V
VDDP
VDDP
B Valid High
0.6 x VDDP
B
IN
XMC4000
IPUH
A
IPUH ≤ 10 μA
Invalid digital input
0.36 x VDDP
IPUH ≥ 100 μA
A Valid Low
VSS
Pull-up active
Figure 11
Pull Device Input Characteristics
Figure 11 visualizes the input characteristics with an active internal pull device:
•
•
in the cases “A” the internal pull device is overridden by a strong external driver;
in the cases “B” the internal pull device defines the input logical state against a weak
external load.
Data Sheet
37
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 20
Standard Pads Class_A1
Parameter
Symbol
Values
Min.
Input leakage current
Input high voltage
Input low voltage
Output high voltage,
POD1) = weak
IOZA1 CC
VIHA1 SR
VILA1 SR
VOHA1
CC
Output high voltage,
POD1) = medium
Output low voltage
VOLA1
Unit
Max.
nA
Note /
Test Condition
0 V ≤ VIN ≤ VDDP
-500
500
0.6 × VDDP
max. 3.6 V
-0.3
VDDP + 0.3 V
0.36 × VDDP V
VDDP - 0.4
−
V
2.4
−
V
VDDP - 0.4
−
V
IOH ≥ -400 μA
IOH ≥ -500 μA
IOH ≥ -1.4 mA
IOH ≥ -2 mA
IOL ≤ 500 μA;
2.4
−
V
−
0.4
V
POD1) = weak
CC
−
0.4
V
IOL ≤ 2 mA;
POD1) = medium
tFA1 CC
Fall time
tRA1 CC
Rise time
−
150
ns
CL = 20 pF;
POD1) = weak
−
50
ns
CL = 50 pF;
POD1) = medium
−
150
ns
CL = 20 pF;
POD1) = weak
−
50
ns
CL = 50 pF;
POD1) = medium
Unit
Note /
Test Condition
μA
0 V ≤ VIN ≤ VDDP
1) POD = Pin Out Driver
Table 21
Standard Pads Class_A1+
Parameter
Symbol
Values
Input leakage current
IOZA1+ CC -1
VIHA1+ SR 0.6 × VDDP
VILA1+ SR -0.3
Min.
Input high voltage
Input low voltage
Data Sheet
Max.
38
1
VDDP + 0.3 V
0.36 × VDDP V
max. 3.6 V
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 21
Standard Pads Class_A1+
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
IOH ≥ -400 μA
IOH ≥ -500 μA
IOH ≥ -1.4 mA
IOH ≥ -2 mA
IOH ≥ -1.4 mA
IOH ≥ -2 mA
IOL ≤ 500 μA;
Max.
VOHA1+
VDDP - 0.4
−
V
CC
2.4
−
V
Output high voltage,
POD1) = medium
VDDP - 0.4
−
V
2.4
−
V
Output high voltage,
POD1) = strong
VDDP - 0.4
−
V
2.4
−
V
−
0.4
V
Output high voltage,
POD1) = weak
Output low voltage
VOLA1+
POD1) = weak
CC
−
0.4
V
IOL ≤ 2 mA;
POD1) = medium
−
0.4
V
IOL ≤ 2 mA;
POD1) = strong
Fall time
tFA1+ CC
−
150
ns
CL = 20 pF;
POD1) = weak
−
50
ns
CL = 50 pF;
POD1) = medium
−
28
ns
CL = 50 pF;
POD1) = strong;
edge = slow
−
16
ns
CL = 50 pF;
POD1) = strong;
edge = soft;
Rise time
tRA1+ CC
−
150
ns
CL = 20 pF;
POD1) = weak
−
50
ns
CL = 50 pF;
POD1) = medium
−
28
ns
CL = 50 pF;
POD1) = strong;
edge = slow
−
16
ns
CL = 50 pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Data Sheet
39
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 22
Standard Pads Class_A2
Parameter
Symbol
Input Leakage current IOZA2
CC
Input high voltage
VIHA2
Values
Unit
Note /
Test Condition
Min.
Max.
-6
6
μA
0 V ≤ VIN <
0.5*VDDP - 1 V;
0.5*VDDP + 1 V
<VIN ≤ VDDP
-3
3
μA
0.5*VDDP - 1 V <
VIN < 0.5*VDDP
+1V
0.6 × VDDP
VDDP + 0.3 V
max. 3.6 V
SR
Input low voltage
0.36 ×
VILA2 SR -0.3
V
VDDP
VOHA2
VDDP - 0.4
−
V
CC
2.4
−
V
Output high voltage,
POD = medium
VDDP - 0.4
−
V
2.4
−
V
Output high voltage,
POD = strong
VDDP - 0.4
−
V
2.4
−
V
−
0.4
V
IOH ≥ -400 μA
IOH ≥ -500 μA
IOH ≥ -1.4 mA
IOH ≥ -2 mA
IOH ≥ -1.4 mA
IOH ≥ -2 mA
IOL ≤ 500 μA
Output low voltage,
POD = medium
−
0.4
V
IOL ≤ 2 mA
Output low voltage,
POD = strong
−
0.4
V
IOL ≤ 2 mA
Output high voltage,
POD = weak
Output low voltage,
POD = weak
Data Sheet
VOLA2
CC
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XMC4000 Family
Electrical Parameters
Table 22
Parameter
Fall time
Rise time
Data Sheet
Standard Pads Class_A2
Symbol
tFA2 CC
Values
Unit
Note /
Test Condition
150
ns
CL = 20 pF;
POD = weak
−
50
ns
CL = 50 pF;
POD = medium
−
3.7
ns
CL = 50 pF;
POD = strong;
edge = sharp
−
7
ns
CL = 50 pF;
POD = strong;
edge = medium
−
16
ns
CL = 50 pF;
POD = strong;
edge = soft
150
ns
CL = 20 pF;
POD = weak
−
50
ns
CL = 50 pF;
POD = medium
−
3.7
ns
CL = 50 pF;
POD = strong;
edge = sharp
−
7.0
ns
CL = 50 pF;
POD = strong;
edge = medium
−
16
ns
CL = 50 pF;
POD = strong;
edge = soft
Min.
Max.
−
tRA2 CC −
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Electrical Parameters
Table 23
HIB_IO Class_A1 special Pads
Parameter
Input leakage current
Symbol
IOZHIB
Values
Unit
Note /
Test Condition
500
nA
0 V ≤ VIN ≤ VBAT
0.6 × VBAT
VBAT + 0.3
V
max. 3.6 V
-0.3
0.36 × VBAT V
Min.
Max.
-500
CC
Input high voltage
VIHHIB
SR
Input low voltage
VILHIB
SR
HYSHIB 0.1 × VBAT
−
V
CC
0.06 ×
−
V
VBAT ≥ 3.13 V
VBAT < 3.13 V
Output high voltage,
POD1) = medium
VOHHIB
VBAT
VBAT - 0.4
−
V
IOH ≥ -1.4 mA
Output low voltage
VOLHIB
−
0.4
V
IOL ≤ 2 mA
tFHIB CC −
50
ns
100
ns
50
ns
100
ns
VBAT ≥ 3.13 V
CL = 50 pF
VBAT < 3.13 V
CL = 50 pF
VBAT ≥ 3.13 V
CL = 50 pF
VBAT < 3.13 V
CL = 50 pF
Input Hysteresis for
HIB_IO pins1)
CC
CC
Fall time
−
Rise time
tRHIB CC −
−
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
3.2.2
Analog to Digital Converters (ADCx)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 24
ADC Parameters (Operating Conditions apply)
Parameter
Symbol
Analog reference voltage5) VAREF
SR
Analog reference ground5) VAGND
SR
Analog reference voltage
range2)5)
VAREF VAGND
Values
Unit
Min.
Typ. Max.
VAGND
−
+1
VDDA + V
0.051)
VSSM - −
VAREF - V
0.05
1
−
1
Note /
Test Condition
VDDA + V
0.1
SR
Analog input voltage
Input leakage at analog
inputs3)
VAIN SR
IOZ1 CC
VAGND
−
VDDA
V
-100
−
200
nA
0.03 × VDDA <
VAIN < 0.97 × VDD
-500
−
100
nA
0 V ≤ VAIN ≤ 0.03
× VDDA
-100
−
500
nA
0.97 × VDDA
≤ VAIN ≤ VDDA
A
Input leakage current at
VAREF
IOZ2 CC
-1
−
1
μA
0 V ≤ VAREF
≤ VDDA
Input leakage current at
VAGND
IOZ3 CC
-1
−
1
μA
0 V ≤ VAGND
≤ VDDA
Internal ADC clock
fADCI CC 2
CAINSW −
−
30
MHz VDDA = 3.3 V
7
20
pF
−
25
30
pF
CAREFSW −
15
30
pF
20
40
pF
Switched capacitance at
the analog voltage inputs4) CC
Total capacitance of an
analog input
Switched capacitance at
the positive reference
voltage input5)6)
CAINTOT
CC
CC
Total capacitance of the
CAREFTOT −
voltage reference inputs5) CC
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
Table 24
ADC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Total Unadjusted Error
Differential Non-Linearity
Error8)
Gain Error8)
Unit
Note /
Test Condition
12-bit resolution7);
VDDA = 3.3 V;
VAREF = VDDA,
dedicated pins for
VDDA and VAREF
Typ. Max.
−
4
LSB
−
3
LSB
-4
−
4
LSB
EAINLCC -3
EAOFF
-4
−
3
LSB
−
4
LSB
−
6
LSB
−
4.5
LSB
−
6
LSB
TUE CC -4
EADNL
-3
CC
EAGAIN
CC
Integral Non-Linearity8)
Offset Error
8)
CC
Total Unadjusted Error
Differential Non-Linearity
Error8)
Gain Error8)
TUE CC -6
EADNL
-4.5
CC
EAGAIN
-6
CC
Integral Non-Linearity8)
Offset Error8)
12-bit resolution7);
VDDA = 3.3 V;
VAREF = VDDA,
shared pin for
VDDA and VAREF
(PG-LQFP-64)
−
4.5
LSB
−
6
LSB
−
1.5
2
mA
during conversion
VDDP = 3.6 V,
TJ = 150 oC
−
30
−
pC
0 V ≤ VAREF
≤ VDDA9)
700
1 700
Ohm
180
550
900
Ohm
−
700
1 700
Ohm
EAINLCC -4.5
EAOFF
-6
CC
Worst case ADC VDDA
power supply current per
active converter
IDDAA
Charge consumption on
VAREF per conversion5)
QCONV
ON resistance of the
analog input path
RAIN CC −
CC
CC
ON resistance for the ADC RAIN7T
test (pull down for AIN7)
CC
Resistance of the
reference voltage input
path
RAREF
CC
1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).
2) If the analog reference voltage is below VDDA, then the ADC converter errors increase. If the reference voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.
3) The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function (see Figure 14).
Data Sheet
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XMC4000 Family
Electrical Parameters
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead, smaller capacitances are successively switched to the reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.
9) The resulting current for a conversion can be calculated with IAREF = QCONV / tc.
The fastest 12-bit post-calibrated conversion of tc = 550 ns results in a typical average current of
IAREF = 54.5 µA.
V
VDDA + 0.05
VDDA
Precise conversion range (12 bit)
VAREF
e.g. VAREF = 4/5 of VDDA
Valid V AREF
Conversion error
increases by 5/4
VAGND + 1
Minimum VAREF - VAGND is 1 V
VAGND
VSSA
t
Figure 12
Data Sheet
VADC Reference Voltage Range
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Electrical Parameters
The power-up calibration of the ADC requires a maximum number of 4 352 fADCI cycles.
REXT
VAIN =
Analog Input Circuitry
RAIN, On
ANx
CEXT
CAINSW
CAINTOT - CAINSW
VAGNDx
RAIN7T
Reference Voltage Input Circuitry
RAREF, On
VAREFx
VAREF
CAREFTOT - CAREFSW
CAREFSW
VAGNDx
Analog_InpRefDiag
Figure 13
ADCx Input Circuits
IOZ1
Single ADC Input
500 nA
200 nA
100 nA
V IN [% VD D A]
-100 nA
3%
97%
100%
-500 nA
ADC-Leakage.vsd
Figure 14
Data Sheet
ADCx Analog Input Leakage Current
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Electrical Parameters
Conversion Time
Table 25
Conversion Time (Operating Conditions apply)
Parameter
Symbol Values
Conversion
time
tC
•
•
•
Unit Note
CC 2 × TADC +
(2 + N + STC + PC +DM) × TADCI
μs
N = 8, 10, 12 for
N-bit conversion
TADC = 1 / fPERIPH
TADCI = 1 / fADCI
STC defines additional clock cycles to extend the sample time
PC adds two cycles if post-calibration is enabled
DM adds one cycle for an extended conversion time of the MSB
Conversion Time Examples
System assumptions:
fADC = 120 MHz i.e. tADC = 8.33 ns, DIVA = 3, fADCI = 30 MHz i.e. tADCI = 33.3 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 33.3 ns + 2 × 8.33 ns = 550 ns
12-bit uncalibrated conversion:
tCN12 = (2 + 12) × tADCI + 2 × tADC = 14 × 33.3 ns + 2 × 8.33 ns = 483 ns
10-bit uncalibrated conversion:
tCN10 = (2 + 10) × tADCI + 2 × tADC = 12 × 33.3 ns + 2 × 8.33 ns = 417 ns
8-bit uncalibrated:
tCN8 = (2 + 8) × tADCI + 2 × tADC = 10 × 33.3 ns + 2 × 8.33 ns = 350 ns
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
3.2.3
Digital to Analog Converters (DACx)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 26
DAC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
per active DAC
channel,
without load
currents of DAC
outputs
RMS supply current
IDD
−
2.5
4
mA
Resolution
RES
CC −
fURATE_ACC −
12
−
Bit
Update rate
2
Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate
fURATE_F CC −
5
Msam data rate, where
ple/s DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
Settling time
tSETTLE CC −
1
2
μs
Slew rate
SR
CC
VOUT_MIN
2
5
−
V/μs
−
0.3
−
V
code value
unsigned: 000H;
signed: 800H
−
2.5
−
V
code value
unsigned: FFFH;
signed: 7FFH
Minimum output
voltage
CC
CC
at full scale jump,
output voltage
reaches target
value ± 20 LSB
Maximum output
voltage
VOUT_MAX
Integral nonlinearity1)
INL
CC -5.5
±2.5
5.5
LSB
RL ≥ 5 kOhm,
CL ≤ 50 pF
Differential nonlinearity
DNL
CC -2
±1
2
LSB
RL ≥ 5 kOhm,
CL ≤ 50 pF
Data Sheet
CC
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XMC4000 Family
Electrical Parameters
Table 26
DAC Parameters (Operating Conditions apply) (cont’d)
Parameter
Symbol
Values
Min.
Offset error
Gain error
Startup time
3dB Bandwidth of
Output Buffer
Output sourcing
current
Typ.
Unit
Max.
Note /
Test Condition
EDOFF CC
EDG_IN CC -5
tSTARTUP CC −
0
5
%
15
30
μs
time from output
enabling till code
valid ±16 LSB
fC1
5
−
MHz
verified by design
-30
−
mA
−
0.6
−
mA
CC 2.5
IOUT_SOURCE −
±20
mV
CC
Output sinking
current
IOUT_SINK
Output resistance
ROUT
RL
CL
CC −
50
−
Ohm
SR 5
−
−
kOhm
SR −
−
50
pF
Signal-to-Noise
Ratio
SNR
CC
−
70
−
dB
examination
bandwidth < 25 kHz
Total Harmonic
Distortion
THD
CC
−
70
−
dB
examination
bandwidth < 25 kHz
Power Supply
Rejection Ratio
PSRR CC
−
56
−
dB
to VDDA
verified by design
Load resistance
Load capacitance
CC
1) According to best straight line method.
Conversion Calculation
Unsigned:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
DAC output
VOUT_MAX
+/- 4LSB
+/- 1LSB
64 LSBs
64 LSBs
VOUT_MIN
fURATE_A (max)
fURATE_F (max)
DAC output
20 LSBs
VOUT_MAX
tSETTLE
tSETTLE
20 LSBs
VOUT_MIN
Figure 15
Data Sheet
DAC Conversion Examples
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Electrical Parameters
3.2.4
Out-of-Range Comparator (ORC)
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The
parameters
in
Table 27
apply
for
the
maximum
reference
voltage
VAREF = VDDA + 50 mV.
Table 27
ORC Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Min.
DC Switching Level VODC
Hysteresis
CC 100
Max.
125
200
mV
−
VODC
mV
CC 55
−
450
ns
45
−
105
ns
−
−
ns
−
−
ns
VOHYS CC 50
Detection Delay of a tODD
persistent
Overvoltage
Unit Note / Test Condition
Typ.
Always detected
Overvoltage Pulse
tOPDD CC 440
Never detected
Overvoltage Pulse
tOPDN CC −
−
49
ns
−
−
30
ns
Release Delay
tORD
tOED
CC 65
−
105
ns
CC −
100
200
ns
Enable Delay
90
VAIN ≥ VAREF + VODC
VAIN ≥ VAREF + 200 mV
VAIN ≥ VAREF + 400 mV
VAIN ≥ VAREF + 200 mV
VAIN ≥ VAREF + 400 mV
VAIN ≥ VAREF + 200 mV
VAIN ≥ VAREF + 400 mV
VAIN ≤ VAREF
1) Always the standard VADC reference, alternate references do not apply to the ORC.
Data Sheet
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XMC4400
XMC4000 Family
VODC
VOHYS
Electrical Parameters
VAREF
VSS
GxORCy
GxORCOUTy
tODD
Figure 16
tORD
GxORCOUTy Trigger Generation
VAIN (V)
T < tOPDN
tOPDN < T < tOPDD
T > tOPDD
VAREF + 400 mV
T < tOPDN
VAREF + 200 mV
tOPDN < T < tOPDD
T > tOPDD
T > tOPDN
VAREF + 100 mV
VAREF
Never
detected
Overvoltage
Pulse
(Too low)
Never
Overvoltage
detected
may be
Overvoltage
detected
Pulse
(level uncertain)
(Too short)
Overvoltage
may be
detected
Always detected
Overvoltage Pulse
Never
detected
Overvoltage
Pulse
(Too short)
Overvoltage
may be
detected
Always detected
Overvoltage Pulse
t
Figure 17
Data Sheet
ORC Detection Ranges
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Electrical Parameters
3.2.5
High Resolution PWM (HRPWM)
The following chapters describe the operating conditions, characteristics and timing
requirements, for all the components inside the HRPWM module. Each description is
given for just one sub unit, e.g., one CSG or one HRC.
All the timing information is related to the module clock, fhrpwm.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.2.5.1
HRC characteristics
Table 28 summarizes the characteristics of the HRC units.
Table 28
HRC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
High resolution step
size1)2)
tHRS CC –
150
–
ps
Startup time (after reset
release)
tstart CC –
–
2
μs
Note /
Test Condition
1) The step size for clock frequencies equal to 180, 120 and 80 MHz is 150 ps.
2) The step size for clock frequencies different from 180, 120 and 80 MHz but within the range from 180 to 64
MHz can be between 118 to 180 ps (fixed over process and operating conditions)
3.2.5.2
CMP and 10-bit DAC characteristics
The Table 29 summarizes the characteristics of the CSG unit.
The specified characteristics require that the setup of the HRPWM follows the
initialization sequence as documented in the Reference Manual.
Table 29
CMP and 10-bit DAC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Min.
DAC Resolution
Typ.
RES
Unit
Max.
10
Note /
Test Condition
bits
CC
DAC differential
nonlinearity
DNL
CC
-1
–
1.5
LSB
Monotonic
behavior,
See Figure 18
DAC integral nonlinearity
INL CC -3
–
3
LSB
See Figure 18
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
Table 29
CMP and 10-bit DAC characteristics (Operating Conditions apply)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
–
–
1
clk
tstart CC –
IDDbias
–
–
98
us
–
400
μA
–
–
2
μs
-10
–
33
μA
VSS
–
VDDP
V
–
–
80
ns
See Figure 20
Input Selector propagation tDhs CC –
delay - Full scale
–
100
ns
See Figure 20
–
–
ns
–
30
MHz
–
940
μA
–
VDDP
V
tFSls CC –
–
160
ns
See Figure 20
Input Selector propagation tDls CC –
delay - Full Scale
–
200
ns
See Figure 20
–
–
ns
–
30
MHz
–
300
μA
CSG Output Jitter
DCSG
CC
Bias startup time
Bias supply current
CC
CSGy startup time
tCSGS
CC
Input operation current1)
IDDCIN
See Figure 19
CC
High Speed Mode
DAC output voltage range VDOUT
CC
DAC propagation delay Full scale
Comparator bandwidth
DAC CLK frequency
Supply current
tFShs
CC
tDhs CC 20
fclk SR –
IDDhs
–
CC
Low Speed Mode
DAC output voltage range VDOUT
CC
DAC propagation delay Full Scale
Comparator bandwidth
DAC CLK frequency
Supply current
0.1 ×
VDDP2)
tDls CC 20
fclk SR –
IDDls
–
CC
1) Typical input resistance RCIN = 100kOhm.
2) The INL error increases for DAC output voltages below this limit.
Data Sheet
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XMC4000 Family
Output
Output
Electrical Parameters
INL
DAC Curve
Ideal DAC
DNL= -0.5LSBs
INL
DNL= -1LSB
Best Fit Straight Line
DNL=1.5LSBs
DAC
code
FS
Figure 18
FS
DAC
code
CSG DAC INL and DNL example
HRPWMx.CyINA
CMP Input
Selector
CSGy
+
HRPWMx.CyINB
CMP
DAC
Control
logic
-
CMP Input Selector
HRPWMx.CyINA/
HRPWMx.CyINB
Figure 19
Data Sheet
IDDcin
Rcin
Input operation current
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3.3 V
CMP Input
Selector
tsishs
0V
Output
Electrical Parameters
CSGy
FS
+
1LSB
CMP
-
DAC
CSGy
+
CMP
FS
0x000
tfshs
DAC
1LSB
0x000
-
tfshs/tsishs
tfshs/tsishs
t
Figure 20
3.2.5.3
DAC and Input Selector Propagation Delay
Clocks
HRPWM DAC Conversion Clock
The DAC conversion clock can be generated internally or it can be controlled via a
HRPWM module pin.
Table 30
External DAC conversion trigger operating conditions
Parameter
Symbol
Values
Min.
Frequency
ON time
OFF time
fetrg SR –
tonetrg SR 2Tccu1)2)
toffetrg SR 2Tccu1)2)
Typ. Max.
Unit Note /
Test Con
dition
–
302)
MHz
–
–
ns
–
–
ns
1) 50% duty cycle is not obligatory
2) Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)
CSG External Clock
It is possible to select an external source, that can be used as a clock for the slope
generation, HRPWMx.ECLKy. This clock is synchronized internally with the module
clock and therefore the external clock needs to meet the criterion described on Table 31.
Data Sheet
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XMC4400
XMC4000 Family
Electrical Parameters
Table 31
External clock operating conditions
Parameter
Symbol
Values
Min.
feclk SR –
–
toneclk SR 2Tccu1)2) –
toffeclk SR 2Tccu1)2) –
Frequency
ON time
OFF time
Unit Note /
Test Con
dition
Typ. Max.
fhrpwm/4
MHz
–
ns
–
ns
Only the
rising
edge is
used
1) 50% duty cycle is not obligatory
2) Only valid if the signal was not previously synchronized/generated with the fccu clock (or a synchronous clock)
3.2.6
Low Power Analog Comparator (LPAC)
The Low Power Analog Comparator (LPAC) triggers a wake-up event from Hibernate
state or an interrupt trigger during normal operation. It does so by comparing VBAT or
another external sensor voltage VLPS with a pre-programmed threshold voltage.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 32
Low Power Analog Comparator Parameters
Parameter
Symbol
Values
Typ.
Max.
Unit Note /
Test Condition
−
3.6
V
0
−
1.2
V
Threshold step size
−
18.75 −
mV
Threshold trigger accuracy
−
−
%
Min.
VBAT supply voltage range for VBAT SR 2.1
LPAC operation
Sensor voltage range
VLPCS
CC
Vth CC
ΔVth CC
Conversion time
tLPCC CC
Average current consumption ILPCAC
−
−
250
μs
−
−
15
μA
150
−
μA
over time
CC
Current consumption during
conversion
ILPCC CC −
Data Sheet
±10
57
for Vth > 0.4 V
for a conversion
interval of
10 ms
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2.7
Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 33
Die Temperature Sensor Parameters
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note /
Test Condition
−
150
°C
Linearity Error
ΔTLE CC −
(to the below defined formula)
±1
−
°C
per ΔTJ ≤ 30 °C
ΔTOE CC −
±6
−
°C
ΔTOE = TJ - TDTS
tM
CC −
tTSST SR −
−
100
μs
−
10
μs
Temperature sensor range
Offset Error
Measurement time
Start-up time after reset
inactive
TSR
SR -40
VDDP ≤ 3.3 V1)
1) At VDDP_max = 3.63 V the typical offset error increases by an additional ΔTOE = ±1 °C.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 33 apply with the following calibration
values:
•
•
DTSCON.BGTRIM = 8H
DTSCON.REFTRIM = 4H
Data Sheet
58
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2.8
USB OTG Interface DC Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 34
USB OTG VBUS and ID Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
VBUS input voltage
range
VIN
CC 0.0
−
5.25
V
A-device VBUS valid
threshold
VB1
CC 4.4
−
−
V
A-device session valid VB2
threshold
CC 0.8
−
2.0
V
B-device session valid VB3
threshold
CC 0.8
−
4.0
V
B-device session end
threshold
VB4
CC 0.2
−
0.8
V
VBUS input
resistance to ground
RVBUS_IN
−
100
kOhm
−
−
Ohm
−
−
Ohm
14
−
25
kOhm
−
−
150
μA
40
CC
RVBUS_PU 281
B-device VBUS pullup resistor
CC
B-device VBUS pulldown resistor
CC
USB.ID pull-up
resistor
CC
VBUS input current
IVBUS_IN
RVBUS_PD 656
RUID_PU
CC
Data Sheet
Note /
Test Condition
59
Pull-up voltage =
3.0 V
0 V ≤ VIN ≤ 5.25 V:
TAVG = 1 ms
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 35
USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating
Conditions apply)
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
Note /
Test Condition
SR −
−
0.8
V
SR 2.0
−
−
V
Input high voltage
(floating) 1)
VIHZ SR 2.7
−
3.6
V
Differential input
sensitivity
VDIS CC 0.2
−
−
V
Differential common
mode range
VCM CC 0.8
−
2.5
V
Output low voltage
VOL
CC 0.0
−
0.3
V
1.5 kOhm pullup to 3.6 V
Output high voltage
VOH CC 2.8
−
3.6
V
15 kOhm pulldown to 0 V
DP pull-up resistor (idle RPUI CC 900
bus)
−
1 575
Ohm
Input low voltage
Input high voltage
(driven)
VIL
VIH
DM pull-up resistor
(upstream port
receiving)
RPUA CC 1 425
−
3 090
Ohm
DP, DM pull-down
resistor
RPD CC 14.25
−
24.8
kOhm
Input impedance DP,
DM
ZINP CC 300
−
−
kOhm 0 V ≤ VIN ≤ VDDP
−
44
Ohm
Driver output resistance ZDRV CC 28
DP, DM
1) Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at Bconnector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
Data Sheet
60
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2.9
Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal (see Figure 21) or in direct
input mode (see Figure 22).
XTAL1
f OSC
GND
XTAL2
Damping resistor
may be needed for
some crystals
V
VPPX_min
VPPX
VPPX_min ≤ VPPX ≤ VPPX_max
tOSCS
t
Figure 21
Data Sheet
Oscillator in Crystal Mode
61
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XMC4400
XMC4000 Family
Electrical Parameters
External Clock
Source
Direct Input Mode
XTAL1
not connected
XTAL2
V
VIHBX_max
Inpu
ltage
h Vo
t Hig
tH
Inpu
igh V
e
oltag
VIHBX_min
VILBX_max
VSS
VILBX_min
g
Volta
t Low
Inpu
e
t
Figure 22
Data Sheet
Oscillator in Direct Input Mode
62
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XMC4400
XMC4000 Family
Electrical Parameters
Table 36
OSC_XTAL Parameters
Parameter
Symbol
Values
Min.
Input frequency
Unit
Note /
Test Condition
Typ.
Max.
fOSC SR 4
−
40
MHz Direct Input Mode
selected
4
−
25
MHz External Crystal
Mode selected
−
−
10
ms
Oscillator start-up
time1)2)
tOSCS
Input voltage at XTAL1
VIX SR -0.5
CC
−
VDDP + V
0.5
Input amplitude (peakto-peak) at XTAL12)3)
Input high voltage at
XTAL14)
VPPX SR 0.4 ×
VDDP
VIHBXSR 1.0
−
VDDP + V
1.0
−
VDDP + V
0.5
VILBX SR -0.5
−
0.4
V
Input leakage current at IILX1 CC -100
XTAL1
−
100
nA
Input low voltage at
XTAL14)
Oscillator power
down
0 V ≤ VIX ≤ VDDP
1) tOSCS is defined from the moment the oscillator is enabled wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) If the shaper unit is enabled and not bypassed.
4) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
Data Sheet
63
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Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 37
RTC_XTAL Parameters
Parameter
Symbol
Values
Min.
Input frequency
Oscillator start-up
time1)2)3)
fOSC SR −
tOSCS
−
Typ.
Unit
Max.
32.768 −
kHz
−
5
s
CC
Input voltage at
RTC_XTAL1
VIX SR -0.3
−
VBAT + V
Input amplitude (peakto-peak) at
RTC_XTAL12)4)
VPPX CC 0.2 ×
VBAT
−
VBAT + V
Input high voltage at
RTC_XTAL15)
VIHBXSR 0.6 ×
VBAT
VILBX SR -0.3
−
Input low voltage at
RTC_XTAL15)
Input Hysteresis for
RTC_XTAL15)6)
Note /
Test Condition
0.3
0.6
VBAT + V
0.3
−
0.36 ×
V
VBAT
VHYSX
0.1 ×
CC
VBAT
−
0.03 ×
V
3.0 V ≤
−
V
VBAT < 3.6 V
VBAT < 3.0 V
100
nA
VBAT
Input leakage current at IILX1 CC -100
RTC_XTAL1
−
Oscillator power
down
0 V ≤ VIX ≤ VBAT
1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 0.2 * VBAT.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT ≥ 3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
4) If the shaper unit is enabled and not bypassed.
5) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
6) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
Data Sheet
64
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2.10
Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
VDDP = 3.3 V, TA = 25 oC
Table 38
Power Supply Parameters
Parameter
Symbol
Values
Min.
Unit
Note /
Test Condition
Typ.
Max.
IDDPA CC −
113
−
−
102
−
120 / 60 / 60
−
82
−
60 / 60 / 120
−
61
−
24 / 24 / 24
−
51
−
1/1/1
Active supply current
Code execution from RAM
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC −
53
−
−
50
−
Active supply current2)
Peripherals disabled
Frequency:
fCPU / fPERIPH in MHz
IDDPA CC −
80
−
−
80
−
120 / 60 / 60
−
65
−
60 / 60 / 120
−
55
−
24 / 24 / 24
−
50
−
1/1/1
1)
Active supply current
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
Data Sheet
65
mA
mA
120 / 120 / 120
120 / 120 / 120
120 / 60 / 60
mA
120 / 120 / 120
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 38
Power Supply Parameters
Parameter
Symbol
Values
Min.
Sleep supply current3)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC −
Sleep supply current
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
Max.
Note /
Test Condition
104
−
−
93
−
120 / 60 / 60
−
78
−
60 / 60 / 120
−
57
−
24 / 24 / 24
−
46
−
1/1/1
−
46
−
100 / 100 / 100
IDDPS CC −
72
−
−
71
−
120 / 60 / 60
−
61
−
60 / 60 / 120
−
52
−
24 / 24 / 24
−
46
−
1/1/1
fCPU / fPERIPH / fCCU in kHz
4)
Unit
Typ.
−
mA
mA
120 / 120 / 120
120 / 120 / 120
46
−
IDDPD CC −
8
−
−
5
−
4/4/4
−
4
−
1/1/1
fCPU / fPERIPH / fCCU in kHz
−
4.5
−
100 / 100 / 100
Hibernate supply current
RTC on7)
IDDPH CC −
Hibernate supply current
RTC off8)
IDDPH CC −
fCPU / fPERIPH / fCCU in kHz
Deep Sleep supply
current5)
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
100 / 100 / 100
mA
6)
12.8
−
−
9.0
−
−
7.7
−
12.0
−
−
8.4
−
−
7.0
−
μA
μA
IDDPA CC −
−
VDDA power supply current IDDA CC −
IDDP current at PORST Low IDDP_PORST −
−
−11)
mA
−
30
mA
Worst case active supply
current9)
170
mA
10)
CC
Data Sheet
24 / 24 / 24
66
VBAT = 3.3 V
VBAT = 2.4 V
VBAT = 2.0 V
VBAT = 3.3 V
VBAT = 2.4 V
VBAT = 2.0 V
VDDP = 3.6 V,
TJ = 150 oC
VDDP = 3.6 V,
TJ = 150 oC
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 38
Power Supply Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
1
W
VDDP = 3.6 V,
TJ = 150 oC
6
−
cycles
−
−
−
ms
Defined by the
wake-up of the
Flash module,
see
Section 3.2.11
−
−
−
ms
Wake-up via
power-on reset
event, see
Section 3.3.2
Min.
Typ.
Max.
PDISS CC −
−
CC −
Wake-up time from Deep
Sleep to Active mode
Wake-up time from
Hibernate mode
Power Dissipation
Wake-up time from Sleep to tSSA
Active mode
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash. Ethernet, USB and CCU clock off.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU ≥ 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) Test Power Loop: fSYS = 120 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer
mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in
500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE,
DTS measurements and FPU calculations.
The power consumption of each customer application will most probably be lower than this value, but must be
evaluated separately.
10) IDDP decreases typically by 5 mA when fSYS decreases by 10 MHz, at constant TJ
11) Sum of currents of all active converters (ADC and DAC)
Data Sheet
67
V1.1, 2014-03
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XMC4400
XMC4000 Family
Electrical Parameters
Peripheral Idle Currents
Test conditions:
•
•
•
•
•
•
fsys and derived clocks at 120 MHz
VDDP = 3.3 V, Ta =25 °C
all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
no I/O activity
the given values are a result of differential measurements with asserted and
deasserted peripheral reset and enabled clock of the peripheral under test
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 39
Peripheral Idle Currents
Parameter
Symbol
Values
Min.
PORTS
ETH
USB
FCE
WDT
POSIFx
MultiCAN
ERU
LEDTSCU0
CCU4x
CCU8x
Unit
Typ.
Max.
IPER CC −
≤ 0.3
−
−
≤ 1.0
−
DAC (digital)1)
−
1.3
−
USICx
−
3.0
−
DSD
VADC (digital)1)
−
4.5
−
DMAx
−
6.0
−
Note /
Test Condition
mA
1) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripheral.
Data Sheet
68
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.2.11
Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 40
Flash Memory Parameters
Parameter
Symbol
Values
Erase Time per 256
Kbyte Sector
tERP CC −
Min.
Unit
Typ.
Max.
5
5.5
s
Erase Time per 64 Kbyte tERP CC −
Sector
1.2
1.4
s
Erase Time per 16 Kbyte tERP CC −
Logical Sector
0.3
0.4
s
Program time per page1) tPRP CC −
5.5
11
ms
−
15
ms
−
−
μs
Erase suspend delay
tFL_ErSusp −
Note /
Test Condition
CC
Wait time after margin
change
tFL_Margin 10
Del CC
−
−
270
μs
20
−
−
ns
For operation
with 1 / fCPU < ta
wait states must
be configured2)
Data Retention Time,
Physical Sector3)4)
tRET CC 20
−
−
years
Max. 1000
erase/program
cycles
Data Retention Time,
Logical Sector3)4)
tRETL CC 20
−
−
years
Max. 100
erase/program
cycles
Data Retention Time,
tRTU CC 20
User Configuration Block
(UCB)3)4)
−
−
years
Max. 4
erase/program
cycles per UCB
Wake-up time
Read access time
tWU CC
ta CC
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
2) The following formula applies to the wait state configuration: FCON.WSPFLASH × (1 / fCPU) ≥ ta.
3) Storage and inactive time included.
4) Values given are valid for an average weighted junction temperature of TJ = 110°C.
Data Sheet
69
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3
AC Parameters
3.3.1
Testing Waveforms
VD D P
VSS
90%
90%
10%
10%
tR
tF
AC_Rise-Fall-Times.vsd
Figure 23
Rise/Fall Time Parameters
VD D P
VD D P / 2
Test Points
VD D P / 2
VSS
AC_TestPoints.vsd
Figure 24
Testing Waveform, Output Delay
VL OAD + 0.1V
VL OAD - 0.1V
Timing
Reference
Points
VOH - 0.1V
VOL + 0.1V
AC_HighImp.vsd
Figure 25
Data Sheet
Testing Waveform, Output High Impedance
70
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XMC4400
XMC4000 Family
Electrical Parameters
3.3.2
Power-Up and Supply Monitoring
PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
VDDP
VDDP
XMC4000
RPORST
(optional)
PORST
PORESET
External
reset
trigger
IPPD
GND
GND
Figure 26
PORST Circuit
Table 41
Supply Monitoring Parameters
Parameter
Supply
Monitoring
Symbol
Values
Min.
Digital supply voltage reset VPOR CC
threshold
Unit
Note /
Test Condition
3)
Typ. Max.
2.791) −
3.052)
V
Core supply voltage reset
threshold
VPV CC
−
−
1.17
V
VDDP voltage to ensure
defined pad states
VDDPPA
−
1.0
−
V
−
−
2
μs
−
2.5
3.5
ms
Time to the first
user code
instruction
−
550
−
μs
Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
CC
tPR SR
Startup time from power-on tSSW CC
PORST rise time
reset with code execution
from Flash
VDDC ramp up time
tVCR CC
1) Minimum threshold for reset assertion.
Data Sheet
71
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS = 180 mV.
3.3 V
VPOR
VD D P
VD D PPA
1.3 V
VDDC
VPV
tV CR
PORST
t PR
t SSW
Pads
as programmed
High-impedance or pull -device active
Undefined
Figure 27
3.3.3
Power-Up Behavior
Power Sequencing
While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Data Sheet
72
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 42
Power Sequencing Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
50
mA
Load increase
on VDDP
Δt ≤ 10 ns
−
150
mA
Load decrease
on VDDP
Δt ≤ 10 ns
−
±100
mV
For maximum
positive or
negative load
step
−
-
μs
Min.
Typ. Max.
Positive Load Step Current ΔIPLS SR
-
−
Negative Load Step
Current
ΔINLS SR
-
VDDC Voltage Over-
ΔVLS CC
-
/ Undershoot from Load
Step
Positive Load Step Settling tPLSS SR 50
Time
Negative Load Step
Settling Time
tNLSS SR 100
−
-
μs
External Buffer Capacitor
on VDDC
CEXT SR 3
4.7
6
μF
In addition
C = 100 nF
capacitor on
each VDDC pin
Positive Load Step Examples
System assumptions:
fCPU = fSYS, target frequency fCPU = 120 MHz, main PLL fVCO = 480 MHz, stepping done
by K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 68 MHz - 96 MHz - 120 MHz (K2 steps 20 - 10 - 7 - 5 - 4)
24 MHz - 68 MHz - 96 MHz - 120 MHz (K2 steps 20 - 7 - 5 - 4)
24 MHz - 68 MHz - 120 MHz (K2 steps 20 - 7 - 4)
Data Sheet
73
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.4
Phase Locked Loop (PLL) Characteristics
Main and USB PLL
Table 43
PLL Parameters
Parameter
Symbol
Values
Unit
Note /
Test Condition
±5
ns
accumulated
over 300 cycles
fSYS = 120 MHz
Low pulse to
total period,
assuming an
ideal input clock
source
Min.
Typ.
Max.
−
−
Accumulated Jitter
DP CC
Duty Cycle1)
DDC CC 46
50
54
%
PLL base frequency
fPLLBASE 30
−
140
MHz
−
16
MHz
−
520
MHz
−
400
μs
CC
VCO input frequency
VCO frequency range
PLL lock-in time
fREF CC 4
fVCO CC 260
tL CC
−
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
Data Sheet
74
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.5
Internal Clock Source Characteristics
Fast Internal Clock Source
Table 44
Fast Internal Clock Parameters
Parameter
Symbol
Min.
Typ.
Max.
Nominal frequency
fOFINC
−
36.5
−
MHz not calibrated
CC
−
24
−
MHz calibrated
ΔfOFI
-0.5
−
0.5
%
automatic
calibration1)2)
-15
−
15
%
factory
calibration,
VDDP = 3.3 V
-25
−
25
%
no calibration,
VDDP = 3.3 V
-7
−
7
%
Variation over
voltage range3)
3.13 V ≤ VDDP ≤
3.63 V
50
−
μs
Accuracy
Values
Unit
CC
Start-up time
tOFIS CC −
Note /
Test Condition
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage.
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Data Sheet
75
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Slow Internal Clock Source
Table 45
Slow Internal Clock Parameters
Parameter
Symbol
Nominal frequency
fOSI CC
ΔfOSI
Accuracy
Values
Unit
Min.
Typ.
−
32.768 −
Max.
kHz
-4
−
%
4
CC
Note /
Test Condition
VBAT = const.
0 °C ≤ TA ≤
85 °C
Start-up time
Data Sheet
-5
−
5
%
-5
−
5
%
-10
−
10
%
50
−
μs
tOSIS CC −
76
VBAT = const.
TA < 0 °C or
TA > 85 °C
2.4 V ≤ VBAT,
TA = 25 °C
1.95 V ≤
VBAT < 2.4 V,
TA = 25 °C
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.6
JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 46
JTAG Interface Timing Parameters
Parameter
Symbol
Min.
Values
Typ.
Max.
Unit Note /
Test Condition
t1
t2
t3
t4
t5
t6
SR
25
–
–
ns
SR
10
–
–
ns
SR
10
–
–
ns
SR
–
–
4
ns
SR
–
–
4
ns
SR
6
–
–
ns
t7
SR
6
–
–
ns
TDO valid after TCK falling t8
edge1) (propagation delay)
CC
–
–
13
ns
CL = 50 pF
3
–
–
ns
CL = 20 pF
2
–
–
ns
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO hold after TCK falling t18 CC
edge1)
TDO high imped. to valid
from TCK falling edge1)2)
t9
–
–
14
ns
CL = 50 pF
TDO valid to high imped.
from TCK falling edge1)
t10 CC –
–
13.5
ns
CL = 50 pF
CC
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
77
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
t1
TCK
0.9 VD D P
0.1 VD D P
0.5 VD D P
t2
t3
t4
t5
JTAG_TCK .vsd
Figure 28
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t10
TDO
t18
JTAG_IO.vsd
Figure 29
Data Sheet
JTAG Timing
78
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.7
Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 47
SWD Interface Timing Parameters (Operating Conditions apply)
Parameter
Symbol
Values
Typ.
Max.
Unit Note /
Test Condition
tSC SR 25
–
–
ns
CL = 30 pF
40
–
–
ns
CL = 50 pF
SR 10
–
500000 ns
SR 10
–
500000 ns
SR 6
–
–
ns
SWDIO input hold
t4
after SWDCLK rising edge
SR 6
–
–
ns
SWDIO output valid time t5
after SWDCLK rising edge
CC –
–
17
ns
CL = 50 pF
–
–
13
ns
CL = 30 pF
t6
SWDIO output hold time
from SWDCLK rising edge
CC 3
–
–
ns
Min.
SWDCLK clock period
t1
t2
t3
SWDCLK high time
SWDCLK low time
SWDIO input setup
to SWDCLK rising edge
tSC
t1
t2
SWDCLK
t6
SWDIO
(Output)
t5
t3
t4
SWDIO
(Input)
Figure 30
Data Sheet
SWD Timing
79
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.8
Embedded Trace Macro Cell (ETM) Timing
The Data timing are to the active clock edge, in half-rate clocking mode that is the rising
and falling clock edge.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply, with CL ≤ 15 pF.
Table 48
ETM Interface Timing Parameters
Parameter
Symbol
Values
Min.
TRACECLK period
TRACECLK high time
TRACECLK low time
TRACECLK and
TRACEDATA rise time
TRACECLK and
TRACEDATA fall time
t1 CC
t2 CC
t3 CC
t4 CC
t5 CC
TRACEDATA output valid t6
time
Typ.
Unit Note /
Test Condition
Max.
16.7
–
–
ns
–
2
–
–
ns
–
2
–
–
ns
–
–
–
3
ns
–
–
–
3
ns
–
–
3
ns
–
CC -2
t1
TRACECLK
t2
Figure 31
t5
t3
t4
ETM Clock Timing
TRACECLK
t6
t6
TRACEDATA
Figure 32
Data Sheet
ETM Data Timing
80
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.9
Peripheral Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
3.3.9.1
Delta-Sigma Demodulator Digital Interface Timing
The following parameters are applicable for the digital interface of the Delta-Sigma
Demodulator (DSD).
The data timing is relative to the active clock edge. Depending on the operation mode of
the connected modulator that can be the rising and falling clock edge.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 49
DSD Interface Timing Parameters
Parameter
Symbol
Values
Typ.
Max.
Unit Note /
Test Condition
CC 33.3
–
–
ns
t1 ≥ 4 x tPERIPH1)
MCLK high time in master t2
mode
CC 9
–
–
ns
t2 > tPERIPH1)
MCLK low time in master
mode
t3
CC 9
–
–
ns
t3 > tPERIPH1)
MCLK period in slave
mode
t1
SR 33.3
–
–
ns
t1 ≥ 4 x tPERIPH1)
MCLK high time in slave
mode
t2
SR tPERIPH –
–
ns
1)
MCLK low time in slave
mode
t3
SR tPERIPH –
–
ns
1)
DIN input setup time to the t4
active clock edge
SR tPERIPH –
+4
–
ns
1)
t5
SR tPERIPH –
+3
–
ns
1)
Min.
MCLK period in master
mode
DIN input hold time from
the active clock edge
t1
1) tPERIPH = 1 / fPERIPH
Data Sheet
81
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
t1
t2
t3
MCLK
t5
t4
DIN
Figure 33
3.3.9.2
DSD Data Timing
Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 50
USIC SSC Master Mode Timing
Parameter
Symbol
Values
Min.
SCLKOUT master clock
period
Unit
Typ. Max.
tCLK CC 33.3
−
−
ns
Slave select output SELO t1
active to first SCLKOUT
transmit edge
CC tSYS 6.51)
−
−
ns
Slave select output SELO t2
inactive after last
SCLKOUT receive edge
CC tSYS 8.51)
−
−
ns
t3
CC -6
−
8
ns
Receive data input
t4
DX0/DX[5:3] setup time to
SCLKOUT receive edge
SR 23
−
−
ns
Data input DX0/DX[5:3]
t5
hold time from SCLKOUT
receive edge
SR 1
−
−
ns
Data output DOUT[3:0]
valid time
Note /
Test Condition
1) tSYS = 1 / fPB
Data Sheet
82
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 51
USIC SSC Slave Mode Timing
Parameter
Symbol
Values
Min.
Unit
Typ. Max.
−
−
ns
Select input DX2 setup to
t10
first clock input DX1 transmit
edge1)
SR 3
−
−
ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11
SR 4
−
−
ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12
SR 6
−
−
ns
Data input DX0/DX[5:3] hold t13
time from clock input DX1
receive edge1)
SR 4
−
−
ns
Data output DOUT[3:0] valid t14
time
CC 0
−
24
ns
DX1 slave clock period
tCLK SR 66.6
Note /
Test Condition
1) These input timing are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
83
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
t3
Last Receive
Edge
Transmit
Edge
t3
Data Output
DOUT[3:0]
t4
Data Input
DX0/DX[5:3]
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t1 0
Select Input
DX2
Clock Input
DX1
t1 1
Active
Inactive
Receive
Edge
First Transmit
Edge
t1 2
Data Input
DX0/DX[5:3]
Inactive
Last Receive
Edge
Transmit
Edge
t1 2
t1 3
Data
valid
t13
Data
valid
t14
t1 4
Data Output
DOUT[3:0]
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 34
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
Data Sheet
84
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.9.3
Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 52
USIC IIC Standard Mode Timing1)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Fall time of both SDA and t1
SCL
CC/SR
-
-
300
ns
Rise time of both SDA and t2
SCL
CC/SR
-
-
1000
ns
0
-
-
µs
250
-
-
ns
4.7
-
-
µs
4.0
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
4.0
-
-
µs
4.7
-
-
µs
-
-
400
pF
Data hold time
t3
Note /
Test Condition
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
Hold time for (repeated)
START condition
CC/SR
Set-up time for repeated
START condition
CC/SR
Set-up time for STOP
condition
CC/SR
t8
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Data Sheet
85
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
Table 53
USIC IIC Fast Mode Timing1)
Parameter
Symbol
Values
Min.
Fall time of both SDA and t1
SCL
CC/SR
Typ.
Unit
Max.
20 +
0.1*Cb
300
ns
20 +
0.1*Cb
300
ns
0
-
-
µs
100
-
-
ns
1.3
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
1.3
-
-
µs
-
-
400
pF
Note /
Test Condition
2)
Rise time of both SDA and t2
SCL
CC/SR
2)
Data hold time
t3
CC/SR
Data set-up time
t4
CC/SR
LOW period of SCL clock
t5
CC/SR
HIGH period of SCL clock t6
CC/SR
t7
Hold time for (repeated)
START condition
CC/SR
Set-up time for repeated
START condition
CC/SR
Set-up time for STOP
condition
CC/SR
t8
t9
Bus free time between a
STOP and START
condition
t10
Capacitive load for each
bus line
Cb SR
CC/SR
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
2) Cb refers to the total capacitance of one bus line in pF.
Data Sheet
86
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
t1
SDA
t2
t4
70%
30%
t1
t3
t2
t6
SCL
th
t7
9
clock
t5
t10
S
SDA
t8
t7
t9
SCL
th
9
clock
Sr
Figure 35
3.3.9.4
P
S
USIC IIC Stand and Fast Mode Timing
Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 54
USIC IIS Master Transmitter Timing
Parameter
Clock period
Clock HIGH
Symbol
t1 CC
t2 CC
Values
Unit
Min.
Typ.
Max.
33.3
−
−
ns
0.35 x
−
−
ns
−
−
ns
0
−
−
ns
−
−
0.15 x
ns
Note /
Test Condition
t1min
Clock Low
t3 CC
0.35 x
t1min
Hold time
Clock rise time
t4 CC
t5 CC
t1min
Data Sheet
87
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
t1
t2
t5
t3
SCK
t4
WA/
DOUT
Figure 36
USIC IIS Master Transmitter Timing
Table 55
USIC IIS Slave Receiver Timing
Parameter
Symbol
t6 SR
t7 SR
Clock period
Clock HIGH
Values
Unit
Min.
Typ.
Max.
66.6
−
−
ns
0.35 x
−
−
ns
−
−
ns
−
−
ns
−
−
ns
Note /
Test Condition
t6min
t8 SR
Clock Low
0.35 x
t6min
t9 SR
Set-up time
0.2 x
t6min
t10 SR
Hold time
0
t6
t7
t8
SCK
t9
t10
WA/
DIN
Figure 37
Data Sheet
USIC IIS Slave Receiver Timing
88
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Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.10
USB Interface Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 56
USB Timing Parameters (operating conditions apply)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit Note /
Test Condition
–
20
ns
CL = 50 pF
–
20
ns
CL = 50 pF
Rise/Fall time matching
tR
CC
4
tF
CC
4
tR/tF
CC 90
–
111.11 %
CL = 50 pF
Crossover voltage
VCRS
–
2.0
CL = 50 pF
Rise time
Fall time
CC 1.3
D+
90%
V
90%
VC R S
DVSS
10%
10%
tF
tR
USB_Rise-Fall-Times.vsd
Figure 38
Data Sheet
USB Signal Timing
89
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.11
Ethernet Interface (ETH) Characteristics
For proper operation of the Ethernet Interface it is required that fSYS ≥ 100 MHz.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.11.1 ETH Measurement Reference Points
ETH Clock
ETH I/O
1.4 V
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
tR
tF
ETH_Testpoints.vsd
Figure 39
Data Sheet
ETH Measurement Reference Points
90
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.11.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Table 57
ETH Management Signal Timing Parameters
Parameter
Symbol
Values
Typ. Max.
Unit Note /
Test Conditi
on
CC 400
–
–
ns
CC 160
–
–
ns
CC 160
–
–
ns
CC 10
–
–
ns
CC 10
–
–
ns
SR 0
–
300
ns
Min.
t1
ETH_MDC high time
t2
t3
ETH_MDC low time
ETH_MDIO setup time (output) t4
ETH_MDIO hold time (output) t5
t6
ETH_MDIO data valid (input)
ETH_MDC period
CL = 25 pF
t1
t3
t2
ETH_MDC
ETH_MDIO sourced by STA:
ETH_MDC
t4
ETH_MDIO
(output)
t5
Valid Data
ETH_MDIO sourced by PHY:
ETH_MDC
t6
ETH_MDIO
(input)
Valid Data
ETH_Timing-Mgmt.vsd
Figure 40
Data Sheet
ETH Management Signal Timing
91
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Electrical Parameters
3.3.11.3 ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are
described.
Table 58
ETH RMII Signal Timing Parameters
Parameter
Symbol
ETH_RMII_REF_CL clock period
t13
Values
Unit Note /
Test Condit
Min. Typ. Max.
ion
SR 20
–
–
ns
CL = 25 pF;
50 ppm
ETH_RMII_REF_CL clock high time t14
SR 7
–
13
ns
CL = 25 pF
ETH_RMII_REF_CL clock low time t15
SR 7
–
13
ns
ETH_RMII_RXD[1:0],
ETH_RMII_CRS setup time
t16
SR 4
–
–
ns
ETH_RMII_RXD[1:0],
ETH_RMII_CRS hold time
t17
SR 2
–
–
ns
ETH_RMII_TXD[1:0],
ETH_RMII_TXEN data valid
t18
CC 4
–
15
ns
t1 3
t1 5
t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
t1 6
ETH_RMII _RXD[1:0]
ETH_RMII _CRS
(sourced by PHY )
t17
Valid Data
ETH_RMII_REF_CL
t18
ETH_RMII _TXD[1:0]
ETH_RMII _TXEN
(sourced by STA )
Figure 41
Data Sheet
Valid Data
Valid Data
ETH_Timing-RMII .vsd
ETH RMII Signal Timing
92
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XMC4400
XMC4000 Family
Package and Reliability
4
Package and Reliability
The XMC4400 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1
Package Parameters
Table 59 provides the thermal characteristics of the packages used in XMC4400.
Table 59
Thermal Characteristics of the Packages
Parameter
Symbol
Limit Values
Unit
Package Types
Exposed Die Pad
Dimensions
Ex × Ey CC
-
7.0 × 7.0
mm
PG-LQFP-100-11
5.8 × 5.8
mm
PG-LQFP-64-19
Thermal resistance
Junction-Ambient
RΘJA
CC
-
20.5
K/W
PG-LQFP-100-111)
-
30
K/W
PG-LQFP-64-191)
Min.
Max.
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
4.1.1
Thermal Considerations
When operating the XMC4400 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
Data Sheet
93
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Package and Reliability
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
H
0.5
7˚ MAX.
+0.05
0.15 -0.06
1.6 MAX.
Package Outlines
0.1±0.05
4.2
1.4 ±0.05
•
•
•
•
0.6 ±0.15
0.08 C 100x
C
12
0.22 ±0.05
0.08 M A-B D C 100x
16
14
1)
0.2 A-B D 100x
Bottom View
0.2 A-B D H 4x
Ex
Ey
16
B
14
A
1)
D
100
100
1
1
Index Marking
Exposed Diepad
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-100-3, -4, -8-PO V11
Figure 42
Data Sheet
PG-LQFP-100-11 (Plastic Green Low Profile Quad Flat Package)
94
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
H
0.5
0.08 C 64x
C
SEATING COPLANARITY
PLANE
7.5
+0.07
0.2 -0.03
0.6 ±0.15
0.08 M A-B D C 64x
12
10
Bottom View
0.2 A-B D 64x
1)
Ex
0.2 A-B D H 4x
Ox
D
Exposed Diepad
Oy
Ey
10
B
12
A
1)
0.5 x 45˚
0˚...7˚
-0.06
0.15 +0.05
1.4 ±0.05
1.6 MAX.
0.1±0.05
STAND OFF
Package and Reliability
64
1
1
64
Index Marking
Index Marking
1) Does not include plastic or metal protrusion of 0.25 max. per side
PG-LQFP-64-6, -8, -12, -22-PO V13
Figure 43
PG-LQFP-64-19 (Plastic Green Low Profile Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
95
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
XMC4400
XMC4000 Family
Quality Declarations
5
Quality Declarations
The qualification of the XMC4400 is executed according to the JEDEC standard
JESD47H.
Note: For automotive applications refer to the Infineon automotive microcontrollers.
Table 60
Quality Parameters
Parameter
Symbol
Values
Min.
Operation lifetime
tOP CC 20
Typ.
Max.
−
−
Unit
Note /
Test Condition
a
TJ ≤ 109°C,
device permanent
on
VHBM
ESD susceptibility
according to Human Body SR
Model (HBM)
−
−
2 000
V
EIA/JESD22A114-B
ESD susceptibility
according to Charged
Device Model (CDM)
VCDM
−
−
500
V
Conforming to
JESD22-C101-C
Moisture sensitivity level
MSL
−
−
3
−
JEDEC
J-STD-020C
SR
CC
Data Sheet
96
V1.1, 2014-03
Subject to Agreement on the Use of Product Information
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Published by Infineon Technologies AG