XMC1100 AB-Step Microcontroller Series for Industrial Applications XMC1000 Family ARM® Cortex™-M0 32-bit processor core Reference Manual V1.2 2014-11 Microcontrollers Edition 2014-11 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. XMC1100 AB-Step Microcontroller Series for Industrial Applications XMC1000 Family ARM® Cortex™-M0 32-bit processor core Reference Manual V1.2 2014-11 Microcontrollers XMC1100 AB-Step XMC1000 Family XMC1100 Reference Manual Revision History: V1.2 2014-11 Previous Version: V1.1 Page Subjects , Page 5-5 Interrupt Subsystem chapter • Interrupt response time section is renamed interrupt latency to better fit the definition. Page 7-11 Memory Organization chapter • Service request generation, debug behaviour, power, reset and clock, initialization and system dependencies sections are added Page 8-6, Page 8-8 Flash chapter • Sector erase description is added • Service request generation, power, reset and clock sections sections are added Page 9-2 PAU chapter • Service request generation, debug behaviour, power, reset and clock, initialization and system dependencies sections are added Page 12-30, Page 12-41, Page 12-42, Page 13-3 Page 14-228 Reference Manual SCU chapter • Registers CGATSTAT0, DBGROMID, CCUCON are updated PRNG chapter • Service request generation, debug behaviour, power, reset and clock, initialization and system dependencies sections are added USIC chapter • Hints on the signal usage to Interconnect tables are added V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family XMC1100 Reference Manual Revision History: V1.2 2014-11 Page 18-17, Page 18-46, Page 18-49 Page 19-2, Page 19-10, Page 20-3, Page 20-5, Page 20-8, Page 20-12, Page 20-14, Ports chapter • A footnote is added to P0_IOCR12 reset value • New section and table on Hardware Controlled I/O function is added Boot and Startup, BSL and User Routines chapters • The pin used to indicate the start of SSW is updated • The length for Chip Variant Identification Number is updated • Enhanced ASC BSL entry sequence is updated • • The status indicators returned by NVM user routines are updated Erase Sector, Program & Verify Flash Block user routines are added Trademarks C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited. Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Reference Manual 1-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents Table of Contents 1 1.1 1.1.1 1.2 1.2.1 1.2.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Core Processing Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Multiple Priority Interrupt System (NVIC) . . . . . . . . . . System Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Timer Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo Random Bit Generator (PRNG) . . . . . . . . . . . . . . . . . . . . . . . Peripherals Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.1.1 2.1.2 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.5.1 2.4 2.4.1 2.5 2.5.1 2.5.2 2.5.3 2.5.4 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Processor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 The Cortex Microcontroller Software Interface Standard . . . . . . . . . . 2-15 CMSIS Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Memory Regions, Types and Attributes . . . . . . . . . . . . . . . . . . . . . . . 2-19 Memory System Ordering of Memory Accesses . . . . . . . . . . . . . . . . 2-19 Behavior of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Software Ordering of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . 2-21 Memory Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Little-endian format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Intrinsic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Exception Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Exception States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Exception Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 Reference Manual L-1 1-1 1-1 1-3 1-3 1-4 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-5 1-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 2.5.4.1 2.5.5 2.5.6 2.5.6.1 2.5.6.2 2.6 2.6.1 2.7 2.7.1 2.7.2 2.7.3 2.8 2.8.1 2.8.2 2.8.2.1 2.8.3 2.8.3.1 2.9 2.9.1 2.9.2 Vector Table Remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Entry and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wakeup from Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Programming Hints . . . . . . . . . . . . . . . . . . . . . . Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System control block usage hints and tips . . . . . . . . . . . . . . . . . . . System timer, SysTick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick usage hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4 4.1 4.1.1 4.1.2 4.2 Service Request Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Service Request Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2 5.3 5.3.1 5.4 Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Nested Vectored Interrupt Controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 5-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Interrupt Node Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Interrupt Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Accessing CPU Registers using CMSIS . . . . . . . . . . . . . . . . . . . . . . . 5-3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 General Module Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 NVIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Interrupt Request Source Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 6 Event Request Unit (ERU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Reference Manual L-2 2-29 2-30 2-31 2-32 2-34 2-35 2-35 2-36 2-36 2-37 2-37 2-38 2-38 2-38 2-38 2-38 2-39 2-40 2-41 2-52 4-1 4-1 4-1 4-1 4-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.9.1 6.10 6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Event Request Select Unit (ERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Event Trigger Logic (ETLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Cross Connect Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Output Gating Unit (OGUy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 ERU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 ERU0 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 7 7.1 7.1.1 7.1.2 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.5.1 7.5.1.1 7.5.2 7.5.2.1 7.5.2.2 7.6 7.7 7.8 7.9 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Cortex-M0 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 SRAM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 ROM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Intellectual Property (IP) Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Blocking of Unauthorized External Access . . . . . . . . . . . . . . . . . . . 7-9 Memory Access Protection during Run-time . . . . . . . . . . . . . . . . . . . . 7-9 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 Peripheral Privilege Access Control . . . . . . . . . . . . . . . . . . . . . . . 7-11 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Debug Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . 7-12 8 8.1 8.1.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.3 8.3.1 Flash Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logical and Physical States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Portions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module Specific Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Manual L-3 8-1 8-1 8-1 8-1 8-2 8-2 8-3 8-3 8-3 8-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 8.3.1.1 8.3.1.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.5 8.6 8.7 8.8 8.8.1 8.8.2 8.8.2.1 8.8.2.2 8.8.3 8.8.4 8.9 8.9.1 8.10 8.10.1 8.10.1.1 8.10.1.2 8.10.2 8.10.2.1 8.10.2.2 8.10.2.3 8.10.2.4 8.10.3 8.10.3.1 8.10.3.2 8.10.4 8.10.5 8.10.6 Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 SFR Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Erase-Protection and Write-Protection . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Properties and Implementation of Error Correcting Code (ECC) . . . . . . . 8-8 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 NVM Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 NVM Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 NVM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Example Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Writing a Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Writing Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Erasing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Erasing a Single Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Erasing Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Erasing a Single Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Erasing Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Verifying Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Verifying a Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Verifying Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Writing to an Already Written Block . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 9 9.1 9.1.1 9.2 9.3 Peripheral Access Unit (PAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Privilege Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Availability and Memory Size . . . . . . . . . . . . . . . . . . . . . . . . . Reference Manual L-4 9-1 9-1 9-1 9-1 9-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 9.4 9.5 9.6 9.7 9.8 9.8.1 9.8.2 9.8.3 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . PAU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Privilege Access Registers (PRIVDISn) . . . . . . . . . . . . . . . Peripheral Availability Registers (AVAILn) . . . . . . . . . . . . . . . . . . . . . . Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10.1 10.1.1 10.1.2 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.8.1 10.8.2 10.8.3 10.8.4 10.9 10.9.1 10.10 Window Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Time-Out Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Pre-warning Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Bad Service Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Service Request Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Initialization and Control Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Initialization & Start of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Software Stop & Resume Operation . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Enter Sleep/Deep-Sleep & Resume Operation . . . . . . . . . . . . . . . . . 10-7 Pre-warning Alarm Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 11 11.1 11.1.1 11.1.2 11.2 11.3 11.4 11.4.1 11.4.2 11.5 11.6 11.7 11.7.1 11.7.2 11.7.3 11.8 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Access Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Service Request Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Service Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Alarm Service Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization and Control Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization & Start of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configure and Enable Periodic Event . . . . . . . . . . . . . . . . . . . . . . . . Configure and Enable Timer Event . . . . . . . . . . . . . . . . . . . . . . . . . . RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Manual L-5 9-2 9-2 9-2 9-2 9-2 9-3 9-6 9-9 11-1 11-1 11-1 11-1 11-2 11-3 11-4 11-4 11-4 11-4 11-4 11-5 11-5 11-5 11-5 11-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 11.8.1 11.9 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 12 12.1 12.1.1 12.1.2 12.2 12.2.1 12.2.1.1 12.2.2 12.2.3 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.5 12.5.1 12.5.2 12.5.2.1 12.5.2.2 12.5.2.3 12.5.2.4 12.5.3 12.5.4 12.6 12.7 12.8 12.9 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 System Control Unit (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Miscellaneous Control Functions (GCU) . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Service Requests Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Service Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 SRAM Memory Content Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 Summary of ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 Power Management (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Embedded Voltage Regulator (EVR) . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Power Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Supply Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 VDDC Response During Load Change . . . . . . . . . . . . . . . . . . . . . . . 12-11 Flash Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Reset Control (RCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Reset Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 Clock Control (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Clock System and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 Loss of Clock Detection and Recovery . . . . . . . . . . . . . . . . . . . . 12-18 Standby Clock Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Startup Control for System Clock . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Clock Gating Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Calibrating DCO based on Temperature . . . . . . . . . . . . . . . . . . . . . 12-20 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 PCU Registers (ANACTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 PCU Registers (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 CCU Registers (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 CCU Registers (ANACTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34 RCU Registers (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 GCU Registers (SCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 Reference Manual L-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 13 13.1 13.1.1 13.2 13.2.1 13.2.2 13.2.3 13.3 13.4 13.5 13.6 13.7 13.7.1 13.7.2 Pseudo Random Number Generator (PRNG) . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Loading Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Streaming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refreshing and Restarting a Random Bit Stream . . . . . . . . . . . . . . . Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-1 13-1 13-1 13-1 13-2 13-2 13-3 13-3 13-3 13-3 13-3 13-4 13-6 14 Universal Serial Interface Channel (USIC) . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 Operating the USIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.2.1 USIC Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.2.1.1 Channel Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.2.1.2 Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.2.1.3 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.2.1.4 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.2.1.5 Channel Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.2.1.6 Data Shifting and Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.2.2 Operating the USIC Communication Channel . . . . . . . . . . . . . . . . . 14-14 14.2.2.1 Protocol Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14.2.2.2 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16 14.2.2.3 General Channel Events and Interrupts . . . . . . . . . . . . . . . . . . . 14-17 14.2.2.4 Data Transfer Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2.2.5 Baud Rate Generator Event and Interrupt . . . . . . . . . . . . . . . . . . 14-20 14.2.2.6 Protocol-specific Events and Interrupts . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3 Operating the Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.1 General Input Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.3.2 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.3.3 Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.3.4 Selected Input Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.3.5 Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.4 Operating the Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.4.1 Fractional Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.4.2 External Frequency Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.4.3 Divider Mode Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 Reference Manual L-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 14.2.4.4 Capture Mode Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4.5 Time Quanta Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4.6 Master and Shift Clock Output Configuration . . . . . . . . . . . . . . . 14.2.5 Operating the Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5.1 Transmit Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5.2 Transmit Data Shift Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5.3 Transmit Control Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5.4 Transmit Data Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6 Operating the Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.1 Receive Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.2 Receive Data Shift Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.6.3 Baud Rate Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.7 Hardware Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8 Operating the FIFO Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.1 FIFO Buffer Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.2 Transmit Buffer Events and Interrupts . . . . . . . . . . . . . . . . . . . . . 14.2.8.3 Receive Buffer Events and Interrupts . . . . . . . . . . . . . . . . . . . . . 14.2.8.4 FIFO Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.5 FIFO Access Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.8.6 Handling of FIFO Transmit Control Information . . . . . . . . . . . . . . 14.3 Asynchronous Serial Channel (ASC = UART) . . . . . . . . . . . . . . . . . . . 14.3.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.1 Idle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.2 Start Bit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.3 Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.4 Parity Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2.5 Stop Bit(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3 Operating the ASC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.1 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.2 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.3 Noise Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.4 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.5 Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.6 Automatic Shadow Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.7 End of Frame Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.8 Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.9 Disabling ASC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.10 Protocol Interrupt Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.11 Data Transfer Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.12 Baud Rate Generator Interrupt Handling . . . . . . . . . . . . . . . . . . . 14.3.3.13 Protocol-Related Argument and Error . . . . . . . . . . . . . . . . . . . . . 14.3.3.14 Receive Buffer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Manual L-8 14-28 14-29 14-30 14-31 14-31 14-32 14-33 14-34 14-36 14-36 14-37 14-38 14-38 14-39 14-40 14-41 14-45 14-50 14-51 14-52 14-54 14-54 14-55 14-56 14-57 14-57 14-57 14-57 14-58 14-58 14-59 14-60 14-60 14-60 14-62 14-62 14-63 14-63 14-63 14-64 14-64 14-65 14-65 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 14.3.3.15 Sync-Break Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-65 14.3.3.16 Transfer Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-65 14.3.4 ASC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-66 14.3.4.1 ASC Protocol Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14-66 14.3.4.2 ASC Protocol Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-69 14.3.5 Hardware LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-72 14.4 Synchronous Serial Channel (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-74 14.4.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-74 14.4.1.1 Transmit and Receive Data Signals . . . . . . . . . . . . . . . . . . . . . . 14-76 14.4.1.2 Shift Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-77 14.4.1.3 Slave Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-80 14.4.2 Operating the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82 14.4.2.1 Automatic Shadow Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82 14.4.2.2 Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82 14.4.2.3 Disabling SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-83 14.4.2.4 Data Frame Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-83 14.4.2.5 Parity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-83 14.4.2.6 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-85 14.4.2.7 Data Transfer Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . 14-85 14.4.2.8 Baud Rate Generator Interrupt Handling . . . . . . . . . . . . . . . . . . . 14-86 14.4.2.9 Protocol-Related Argument and Error . . . . . . . . . . . . . . . . . . . . . 14-86 14.4.2.10 Receive Buffer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-86 14.4.2.11 Multi-IO SSC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-86 14.4.3 Operating the SSC in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14-88 14.4.3.1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-89 14.4.3.2 MSLS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-90 14.4.3.3 Automatic Slave Select Update . . . . . . . . . . . . . . . . . . . . . . . . . . 14-91 14.4.3.4 Slave Select Delay Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 14-92 14.4.3.5 Protocol Interrupt Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-93 14.4.3.6 End-of-Frame Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-94 14.4.4 Operating the SSC in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14-96 14.4.4.1 Protocol Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-96 14.4.4.2 End-of-Frame Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-97 14.4.5 SSC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-98 14.4.5.1 SSC Protocol Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . 14-98 14.4.5.2 SSC Protocol Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14-102 14.4.6 SSC Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-104 14.4.6.1 Closed-loop Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-104 14.4.6.2 Delay Compensation in Master Mode . . . . . . . . . . . . . . . . . . . . 14-107 14.4.6.3 Complete Closed-loop Delay Compensation . . . . . . . . . . . . . . . 14-108 14.5 Inter-IC Bus Protocol (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-109 14.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-109 14.5.1.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-109 Reference Manual L-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 14.5.1.2 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1.3 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2 Operating the IIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.1 Transmission Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.2 Byte Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.3 Master Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.4 Non-Acknowledge and Error Conditions . . . . . . . . . . . . . . . . . . 14.5.2.5 Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.6 Data Transfer Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.7 IIC Protocol Interrupt Events . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.8 Baud Rate Generator Interrupt Handling . . . . . . . . . . . . . . . . . . 14.5.2.9 Receiver Address Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.10 Receiver Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.2.11 Receiver Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3 Symbol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3.1 Start Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3.2 Repeated Start Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3.3 Stop Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.3.4 Data Bit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4 Data Flow Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4.1 Transmit Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4.2 Valid Master Transmit Data Formats . . . . . . . . . . . . . . . . . . . . . 14.5.4.3 Master Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . 14.5.4.4 Slave Transmit/Receive Modes . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5 IIC Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5.1 IIC Protocol Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.5.2 IIC Protocol Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Inter-IC Sound Bus Protocol (IIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.2 Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.3 Transfer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.4 Connection of External Audio Components . . . . . . . . . . . . . . . . 14.6.2 Operating the IIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.1 Frame Length and Word Length Configuration . . . . . . . . . . . . . 14.6.2.2 Automatic Shadow Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.3 Mode Control Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.4 Transfer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.5 Parity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.6 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.7 Data Transfer Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.8 Baud Rate Generator Interrupt Handling . . . . . . . . . . . . . . . . . . 14.6.2.9 Protocol-Related Argument and Error . . . . . . . . . . . . . . . . . . . . Reference Manual L-10 14-110 14-111 14-112 14-113 14-113 14-113 14-114 14-114 14-114 14-115 14-116 14-116 14-117 14-117 14-118 14-119 14-119 14-120 14-120 14-121 14-121 14-123 14-126 14-128 14-129 14-129 14-132 14-135 14-135 14-135 14-136 14-137 14-137 14-138 14-138 14-139 14-139 14-139 14-141 14-141 14-141 14-142 14-142 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 14.6.2.10 Transmit Data Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.11 Receive Buffer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.12 Loop-Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3 Operating the IIS in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3.1 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3.2 WA Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3.3 Master Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3.4 Protocol Interrupt Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.4 Operating the IIS in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.4.1 Protocol Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.5 IIS Protocol Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.5.1 IIS Protocol Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.5.2 IIS Protocol Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.7 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 Debug Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.10 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . 14.11 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.2 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.3 Channel Control and Configuration Registers . . . . . . . . . . . . . . . . 14.11.3.1 Channel Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.3.2 Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.3.3 Kernel State Configuration Register . . . . . . . . . . . . . . . . . . . . . 14.11.3.4 Interrupt Node Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.4 Protocol Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.4.1 Protocol Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.4.2 Protocol Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.4.3 Protocol Status Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.5 Input Stage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.5.1 Input Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.6 Baud Rate Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.6.1 Fractional Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.6.2 Baud Rate Generator Register . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.6.3 Capture Mode Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.7 Transfer Control and Status Registers . . . . . . . . . . . . . . . . . . . . . 14.11.7.1 Shift Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.7.2 Transmission Control and Status Register . . . . . . . . . . . . . . . . 14.11.7.3 Flag Modification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.8 Data Buffer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.8.1 Transmit Buffer Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.8.2 Receive Buffer Registers RBUF0, RBUF1 . . . . . . . . . . . . . . . . 14.11.8.3 Receive Buffer Registers RBUF, RBUFD, RBUFSR . . . . . . . . . Reference Manual L-11 14-142 14-143 14-143 14-143 14-144 14-145 14-145 14-146 14-146 14-147 14-147 14-147 14-150 14-153 14-153 14-153 14-153 14-153 14-157 14-157 14-158 14-158 14-163 14-164 14-167 14-168 14-168 14-169 14-170 14-171 14-171 14-177 14-177 14-178 14-181 14-181 14-181 14-185 14-191 14-193 14-193 14-194 14-200 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 14.11.9 FIFO Buffer and Bypass Registers . . . . . . . . . . . . . . . . . . . . . . . . 14.11.9.1 Bypass Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.9.2 General FIFO Buffer Control Registers . . . . . . . . . . . . . . . . . . . 14.11.9.3 Transmit FIFO Buffer Control Registers . . . . . . . . . . . . . . . . . . 14.11.9.4 Receive FIFO Buffer Control Registers . . . . . . . . . . . . . . . . . . . 14.11.9.5 FIFO Buffer Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.11.9.6 FIFO Buffer Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.12 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.12.1 USIC Module 0 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-204 14-204 14-207 14-213 14-217 14-222 14-225 14-226 14-227 15 15.1 15.1.1 15.1.2 15.1.3 15.2 15.2.1 15.3 15.3.1 15.3.2 15.4 15.4.1 15.4.1.1 15.4.2 15.4.3 15.4.4 15.5 15.6 15.6.1 15.6.2 15.6.3 15.6.4 15.6.5 15.6.6 15.6.7 15.6.8 15.6.9 15.7 15.7.1 15.7.2 15.7.3 Analog-to-Digital Converter (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 Analog Module Activation and Control . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Analog Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Sigma-Delta-Loop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Conversion Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Channel Scan Request Source Handling . . . . . . . . . . . . . . . . . . . . . 15-5 Analog Input Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Conversion Result Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Storage of Conversion Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Result Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Data Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 Module Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 Conversion Request Source Registers . . . . . . . . . . . . . . . . . . . . . . 15-23 Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 Result Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31 Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-35 Service Request Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-36 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 Product-Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 Analog Module Connections in the XMC1100 . . . . . . . . . . . . . . . . . 15-39 Digital Module Connections in the XMC1100 . . . . . . . . . . . . . . . . . 15-40 16 16.1 Temperature Sensor (TSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Reference Manual L-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 16.2 16.3 16.3.1 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 17 Capture/Compare Unit 4 (CCU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.2.1 CC4y Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.2.2 Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.2.3 Connection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.2.4 Starting/Stopping the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.2.5 Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.2.5.1 Calculating the PWM Period and Duty Cycle . . . . . . . . . . . . . . . 17-14 17.2.5.2 Updating the Period and Duty Cycle . . . . . . . . . . . . . . . . . . . . . . 17-15 17.2.5.3 Edge Aligned Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.2.5.4 Center Aligned Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17.2.5.5 Single Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 17.2.6 Active/Passive Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.2.7 External Events Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.2.7.1 External Start/Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17.2.7.2 External Counting Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.2.7.3 External Gating Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.2.7.4 External Count Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.2.7.5 External Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28 17.2.7.6 External Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29 17.2.7.7 Capture Extended Read Back Mode . . . . . . . . . . . . . . . . . . . . . . 17-35 17.2.7.8 External Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17.2.7.9 TRAP Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 17.2.7.10 Status Bit Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 17.2.8 Multi-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-44 17.2.9 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47 17.2.10 PWM Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52 17.2.11 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57 17.2.11.1 Normal Prescaler Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-58 17.2.11.2 Floating Prescaler Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-58 17.2.12 CCU4 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-60 17.2.12.1 PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-60 17.2.12.2 Prescaler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-62 17.2.12.3 PWM Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-64 17.2.12.4 Capture Mode Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-67 17.3 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-73 Reference Manual L-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 17.4 17.5 17.5.1 17.5.2 17.6 17.6.1 17.6.2 17.7 17.7.1 17.7.2 17.8 17.8.1 Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-77 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-77 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-77 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-78 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . 17-78 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-79 System Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-79 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-80 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 Slice (CC4y) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-101 Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-137 CCU40 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-137 18 18.1 18.1.1 18.1.2 18.1.3 18.2 18.2.1 18.2.2 18.3 18.4 18.5 18.6 18.7 18.8 18.8.1 18.8.2 18.8.3 18.8.4 18.8.5 18.8.6 18.8.7 18.8.8 18.9 18.10 18.10.1 18.10.2 18.10.3 General Purpose I/O Ports (Ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 GPIO and Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 Input Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 Hardware Controlled I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 Power Saving Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 Analog Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . 18-10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 Port Input/Output Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 Pad Hysteresis Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 Pin Function Decision Control Register . . . . . . . . . . . . . . . . . . . . . . 18-24 Port Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 Port Output Modification Register . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 Port Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 Port Pin Power Save Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35 Port Pin Hardware Select Register . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 Port Pin for Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-45 Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . 18-46 19 19.1 19.1.1 Boot and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 Startup Sequence and System Dependencies . . . . . . . . . . . . . . . . . . . 19-2 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Reference Manual L-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 19.1.2 19.1.3 19.1.3.1 19.1.4 19.1.5 19.2 19.2.1 19.2.1.1 19.2.1.2 19.2.1.3 19.2.1.4 19.2.1.5 19.2.2 19.2.3 19.2.3.1 19.2.3.2 19.3 System Reset Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Startup Software (SSW) Execution . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Clock system handling by SSW . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 Configuration of Special System Functions as part of User code initialization 19-3 Configuration of Clock System and Miscellaneous Functions . . . . . . 19-4 Start-up Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 Start-up modes in XMC1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 User productive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 User mode with debug enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 User mode with debug enabled and Halt After Reset (HAR) . . . . . 19-6 Standard Bootstrap Loader modes . . . . . . . . . . . . . . . . . . . . . . . . 19-6 Bootstrap Loader modes with time-out . . . . . . . . . . . . . . . . . . . . . 19-6 Boot Mode Index (BMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 Start-up mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 BMI handling by SSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 Debug system handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 Data in Flash for SSW and User SW . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 20 20.1 20.1.1 20.1.2 20.1.2.1 20.1.2.2 20.1.3 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.3.7 20.4 Bootstrap Loaders (BSL) and User Routines . . . . . . . . . . . . . . . . . . 20-1 ASC (UART) Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 Pin usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 ASC BSL execution flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 ASC BSL entry check sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 ASC BSL download sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 ASC BSL protocol data definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 SSC Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 Firmware routines available for the user . . . . . . . . . . . . . . . . . . . . . . . 20-11 Erase Flash Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 Erase, Program & Verify Flash Page . . . . . . . . . . . . . . . . . . . . . . . . 20-13 Request BMI installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 Calculate chip temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 Erase Flash Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 Program & Verify Flash Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 Calculate target level for temperature comparison . . . . . . . . . . . . . 20-14 Data in Flash used by the User Routines . . . . . . . . . . . . . . . . . . . . . . 20-15 21 21.1 21.1.1 21.1.2 21.2 21.2.1 21.2.2 Debug System (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Space (SCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Watchpoint and Trace (DWT) . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Manual L-15 21-1 21-1 21-2 21-2 21-2 21-3 21-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Table of Contents 21.2.3 Break Point Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.4 ROM Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.5 Debug tool interface access - SWD . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.5.1 SWD based transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.5.2 SWD based errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.6 Debug tool interface access - Single Pin Debug (SPD) . . . . . . . . . . . 21-6 21.2.7 Debug accesses and Flash protection . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.2.8 Halt after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.2.8.1 HAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.2.8.2 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 21.2.9 Halting Debug and Peripheral Suspend . . . . . . . . . . . . . . . . . . . . . 21-12 21.2.10 Debug System based processor wake-up . . . . . . . . . . . . . . . . . . . . 21-14 21.2.11 Debug Access Server (DAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 21.2.12 Debug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 21.2.12.1 Internal pull-up and pull-down on SWD/SPD pins . . . . . . . . . . . . 21-15 21.2.13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.3 Debug System Power Save Operation . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.4 Service Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.5 Debug behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.6 Power, Reset and Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.6.1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.6.2 Debug System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.6.3 Debug System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.7 Initialization and System Dependencies . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.7.1 ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.7.2 ROM Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.8 Debug System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 21.8.1 DFSR - Debug Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . 21-20 21.8.2 DHCSR - Debug Halting Control and Status Register . . . . . . . . . . . 21-21 21.8.3 DCRSR - Debug Core Register Selector Register . . . . . . . . . . . . . 21-27 21.8.4 DCRDR - Debug Core Register Data Register . . . . . . . . . . . . . . . . 21-29 21.8.5 DEMCR - Debug Exception and Monitor Control Register . . . . . . . 21-29 21.8.6 DWT_CTRL - Data Watchpoint Control Register . . . . . . . . . . . . . . 21-31 21.8.7 DWT_PCSR - Program Counter Sample Register . . . . . . . . . . . . . 21-31 21.8.8 DWT_COMPx - DWT Comparator register . . . . . . . . . . . . . . . . . . . 21-32 21.8.9 DWT_MASKx - DWT Comparator Mask Register . . . . . . . . . . . . . . 21-33 21.8.10 DWT_FUNCTIONx - Comparator Function Register . . . . . . . . . . . . 21-34 21.8.11 BP_CTRL - Breakpoint Control Register . . . . . . . . . . . . . . . . . . . . . 21-35 21.8.12 Breakpoint Comparator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 Reference Manual L-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document About this Document This Reference Manual is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the behavior of the XMC1100 series functional units and their interaction. The manual describes the functionality of the superset device of the XMC1100 microcontroller series. For the available functionality (features) of a specific XMC1100 derivative (derivative device), please refer to the respective Data Sheet. For simplicity, the various device types are referenced by the collective term XMC1100 throughout this manual. XMC1000 Family User Documentation The set of user documentation includes: • • • Reference Manual – decribes the functionality of the superset device. Data Sheets – list the complete ordering information, available features and electrical characteristics of derivative devices. Errata Sheets – list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions of those documents. Related Documentations The following documents are referenced: • • • • ARM® Cortex M0 – Technical Reference Manual – User Guide, Reference Material ARM®v6-M Architecture Reference Manual AMBA® 3 AHB-Lite Protocol Specification AMBA® 3 APB Protocol Specification Copyright Notice • Portions of CPU chapter Copyright © 2009, 2010 by ARM, Ltd. All rights reserved. Used with permission. Reference Manual Preface, V2.0 P-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document Text Conventions This document uses the following naming conventions: • • • • • • • Functional units of the XMC1100 are given in plain UPPER CASE. For example: “The USIC0 unit supports…”. Pins using negative logic are indicated by an overline. For example: “The WAIT input has…”. Bit fields and bits in registers are in general referenced as “Module_RegisterName.BitField” or “Module_RegisterName.Bit”. For example: “The USIC0_PCR.MCLK bit enables the…”. Most of the register names contain a module name prefix, separated by an underscore character “_” from the actual register name (for example, “USIC0_PCR”, where “USIC0” is the module name prefix, and “PCR” is the kernel register name). In chapters describing the kernels of the peripheral modules, the registers are mainly referenced with their kernel register names. The peripheral module implementation sections mainly refer to the actual register names with module prefixes. Variables used to describe sets of processing units or registers appear in mixed upper and lower cases. For example, register name “MOFCRn” refers to multiple “MOFCR” registers with variable n. The bounds of the variables are always given where the register expression is first used (for example, “n = 0-31”), and are repeated as needed in the rest of the text. The default radix is decimal. Hexadecimal constants are suffixed with a subscript letter “H”, as in 100H. Binary constants are suffixed with a subscript letter “B”, as in: 111B. When the extent of register fields, groups register bits, or groups of pins are collectively named in the body of the document, they are represented as “NAME[A:B]”, which defines a range for the named group from B to A. Individual bits, signals, or pins are given as “NAME[C]” where the range of the variable C is given in the text. For example: CFG[2:0] and SRPN[0]. Units are abbreviated as follows: – MHz = Megahertz – μs = Microseconds – kBaud, kbit = 1000 characters/bits per second – MBaud, Mbit = 1,000,000 characters/bits per second – Kbyte, KB = 1024 bytes of memory – Mbyte, MB= 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The kBaud unit scales the expression preceding it by 1000. The M prefix scales by 1,000,000 or 1048576. For example, 1 Kbyte is 1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits per second, 1 MBaud/Mbit are 1000000 characters/bits per second, and 1 MHz is 1,000,000 Hz. Reference Manual Preface, V2.0 P-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document • Data format quantities are defined as follows: – Byte = 8-bit quantity – Half-word = 16-bit quantity – Word = 32-bit quantity – Double-word = 64-bit quantity Bit Function Terminology In tables where register bits or bit fields are defined, the following conventions are used to indicate the access types. Table 1 Bit Function Terminology Bit Function Description rw The bit or bit field can be read and written. rwh As rw, but bit or bit field can be also set or reset by hardware. If not otherwise documented the software takes priority in case of a write conflict between software and hardware. r The bit or bit field can only be read (read-only). w The bit or bit field can only be written (write-only). A read to this register will always give a default value back. rh This bit or bit field can be modified by hardware (read-hardware, typical example: status flags). A read of this bit or bit field give the actual status of this bit or bit field back. Writing to this bit or bit field has no effect to the setting of this bit or bit field. Register Access Modes Read and write access to registers and memory locations are sometimes restricted. In memory and register access tables, the following terms are used. Table 2 Register Access Modes Symbol Description PV (SV), U Access permitted in Privileged (Supervisor) Mode. Note: ARM® Cortex M0 processor does not support different privilege levels. Only Privileged (Supervisor) Mode is supported in XMC1000 Family. Symbol “U” and Symbol “PV” can be used to represent the access permitted in this mode. BP Indicates that this register can only be access when the bit protection is disabled. See detailed description of Bit Protection Scheme in the Memory Organisation chapter. Reference Manual Preface, V2.0 P-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document Table 2 Register Access Modes (cont’d) Symbol Description 32 Only 32-bit word accesses are permitted to this register/address range. NC No change, indicated register is not changed. BE Indicates that an access to this address range generates a Bus Error. nBE Indicates that no Bus Error is generated when accessing this address range. Reserved Bits Register bit fields named Reserved or 0 indicate unimplemented functions with the following behavior. • • • Reading these bit fields returns 0. These bit fields should be written with 0 if the bit field is defined as r or rh. These bit fields have to be written with 0 if the bit field is defined as rw. These bit fields are reserved. The detailed description of these bit fields can be found in the register descriptions. Abbreviations and Acronyms The following acronyms and terms are used in this document: AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture ANACTRL Analog Control Unit APB Advanced Peripheral Bus ASC Asynchronous Serial Channel BCCU Brightness and Colour Control Unit BMI Boot Mode Index CMSIS Cortex Microcontroller Software Interface Standard CPU Central Processing Unit CCU4 Capture Compare Unit 4 CCU8 Capture Compare Unit 8 CRC Cyclic Redundancy Code DCO Digitally Controlled Oscillator ECC Error Correction Code ERU Event Request Unit Reference Manual Preface, V2.0 P-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document EVR Embedded Voltage Regulator FPU Floating Point Unit GPIO General Purpose Input/Output HMI Human-Machine Interface IIC Inter Integrated Circuit (also known as I2C) IIS Inter-IC Sound Interface I/O Input / Output JTAG Joint Test Action Group = IEEE1149.1 LED Light Emitting Diode LEDTS LED and Touch Sense Control Unit MSB Most Significant Bit NC Not Connected NMI Non-Maskable Interrupt NVIC Nested Vectored Interrupt Controller ORC Out of Range Comparator PAU Peripheral Access Unit POSIF Position Interface PRNG Pseudo Random Number Generator ROM Read-Only Memory RAM Random Access Memory RTC Real Time Clock SCU System Control Unit SFR Special Function Register SHS Sample and Hold Sequencer SPI Serial Peripheral Interface SRAM Static RAM SR Service Request SSC Synchronous Serial Channel SSW Start-up Software TSE Temperature Sensor UART Universal Asynchronous Receiver Transmitter USIC Universal Serial Interface Channel Reference Manual Preface, V2.0 P-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family About this Document VADC Versatile Analog-to-Digital Converter WDT Watchdog Timer Reference Manual Preface, V2.0 P-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction Introduction Reference Manual V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction 1 Introduction The XMC1100 series belongs to the XMC1000 Family of industrial microcontrollers based on the ARM Cortex-M0 processor core. The XMC1100 series devices are designed for general purpose applications. Increasing complexity and demand for computing power of embedded control applications requires microcontrollers to have a significant CPU performance, integrated peripheral functionality and rapid development environment enabling short time-tomarket, without compromising cost efficiency. Nonetheless the architecture of the XMC1100 microcontroller pursue successful hardware and software concepts, which have been established in Infineon microcontroller families. 1.1 Overview The XMC1100 series devices combine the extended functionality and performance of the Cortex-M0 core with powerful on-chip peripheral subsystems and on-chip memory units. The following key features are available within the range of XMC1100 series devices: CPU Subsystem • • • CPU Core – High Performance 32-bit Cortex-M0 CPU – Most of 16-bit Thumb instruction set – Subset of 32-bit Thumb2 instruction set – High code density with 32-bit performance – Single cycle 32-bit hardware multiplier – System timer (SysTick) for Operating System support – Ultra low power consumption Nested Vectored Interrupt Controller (NVIC) Event Request Unit (ERU) for programmable processing of external and internal service requests On-Chip Memories • • • 8 kbytes on-chip ROM 16 kbytes on-chip high-speed SRAM up to 64 kbytes on-chip Flash program and data memory Reference Manual Architectural Overview, V1.0 1-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction System Control and Peripherals • • • • • • • • Universal Serial Interface Channels (USIC), usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces A/D Converters, up to 12 channels, includes a 12-bit analog to digital converter Capture/Compare Units 4 (CCU4) for use as general purpose timers Window Watchdog Timer (WDT) for safety sensitive applications Real Time Clock module with alarm support (RTC) System Control Unit (SCU) for system configuration and control Temperature Sensor (TSE) Pseudo random number generator (PRNG), provides random data with fast generation times Input/Output Lines With Individual Bit Controllability • • • Tri-stated in input mode Push/pull or open drain output mode Configurable pad hysteresis Debug System • • • Access through the standard ARM serial wire debug (SWD) or the single pin debug (SPD) interface A breakpoint unit (BPU) supporting up to 4 hardware breakpoints A watchpoint unit (DWT) supporting up to 2 watchpoints Packages Information • • • • PG-VQFN-40 PG-VQFN-24 PG-TSSOP-38 PG-TSSOP-16 Note: For details about package availability for a particular derivative please check the datasheet. Reference Manual Architectural Overview, V1.0 1-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction 1.1.1 Block Diagram The diagram below shows the functional blocks and their basic connectivity within the XMC1100 System. Cortex-M0 CPU Analog system EVR 2 x DCO Debug system NVIC SWD SPD ANACTRL SFRs PRNG 16-bit APB Bus Temperature sensor AHB to APB Bridge PAU AHB-Lite Bus Flash SFRs 1) 64k + 0.5k Flash PORTS CCU40 16k SRAM WDT USIC0 8k ROM SCU VADC RTC Memories ERU0 1) 0.5kbytes of sector 0 (readable only). Figure 1-1 1.2 XMC1100 Functional diagram Core Processing Units The XMC1100 system core consists of the CPU and the memory interface blocks for memories. Reference Manual Architectural Overview, V1.0 1-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction 1.2.1 Central Processing Unit (CPU) The ARM Cortex-M0 processor is built on a highly area and power optimized 32-bit processor core, with a 3-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single cycle multiplier. The instruction set is based on the 16-bit Thumb instrcution set and includes Thumb-2 technology. This provides the exceptional perfomance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. 1.2.2 Programmable Multiple Priority Interrupt System (NVIC) The XMC1100 provides separate interrupt nodes that may be assigned to 4 interrupt priority levels. Most interrupt sources are connected to a dedicated interrupt node. In some cases, multi-source interrupt nodes are incorporated for efficient use of system resources. These nodes can be activated by several source requests and are controlled via interrupt subnode control registers. 1.3 System Units The XMC1100 controllers provide a number of system resources designed around the CPU. 1.3.1 Memories 8 kbytes of ROM (ROM) memory for boot code execution and exception vector table. The ROM contains system basic initialization sequence code and is executed immediately after reset release. The Bootstrap Loaders(BSL) and User Routines are also stored in the ROM. Up to 64 kbytes of on-chip Flash memory store code or constant data. Dynamic error correction provides high read data security for all read accesses. 16 kbytes of on-chip code RAM (SRAM) are provided to store user code or data, as well as system variables such as system stack. The SRAM is accessed via the AHB and provides zero-waitstate access for CPU code execution. 1.3.2 Watchdog Timer (WDT) The main purpose of the Window Watchdog Timer is to improve the system integrity. WDT triggers the system reset or other corrective action like e.g. an interrupt if the main program, due to some fault condition, neglects to regularly service the watchdog. The intention is to bring the system back from the unresponsive state into normal operation. Reference Manual Architectural Overview, V1.0 1-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction 1.3.3 Real Timer Clock (RTC) Real-time clock (RTC) is a clock that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time in a digital format for clock displays and computer systems.. 1.3.4 System Control unit (SCU) The System Control Unit (SCU) handles all system cotnrol tasks besides the debug related tasks. All functions are tightly coupled and thus, they are conveniently handled by one unit, SCU. It consists of the Power Control Unit (PCU), Reset Control Unit, Clock Control Unit (CCU) and the Miscellaneous Control Unit (GCU). The CCU generates the Main clock (MCLK) and the fast Peripheral clock (PCLK) using the 64MHz DCO1 oscillator. The PCU has a Embedded Voltage Regulator (EVR) that is used to generate the core voltage. It also provides voltage monitoring detectors to secure system performance under critical condition (eg. brownout). 1.3.5 Pseudo Random Bit Generator (PRNG) The pseudo random bit generator (PRNG) provides random data with fast generation times. 1.4 Peripherals Units XMC1100 offers a set of on-chip peripherals to support industrial applications. Universal Serial Interface Channel (USIC) The USIC is a flexible interface module covering several serial communication protocols such as ASC, LIN, SSC, I2C, I2S. A USIC module contains two independent communication channels which can be used in parallel. A FIFO allows transmit and result buffering for relaxing real-time conditions. Multiple chip select signals are available for communication with multiple devices on the same channel. Analog to Digital Converter (VADC) The Versatile Analog-to-Digital Converter module consists of an independent kernels which operate according to the successive approximation principle (SAR). The resolution is programmable from 8 to 12bit. The kernel provides a versatile state machine allowing complex measurement sequences. The kernels can be synchronized and conversions may run completely in background. Multiple trigger events can be prioritized and allow the exact measurement of time critical signals. The result buffering and handling avoids data loss and ensures consistency. Self-test mechanisms can be used for plausibility checks. Reference Manual Architectural Overview, V1.0 1-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Introduction The basic structure supports a clean software architecture where tasks may only read valid results and do not need to care for starting conversions. Capture/Compare Unit 4 (CCU4) The CCU4 peripheral is a major component for systems that need general purpose timers for signal monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like switched mode power supplies or uninterruptible power supplies can easily be implemented with the functions inside the CCU4 peripheral. The internal modularity of CCU4 translates into a software friendly system for fast code development and portability between applications. General Purpose I/O Ports (PORTS) The Ports provide a generic and very flexible software and hardware interface for all standard digital I/Os. Each Port slice has individual interfaces for the operation as General Purpose I/O and it further provides the connectivity to the on-chip periphery and the control for the pad characteristics. Temperature Sensor (TSE) The Temperature Sensor generates a measurement result that indicates directly the die temperature. It is also capable of generating interrupt requests when the temperature measurement crosses the selectable upper/lower threshold value. 1.5 Debug Unit The on-chip debug system based on the ARM Cortex-M0TM debug system provides a broad range of debug and emulation features built into the XMC1100. The user software running on the XMC1100 can thus be debugged within the target system environment. The Debug unit is controlled by an external debugging tool via the debug interface. The debugger controls the Debug unit via a set of dedicated registers accessible via the debug interface. Additionally, the Debug unit can be controlled by the CPU, e.g. by a monitor program. Multiple breakpoints can be triggered by on-chip hardware or by software. Single stepping is supported as well as the injection of arbitrary instructions and read/write access to the complete internal address space. A breakpoint trigger can be answered with a CPU-halt, a monitor call or a data transfer. The data transferred at a watchpoint (see above) can be obtained via the debug interface for increased performance. Reference Manual Architectural Overview, V1.0 1-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family CPU Subsystem CPU Subsystem Reference Manual V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2 Central Processing Unit (CPU) XMC1100 features the ARM Cortex-M0 processor. An entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. This CPU offers significant benefits to users, including: • • • • • a simple architecture that is easy to learn and program ultra-low power, energy efficient operation excellent code density deterministic, high-performance interrupt handling upward compatibility with Cortex-M processor family References to ARM Documentation The following documents can be accessed through http://infocenter.arm.com [1] Cortex™-M0 Devices, Generic User Guide (ARM DUI 0467B) [2] ARMv6-M Architecture Reference Manual (ARM DDI 0419) [3] Cortex Microcontroller Software Interface Standard (CMSIS) References to ARM Figures [4] http://www.arm.com 2.1 Overview The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor core, with a 3-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the 16-bit Thumb® instruction set and includes Thumb-2 technology. The Cortex-M0 instruction set provides exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. The Cortex-M0 processor closely integrates a configurable NVIC, to deliver industry leading interrupt performance. The NVIC provides 4 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart load-multiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. Reference Manual CPU, V2.1 2-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down. 2.1.1 Features The CPU provides the following functionality: • • • • • • Thumb instruction set combines high code density with 32-bit performance integrated sleep modes for low power consumption fast code execution permits slower processor clock or increases sleep mode time single cycle 32-bit hardware multiplier high-performance interrupt handling for time-critical applications extensive debug capabilities: – Serial Wire Debug and Single Pin Debug reduce the number of pins required for debugging. 2.1.2 Block Diagram The Cortex-M0 core components comprise of: Processor Core The CPU provides most 16-bit Thumb instruction set and subset of 32-bit Thumb2 instruction set. Nested Vectored Interrupt Controller The NVIC is an embedded interrupt controller that supports low latency interrupt processing. Debug Solution The XMC1100 implements a complete hardware debug solution. • • Single Pin Debug (SPD) or 2-pin Serial Wire Debug (SWD) Extensive hardware breakpoint and watchpoint options This provides high system control and visibility of the processor and memory even in small package devices. Reference Manual CPU, V2.1 2-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Cortex -M0 components Cortex -M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Debug Cortex -M0 processor core Breakpoint and watchpoint unit Bus Matrix Debugger Interface AHB-Lite interface Figure 2-1 Debug Access Port (DAP) Single Pin or Serial Wire debug -port Cortex-M0 Block Diagram System Level Interface The Cortex-M0 processor provides a single system-level interface using AMBA® technology to provide high speed, low latency memory accesses. 2.2 Programmers Model This section describes the Cortex-M0 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and stacks. 2.2.1 Processor Mode The processor modes are: • • Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished all exception processing. 2.2.2 Stacks The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked item in memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory Reference Manual CPU, V2.1 2-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) location. The processor implements two stacks, the main stack and the process stack, with a pointer for each held in independent registers, see Stack Pointer. In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see CONTROL Register. In Handler mode, the processor always uses the main stack. The options for processor operations are: Table 2-1 Summary of processor mode, execution, and stack use options Processor mode Used to execute Stack used Thread Applications Main stack or process stack1) Handler Exception handlers Main stack 1) See CONTROL Register. Reference Manual CPU, V2.1 2-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.2.3 Core Registers R0 R1 R2 R3 Low registers R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) Figure 2-2 PSP PSR Program status register PRIMASK Interrupt mask register CONTROL CONTROL register MSP Special registers Core registers The processor core registers are: Table 2-2 Core register set summary Name Type1) Reset value Description R0-R12 rw Unknown General-purpose registers on Page 2-6 MSP rw See description Stack Pointer on Page 2-6 PSP rw Unknown Stack Pointer on Page 2-6 LR rw Unknown Link Register on Page 2-7 PC rw See description Program Counter on Page 2-8 PSR rw Unknown Program Status Register on Page 2-8 Reference Manual CPU, V2.1 2-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-2 Core register set summary (cont’d) Name Type1) Reset value Description APSR rw Unknown Application Program Status Register on Page 2-9 IPSR r 00000000H Interrupt Program Status Register on Page 2-10 EPSR r Unknown Execution Program Status Register on Page 2-12 PRIMASK rw 00000000H Priority Mask Register on Page 2-13 CONTROL rw 00000000H CONTROL Register on Page 2-14 1) Describes access type during program execution in thread mode and handler mode. Debug access can differ. General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. Note: For information on how to program the core registers, please refer to the ARMv6M Architecture Reference Manual [2]. Rx (x=0-12) General-purpose register Rx 31 30 29 28 27 26 Reset Value: XXXXXXXXH 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Value rw 15 14 13 12 11 10 9 8 7 Value rw Field Bits Type Description Value [31:0] rw Content of Register Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use: • 0 = Main Stack Pointer (MSP). This is the reset value. Reference Manual CPU, V2.1 2-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) • 1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 00000000H. Note: For information on how to program the core registers, please refer to the ARMv6M Architecture Reference Manual [2]. SP Stack Pointer 31 30 29 Reset Value: 00000000H 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Value rw 15 14 13 12 11 10 9 8 7 Value rw Field Bits Type Description Value [31:0] rw Content of Register Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the LR value is unknown. Note: For information on how to program the core registers, please refer to the ARMv6M Architecture Reference Manual [2]. LR Link Register 31 30 29 Reset Value: XXXXXXXXH 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Value rw 15 14 13 12 11 10 9 8 7 Value rw Reference Manual CPU, V2.1 2-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description Value [31:0] rw Content of Register Program Counter The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 00000004H. Bit [0] of the value is loaded into the EPSR T-bit at reset and must be 1. Note: For information on how to program the core registers, please refer to the ARMv6M Architecture Reference Manual [2]. PC Program Counter 31 30 29 28 Reset Value: 00000004H 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Value rw 15 14 13 12 11 10 9 8 7 Value rw Field Bits Type Description Value [31:0] rw Content of Register Program Status Register The Program Status Register (PSR) combines: • • • Application Program Status Register (APSR) Interrupt Program Status Register (IPSR) Execution Program Status Register (EPSR) These registers are mutually exclusive bit fields in the 32-bit PSR. Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • • read all of the registers using PSR with the MRS instruction write to the APSR N, Z, C, and V bits using APSR with the MSR instruction Reference Manual CPU, V2.1 2-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) The PSR combinations and attributes are: Table 2-3 PSR register combinations Register Type Combination 1)2) PSR rw APSR, EPSR, and IPSR IEPSR r EPSR and IPSR IAPSR rw1) APSR and IPSR 2) EAPSR rw APSR and EPSR 1) The processor ignores writes to the IPSR bits. 2) Reads of the EPSR bits return zero, and the processor ignores writes to the these bits Application Program Status Register The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 2-2 for its attributes. APSR Application Program Status Register 27 26 31 30 29 28 N Z C V 0 rw rw rw rw rw 15 14 13 12 11 10 25 Reset Value: XXXXXXXXH 9 24 23 8 7 22 21 20 19 18 17 16 5 4 3 2 1 0 6 0 rw Field Bits Type Description N 31 rw Negative flag Z 30 rw Zero flag C 29 rw Carry or borrow flag V 28 rw Overflow flag 0 [27:0] r Reserved Reference Manual CPU, V2.1 2-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Interrupt Program Status Register The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 2-2 for its attributes. IPSR Interrupt Program Status Register 31 30 29 28 27 26 25 Reset Value: 00000000H 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 ISR_NUMBER r r Field Bits Type Description 0 [31:6] r Reference Manual CPU, V2.1 Reserved 2-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description ISR_NUMBER [5:0] r Reference Manual CPU, V2.1 Number of the current exception 0D Thread mode Reserved 1D 2D Reserved 3D HardFault Reserved 4D 5D Reserved 6D Reserved Reserved 7D 8D Reserved 9D Reserved 10D Reserved 11D SVCall 12D Reserved 13D Reserved 14D PendSV 15D SysTick 16D IRQ0 ... 47D IRQ31 48D-63D Reserved See Exception types in Section 2.5.2 for more information. 2-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Execution Program Status Register The EPSR contains the Thumb state bit. See the register summary in Table 2-2 for the EPSR attributes. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the cause of the fault. See Exception Entry and Return in Section 2.5.6. EPSR Execution Program Status Register 31 15 30 14 29 13 28 27 26 25 Reset Value: XXXXXXXXH 24 23 22 21 20 0 T 0 r r r 12 11 10 9 8 7 6 5 4 19 18 17 16 3 2 1 0 0 r Field Bits Type Description 0 [31:25] r Reserved T 24 r Thumb state bit See Thumb state. 0 [23:0] r Reserved Interruptible-restartable instructions When an interrupt occurs during the execution of an LDM, STM, PUSH, POP instruction, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning. Thumb state The Cortex-M0 processor only supports execution of instructions in Thumb state. The following can clear the T bit to 0: • instructions BLX, BX and POP{PC} Reference Manual CPU, V2.1 2-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) • • restoration from the stacked xPSR value on an exception return bit[0] of the vector value on an exception entry. Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See Lockup in Section 2.6.1 for more information. Exception mask registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks or code sequences requiring atomicity. Exceptions can be disabled or re-enabled by the MSR and MRS instructions, or the CPS instruction, to change the value of PRIMASK or FAULTMASK. Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 2-2 for its attributes. PRIMASK Priority Mask Register 31 30 29 28 Reset Value: 00000000H 27 26 25 24 23 22 21 20 19 18 17 7 6 5 4 3 2 1 16 0 r 15 14 13 12 11 10 9 8 0 PRI MAS K rw 0 r Field Bits Type Description 0 [31:1] r Reserved PRIMASK 0 rw Priority Mask No effect. 0B 1B Prevents the activation of all exceptions with configurable priority. Reference Manual CPU, V2.1 2-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) CONTROL Register The CONTROL register controls the stack used when the processor is in Thread mode. See the register summary in Table 2-2 for its attributes. CONTROL CONTROL Register 31 30 29 28 Reset Value: 00000000H 27 26 25 24 23 22 21 20 19 18 7 6 5 4 3 2 17 16 0 r 15 14 13 12 11 10 9 8 1 0 0 SPS EL 0 r rw r Field Bits Type Description 0 [31:2] r Reserved SPSEL 1 rw Active stack pointer This bit defines the current stack. In Handler mode, this bit reads as zero and ignores writes. MSP is the current stack pointer 0B PSP is the current stack pointer 1B 0 0 r Reserved Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register. In an OS environment, it is recommended that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruction to set the Active stack pointer bit to 1. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer. Reference Manual CPU, V2.1 2-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.2.4 Exceptions and Interrupts The Cortex-M0 processor supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An interrupt or exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See Exception entry on Section 2.5.6.1 and Exception return on Section 2.5.6.2 for more information. The NVIC registers control interrupt handling. See Interrupt System chapter for more information. 2.2.5 Data Types The processor: • • supports the following data types: – 32-bit words – 16-bit halfwords – 8-bit bytes manages all data memory accesses as little-endian. See Memory regions, types and attributes in Section 2.3.1 for more information. 2.2.6 The Cortex Microcontroller Software Interface Standard For a Cortex-M0 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) [3] defines: • • • a common way to: – access peripheral registers – define exception vectors the names of: – the registers of the core peripherals – the core exception vectors a device-independent interface for RTOS kernels. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M0 processor. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. Reference Manual CPU, V2.1 2-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Note: This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS: • • • • Power Management Programming Hints in Section 2.7.3 CMSIS Functions in Section 2.2.7 Accessing CPU Registers using CMSIS in Interrupt System chapter NVIC programming hints in Interrupt System chapter For additional information please refer to http://www.onarm.com/cmsis 2.2.7 CMSIS Functions ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMSIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, an inline assembler may be used to access the relevant instruction. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 2-4 CMSIS functions to generate some Cortex-M0 instructions Instruction CMSIS intrinsic function CPSIE i void __enable_irq (void) CPSID i void __disable_irq (void) ISB void __ISB (void) DSB void __DSB (void) DMB void __DMB (void) NOP void __NOP (void) REV uint32_t __REV (uint32_t int value) REV16 uint32_t __REV16 (uint32_t int value) REVSH uint32_t __REVSH (uint32_t int value) WFE void __WFE (void) WFI void __WFI (void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Reference Manual CPU, V2.1 2-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-5 CMSIS functions to access the special registers Special register Access CMSIS function PRIMASK Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) CONTROL Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) MSP PSP Reference Manual CPU, V2.1 Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfMainStack) 2-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.3 Memory Model This section describes the processor memory map and the behavior of memory accesses. The processor has a fixed default memory map that provides up to 4GB of addressable memory. The memory map is: 0xFFFFFFFF Device 511MB 0xE0100000 0xE00FFFFF Private peripheral 1.0MB bus 0xE0000000 0xDFFFFFFF External device 1.0GB 0xA0000000 0x9FFFFFFF External RAM 1.0GB 0x60000000 0x5FFFFFFF Peripheral 0.5GB 0x40000000 0x3FFFFFFF SRAM 0.5GB 0x20000000 0x1FFFFFFF Code 0.5GB 0x00000000 Figure 2-3 Memory map Reference Manual CPU, V2.1 2-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see About the Private Peripherals in Section 2.8.1. 2.3.1 Memory Regions, Types and Attributes The memory map is split into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. The additional memory attributes include: Execute Never (XN) Means the processor prevents instruction accesses. A HardFault exception is generated on execution of an instruction fetched from an XN region of memory. 2.3.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing any re-ordering does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see Software ordering of memory accesses in Section 2.3.4. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is described in Figure 2-4. Reference Manual CPU, V2.1 2-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Normal access Device access Stronglyordered access Normal access - - - Device access - < < Strongly-ordered access - <- < A2 A1 Figure 2-4 Memory system ordering Where: • • “-” Means that the memory system does not guarentee the ordering of the accesses. “<” Means that accesses are observed in program order, that is, A1 is always observed before A2. 2.3.3 Behavior of Memory Accesses The behavior of accesses to each region in the memory map is: Table 2-6 Memory access behavior Address range Memory region Memory type1) XN1) Description 0x000000000x1FFFFFFF Code Normal - Executable region for program code. Data can be placed here. 0x200000000x3FFFFFFF SRAM Normal - Executable region for data. Code can be placed here. 0x400000000x5FFFFFFF Peripheral Device XN Peripherals region. 0x600000000x9FFFFFFF External RAM Normal - Executable region for data. 0xA00000000xDFFFFFFF External device XN External device memory. Reference Manual CPU, V2.1 Device 2-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-6 Memory access behavior (cont’d) Address range Memory region Memory type1) XN1) Description 0xE00000000xE00FFFFF Private Peripheral Bus Stronglyordered XN This region includes the NVIC, system timer, and system control block. Only word accesses can be used in this region. 0xE01000000xFFFFFFFF Device Device XN Vendor specific 1) See Memory regions, types and attributes in Section 2.3.1 for more information. The Code, SRAM, and external RAM regions can hold programs. 2.3.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: • • • the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. memory or devices in the memory map have different wait states some memory accesses are buffered or speculative. Memory system ordering of memory accesses in Section 2.3.2 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. Reference Manual CPU, V2.1 2-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.3.5 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Section 2.3.5.1 describes how words of data are stored in memory. 2.3.5.1 Little-endian format In little-endian format, the processor stores the least significant byte (lsbyte) of a word at the lowest-numbered byte, and the most significant byte (msbyte) at the highestnumbered byte. An example of the little-endian format is described in Figure 2-5. Memory 7 Register 0 31 Address Figure 2-5 A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Little-endian format (Example) Reference Manual CPU, V2.1 2-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.4 Instruction Set Table 2-7 lists the supported Cortex-M0 instructions. For more information on the instructions and operands, please refer to the Cortex™-M0 Devices, Generic User Guide available through [1]. Table 2-7 Cortex-M0 instructions Mnemonic Operands Brief description Flags ADCS {Rd,} Rn, Rm Add with carry N,Z,C,V ADD{S} {Rd,} Rn, <Rm|#imm> Add N,Z,C,V ADR Rd, label PC-relative Address to Register - ANDS {Rd,} Rn, Rm Bitwise AND N,Z ASRS {Rd,} Rm, <Rs|#imm> Arithmetic Shift Right N,Z,C B{cc} label Branch {conditionally} - BICS {Rd,} Rn, Rm Bit Clear N,Z BKPT #imm Breakpoint - BL label Branch with Link - BLX Rm Branch indirect with Link - BX Rm Branch indirect - CMN Rn, Rm Compare Negative N,Z,C,V CMP Rn, <Rm|#imm> Compare N,Z,C,V CPSID i Change Processor State, Disable Interrupts - CPSIE i Change Processor State, Enable Interrupts - DMB - Data Memory Barrier - DSB - Data Synchronization Barrier - EORS {Rd,} Rn, Rm Exclusive OR N,Z ISB - Instruction Synchronization Barrier - LDM Rn{!}, reglist Load Multiple registers, increment after - Reference Manual CPU, V2.1 2-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-7 Cortex-M0 instructions (cont’d) Mnemonic Operands Brief description Flags LDR Rt, label Load Register from PCrelative address - LDR Rt, [Rn, <Rm|#imm>] Load Register with word - LDRB Rt, [Rn, <Rm|#imm>] Load Reigster with byte - LDRH Rt, [Rn, <Rm|#imm>] Load Reigster with halfword - LDRSB Rt, [Rn, <Rm|#imm>] Load Reigster with signed byte - LDRSH Rt, [Rn, <Rm|#imm>] Load Reigster with signed halfword - LSLS {Rd,} Rn, <Rs|#imm> Logical Shift Left N,Z,C LSRS {Rd,} Rn, <Rs|#imm> Logical Shift Right N,Z,C MOV{S} Rd, Rm Move N,Z MRS Rd, spec_reg Move to general register from special register MSR spec_reg, Rm Move to special register from general register N,Z,C,V MULS Rd, Rn, Rm Multiply, 32-bit result N,Z MVNS Rd, Rm Bitwise NOT N,Z NOP - No Operation - ORRS {Rd,} Rn, Rm Logical OR N,Z POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - REV Rd, Rm Byte-Reverse word - REV16 Rd, Rm Byte-Reverse packed halfwords - REVSH Rd, Rm Byte-Reverse signed halfword - RORS {Rd,} Rn, Rs Rotate Right N,Z,C RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V Reference Manual CPU, V2.1 2-24 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-7 Cortex-M0 instructions (cont’d) Mnemonic Operands Brief description Flags SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V STM Rn!, reglist Store Multiple registers, increment after - STR Rt, [Rn, <Rm|#imm>] Store Register as word - STRB Rt, [Rn, <Rm|#imm>] Store Register as byte - STRH Rt, [Rn, <Rm|#imm>] Store Register as halfword - SUB{S} {Rd,} Rn, <Rm|#imm> Subtract N,Z,C,V SVC #imm Supervisor Call - SXTB Rd, Rm Sign extend byte - SXTH Rd, Rm Sign extend halfword - TST Rn, Rm Logical AND based test N,Z UXTB Rd, Rm Zero extend a byte - UXTH Rd, Rm Zero extend a halfword - WFE - Wait for Event - WFI - Wait for Interrupt - 2.4.1 Intrinsic Functions ISO/IEC C code cannot directly access some Cortex-M0 instructions. The intrinsic functions that can generate these instructions, provided by the CMSIS and might be provided by a C compiler are described in Section 2.2.7. Reference Manual CPU, V2.1 2-25 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.5 Exception Model This section describes the exception model. It describes: • • • • • • Exception states (Section 2.5.1) Exception types (Section 2.5.2) Exception handlers (Section 2.5.3) Vector table (Section 2.5.4) Exception priorities (Section 2.5.5) Exception entry and return (Section 2.5.6) 2.5.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state. Active and pending Reference Manual CPU, V2.1 The exception is being serviced by the processor and there is a pending exception from the same source. 2-26 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.5.2 Exception Types The exception types are described in Table 2-8. Table 2-8 Exception types Exception Types Descriptions Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts in Thread mode. HardFault A HardFault is an exception that occurs because of an error during normal or exception processing. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. SysTick A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick. Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 Properties of the different exception types Exception Exception IRQ number1) number1) type Priority 1 - Reset -3, the highest 0x00000004 2 - Reserved - - - 3 -13 HardFault -1 0x0000000C Synchronous Reference Manual CPU, V2.1 2-27 Vector address or offset2) Activation Asynchronous V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Table 2-9 Properties of the different exception types (cont’d) Exception IRQ Exception number1) number1) type Priority Vector address or offset2) Activation - - 4-10 - Reserved - 11 -5 SVCall Configurable3) 0x0000002C Synchronous 12-13 - Reserved - - - 3) 14 -2 PendSV Configurable 0x00000038 Asynchronous 15 -1 SysTick Configurable3) 0x0000003C Asynchronous 16 and above 0 and above Interrupt (IRQ) 3) Configurable 0x00000040 and above4) Asynchronous 1) To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register. 2) See Vector table in Section 2.5.4 for more information. 3) See Interrupt Priority Registers in Interrupt System chapter. 4) Increasing in steps of 4. For an asynchronous exception, other than reset, the processor can execute additional instructions between when the exception is triggered and when the processor enters the exception handler. Software can disable the exceptions in Table 2-9 which have configurable priority, see Interrupt Clear-enable Register in Interrupt System chapter. For more information about HardFaults, see Fault handling in Section 2.6. 2.5.3 Exception Handlers The processor handles exceptions using: Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ31 are the exceptions handled by ISRs. Fault handlers HardFault is the only exception handled by the fault handler. System handlers PendSV, SVCall, SysTick, and the HardFault are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 2-6 shows the order of Reference Manual CPU, V2.1 2-28 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is written in Thumb code. Exception number IRQ number 47 31 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x00BC . . . 0x0048 0x0044 0x0040 0x003 C 0x0038 IRQ31 . . . IRQ2 IRQ1 IRQ0 Systick PendSV Reserved 12 11 Vector -5 10 0x002 C SVCall 9 8 7 Reserved 6 5 4 3 -13 2 1 0x0010 0x000 C 0x0004 0x0000 Figure 2-6 Hard fault Reserved Reset Initial SP value Vector table The vector table is fixed at address 0x00000000. 2.5.4.1 Vector Table Remap In XMC1100, the vector table is located inside the ROM. Therefore, the vector table is remapped to the SRAM based on the mapping shown in Table 2-10. The user application uses these locations as entry points for the actual exception and interrupt handlers. This is done by placing the code for these handlers or having the branch instruction to the handlers there. Reference Manual CPU, V2.1 2-29 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) For example, upon an exception entry due to IRQ0, the processor reads the intermediate handler start address 2000’0040H (fixed in ROM) from the vector table and starts execution from there. If the actual handler is located in another address location due to size contraints, the address 2000’0040H should trigger a load and a branch instruction to jump to this new location. Note: The user application needs to reserve the SRAM addresses 2000’000CH 2000’00BFH for the remapped vector table if all vectors are used. Table 2-10 Remapped Vector Table Exception IRQ Number Number Vector Default Vector Address Remapped Vector Address - - Initial SP Value 0000’0000H 1000’1000H 1 - Reset 0000’0004H 1000’1004H1) 3 -13 HardFault 0000’000CH 2000’000CH 11 -5 SVCall 0000’002CH 2000’002CH 14 -2 PendSV 0000’0038H 2000’0038H 15 -1 SysTick 0000’003CH 2000’003CH 16-47 0-31 IRQn (n=0-31) 0000’0040H + (n*4) 2000’0040H + (n*4) 1) The remapped reset vector address refers to the location (start of the Flash memory) that the startup software jumps to upon exiting the startup sequence in user mode. 2.5.5 Exception Priorities Table 2-9 shows that all exceptions have an associated priority, with: • • a lower priority value indicating a higher priority configurable priorities for all exceptions except Reset and HardFault. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities see • • System Handler Priority Registers SHPR2, SHPR3. Interrupt Priority Registers in Interrupt System chapter. Note: Configurable priority values are in the range 0-192, in steps of 64. This means that the Reset and HardFault exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. Reference Manual CPU, V2.1 2-30 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Exception Entry and Return Exception handling can be described using the following terms: Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. When one exception preempts another, the exceptions are called nested exceptions. See Exception entry in Section 2.5.6.1 for more information. Source of figure [4]. Return Reference Manual CPU, V2.1 This occurs when the exception handler is completed, and: • there is no pending exception with sufficient priority to be serviced • the completed exception handler was not handling a latearriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See Exception return in Section 2.5.6.2 for more information. 2-31 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Source of figure [4]. Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. Source of figure [4]. 2.5.6.1 Exception entry Exception entry occurs when there is a pending exception with sufficient priority and either: Reference Manual CPU, V2.1 2-32 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) • • the processor is in Thread mode the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has greater priority than any limits set by the mask register, see Exception mask registers. An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a latearriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred as a stack frame. The stack frame contains the following information, as illustrated in Figure 2-7. Decreasing memory address Figure 2-7 SP + 0x001C SP + 0x0018 SP + 0x0014 SP + 0x0010 SP + 0x000C SP + 0x0008 SP + 0x0004 SP + 0x0000 <previous> xPSR PC LR R12 R3 R2 R1 R0 SP points here before interrupt SP points here after interrupt Exception stack frame Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The stack frame is aligned to a double-word address. The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. The processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. Reference Manual CPU, V2.1 2-33 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. 2.5.6.2 Exception return Exception return occurs when the processor is in Handler mode and execution of one of the following instructions attempts to set the PC to an EXC_RETURN value: • • a POP instruction that loads the PC a BX instruction using any register. The processor saves an EXC_RETURN value to the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. Bits [31:4] of an EXC_RETURN value are set to 1. When this value is loaded into the PC, the processor detects that the exception is complete, and starts the exception return sequence. Bits [3:0] of the EXC_RETURN value indicate the required return stack and processor mode. Table 2-11 shows the EXC_RETURN values with description of the exception return behavior. Table 2-11 Exception return behavior EXC_RETURN[31:0] Description 0xFFFFFFF1 Return to Handler mode. Exception return gets state from the main stack. Execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode. Exception return gets state from MSP. Execution uses MSP after return. 0xFFFFFFFD Return to Thread mode. Exception return gets state from the PSP. Execution uses PSP after return. All other values Reserved. Reference Manual CPU, V2.1 2-34 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.6 Fault Handling Faults are a subset of the exceptions, see Exception model in Section 2.5. All faults result in the HardFault exception being taken or cause lockup if they occur in the HardFault handler. The faults are: • • • • • • • • • execution of an SVC instruction at a priority equal or higher than SVCall execution of a BKPT instruction without a debugger attached a system-generated bus error on a load or store execution of an instruction from an XN memory address execution of an instruction from a location for which the system generates a bus fault a system-generated bus error on a vector fetch execution of an undefined instruction execution of an instruction when not in Thumb-State as a result of the T-bit being previously cleared to 0 an attempted load or store to an unaligned address Note: Only Resetcan preempt the fixed priority HardFault handler. A HardFault can preempt any exception other than Reset, or another hard fault. 2.6.1 Lockup The processor enters a lockup state if a fault occurs when executing the HardFault handlers, or if the system generates a bus error when unstacking the PSR on an exception return using the MSP. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until one of the following occurs: • • it is reset it is halted by a debugger Reference Manual CPU, V2.1 2-35 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.7 Power Management The Cortex-M0 processor sleep modes reduce power consumption: • • Sleep mode Deep sleep mode The SLEEPDEEP bit of the SCR selects which sleep mode is used, see System Control Register SCR. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 2.7.1 Entering Sleep Mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. Wait for interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. Wait for event The wait for event instruction, WFE, causes entry to sleep mode depending on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the value of the event register: 0 1 The processor stops executing instructions and enters sleep mode. The processor clears the register to 0 and continues executing instructions without entering sleep mode. If the event register is 1, this indicate that the processor must not enter sleep mode on execution of a WFE instruction. Typically, this is because an external event is asserted. Software cannot access this register directly. Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler and returns to Thread mode, it immediately enters sleep mode. This mechanism is used in applications that only require the processor to run when an interrupt occurs. Reference Manual CPU, V2.1 2-36 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.7.2 Wakeup from Sleep Mode The conditions for the processor to wakeup depend on the mechanism that caused it to enter sleep mode. Wakeup from WFI or Sleep-on-exit The following events are WFI wake-up events: • • • reset event debug event, if debug is enabled exception at a priority that would preempt any currently active exceptions, if PRIMASK was set to 0 Note: If PRIMASK is set to 1, an interrupt or exception that has a higher priority than the current exception priority will cause the processor to wake up. Interrupt handler is not executed until the processor sets PRIMASK to 0. For more information about PRIMASK, see Exception mask registers. Wakeup from WFE The following events are WFE wake-up events: • • • • reset event exception or interrupt with sufficient priority to cause exception entry exception or interrupt entering pending state, if SEVONPEND is set to 1 (See SCR) debug event, if debug is enabled Note: Wakeup by Event Register (see The Event Register in ARMv6-M Architecture Reference Manual [2]) is not possible in XMC1100. Nevertheless, SEV instruction will set the event register. 2.7.3 Power Management Programming Hints ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for these instructions: void __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt Reference Manual CPU, V2.1 2-37 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.8 Private Peripherals The following sections are the reference material for the ARM Cortex-M0 core peripherals. 2.8.1 About the Private Peripherals The address map of the Private Peripheral Bus (PPB) is: Table 2-12 Core peripheral register regions Address Core peripheral Description 0xE000E008- System Control Block 0xE000E00F See Section 2.8.2 and Section 2.9.1 0xE000E010- System timer 0xE000E01F See Section 2.8.3 and Section 2.9.2 0xE000E100- Nested Vectored Interrupt 0xE000E4EF Controller See Interrupt System chapter 0xE000ED00- System Control Block 0xE000ED3F See Section 2.8.2 and Section 2.9.1 0xE000EF00- Nested Vectored Interrupt 0xE000EF03 Controller See Interrupt System chapter 2.8.2 System control block The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. 2.8.2.1 System control block usage hints and tips Ensure software uses aligned 32-bit word size transactions to access all the system control block registers. 2.8.3 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads, that is wraps to, the value in the SYST_RVR register on the next clock cycle, then counts down on subsequent clock cycles. Note: When the processor is halted for debugging the counter does not decrement. Reference Manual CPU, V2.1 2-38 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.8.3.1 SysTick usage hints and tips The interrupt controller clock updates the SysTick count. When processor clock is selected and the clock signal is stopped for low power mode, the SysTick counter stops. When external clock is selected, the clock continues to run in low power mode and SysTick can be used as a wakeup source. Ensure software uses aligned word accesses to access the SysTick registers. If the SysTick counter reload and current value are undefined at reset, the correct initialization sequence for the SysTick counter is: 1. Program reload value. 2. Clear current value. 3. Program Control and Status register. Reference Manual CPU, V2.1 2-39 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.9 PPB Registers The CPU private peripherals registers base address is E000E000H. Table 2-13 Register Overview Short Name Description Offset Access Mode Description Address Read Write See System Control Space (SCS) CPUID CPUID Base Register D00H PV, 32 PV, 32 Page 2-41 ICSR Interrupt Control and State Register D04H PV, 32 PV, 32 Page 2-42 AIRCR Application Interrupt and Reset Control Register D0CH PV, 32 PV, 32 Page 2-45 SCR System Control Register D10H PV, 32 PV, 32 Page 2-46 CCR Configuration and Control Register D14H PV, 32 PV, 32 Page 2-48 SHPR2 System Handler Priority D1CH Register 2 PV, 32 PV, 32 Page 2-49 SHPR3 System Handler Priority D20H Register 3 PV, 32 PV, 32 Page 2-50 SHCSR System Handler Control D24H and State Register PV, 32 PV, 32 Page 2-51 System Timer (SysTick) SYST_CSR SysTick Control and Status Register 010H PV, 32 PV, 32 Page 2-52 SYST_RVR SysTick Reload Value Register 014H PV, 32 PV, 32 Page 2-54 SYST_CVR SysTick Current Value Register 018H PV, 32 PV, 32 Page 2-55 SYST_CALIB SysTick Calibration Value Register 01CH PV, 32 - Page 2-56 Reference Manual CPU, V2.1 2-40 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.9.1 SCS Registers CPUID The CPUID register contains the processor part number, version, and implementation information. CPUID CPUID Base Register 31 15 30 14 29 28 (E000ED00H) 27 26 25 24 23 Reset Value: 410CC200H 22 21 20 19 18 17 Implementer Variant Architecture r r r 13 12 11 10 9 8 7 6 5 4 2 1 PartNo Revision r r Field Bits Type Description Revision [3:0] r Revision Number 0H Patch 0 PartNo [15:4] r Part Number of the Processor C20H Cortex-M0 Architecture [19:16] r Architecture CH ARMv6-M Variant [23:20] r Variant Number 0H Revision 0 Implementer [31:24] r Implementer Code 41H ARM Reference Manual CPU, V2.1 3 2-41 16 0 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) ICSR The ICSR: • • provides: – set-pending and clear-pending bits for the PendSV and SysTick exceptions indicates: – the exception number of the exception being processed – whether there are preempted active exceptions – the exception number of the highest priority pending exception – whether any interrupts are pending. ICSR Interrupt Control and State Register (E000ED04H) 31 30 29 0 r 15 28 27 26 25 24 PEN PEN PEN PEN DSV DSV DST DST SET CLR SET CLR rw w rw w 14 13 12 11 10 23 r 8 22 21 20 ISRP ENDI NG r 0 9 Reset Value: 00000000H 7 6 5 4 19 18 17 0 VECTPEN DING r r 3 2 1 VECTPENDING 0 VECTACTIVE r r r Field Bits Type Description VECTACTIVE1) [5:0] r 16 0 Active Exception Number 00H Thread mode Non-zero value The exception number of the currently active exception. Note: Subtract 16 from this value to obtain the CMSIS IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see Interrupt Program Status Register. 0 Reference Manual CPU, V2.1 [11:6] r Reserved Read as 0; should be written with 0. 2-42 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description VECTPENDING [17:12] r Pending Exception Number Indicates the exception number of the highest priority pending enabled exception. No pending exceptions 0H Non-zero value: The exception number of the highest priority pending enabled exception. 0 [21:18] r Reserved Read as 0; should be written with 0. ISRPENDING 22 Interrupt Pending Flag This bit sets the interrupt pending flag, excluding faults. Interrupt not pending 0B Interrupt pending. 1B 0 [24:23] r Reserved Read as 0; should be written with 0. PENDSTCLR 25 w SysTick Exception Clear-pending No effect 0B 1B removes the pending state from the SysTick exception. This bit is write-only. On a register read, this value is unknown. PENDSTSET 26 rw SysTick Exception Set-pending 0D SysTick exception is not pending 1D SysTick exception is pending. A write of 0 to the bit has no effect. PENDSVCLR 27 w PendSV Clear Pending This bit clears a pending PendSV exception. Do not clear. 0B 1B Removes pending state from PendSV exception. PENDSVSET 28 rw PendSV Set Pending This bit sets a pending PendSV exception or reads back the current state. PendSV exception is not pending. 0B 1B PendSV excepton is pending. r Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending. A software write of 0 to the bit has no effect. Reference Manual CPU, V2.1 2-43 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits 0 [31:29] r Type Description Reserved Read as 0; should be written with 0. 1) This is the same value as IPSR bits[5:0], see Interrupt Program Status Register. Note: The result is unpredictable if: 1. Both PENDSVSET and PENDSVCLR bits are set to 1. 2. Both PENDSTSET and PENDSTCLR bits are set to 1. Reference Manual CPU, V2.1 2-44 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) AIRCR The AIRCR register provides endian status for data accesses and reset control of the system. To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. AIRCR Application Interrupt and Reset Control Register (E000ED0CH) 31 30 29 28 27 26 25 24 23 Reset Value: FA050000H 22 21 20 19 6 5 4 3 18 17 16 2 1 0 0 0 w r VECTKEY rw 15 14 13 12 11 10 9 8 ENDI ANN ESS 0 r r 7 SYS RES ETR EQ w Field Bits Type Description 0 0 r Reserved Read as 0; should be written with 0. 0 1 w Reserved Must be written with 0. SYSRESETREQ 2 w System Reset Request 0B No effect. Requests a system level reset. 1B This bit is read as 0. 0 [14:3] r Reserved Read as 0; should be written with 0. ENDIANNESS 15 r Data Endianness 0B Little-endian VECTKEY [31:16] rw Reference Manual CPU, V2.1 Register Key Reads as unknown. On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. 2-45 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) SCR The SCR controls features of entry to and exit from low power state. SCR System Control Register 31 30 29 28 (E000ED10H) 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 SEV ONP END 0 r rw r SLE SLE EPO EPD NEXI EEP T rw rw 0 r Field Bits Type Description 0 0 r Reserved Read as 0; should be written with 0. SLEEPONEXIT 1 rw Sleep-on-exit This bit indicates sleep-on-exit when returning from Handler mode to Thread mode. 0B Do not sleep when returning to Thread mode. 1B Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. SLEEPDEEP 2 rw Low Power Sleep Mode This bit controls whether the processor uses sleep or deep sleep as its low power mode. Sleep 0B Deep sleep 1B 0 3 r Reserved Read as 0; should be written with 0. Reference Manual CPU, V2.1 2-46 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description SEVONPEND 4 rw Send Event on Pending bit 0B Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. Enabled events and all interrupts, including 1B disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. 0 [31:5] r Reserved Read as 0; should be written with 0. Reference Manual CPU, V2.1 2-47 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) CCR The CCR is a read-only register and it indicates some aspects of the behavior of the Cortex-M0 processor. CCR Configuration and Control Register (E000ED14H) 31 30 29 28 27 26 25 24 Reset Value: 00000208H 23 22 21 20 7 6 5 4 19 18 17 16 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 STK ALIG N 0 r r r UNA LIGN _TR P r 0 r Field Bits Type Description 0 [2:0] r Reserved Read as 0; should be written with 0. UNALIGN_TRP 3 r Unaligned Access Traps This bit always reads as 1, indicates that all unaligned accesses generate a HardFault. 0 [8:4] r Reserved Read as 0; should be written with 0. STKALIGN 9 r Stack Alignment This bit always reads as 1, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 0 [31:10] r Reference Manual CPU, V2.1 Reserved Read as 0; should be written with 0. 2-48 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) System Handler Priority Registers The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the exception handlers that have configurable priority. SHPR2-SHPR3 are word accessible. To access to the system exception priority level using CMSIS, the following CMSIS functions are used: • • uint32_t NVIC_GetPriority(IRQn_Type IRQn) void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) The system fault handlers, the priority field and register for each handler are: Table 2-14 System fault handler priority fields Handler Field Register description SVCall PRI_11 System Handler Priority Register 2 on Page 2-49 PendSV PRI_14 System Handler Priority Register 3 on Page 2-50 SysTick PRI_15 Each PRI_N field is 8 bits wide, but the XMC1100 implements only bits [7:6] of each field, and bits [5:0] read as zero and ignore writes. SHPR2 The SHPR2 register sets the priority level for the SVCall handler. SHPR2 System Handler Priority Register 2 (E000ED1CH) 31 15 30 14 29 13 28 27 26 25 24 23 Reset Value: 00000000H 22 21 20 PRI_11 0 rw r 12 11 10 9 8 7 6 5 4 19 18 17 16 3 2 1 0 0 r Reference Manual CPU, V2.1 2-49 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description 0 [23:0] r PRI_11 [31:24] rw Reserved Read as 0; should be written with 0. Priority of System Handler 11 SVCall. SHPR3 The SHPR3 register sets the priority level for the PendSV and SysTick handlers. SHPR3 System Handler Priority Register 3 (E000ED20H) 31 15 30 14 29 13 28 27 26 25 24 23 Reset Value: 00000000H 22 21 20 19 PRI_15 PRI_14 rw rw 12 11 10 9 8 7 6 5 4 3 18 17 16 2 1 0 0 r Field Bits Type Description 0 [15:0] r PRI_14 [23:16] rw Priority of System Handler 14 PendSV. PRI_15 [31:24] rw Priority of System Handler 15 SysTick exception. Reference Manual CPU, V2.1 Reserved Read as 0; should be written with 0. 2-50 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) SHCSR The SHCSR register controls and provides the status of system handlers. SHCSR System Handler Control and State Register (E000ED24H) 31 30 29 28 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 SVC ALL PEN DED rw 0 r Field Bits Type Description 0 [14:0] r Reserved Read as 0; should be written with 0. rw SVCall Pending bit This bit reflects the pending state on a read, and updates the pending state, to the value written, on a write. SVCall is not pending. 0B 1B SVCall is pending1). SVCALLPENDE 15 D 0 [31:16] r Reserved Read as 0; should be written with 0. 1) Pending state bits are set to 1 when an exception occurs, and are cleared to 0 when an exception becomes active. Reference Manual CPU, V2.1 2-51 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) 2.9.2 SysTick Registers SYST_CSR The SYST_CSR register enables the SysTick features. Reading SYST_CSR clears the COUNTFLAG bit to 0. SYST_CSR SysTick Control and Status Register (E000E010H) 31 30 29 28 27 26 25 24 23 Reset Value: 00000000H 22 21 20 19 18 17 0 r 15 14 13 12 11 10 9 16 COU NTF LAG rw 8 7 6 5 4 3 2 1 0 CLK TICK ENA SOU INT BLE RCE rw rw rw 0 r Field Bits Type Description ENABLE 0 rw Counter Enable This bit enables the counter. Counter disabled. 0B 1B Counter enabled. TICKINT 1 rw SysTick Exception Request This bit enables the SysTick exception request. 0B Counting down to zero does not assert the SysTick exception request. Counting down to zero to assert the SysTick 1B exception request. In software, COUNTFLAG bit can be used to determine if SysTick has counted to zero. CLKSOURCE 2 rw Clock Source This bit selects the SysTick timer clock source. 0B External clock1). Processor clock. 1B Reference Manual CPU, V2.1 2-52 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) Field Bits Type Description 0 [15:3] r Reserved Read as 0; should be written with 0. COUNTFLAG 16 rw Counter Flag This bit returns 1 if timer counted to 0 since the last read of this register. 0 [31:17] r Reserved Read as 0; should be written with 0. 1) In XMC1100, the external clock refers to the on-chip 32 kHz standby clock. When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting. Reference Manual CPU, V2.1 2-53 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) SYST_RVR The SYST_RVR register specifies the start value to load into the SYST_CVR register. SYST_RVR SysTick Reload Value Register 31 15 30 14 29 13 28 27 26 (E000E014H) 25 24 23 Reset Value: XXXXXXXXH 22 21 20 19 0 RELOAD r rw 12 11 10 9 8 7 6 5 4 3 18 17 16 2 1 0 RELOAD rw Field Bits Type Description RELOAD [23:0] rw 0 [31:24] r Reload Value This field sets the value to load into the SYST_CVR register when the counter is enabled and when it reaches 0. Reserved Read as 0; should be written with 0. Notes on calculating the RELOAD value 1. The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but this has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. 2. The RELOAD value is calculated according to its use. For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. Reference Manual CPU, V2.1 2-54 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) SYST_CVR The SYST_CVR register contains the current value of the SysTick counter. Writing to the SYST_CVR clears the register and the COUNTFLAG status bit to 0. The write does not trigger the SysTick exception logic. Reading the register returns its value at the time it is accessed. SYST_CVR SysTick Current Value Register 31 15 30 14 29 13 28 27 26 (E000E018H) 25 24 23 Reset Value: XXXXXXXXH 22 21 20 19 0 CURRENT r rw 12 11 10 9 8 7 6 5 4 3 18 17 16 2 1 0 CURRENT rw Field Bits Type Description CURRENT [23:0] rw 0 [31:24] r Reference Manual CPU, V2.1 SysTick Counter Current Value When read, it returns the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0. Reserved Read as 0; should be written with 0. 2-55 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Central Processing Unit (CPU) SYST_CALIB The SYST_CALIB register indicates the SysTick calibration properties. SYST_CALIB SysTick Calibration Value Register(E000E01CH) 31 30 29 28 27 NOR SKE EF W r r 15 14 13 12 26 25 24 23 Reset Value: 40000147H 22 21 20 19 0 TENMS r r 11 10 9 8 7 6 5 4 3 18 17 16 2 1 0 TENMS r Field Bits Type Description TENMS [23:0] r 0 [29:24] r Reserved Read as 0; should be written with 0. SKEW 30 r Clock Skew This bit is read as 1. It indicates that 10ms calibration value is inexact, because of the clock frequency. NOREF 31 r Reference Clock This bit is read as 0. It indicates that external reference clock is provided. Reference Manual CPU, V2.1 10 Milliseconds The reload value for 10ms timing is subject to system clock skew errors. The default value of TENMS is 0x000147. 2-56 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Bus System 3 Bus System The single master bus system in XMC1100 consists of a high-performance system bus based on the industry AMBA 3 AHB-Lite Protocol standard for memories and highbandwidth on-chip peripherals and a narrower APB for low-bandwidth on-chip peripherals. 3.1 Bus Interfaces This chapter describes the features for the two kinds of interfaces. • • Memory Interface Peripheral Interface All on-chip modules implement Little Endian data organization. Memory Interface The on-chip memories are capable to accept a transfer request with each bus clock cycle. The memory interface data bus width is 32-bit. Flash memory supports only 32-bit accesses while SRAM allows 32-bit, 16-bit and 8-bit write accesses. Read accesses to SRAM is always 32-bit wide. Peripheral Interface Each slave on the AHB-Lite supports 32-bit accesses. Additionally: • USIC0 supports 8-bit and 16-bit accesses Each slave on the APB supports only 16-bit accesses. Note: Unaligned memory accesses to memory or peripheral slaves result in a HardFault exception. Reference Manual Bus System, V1.0 3-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Service Request Processing 4 Service Request Processing A hardware pulse is called Service Request (SR) in an XMC1100 system. Service Requests are the fastest way to send trigger “messages” between connected on-chip resources. An SR can generate any of the following requests • • Interrupt Peripheral action This chapter describes the available Service Requests and the different ways to select and process them. Table 4-1 Abbreviations ERU Event Request Unit NVIC Nested Vectored Interrupt Controller SR Service Request 4.1 Overview Efficient Service Request Processing is based on the interconnect between the request sources and the request processing units. XMC1100 provides both fixed and programmable interconnect. 4.1.1 Features The following features are provided for Service Request processing: • Connectivity matrix between Service Requests and request processing units – Fixed connections – Programmable connections using ERU 4.1.2 Block Diagram Figure 4-1 shows a representation of the interaction between the request sources and the request processing units. Reference Manual Service Request Processing, V1.0 4-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Service Request Processing On-Chip Unit Outputs PORTS Interconnections ERU NVIC On-Chip Unit Inputs PORTS Req CPU Core CPU Figure 4-1 Block Diagram on Service Request Processing Reference Manual Service Request Processing, V1.0 4-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Service Request Processing 4.2 Service Request Distribution Figure 4-2 shows an example of how a service request can be distributed concurrently. To support the concurrent distribution to multiple receivers, the receiving modules are capable to enable/disable incoming requests. NVIC (Interrupt ) VADC0.<input _x> CCU4.SR3 ERU0.<input _x> Figure 4-2 Example for Service Request Distribution The units involved in Service Request distribution can be subdivided into • • Embedded real time services Interrupt services Embedded real time services Connectivity between On-Chip Units and PORTS is real time application and also chip package dependant. Related connectivity and availability of pins can be looked up in the • • • “Interconnects” Section of the respective module(s) chapters “Parallel Ports” chapter and Data Sheet for PORTS “Event Request Unit” chapter Interrupt services The following table gives an overview on the number of service requests per module and how the service requests are assigned to NVIC Interrupt service provider. Service Requests are always of of type “Pulse” in XMC1100. Reference Manual Service Request Processing, V1.0 4-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Service Request Processing Table 4-2 Interrupt services per module Modules Request Sources NVIC Type VADC 4 2 Pulse CCU40 4 4 Pulse USIC0 6 6 Pulse SCU 2 2 Pulse ERU0 4 4 Pulse Total 20 18 - Reference Manual Service Request Processing, V1.0 4-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 5 Interrupt Subsystem The interrupt Subsystem in XMC1100 consists of the Nested Vectored Interrupt Controller (NVIC) and the respective modules’ interrupt generation blocks. Note: The CPU exception model is described in the CPU chapter. 5.1 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex M0 processor unit. Due to a tight coupling with the CPU, it provides the lowest interrupt latency and efficient processing of late arriving interrupts. 5.1.1 Features The NVIC supports the following features: • • • • 32 interrupt nodes 4 programmable priority levels for each interrupt node Support for interrupt tail-chaining and late-arrival Software interrupt generation 5.1.2 Interrupt Node Assignment Table 5-1 lists the service request sources per peripheral and their assignment to NVIC interrupt nodes. For calculation of the vector routine address, please refer to the section on Vector Table in the CPU chapter. Table 5-1 Interrupt Node assignment Service Request Node ID Description SCU.SR0 SCU.SR2 System Control SR0 is the system critical request SR1 is the common SCU request 0...1 NC 2 Reserved ERU0.SR0 ERU0.SR3 3...6 External Request Unit 0 NC 7...8 Reserved USIC0.SR0 USIC0.SR5 9...14 Universal Serial Interface Channel (Module 0) VADC0.C0SR0 VADC0.C0SR1 15...16 Analog to Digital Converter (Common) NC 17...20 Reserved Reference Manual NVIC, V1.9 5-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem Table 5-1 Interrupt Node assignment (cont’d) Service Request Node ID Description CCU40.SR0 CCU40.SR3 21...24 Capture Compare Unit 4 (Module 0) NC 25...31 Reserved 5.1.3 Interrupt Signal Generation In XMC1100, all peripherals support only the generation of pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock (MCLK). To ensure the NVIC detects the interrupt, the peripheral asserts the interrupt signal for at least one MCLK clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see Hardware and software control of interrupts. The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. Hardware and software control of interrupts The Cortex-M0 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: • • • the NVIC detects that the interrupt signal is active and the interrupt is not active the NVIC detects a rising edge on the interrupt signal software writes to the corresponding interrupt set-pending register bit, see Interrupt Set-pending Register NVIC_ISPR. A pending interrupt remains pending until one of the following: • • The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then: – The NVIC continues to monitor the interrupt signal, and If this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, the state of the interrupt changes to inactive when the processor returns from the ISR. Software writes to the corresponding interrupt clear-pending register bit. – The state of the interrupt changes to inactive, if the state was pending; or active, if the state was active and pending. Reference Manual NVIC, V1.9 5-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 5.1.4 NVIC design hints and tips An interrupt node can enter pending state even if it is disabled. Disabling an interrupt node only prevents the processor from taking interrupts from that node. NVIC programming hints Software uses the CPSIE i and CPSID i instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 5-2 CMSIS functions for NVIC control CMSIS interrupt control function Description void NVIC_EnableIRQ (IRQn_t IRQn) Enable IRQn void NVIC_DisableIRQ (IRQn_t IRQn) Disable IRQn uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true (1) if IRQn is pending void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void) Reset the system The input parameter IRQn is the IRQ number. For more information about these functions, please refer to the CMSIS documentation. 5.1.5 Accessing CPU Registers using CMSIS CMSIS functions enable software portability between different Cortex-M profile processors. To access the NVIC registers when using CMSIS, use the following functions: Table 5-3 CMSIS access NVIC functions CMSIS function Description void NVIC_EnableIRQ (IRQn_Type IRQn) 1) void NVIC_DisableIRQ (IRQn_Type IRQn) Reference Manual NVIC, V1.9 1) 5-3 Enables an interrupt or exception. Disables an interrupt or exception. V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem Table 5-3 CMSIS access NVIC functions (cont’d) CMSIS function Description void NVIC_SetPendingIRQ (IRQn_Type IRQn)1) Sets the pending status of interrupt or exception to 1. void NVIC_ClearPendingIRQ (IRQn_Type IRQn)1) Clears the pending status of interrupt or exception to 0. uint32_t NVIC_GetPendingIRQ (IRQn_Type Reads the pending status of interrupt or exception. IRQn)1) This function returns non-zero value if the pending status is set to 1. void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)1) Sets the priority of an interrupt or exception with configurable priority level to 1. uint32_t NVIC_GetPriority(IRQn_Type IRQn)1) Reads the priority of an interrupt or exception with configurable priority level. This function return the current priority level. 1) The input parameter IRQn is the IRQ number. 5.1.6 Interrupt Priority An interrupt node can be assigned one of four priority levels. The levels are in steps of 64, from 0 to 192, and defined in an 8-bit priority field in the Interrupt Priority Register x (IPRx). A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. Since there are four priority fields in each IPRx register and each field corresponds to one interrupt node, altogether 8 IPRx registers (IPR0...IPR7) are needed as shown in Figure 5-1. Reference Manual NVIC, V1.9 5-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 31 16 15 PRI_3 (node 4n+3) PRI_2 (node 4n+2) PRI_3 (node 3) PRI_2 (node 2) IPR0 Figure 5-1 0 PRI_0 (node 28) PRI_1 (node 4n+1) PRI_0 (node 4n) PRI_1 (node 1) PRI_0 (node 0) ... ... IPRn 8 7 PRI_1 (node 29) ... PRI_2 (node 30) ... IPR7 24 23 PRI_3 (node 31) Interrupt Priority Register The IPR number and byte offset for interrupt node m (0...31) can be found as follows: • • • the corresponding IPR number n is given by n = m DIV 4 the byte offset of the required Priority field in this register is m MOD 4, where: – byte offset 0 refers to register bits [7:0] – byte offset 1 refers to register bits [15:8] – byte offset 2 refers to register bits [23:16] – byte offset 3 refers to register bits [31:24] for example, Priority field of interrupt node 21 is located at IPR5.[15:8], since – n = 21 DIV 4 = 5 – byte offset = 21 MOD 4 = 1 Note: IPRx registers are only word-accessible. Refer to Table 5-2 for more information on the access to the interrupt node priority array, which provides the software view of the interrupt node priorities. 5.1.7 Interrupt Latency The XMC1100 interrupt latency, defined as the time from detection of the generated pulse and latching of the interrupt by NVIC to execution of the first instruction at the interrupt handler, is typically 21 MCLK cycles as shown in Figure 5-2. Reference Manual NVIC, V1.9 5-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 1 2 15 16 17 18 19 20 21 MCLK Interrupt becomes Active in NVIC 16-cycle latency due to core LDR BX (Instructions in the remapped vector table ) 1st instruction at remapped interrupt vector Overall interrupt latency= 21 MCLK cycles Figure 5-2 Typical XMC1100 Interrupt Latency This assumes the following conditions: • • • Interrupt generation is enabled No occurrence of interrupt pre-emption, late-arrival or tail-chaining Delays due to memory wait states are not taken into account 5.2 General Module Interrupt Structure A module might have multiple interrupt sources. Each interrupt source has typically the following structure (see Figure 5-3): • • • • An interrupt source status flag A set bit to allow software to set the flag to 1 A clear bit to allow software to reset the flag to 0 An enable bit to trigger interrupt when the hardware event occurs or status flag set bit is set (i.e. software triggered interrupt) Note: If a flag set event (due to a peripheral HW event) occurs in the same clock cycle as a flag clear event (due to SW Setting of the Clear bit), the set has higher priority over the clear. Note: Setting of the status flag by a hardware event or software writing to status flag set bit, is independent of interrupt generation enabled/disabled. Similarly, interrupt generation is independent of the level of the status flag. Additionally, some modules might have more interrupt sources than interrupt lines. Therefore, they include an interrupt routing management block, which maps the interrupt sources to the interrupt lines. For further details and exceptions to the above general structure, refer to the respective module chapters. An overview of all XMC1100 interrupt sources is given at the end of the chapter. Reference Manual NVIC, V1.9 5-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem Enable bit HW event X Service Request Output to NVIC OR Set Clear bit Clear Status flag Set N trigger sources Interrupt Routing Management block M Outputs Set bit Figure 5-3 Typical Module Interrupt Structure To enable a module HW event for interrupt generation, SW has to: • • • Enable the interrupt node that is allocated to the module in the NVIC, through the NVIC_ISER register. If the module has an interrupt routing management block, select an available service request output through which the interrupt will be generated to the NVIC. This is usually done by configuring a interrupt node pointer register in the module. Finally, set the interrupt enable bit of the module HW event for interrupt generation. Reference Manual NVIC, V1.9 5-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 5.3 Registers Table 5-4 Registers Address Space Module Base Address End Address CPU PPB: System Control Space (SCS) E000E000H E000EFFFH Note Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 5-5 Register Overview Short Name Description Offset Access Mode Description Address Read Write See Nested Vectored Interrupt Controller (NVIC) NVIC_ISER Interrupt Set-enable Registers 100H U, PV U, PV Page 5-9 NVIC_ICER Interrupt Clear-enable Registers 180H U, PV U, PV Page 5-10 NVIC_ISPR Interrupt Set-pending Registers 200H U, PV U, PV Page 5-11 NVIC_ICPR Interrupt Clear-pending 280H Registers U, PV U, PV Page 5-12 NVIC_IPR0 NVIC_IPR7 Interrupt Priority Registers U, PV U, PV Page 5-13 Reference Manual NVIC, V1.9 400H41CH 5-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem 5.3.1 NVIC Registers NVIC_ISER The ISER register enables interrupt nodes, and shows which interrupt nodes are enabled. NVIC_ISER Interrupt Set-enable Register 31 30 29 28 27 26 (E000E100H) 25 24 23 Reset Value: 00000000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SETENA rw 15 14 13 12 11 10 9 8 7 SETENA rw Field Bits Type Description SETENA [31:0] rw Interrupt Node Set-enable 0B Read: Interrupt node disabled. Write: No effect. Read: Interrupt node enabled. 1B Write: Enable interrupt node If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Reference Manual NVIC, V1.9 5-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem NVIC_ICER The ICER register disables interrupt nodes, and shows which interrupt nodes are enabled. NVIC_ICER IInterrupt Clear-enable Register 31 30 29 28 27 26 (E000E180H) 25 24 23 Reset Value: 00000000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLRENA rw 15 14 13 12 11 10 9 8 7 CLRENA rw Field Bits Type Description CLRENA [31:0] rw Reference Manual NVIC, V1.9 Interrupt Node Clear-enable 0B Read: Interrupt node disabled. Write: No effect Read: Interrupt node enabled. 1B Write: Disable interrupt node. 5-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem NVIC_ISPR The ISPR register forces interrupt nodes into the pending state, and shows which interrupt nodes are pending. NVIC_ISPR Interrupt Set-pending Register (E000E200H) 31 30 29 28 27 26 25 24 23 Reset Value: 00000000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SETPEND rw 15 14 13 12 11 10 9 8 7 SETPEND rw Field Bits Type Description SETPEND [31:0] rw Interrupt Node Set-pending 0B Read: Interrupt node is not pending. Write: No effect Read: Interrupt node is pending. 1B Write: Change interrupt state to pending. Note: Writing 1 to the ISPR bit corresponding to: - an interrupt node that is pending has no effect - a disabled interrupt node sets the state of that interrupt node to pending Reference Manual NVIC, V1.9 5-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem NVIC_ICPR The ICPR register removes the pending state from interrupt nodes, and shows which interrupt nodes are pending. NVIC_ICPR Interrupt Clear-pending Register (E000E280H) 31 30 29 28 27 26 25 24 23 Reset Value: 00000000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLRPEND rw 15 14 13 12 11 10 9 8 7 CLRPEND rw Field Bits Type Description CLRPEND [31:0] rw Interrupt Node Clear-pending 0B Read: Interrupt node is not pending. Write: No effect. Read: Interrupt node is pending. 1B Write: Remove interrupt state from pending. Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt node. Reference Manual NVIC, V1.9 5-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Interrupt Subsystem NVIC_IPRx (x=0-7) The IPR0-IPR7 registers provide a 8-bit priority field for each interrupt node. Each register holds four priority fields. Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt node. The processor implements only bits [7:6] of each field, bits [5:0] reads as 0 and ignores writes. This means writing 255 to a priority register saves value 192 to the register. NVIC_IPRx (x=0-7) Interrupt Priority Register x (E000E400H + 4*x) 31 15 30 14 29 13 28 27 26 25 24 23 22 Reset Value: 00000000H 21 19 PRI_3 PRI_2 rw rw 12 11 10 9 8 7 6 5 4 3 PRI_1 PRI_0 rw rw Field Bits PRI_3 [31:24] rw Priority, Byte Offset 3 PRI_2 [23:16] rw Priority, Byte Offset 2 PRI_1 [15:8] rw Priority, Byte Offset 1 PRI_0 [7:0] rw Priority, Byte Offset 0 5.4 20 18 17 16 2 1 0 Type Description Interrupt Request Source Overview An overview of all XMC1100 interrupt sources and related register bits are shown in the next few pages. Reference Manual NVIC, V1.9 5-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information 0 SCU.SR0 Reference Manual NVIC, V1.9 SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW SRAM parity error USIC RAM parity error Loss of clock LOCI PEU0I PESRAMI FLCMPLTI ECC2REA D NVM_NVM STATUS SCU_ SRRAW FLECC2I SCU_ SRRAW Flash operation complete Flash double bit ECC1) SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK NVM_ NVMCONF - SCU_ SRMSK Register LOCI PEU0I PESRAMI INT_ON - FLECC2I Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET - SCU_ SRSET Register Set Flag LOCI PEU0I PESRAMI FLCMPLTI - FLECC2I Bit SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR NVM_NVM PROG SCU_ SRCLR Register Clear Flag LOCI PEU0I PESRAMI FLCMPLTI RSTECC FLECC2I Bit - - - - - - Register - - - - - - Bit Node Pointer XMC1100 AB-Step XMC1000 Family 5-14 Subject to Agreement on the Use of Product Information V1.2, 2014-11 Reference Manual NVIC, V1.9 5-15 Reserved ERU0. SR[3:0] 3, 4, 5, 6 SCU.SR1 2 1 SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW VDDC drops below VDROP VDDC rises above VCLIP TSE done TSE compare high TSE compare low SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW SCU_ SRRAW RTC CTR Mirror Register updated RTC ATIM0 Mirror Register updated RTC ATIM1 Mirror Register updated RTC TIM0 Mirror Register updated ERU0_IOUTx (x=0-3) RTC_TIM1 RTC_TIM0 RTC_ ATIM1 RTC_ ATIM0 RTC_CTR AI PI PRWARN TSE_LOW TSE_HIGH TSE_ DONE VCLIPI VDROPI VDDPI SBYCLKFI SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK - - SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK SCU_ SRMSK See section on ERU0 for details. SCU_ SRRAW SCU_ SRRAW RTC alarm RTC TIM1 Mirror Register updated SCU_ SRRAW RTC periodic event SCU_ SRRAW SCU_ SRRAW VDDP prewarning WDT pre-warning SCU_ SRRAW Standby clock failure Register RTC_TIM1 RTC_TIM0 RTC_ ATIM1 RTC_ ATIM0 RTC_CTR - - PRWARN TSE_LOW TSE_HIGH TSE_ DONE VCLIPI VDROPI VDDPI SBYCLKFI Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET SCU_ SRSET Register Set Flag RTC_TIM1 RTC_TIM0 RTC_ ATIM1 RTC_ ATIM0 RTC_CTR AI PI PRWARN TSE_LOW TSE_HIGH TSE_ DONE VCLIPI VDROPI VDDPI SBYCLKFI Bit SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR SCU_ SRCLR Register Clear Flag RTC_TIM1 RTC_TIM0 RTC_ ATIM1 RTC_ ATIM0 RTC_CTR AI PI PRWARN TSE_LOW TSE_HIGH TSE_ DONE VCLIPI VDROPI VDDPI SBYCLKFI Bit - - - - - - - - - - - - - - - Register - - - - - - - - - - - - - - - Bit Node Pointer XMC1100 AB-Step XMC1000 Family Subject to Agreement on the Use of Product Information V1.2, 2014-11 Reserved USIC0_S R[5:0] 7, 8 9, 10, 11, 12, 13, 14 USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC: Standard receive event USIC: Receive start event Reference Manual NVIC, V1.9 USIC: Alternate receive event USIC: Transmit shift event USIC: Transmit buffer event USIC: Data lost event USIC: BRG event BRGIF DLIF TBIF TSIF AIF RSIF RIF USIC0_ CCR USIC0_ CCR USIC0_ CCR USIC0_ CCR USIC0_ CCR USIC0_ CCR USIC0_ CCR Register BRGIEN DLIEN TBIEN TSIEN AIEN RSIEN RIEN Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 - - - - - - - Register Set Flag - - - - - - - Bit USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR Register Clear Flag CBRGIF CDLIF CTBIF CTSIF CAIF CRSIF CRIF Bit USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR Register PINP PINP TBINP TSINP AINP TBINP RINP Bit Node Pointer XMC1100 AB-Step XMC1000 Family 5-16 Subject to Agreement on the Use of Product Information V1.2, 2014-11 9, 10, 11, 12, 13, 14 USIC0_S R[5:0] Reference Manual NVIC, V1.9 5-17 USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR ASC: Receiver noise detected ASC: Format error in stop bit 0 ASC: Format error in stop bit 1 ASC: Receive frame finished ASC: Transmit frame finished USIC0_ TRBSR USIC: Alternate receive buffer event ASC: Collision detected USIC0_ TRBSR USIC: Standard receive buffer event USIC0_ PSR USIC0_ TRBSR USIC: Standard receive buffer event ASC: Synchronisation break detected USIC0_ TRBSR USIC: Transmit Buffer error event USIC0_ TRBSR USIC0_ TRBSR USIC: Standard transmit buffer event USIC: Receive buffer error event USIC0_ TRBSR USIC: Standard transmit buffer event TFF RFF FER1 FER0 RNS COL SBD RBERI USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ RBCTR USIC0_ RBCTR USIC0_ RBCTR SRBT ARBI USIC0_ RBCTR USIC0_ TBCTR USIC0_ TBCTR SRBI TBERI STBT STBI USIC0_ TBCTR Register FFIEN FFIEN FEIEN FEIEN RNIEN CDIEN SBDIEN RBERIEN ARBIEN SRBIEN SRBIEN TBERIEN STBIEN STBIEN Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 - - - - - - - - - - - - - - Register Set Flag - - - - - - - - - - - - - - Bit USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ TRBSCR USIC0_ TRBSCR - USIC0_ TRBSCR USIC0_ TRBSCR - USIC0_ TRBSCR Register Clear Flag CTFF CRFF CFER1 CFER0 CRNS CCOL CSBD CRBERI CARBI - CSRBI CTBERI - CSTBI Bit USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ RBCTR USIC0_ RBCTR USIC0_ RBCTR USIC0_ RBCTR USIC0_ TBCTR USIC0_ TBCTR USIC0_ TBCTR Register PINP PINP PINP PINP PINP PINP PINP ARBINP ARBINP SRBINP SRBINP ATBINP STBINP STBINP Bit Node Pointer XMC1100 AB-Step XMC1000 Family Subject to Agreement on the Use of Product Information V1.2, 2014-11 9, 10, 11, 12, 13, 14 USIC0_S R[5:0] USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR USIC0_ PSR SSC: MSLS event detected SSC: Parity error detected SSC: DX2T event detected Reference Manual NVIC, V1.9 IIC: Wrong TDF code detected IIC: Start condition received IIC: Repeated start condition received IIC: Stop condition received IIC: NACK received IIC: Arbitration lost 5-18 IIC: Slave read request IIC: Error detected IIC: ACK received IIS: DX2T event detected IIS: WA falling edge event IIS: WA rising edge event IIS: WA generation end END WARE WAFE DX2TEV ACK ERR SRR ARL NACK PCR RSCR SCR WTDF DX2TEV PAERR MSLSEV USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR USIC0_ PCR Register ENDIEN WAREIEN WAFEIEN DX2TIEN ACKIEN ERRIEN SRRIEN ARLIEN NACKIEN PCRIEN RSCRIEN SCRIEN ERRIEN DX2TIEN PARIEN MSLSIEN Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 - - - - - - - - - - - - - - - - Register Set Flag - - - - - - - - - - - - - - - - Bit USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR USIC0_ PSCR Register Clear Flag CEND CWARE CWAFE CDX2TEV CACK CERR CSRR CARL CNACK CPCR CRSCR CSCR CWTDF CDX2TEV CPAERR CMSLSEV Bit USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR USIC0_ INPR Register PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP PINP Bit Node Pointer XMC1100 AB-Step XMC1000 Family Subject to Agreement on the Use of Product Information V1.2, 2014-11 Reference Manual NVIC, V1.9 17, 18, 19, 20 15, 16, Reserved VADC0_ C0SR[1:0] VADC0_G xSEFLAG VADC0_G xSEFLAG VADC0_G xCEFLAG VADC0_G xREFLAG VADC0_G xREFLAG VADC0_G LOBEFLA G VADC0_G LOBEFLA G Source Event 0 Source Event 1 Channel Event y (y=0-7) Result Event y (y=0-7) Result Event y (y=8-15) Global Source Event Global Result Event REVGLB SEVGLB REVy REVy CEVy SEV1 SEV0 VADC0_G LOBERCR VADC0_B RSMR VADC0_G xRCRy VADC0_G xRCRy VADC0_G xCHCTRy VADC0_G xASMR VADC0_G xQINR0 Register SRGEN ENSI SRGEN SRGEN CHEVMOD E ENSI ENSI Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 VADC0_G LOBEFLA G VADC0_G LOBEFLA G VADC0_G xREFLAG VADC0_G xREFLAG VADC0_G xCEFLAG VADC0_G xSEFLAG VADC0_G xSEFLAG Register Set Flag REVGLB SEVGLB REVy REVy CEVy SEV1 SEV0 Bit VADC0_G LOBEFLA G VADC0_G LOBEFLA G VADC0_G xREFCLR VADC0_G xREFCLR VADC0_G xCEFCLR VADC0_G xSEFCLR VADC0_G xSEFCLR Register Clear Flag REVGLBC LR SEVGLBC LR REVy REVy CEVy SEV1 SEV0 Bit VADC0_G LOBEVNP VADC0_G LOBEVNP VADC0_G xREVNP1 VADC0_G xREVNP0 VADC0_G xCEVNP VADC0_G xSEVNP VADC0_G xSEVNP Register SEV0NP REV0NP REVyNP REVyNP CEVyINP SEV1NP SEV0NP Bit Node Pointer XMC1100 AB-Step XMC1000 Family 5-19 Subject to Agreement on the Use of Product Information V1.2, 2014-11 Reference Manual NVIC, V1.9 5-20 Reserved CCU40_ SR[3:0] CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS CCU40_ CC4yINTS Event 0 edge(s) information from event selector Event 1 edge(s) information from event selector Event 2 edge(s) information from event selector Period Match while counting up Compare Match while counting up Compare Match while counting down One Match while counting down Entering Trap State TRPF OMDS CMDS CMUS PMUS E2AS E1AS E0AS CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE CCU40_ CC4yINTE E2AE OME CMDE CMUE PME E2AE E1AE E0AE CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS CCU40_ CC4ySWS Register Set Flag STRPF SOM SCMD SCMU SPM SE2A SE1A SE0A Bit CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR CCU40_ CC4ySWR Register Clear Flag RTRPF ROM RCMD RCMU RPM RE2A RE1A RE0A Bit CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS CCU40_ CC4ySRS Register E2SR POSR CMSR CMSR POSR E2SR E1SR E0SR Bit Node Pointer 1) Flash ECC double bit error has two status flags, each having its own clear bit. It is sufficient to use only one of the status flag and ignore the other. 31 30, 29, 28, 27, 26, 25, 21, 22, 23, 24 Register Bit Interrupt Enable Register Bit Status Flag Interrupt Source Overview IRQ Interrupt Interrupt Node Source Table 5-6 XMC1100 AB-Step XMC1000 Family Subject to Agreement on the Use of Product Information V1.2, 2014-11 XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) 6 Event Request Unit (ERU) As described in the Service Request Processing chapter, XMC1100 uses the Event Request Unit (ERU) to support the programmable interconnection for the processing of service requests. 6.1 Features The ERU supports these features: • • • • • Flexible processing of external and internal service requests Programmable for edge and/or level triggering Multiple inputs per channel Triggers combinable from multiple inputs Input and output gating 6.2 Overview The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit. ERU Figure 6-1 3 3 2 ADC 1 1 0 0 >1 CAPCOM & Trigger Cross Connect Event Trigger Logic / Event Status Flag Event Co mbinations & Event Input Selectors Source Inputs Channel 1 Source Inputs Channel 0 GPIO 2 Source Inputs Ch annel 3 CAPCOM EVENTS Source Inputs Channel 2 ADC Event Service by Action Providers Event Request Unit TRIGGERS Outp ut Gating Unit 0 Service Requests by Event Sources IRQ USIC Event Request Unit Overview Each ERU unit consists of the following blocks: • An Event Request Select (ERS) unit. – Event Input Selectors allow the selection of one out of two inputs. For each of these two inputs, an vector of 4 possible signals is available. – Event Combinations allow a logical combination of two input signals to a common trigger. Reference Manual Service Request Processing, V1.0 6-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) • • • An Event Trigger Logic (ETL) per Input Channel allows the definition of the transition (edge selection, or by software) that lead to a trigger event and can also store this status. Here, the input levels of the selected signals are translated into events. The Trigger Cross Connect Matrix distributes the events and status flags to the Output Channels. Additionally, trigger signals from other modules are made available and can be combined with the local triggers. An Output Gating Unit (OGU) combines the trigger events and status information and gates the Output depending on a gating signal. Note: An event of one Input can lead to reactions on several Outputs, or also events on several Inputs can be combined to a reaction on one Output. 6.3 Event Request Select Unit (ERS) For each Input Channel x (x = 0-3), an ERSx unit handles the input selection for the associated ETLx unit. Each ERSx performs a logical combination of two signals (Ax, Bx) to provide one combined output signal ERSxO to the associated ETLx. Input Ax can be selected from 4 options of the input vector ERU_xA[3:0] and can be optionally inverted. A similar structure exists for input Bx (selection from ERU_xB[3:0]). In addition to the direct choice of either input Ax or Bx or their inverted values, the possible logical combinations for two selected inputs are a logical AND or a logical OR. EXISEL. EXSxA EXICONx. NA Select Input Ax Select Polarity Ax EXICONx. SS ERU_xA0 ERU_xA1 ERU_xA2 Ax Bx ERU_xA3 1 Ax OR Bx ERU_xB0 ERU_xB1 ERU_xB2 Select Input Bx Select Polarity Bx EXISEL. EXSxB EXICONx. NB & Ax AND Bx Select Source for ERSxO ERSxO ETLx ERU_xB3 Figure 6-2 ERSx Event Request Select Unit Overview Reference Manual Service Request Processing, V1.0 6-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) The ERS units are controlled via register ERU0_EXISEL (one register for all four ERSx units) and registers EXICONx (one register for each ERSx and associated ETLx unit, e.g. ERU0_EXICONx (x=0-3) for Input Channel 0). 6.4 Event Trigger Logic (ETLx) For each Input Channel x (x = 0-3), an event trigger logic ETLx derives a trigger event and related status information from the input ERSxO. Each ETLx is based on an edge detection block, where the detection of a rising or a falling edge can be individually enabled. Both edges lead to a trigger event if both enable bits are set (e.g. to handle a toggling input). Each of the four ETLx units has an associated EXICONx register, that controls all options of an ETLx (the register also holds control bits for the associated ERSx unit, e.g. ERU0_EXICONx (x=0-3) to control ERS0 and ETL0). EXICONx. FE EXICONx. LD Modify Status Flag ERSx ERSxO Detect Event (edge) ETLx set clear Status Flag FL EXICONx.FL to all OGUy edge event TRx0 to OGU0 Enable Trigger Pulse trigger pulse Select Trigger Output TRx1 to OGU1 TRx2 to OGU2 TRx3 to OGU3 EXICONx. RE Figure 6-3 EXICONx. PE EXICONx. OCS Event Trigger Logic Overview When the selected event (edge) is detected, the status flag EXICONx.FL becomes set. This flag can also be modified by software. Two different operating modes are supported by this status flag. It can be used as “sticky” flag, which is set by hardware when the desired event has been detected and has to be cleared by software. In this operating mode, it indicates that the event has taken place, but without indicating the actual status of the input. Reference Manual Service Request Processing, V1.0 6-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) In the second operating mode, it is cleared automatically if the “opposite” event is detected. For example, if only the falling edge detection is enabled to set the status flag, it is cleared when the rising edge is detected. In this mode, it can be used for pattern detection where the actual status of the input is important (enabling both edge detections is not useful in this mode). The output of the status flag is connected to all following Output Gating Units (OGUy) in parallel (see Figure 6-4) to provide pattern detection capability of all OGUy units based on different or the same status flags. In addition to the modification of the status flag, a trigger pulse output TRxy of ETLx can be enabled (by bit EXICONx.PE) and selected to trigger actions in one of the OGUy units. The target OGUy for the trigger is selected by bit field EXICON.OCS. The trigger becomes active when the selected edge event is detected, independently from the status flag EXICONx.FL. 6.5 Cross Connect Matrix The matrix shown in Figure 6-4 distributes the trigger signals (TRxy) and status signals (EXICONx.FL) from the different ETLx units between the OGUy units. In addition, it receives peripheral trigger signals that can be OR-combined with the ETLx trigger signals in the OGUy units. Reference Manual Service Request Processing, V1.0 6-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) EXICON0.FL Pattern Detection Inputs TR00 TR01 ETL0 OGU0 TR02 ERU_PDOUT0 ERU_GOUT0 ERU_IOUT0 ERU_TOUT0 TR03 Trigger Inputs TRx0 Peripheral Triggers EXICON1.FL Pattern Detection Inputs TR10 TR11 ETL1 OGU1 TR12 ERU_PDOUT1 ERU_GOUT1 ERU_IOUT1 ERU_TOUT1 TR13 Trigger Inputs TRx1 Peripheral Triggers EXICON2.FL TR20 Pattern Detection Inputs ERU_PDOUT2 OGU2 ERU_IOUT2 TR21 ETL2 TR22 ERU_GOUT2 ERU_TOUT2 TR23 Trigger Inputs TRx2 Peripheral Triggers Pattern Detection Inputs ERU_PDOUT3 OGU3 ERU_IOUT3 EXICON3.FL TR30 TR31 ETL3 TR32 ERU_TOUT3 TR33 Figure 6-4 6.6 ERU_GOUT3 Trigger Inputs TRx3 Peripheral Triggers ERU Cross Connect Matrix Output Gating Unit (OGUy) Each OGUy (y = 0-3) unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system. Figure 6-5 illustrates the logic blocks within an OGUy unit. All functions of an OGUy unit are controlled by its associated Reference Manual Service Request Processing, V1.0 6-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) EXOCONy register, e.g. ERU0_EXOCONx (x=0-3) for OGU0. The function of an OGUy unit can be split into two parts: • • Trigger Combination: All trigger signals TRxy from the Input Channels that are enabled and directed to OGUy, a selected peripheral-related trigger event, and a pattern change event (if enabled) are logically OR-combined. Pattern Detection: The status flags EXICONx.FL of the Input Channels can be enabled to take part in the pattern detection. A pattern match is detected while all enabled status flags are set. Status Flags EXICON0.FL EXOCONy. IPEN0 EXOCONy. GEEN EXICON1.FL ERU_PDOUTy EXOCONy. IPEN1 Detect Pattern EXICON2.FL EXOCONy. PDR EXOCONy. IPEN2 Select Gating Scheme EXICON3.FL Triggers from Input Channels EXOCONy. GP EXOCONy. IPEN3 TR0y ERU_GOUTy Combine OGU Triggers (OR) TR1y TR2y TR3y Interrupt Gating (AND) ERU_IOUTy ERU_TOUTy ERU_OGUy1 Peripheral Triggers Figure 6-5 ERU_OGUy2 ERU_OGUy3 Select Periph. Triggers EXOCONy. ISS OGUy Output Gating Unit for Output Channel y Each OGUy unit generates 4 output signals that are distributed to the system (not all of them are necessarily used): • ERU_PDOUTy to directly output the pattern match information for gating purposes in other modules (pattern match = 1). Reference Manual Service Request Processing, V1.0 6-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) • • • ERU_GOUTy to output the pattern match or pattern miss information (inverted pattern match), or a permanent 0 or 1 under software control for gating purposes in other modules. ERU_TOUTy as combination of a peripheral trigger, a pattern detection result change event, or the ETLx trigger outputs TRxy to trigger actions in other modules. ERU_IOUTy as gated trigger output (ERU_GOUTy logical AND-combined with ERU_TOUTy) to trigger service requests (e.g. the service request generation can be gated to allow service request activation during a certain time window). Trigger Combination The trigger combination logically OR-combines different trigger inputs to form a common trigger ERU_TOUTy. Possible trigger inputs are: • • • In each ETLx unit of the Input Channels, the trigger output TRxy can be enabled and the trigger event can be directed to one of the OGUy units. One out of three peripheral trigger signals per OGUy can be selected as additional trigger source. These peripheral triggers are generated by on-chip peripheral modules, such as capture/compare or timer units. The selection is done by bit field EXOCONy.ISS. In the case that at least one pattern detection input is enabled (EXOCONy.IPENx) and a change of the pattern detection result from pattern match to pattern miss (or vice-versa) is detected, a trigger event is generated to indicate a pattern detection result event (if enabled by ECOCONy.GEEN). The trigger combination offers the possibility to program different trigger criteria for several input signals (independently for each Input Channel) or peripheral signals, and to combine their effects to a single output, e.g. to generate an service request or to start an ADC conversion. This combination capability allows the generation of a service request per OGU that can be triggered by several inputs (multitude of request sources results in one reaction). The selection is defined by the bit fields ISS in registers ERU0_EXOCONx (x=0-3). Pattern Detection The pattern detection logic allows the combination of the status flags of all ETLx units. Each status flag can be individually included or excluded from the pattern detection for each OGUy, via control bits EXOCONy.IPENx. The pattern detection block outputs the following pattern detection results: • • Pattern match (EXOCONy.PDR = 1 and ERU_PDOUTy = 1): A pattern match is indicated while all status flags FL that are included in the pattern detection are 1. Pattern miss (EXOCONy.PDR = 0 and ERU_PDOUTy = 0): A pattern miss is indicated while at least one of the status flags FL that are included in the pattern detection is 0. Reference Manual Service Request Processing, V1.0 6-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) In addition, the pattern detection can deliver a trigger event if the pattern detection result changes from match to miss or vice-versa (if enabled by EXOCONy.GEEN = 1). The pattern result change event is logically OR-combined with the other enabled trigger events to support service request generation or to trigger other module functions (e.g. in the ADC). The event is indicated when the pattern detection result changes and EXOCONy.PDR becomes updated. The service request generation in the OGUy is based on the trigger ERU_TOUTy that can be gated (masked) with the pattern detection result ERU_PDOUTy. This allows an automatic and reproducible generation of service requests during a certain time window, where the request event is elaborated by the trigger combination block and the time window information (gating) is given by the pattern detection. For example, service requests can be issued on a regular time base (peripheral trigger input from capture/compare unit is selected) while a combination of input signals occurs (pattern detection based on ETLx status bits). A programmable gating scheme introduces flexibility to adapt to application requirements and allows the generation of service requests ERU_IOUTy under different conditions: • • • • Pattern match (EXOCONy.GP = 10B): A service request is issued when a trigger event occurs while the pattern detection shows a pattern match. Pattern miss (EXOCONy.GP = 11B): A service request is issued when the trigger event occurs while the pattern detection shows a pattern miss. Independent of pattern detection (EXOCONy.GP = 01B): In this mode, each occurring trigger event leads to a service request. The pattern detection output can be used independently from the trigger combination for gating purposes of other peripherals (independent use of ERU_TOUTy and ERU_PDOUTy with service requests on trigger events). No service requests (EXOCONy.GP = 00B, default setting) In this mode, an occurring trigger event does not lead to a service request. The pattern detection output can be used independently from the trigger combination for gating purposes of other peripherals (independent use of ERU_TOUTy and ERU_PDOUTy without service requests on trigger events). 6.7 Power, Reset and Clock ERU is running on the main clock, MCLK. It is consuming power in all operating modes as long as the MCLK continues to run. Reference Manual Service Request Processing, V1.0 6-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) 6.8 Initialization and System Dependencies Service Requests must always be enabled at the source and at the destination. Additionally it must be checked whether it is necessary to program the ERU0 process and route a request. Enabling Peripheral SRx Outputs • • Peripherals’ SRx outputs must be selectively enabled. This procedure depends on the individual peripheral. Please look up the section “Service Request Generation” within a peripheral chapter for details. Optionally ERU0 must be programmed to process and route the request Enabling External Requests • • Selected PORTS must be programmed for input ERU0 must be programmed to process and route the external request Note: The number of external service request inputs may be limited by the package used. Reference Manual Service Request Processing, V1.0 6-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) 6.9 Registers Table 6-1 Registers Address Space Module Base Address End Address ERU0 4001 0600H 4001 06FFH Note Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 6-2 Register Overview Short Name Description Offset Access Mode Description Address Read Write See EXISEL ERU External Input Control Selection 0000H U, PV U, PV Page 6-11 EXICON0 ERU External Input Control Selection 0010H U, PV U, PV Page 6-13 EXICON1 ERU External Input Control Selection 0014H U, PV U, PV Page 6-13 EXICON2 ERU External Input Control Selection 0018H U, PV U, PV Page 6-13 EXICON3 ERU External Input Control Selection 001CH U, PV U, PV Page 6-13 EXOCON0 ERU Output Control Register 0020H U, PV U, PV Page 6-15 EXOCON1 ERU Output Control Register 0024H U, PV U, PV Page 6-15 EXOCON2 ERU Output Control Register 0028H U, PV U, PV Page 6-15 EXOCON3 ERU Output Control Register 002CH U, PV U, PV Page 6-15 Reference Manual Service Request Processing, V1.0 6-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) 6.9.1 ERU Registers ERU0_EXISEL Event Input Select 31 30 29 28 (00H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 EXS3B EXS3A EXS2B EXS2A EXS1B EXS1A EXS0B EXS0A rw rw rw rw rw rw rw rw Field Bits Type Description EXS0A [1:0] rw Event Source Select for A0 (ERS0) This bit field defines which input is selected for A0. 00B Input ERU_0A0 is selected 01B Input ERU_0A1 is selected 10B Input ERU_0A2 is selected 11B Input ERU_0A3 is selected EXS0B [3:2] rw Event Source Select for B0 (ERS0) This bit field defines which input is selected for B0. 00B Input ERU_0B0 is selected 01B Input ERU_0B1 is selected 10B Input ERU_0B2 is selected 11B Input ERU_0B3 is selected EXS1A [5:4] rw Event Source Select for A1 (ERS1) This bit field defines which input is selected for A1. 00B Input ERU_1A0 is selected 01B Input ERU_1A1 is selected 10B Input ERU_1A2 is selected 11B Input ERU_1A3 is selected EXS1B [7:6] rw Event Source Select for B1 (ERS1) This bit field defines which input is selected for B1. 00B Input ERU_1B0 is selected 01B Input ERU_1B1 is selected 10B Input ERU_1B2 is selected 11B Input ERU_1B3 is selected Reference Manual Service Request Processing, V1.0 6-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Field Bits Type Description EXS2A [9:8] rw Event Source Select for A2 (ERS2) This bit field defines which input is selected for A2. 00B Input ERU_2A0 is selected 01B Input ERU_2A1 is selected 10B Input ERU_2A2 is selected 11B Input ERU_2A3 is selected EXS2B [11:10] rw Event Source Select for B2 (ERS2) This bit field defines which input is selected for B2. 00B Input ERU_2B0 is selected 01B Input ERU_2B1 is selected 10B Input ERU_2B2 is selected 11B Input ERU_2B3 is selected EXS3A [13:12] rw Event Source Select for A3 (ERS3) This bit field defines which input is selected for A3. 00B Input ERU_3A0 is selected 01B Input ERU_3A1 is selected 10B Input ERU_3A2 is selected 11B Input ERU_3A3 is selected EXS3B [15:14] rw Event Source Select for B3 (ERS3) This bit field defines which input is selected for B3. 00B Input ERU_3B0 is selected 01B Input ERU_3B1 is selected 10B Input ERU_3B2 is selected 11B Input ERU_3B3 is selected 0 [31:16] r Reserved Read as 0; should be written with 0. Reference Manual Service Request Processing, V1.0 6-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) ERU0_EXICONx (x=0-3) Event Input Control x (10H + 4*x) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 NB NA SS FL OCS FE RE LD PE r rw rw rw rwh rw rw rw rw rw Field Bits Type Description PE 0 rw Output Trigger Pulse Enable for ETLx This bit enables the generation of an output trigger pulse at TRxy when the selected edge is detected (set condition for the status flag FL). 0B The trigger pulse generation is disabled 1B The trigger pulse generation is enabled LD 1 rw Rebuild Level Detection for Status Flag for ETLx This bit selects if the status flag FL is used as “sticky” bit or if it rebuilds the result of a level detection. 0B The status flag FL is not cleared by hardware and is used as “sticky” bit. Once set, it is not influenced by any edge until it becomes cleared by software. The status flag FL rebuilds a level detection of 1B the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0. RE 2 rw Rising Edge Detection Enable ETLx This bit enables/disables the rising edge event as edge event as set condition for the status flag FL or as possible trigger pulse for TRxy. A rising edge is not considered as edge event 0B A rising edge is considered as edge event 1B Reference Manual Service Request Processing, V1.0 6-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Field Bits Type Description FE 3 rw Falling Edge Detection Enable ETLx This bit enables/disables the falling edge event as edge event as set condition for the status flag FL or as possible trigger pulse for TRxy. A falling edge is not considered as edge event 0B A falling edge is considered as edge event 1B OCS [6:4] rw Output Channel Select for ETLx Output Trigger Pulse This bit field defines which Output Channel OGUy is targeted by an enabled trigger pulse TRxy. 000B Trigger pulses are sent to OGU0 001B Trigger pulses are sent to OGU1 010B Trigger pulses are sent to OGU2 011B Trigger pulses are sent to OGU3 Others: Reserved, do not use this combination FL 7 rwh Status Flag for ETLx This bit represents the status flag that becomes set or cleared by the edge detection. 0B The enabled edge event has not been detected 1B The enabled edge event has been detected SS [9:8] rw Input Source Select for ERSx This bit field defines which logical combination is taken into account as ERSxO. 00B Input A without additional combination 01B Input B without additional combination 10B Input A OR input B 11B Input A AND input B NA 10 rw Input A Negation Select for ERSx This bit selects the polarity for the input A. 0B Input A is used directly Input A is inverted 1B NB 11 rw Input B Negation Select for ERSx This bit selects the polarity for the input B. Input B is used directly 0B Input B is inverted 1B 0 [31:12] r Reference Manual Service Request Processing, V1.0 Reserved Read as 0; should be written with 0. 6-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) ERU0_EXOCONx (x=0-3) Event Output Trigger Control x (20H + 4*x) 31 30 29 28 27 26 25 24 Reset Value: 0000 0008H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 IPEN IPEN IPEN IPEN 3 2 1 0 rw rw rw rw 9 8 0 GP PDR GEE N ISS r rw rh rw rw Field Bits Type Description ISS [1:0] rw Internal Trigger Source Selection This bit field defines which input is selected as peripheral trigger input for OGUy. 00B The peripheral trigger function is disabled 01B Input ERU_OGUy1 is selected 10B Input ERU_OGUy2 is selected 11B Input ERU_OGUy3 is selected GEEN 2 rw Gating Event Enable Bit GEEN enables the generation of a trigger event when the result of the pattern detection changes from match to miss or vice-versa. The event detection is disabled 0B 1B The event detection is enabled PDR 3 rh Pattern Detection Result Flag This bit represents the pattern detection result. 0B A pattern miss is detected A pattern match is detected 1B Reference Manual Service Request Processing, V1.0 6-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Field Bits Type Description GP [5:4] rw Gating Selection for Pattern Detection Result This bit field defines the gating scheme for the service request generation (relation between the OGU output ERU_PDOUTy and ERU_GOUTy). 00B ERU_GOUTy is always disabled and ERU_IOUTy can not be activated 01B ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy 10B ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1) 11B ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0) IPENx (x = 0-3) 12+x rw Pattern Detection Enable for ETLx Bit IPENx defines whether the trigger event status flag EXICONx.FL of ETLx takes part in the pattern detection of OGUy. Flag EXICONx.FL is excluded from the pattern 0B detection Flag EXICONx.FL is included in the pattern 1B detection 0 [31:16] r , [11:6] 6.10 Reserved Read as 0; should be written with 0. Interconnects This section describes how the ERU0 module is connected within the XMC1100 system. Reference Manual Service Request Processing, V1.0 6-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) PORTS External Events PORTS ERU0 Internal Events xB[3:0] - Select - Combine - Detect y x - CrossConnect - Gate GOUTy LEVEL IOUTy PDOUTy TRIGGER LEVEL PERIPH PERIPH PERIPH x=0-3 6.10.1 SR3-6 PORTS xA[3:0] Figure 6-6 NVIC.SRn PORTS Top-Level Cross Interconnect y=0-3 ERU Interconnects Overview ERU0 Connections The following table shows the ERU0 connections. Table 6-3 ERU0 Pin Connections Global Inputs/Outputs Connected To I/O ERU0.0A0 reserved I ERU0.0A1 P2.4 I ERU0.0A2 reserved I ERU0.0A3 VADC0.G0BFLOUT0 I ERU0.0B0 P2.0 I ERU0.0B1 P2.2 I Reference Manual Service Request Processing, V1.0 6-17 Description from ADC boundary flag V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Table 6-3 ERU0 Pin Connections Global Inputs/Outputs Connected To I/O ERU0.0B2 reserved I ERU0.0B3 VADC0.G1BFLOUT0 I ERU0.1A0 reserved from ADC boundary flag I ERU0.1A1 P2.5 I ERU0.1A2 reserved I ERU0.1A3 VADC0.G0BFLOUT1 I ERU0.1B0 P2.1 I ERU0.1B1 P2.3 I ERU0.1B2 reserved I ERU0.1B3 VADC0.G1BFLOUT1 I ERU0.2A0 reserved from ADC boundary flag from ADC boundary flag I ERU0.2A1 P2.6 I ERU0.2A2 reserved I ERU0.2A3 VADC0.G0BFLOUT2 I ERU0.2B0 P2.10 I ERU0.2B1 P2.11 I ERU0.2B2 reserved I ERU0.2B3 VADC0.G1BFLOUT2 I ERU0.3A0 reserved from ADC boundary flag from ADC boundary flag I ERU0.3A1 P2.7 I ERU0.3A2 reserved I ERU0.3A3 VADC0.G0BFLOUT3 I ERU0.3B0 P2.9 I ERU0.3B1 P2.8 I ERU0.3B2 reserved I ERU0.3B3 VADC0.G1BFLOUT3 I ERU0.OGU01 CCU40.SR0 I ERU0.OGU02 VADC0.C0SR2 I ERU0.OGU03 reserved I ERU0.OGU11 CCU40.SR1 I Reference Manual Service Request Processing, V1.0 Description 6-18 from ADC boundary flag from ADC boundary flag V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Table 6-3 ERU0 Pin Connections Global Inputs/Outputs Connected To I/O ERU0.OGU12 VADC0.C0SR2 I ERU0.OGU13 reserved I ERU0.OGU21 CCU40.SR2 I ERU0.OGU22 VADC0.C0SR3 I ERU0.OGU23 reserved I ERU0.OGU31 CCU40.SR3 I ERU0.OGU32 VADC0.C0SR3 I ERU0.OGU33 reserved I ERU0.PDOUT0 VADC0.BGREQGTO O VADC0.G0REQGTO VADC0.G1REQGTO CCU40.IN1D CCU40.IN0J reserved USIC0_CH1.HWIN0 P0.0 P2.11 ERU0.GOUT0 P0.0 P2.11 O ERU0.TOUT0 not connected O ERU0.IOUT0 NVIC.ERU0.SR0 O VADC0.BGREQTRM VADC0.G0REQTRM VADC0.G1REQTRM CCU40.CLKB CCU40.IN0K ERU0.PDOUT1 VADC0.BGREQGTP O VADC0.G0REQGTP VADC0.G1REQGTP CCU40.IN0D CCU40.IN1J USIC0_CH1.HWIN2 P0.1 P2.10 Reference Manual Service Request Processing, V1.0 6-19 Description V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Table 6-3 ERU0 Pin Connections Global Inputs/Outputs Connected To I/O ERU0.GOUT1 P0.1 P2.10 O ERU0.TOUT1 not connected O ERU0.IOUT1 NVIC.ERU0.SR1 O VADC0.BGREQTRN VADC0.G0REQTRN VADC0.G1REQTRN CCU40.CLKC CCU40.IN1K ERU0.PDOUT2 VADC0.BGREQGTK O VADC0.G0REQGTK VADC0.G1REQGTK CCU40.IN3D CCU40.IN2J P0.2 P2.1 ERU0.GOUT2 P0.2 P2.1 O ERU0.TOUT2 not connected O ERU0.IOUT2 NVIC.ERU0.SR2 O VADC0.BGREQTRG VADC0.G0REQTRG VADC0.G1REQTRG CCU40.IN2K ERU0.PDOUT3 VADC0.BGREQGTL VADC0.G0REQGTL VADC0.G1REQGTL CCU40.IN3J CCU40.IN2D P0.3 P2.0 O ERU0.GOUT3 P0.3 P2.0 O Reference Manual Service Request Processing, V1.0 6-20 Description V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Event Request Unit (ERU) Table 6-3 ERU0 Pin Connections Global Inputs/Outputs Connected To I/O ERU0.TOUT3 not connected O ERU0.IOUT3 NVIC.ERU0.SR3 O VADC0.BGREQTRH VADC0.G0REQTRH VADC0.G1REQTRH CCU40.IN3K Reference Manual Service Request Processing, V1.0 6-21 Description V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family On-Chip Memories On-Chip Memories Reference Manual V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization 7 Memory Organization This chapter provides description of the system memory organization, memory accesses and memory protection strategy. References [5] Cortex®-M0 User Guide, ARM DUI 0497A (ID112109) 7.1 Overview The Memory Map in XMC1100 is based on standard ARM Cortex-M0 system memory map. 7.1.1 Features The Memory Map implements the following features: • • Compatibility with standard ARM Cortex-M0 CPU [5] Full compatibility across entire XMC1000 Family 7.1.2 Cortex-M0 Address Space The system memory map defines several regions. Address boundaries of each of the regions are determined by the Cortex-M0 core architecture. Reference Manual Memory Organization, V1.14 7-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization FFFF’FFFF H F000’1000 H F000’0000 H FFFF’FFFF H Reserved Device System ROM Table E010’0000 H Private Peripheral Bus Reserved E000’0000 H E010’0000 H E010’0000 H E000’F000 H E000 ’E000 H External Device (Reserved) Reserved A000’0000 H SCS External RAM (Reserved) Reserved Peripheral E000’0000 H 6000 ’0000 H Application Peripherals 5000 ’0000 H Central Peripherals 4800 ’0000 H System Peripherals 4000 ’0000 H SRAM Code 2000 ’0000 H Flash 1000 ’0000 H ROM 0000 ’0000 H Figure 7-1 7.2 XMC1100 Address Space Memory Regions The XMC1100 device-specific address map contains on-chip memories and peripherals. The memory regions for XMC1100 are described in Table 7-1. Table 7-1 Memory Regions Start (hex) End (hex) Size (hex) Space name Usage 00000000 1FFFFFFF 20000000 Code ROM Firmware, Flash 20000000 3FFFFFFF 20000000 SRAM Fast internal SRAM 40000000 47FFFFFF 08000000 Peripheral System Peripherals group Reference Manual Memory Organization, V1.14 7-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Table 7-1 Memory Regions (cont’d) Start (hex) End (hex) Size (hex) Space name Usage 48000000 4FFFFFFF 08000000 Peripheral Central Peripherals group 50000000 57FFFFFF 08000000 Peripheral Application Peripherals group 58000000 5FFFFFFF 08000000 Peripheral reserved 60000000 9FFFFFFF 40000000 External SRAM reserved A0000000 DFFFFFFF 40000000 External Device reserved E0000000 E00FFFFF 00100000 Private Peripheral Bus CPU E0100000 EFFFFFFF 0FF00000 Vendor specific 1 reserved F0000000 FFFFFFFF 10000000 Vendor specific 2 System ROM Table 7.3 Memory Map Table 7-2 defines detailed system memory map of XMC1100 where each individual peripheral or memory instance implement its own address spaces. For detailed register description of the system components and peripherals, please refer to respective chapters of this document. Note: Depending on the device variant, not all peripherals and memory address ranges may be available. Reference Manual Memory Organization, V1.14 7-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Table 7-2 Memory Map Address space Code SRAM2) Address Range Description Access Type1) Read Write 00000000H 00000AFFH ROM (user-readable) U, PV nBE 00000B00H 00001FFFH ROM (non-user-readable) BE BE 00002000H 0FFFFFFFH reserved BE BE 10000000H 10000DFFH Flash Sector 0 (non-user-readable) nBE nBE 10000E00H 10000FFFH Flash Sector 0 (user-readable) U, PV nBE 10001000H 10010FFFH Flash (64 Kbytes) U, PV U, PV 10011000H 1FFFFFFFH reserved BE BE 20000000H 20000FFFH SRAM Block 0 U, PV U, PV 20001000H 20001FFFH SRAM Block 1 U, PV U, PV 20002000H 20002FFFH SRAM Block 2 U, PV U, PV 20003000H 20003FFFH SRAM Block 3 U, PV U, PV 20004000H 3FFFFFFFH reserved BE BE Reference Manual Memory Organization, V1.14 7-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Table 7-2 Memory Map (cont’d) Address space System Peripherals Address Range Description Access Type1) Read Write 40000000H 400007FFH Memory Control U, PV U, PV 40000800H 4000FFFFH reserved BE BE 40010000H 40010FFFH SCU (including RTC) U, PV U, PV 40011000H 4001107FH ANACTRL U, PV U, PV 40011080H 4001FFFFH reserved BE BE 40020000H 4002001FH WDT U, PV U, PV 40020020H 4003FFFFH reserved BE BE Reference Manual Memory Organization, V1.14 7-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Table 7-2 Memory Map (cont’d) Address space System Peripherals (cont’d) Address Range Description Access Type1) Read Write 40040000H 4004007FH Port 0 U, PV U, PV 40040080H 400400FFH reserved BE BE 40040100H 4004017FH Port 1 U, PV U, PV 40040180H 400401FFH reserved BE BE 40040200H 4004027FH Port 2 U, PV U, PV 40040280H 4004FFFFH reserved BE BE 40050000H 400500DFH Flash Registers U, PV U, PV 400500E0H 47FFFFFFH reserved BE BE Central Peripherals 48000000H 480001FFH USIC0 Channel 0 U, PV U, PV 48000200H 480003FFH USIC0 Channel 1 U, PV U, PV 48000400H 480007FFH USIC0 RAM nBE BE 48000800H 4801FFFFH reserved BE BE 48020000H 4802000FH PRNG U, PV U, PV 48020010H 4802FFFFH reserved BE BE Reference Manual Memory Organization, V1.14 7-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Table 7-2 Memory Map (cont’d) Address space Address Range Description Access Type1) Read Write VADC0 General and U, PV Global Registers U, PV 48030400 H 48033FFFH reserved BE BE 48034000H 480341FFH SHS0 U, PV U, PV 48034200H 4803FFFFH reserved BE BE 48040000H 480401FFH CCU40 CC40 and Kernel Registers U, PV U, PV 48040200H 480402FFH CCU40 CC41 U, PV U, PV 48040300H 480403FFH CCU40 CC42 U, PV U, PV 48040400H 480404FFH CCU40 CC43 U, PV U, PV 48040500H 4FFFFFFFH reserved BE BE Peripheral 50000000H 5FFFFFFFH reserved BE BE External SRAM 60000000H 9FFFFFFFH reserved BE BE External Device A0000000H DFFFFFFFH reserved BE BE Private Peripheral Bus E0000000H E00FFFFFH NVIC, System timer, U, PV System Control Block U, PV Vendor specific 1 E0100000H EFFFFFFFH reserved BE BE Vendor specific 2 F0000000H F0000FFFH System ROM Table U, PV nBE F0001000H FFFFFFFFH reserved BE BE Central Peripherals 48030000H (cont’d) 480303FFH Reference Manual Memory Organization, V1.14 7-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization 1) For address ranges taken up by peripherals, the access type for each address in the range may differ from that shown in the table. Refer to respective chapters for details. 2) The address range 2000’0000H to 2000’01FFH will be overwritten by start-up software during device start-up. 7.4 Memory Access This section describes the memory accesses to the different type of memories in XMC1100. 7.4.1 Flash Memory Access The XMC1100 provides up to 64 Kbytes of Flash memory for instruction code or constant data, starting at address 1000’1000H. This excludes Flash sector 0, which is used to store system information and is always read only. The Flash memory will insert waitstates during memory read automatically if needed. For details of Flash memory access, refer to the Flash Architecture chapter. 7.4.2 SRAM Access The XMC1100 provides 16 Kbytes of SRAM for instruction code or constant data, as well as system variables such as the system stack, starting at address 2000’0000H. The SRAM supports 8-bit, 16-bit and 32-bit writes, and generates one parity bit for each 8 bits of written data. A read operation will check for parity errors on the 32-bit read data. Accesses to the SRAM require no wait states. The 16 Kbytes of SRAM is logically divided into four blocks of 4 Kbytes each. Accesses to blocks 1, 2 and 3 can be disabled and enabled again during run-time with the peripheral privilege access scheme. See PAU chapter for details. Note: The address range 2000’0000H to 2000’01FFH will be overwritten by the start-up software during device start-up. Therefore, these addresses should not be targeted during the download of code/data by the bootstrap loader into the SRAM nor should they store critical data that are still needed by the application after a system reset or SW master reset. 7.4.3 ROM Access The XMC1100 provides 8 Kbytes of ROM, which contains the startup software, vector table and user routines. Read accesses to the ROM require no wait states. 7.5 Memory Protection Strategy Two aspects of memory protection are considered: 1. Intellectual Property (IP) Protection Reference Manual Memory Organization, V1.14 7-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization 2. Memory Access Protection during Run-time The memory protection measures available in XMC1100 are listed in Table 7-3. Table 7-3 Memory Protection Measures Protection Aspects Protection Measures Protection Target IP protection Blocking of unauthorized external access Flash memory contents Memory access protection Bit protection scheme Peripheral privilege access control 7.5.1 Specific system-critical registers/bit fields Specific address ranges; each range can be controlled independently Intellectual Property (IP) Protection IP protection refers to the prevention against unauthorized read out of critical data and user IP from Flash memory. 7.5.1.1 Blocking of Unauthorized External Access In XMC1100, the Boot Mode Index (BMI) is used to control the boot options such that once the BMI is programmed to enter user mode (productive), it is not allowed to enter the other boot modes without an erase of the complete user Flash (including sector 0). Therefore, boot options that load and execute external code, including unauthorized code that might read out the Flash memory contents, will be blocked and only user code originating from the Flash memory can be executed. 7.5.2 Memory Access Protection during Run-time Memory access protection refers to the prevention against unintended write access on a memory address space during run-time. 7.5.2.1 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected register bits (i.e., protected bits) using the PASSWD register in the SCU module. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B, for example, writing 0000’00C0H to PASSWD register disables the bit protection scheme. Reference Manual Memory Organization, V1.14 7-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Access is opened for maximum 32 MCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 MCLK cycles, there will be a recount of 32 MCLK cycles. Table 7-4 shows the list of protected bit in XMC1100. Table 7-4 List of Protected Register Bit Fields Register Bit Field SCU_CLKCR FDIV, IDIV, PCLKSEL, RTCLKSEL SCU_CGATSET0 All bits SCU_CGATCLR0 All bits VADC0_ACCPROT0 All bits VADC0_ACCPROT1 All bits Write to all protected registers except VADC0_ACCPROT[1:0], without opening access through bit field PASS, will be ignored. No bus error will be generated. User should read back the register value to ensure the write has taken place. Write to VADC0_ACCPROT[1:0], without opening access through bit field PASS, will trigger a hard fault. If an interrupt occurs immediately after the access is opened and the interrupt service routine requires more than 32 MCLK cycles, the write to the register will happen after the access is closed and thereby, triggering a hard fault. To avoid this, interrupts should be disabled before writing to these two registers. The PASSWD register is also described in the SCU chapter. SCU_PASSWD Password Register 31 30 29 (4001 0024H) 28 27 26 25 24 Reset Value: 0000 0007H 23 22 21 20 19 7 6 5 4 3 18 17 16 2 1 0 0 r 15 14 13 12 11 10 9 8 0 PASS PRO TS r w rh Reference Manual Memory Organization, V1.14 7-10 MODE rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits 00B Scheme disabled - direct access to the protected bits is allowed. 11B Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default) Others: Scheme enabled, similar to the setting for MODE = 11B. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B. Only then will the MODE bit field be registered. PROTS 2 rh Bit Protection Signal Status Bit This bit shows the status of the protection. 0B Software is able to write to all protected bits. Software is unable to write to any of the 1B protected bits. PASS [7:3] w Password Bits This bit protection scheme only recognizes the following three passwords: 11000BEnables writing of the bit field MODE. 10011BOpens access to writing of all protected bits. 10101BCloses access to writing of all protected bits. 0 [31:8] r Reserved 7.5.2.2 Peripheral Privilege Access Control All CPU accesses are privileged accesses. In XMC1100, a separate scheme called Peripheral Privilege Access Control, which allows a peripheral’s memory address space to be disabled to block any unintended write or read access, is provided. The address space can be re-enabled when necessary. Refer to the PAU chapter for details. 7.6 Service Request Generation Memory modules and other system components are capable of generating error responses indicated to the CPU as bus error exceptions or interrupts. Reference Manual Memory Organization, V1.14 7-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Types of Error Causes • • • Unsupported Access Mode Access to Invalid Address Data integrity Error (memories only) Errors that cannot be indicated with bus errors get indicated with service requests that get propagated to the CPU as interrupts. Unsupported Access Modes Unsupported access modes can be classified in various ways and are usually specific to the module that access is performed to. Typical examples of unsupported access modes are write access to read-only type of address mapped resources, protected memory regions. For module specific limitations please refer to individual module chapters. Invalid Address Accesses to invalid addresses result in error responses. Invalid addresses are defined as those that do not mapped to any valid resources. This applies to single addresses and to wider address ranges. Some invalid addresses within valid module address ranges may not produce error responses and this is specific to individual modules. Data Integrity Error Accesses to corrupted data in the memories result in either ECC (Error Correction Code) (ECC) or parity errors. The occurrence of such errors get signalized to the system through an SCU interrupt. 7.7 Debug Behaviour The bus system in debug mode allows debug probe access to all system resources. No special handling of HALT mode is implemented and all interfaces respond with a valid bus response upon accesses. 7.8 Power, Reset and Clock The bus system clocking scheme enables stable system operation and accesses to system resources for all valid system clock rates. 7.9 Initialization and System Dependencies No initialization is required for the memory system from user point of view. All valid memories are available after reset. Some peripherals may need to be initialized (e.g. disable clock gating) before they can be accessed. For details please refer to individual peripheral chapters. Reference Manual Memory Organization, V1.14 7-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Memory Organization Reference Manual Memory Organization, V1.14 7-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8 Flash Architecture This chapter describes the non volatile memory (NVM) module. 8.1 Overview The XMC1100 has an embedded user-programmable NVM for storage of user code and data. 8.1.1 Features The NVM has the following features: • • • • • • • • • Reading by word, writing by block and erasing by page (256 bytes) or sector (4 Kbytes). Fast personalization support. Automatic verify support. Up to 50,000 erase cycles per page. Minimum data retention of 10 years in cells that were never previously programmed. Flash programming voltage generated on-chip. Configurable erase and write protection. Power saving sleep mode. Incremental write without erase for semaphores. 8.2 Definitions Throughout the document the terms NVM (Non Volatile Memory) and Flash are used as synonyms, disregarding the fact that NVM describes a broader class of memories, where the described Flash is only a special case. Reference Manual NVM, V1.3 8-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture sector N_LOG_SEC-1 page 15 1 sector = 16 pages NVM N_LOG_SEC * 4 KB redundancy sector sector 1 sector 0 page 14 page 13 page 1 page 0 1 page = 16 data blocks data block 0 data block 1 data block 14 data block 2 data block 15 1 block = 4 words word 0 word 1 word 2 word 3 NVM_LOGICAL_ STRUCTURE Figure 8-1 8.2.1 Logical structure of the NVM module Logical and Physical States Erasing The erased state of a cell is ‘1’. Forcing an NVM cell to this state is called erasing. Erasing is possible with a granularity of a page (see below). Writing The written state of a cell is ‘0’. Changing an erased cell to this state is called writing. Writing is possible with a granularity of a block (see below). Programming The combination of erasing and writing is called programming. Programming often means also writing a previously erased page. Note: The termini write and writing are also used for accessing special function registers. The meaning depends therefore on the context. 8.2.2 Data Portions Word A word consists of 32 bits. A word represents the data size which is read from or written to the NVM module within one access cycle. Block Reference Manual NVM, V1.3 8-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture A block consists of 4 words (128 bit data, extended by 4 bit parity, and 6 bit ECC). A block represents the smallest data portion that can be written. Page A page consists of 16 blocks. Sector A sector consists of 16 pages. 8.2.3 Address Types Physical Address Address of the CPU system. Base Address or Memory Base Address Physical address of the lower boundary for memory accesses of an NVM module. Logical Address Memory address offset inside the NVM module: If the memory is addressed, the logical address is the physical address subtracted by the base address of the module. Sector Address Module specific part of the logical address specifying the sector, for calculation see Section 8.3.1. Page Address Module specific part of the logical address, for calculation see Section 8.3.1. 8.2.4 Module Specific Definitions The following table defines NVM specific constants used throughout this chapter. Table 8-1 Module Specific Definitions Module size [KB] 204 Constant name Value Comment N_BLOCKS 16 Number of blocks per page N_PAGES 16 Number of pages per sector N_SECTORS 52 Number of sectors including redundancy N_LOG_SEC 51 Number of sectors excluding redundancy 8.3 Module Components Reference Manual NVM, V1.3 8-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.3.1 Memory Cell Array The non-volatile memory cells are organized in sectors, which consist of pages, which on their part are structured in blocks. A logical memory address addr has the following structure: MSB LSB 0 Sector address 6 bits Page address 4 bits Block address 4 bits Word address Word offset 2 bits 2 bits ignored Logical_ address_decomposition.vsd Figure 8-2 • • • • • Decomposition of Logical Address addr[1:0] = word offset, for a memory address undefined and ignored addr[3:2] = word address addr[7:4] = block address addr[11:8] = page address addr[17:12] = sector address. The memory subsystem always accesses whole words, therefore the word offset is ignored by the NVM module. 8.3.1.1 Page Each page consists of 16 data blocks of 138 bits each (including parity bits and ECC bits). A page is the granularity of data that can be erased in the cell array. Block 0 Block N_BLOCK-1 Block 1 138-bit data (including parity and ECC) Page_structure.vsd Figure 8-3 Structure of a Page Reference Manual NVM, V1.3 8-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.3.1.2 Sector 16 pages form a sector. The whole cell array is build of 52 sectors. 8.4 Functional Description The NVM module supports read and write accesses to the memory and to the special function registers (SFRs). No read-modify-write mechanism is supported for SFRs. The main tasks of the NVM module are reading and writing from/to the memory array. 8.4.1 SFR Accesses Reading the special function registers is possible in every mode of the NVM module. Register write is not possible while the state machine is busy. The write is stalled in this case. For other exceptions see Section 8.8.2.2. 8.4.2 Memory Read The NVM memory can be read with a minimum granularity of a word provided that the word is in the memory address range of the module. If the word is not within the memory address range of the NVM module, the module does not react at all and a different memory module may handle the access. Memory read accesses are only possible while no FSM procedure (erase, write, verify, sleep or wake-up) is in progress. A memory read access while the FSM is busy is stalled until the FSM is idle again. Then the access is carried out. Such a stall will also stop the CPU from executing code. The NVM will insert waitstates during memory read automatically if needed. 8.4.3 Memory Write From the user’s viewpoint data is written directly to the memory array. Module internally one block is buffered and the ECC bits are calculated. Then a finite state machine is started that writes the ECC and data bits to the memory field. Writing does not support wrap-around, i.e. writing of a block has always to start with word 0 of the selected block and then automatically continues in ascending order up to word 3. Since a block has to be written in four word writing steps, a special procedure has to be followed to transfer complete block data to the NVM: Writing of a block has always to start with word 0 of the addressed block. The following three writes need to address the other three words of the same block in ascending order. If this rule is not observed, the already provided words are discarded. If in this case the last provided word is addressing a word 0, this word is already accepted as the first word of a new block write procedure. Intermediate read operations do not influence the write data transfer. Intermediate read Reference Manual NVM, V1.3 8-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture operations targeting the same address as the interrupted write operation are served from the memory array, i.e. do not read back the already transferred write data. To write to the memory array, the NVM module has to be set to one-shot or continuous write mode by setting the SFR NVMPROG to the corresponding value. Data to be written can now be written to the desired address. It is not checked, if the addressed block was erased before. Writing to a non erased block leads to corrupted data since writing can only clear bits but not set any bits. Reading such a block will lead most probably to an ECC fault. A write access to the NVM when not in write mode does not trigger an exception or interrupt. The data is lost. Writes to the NVM are also used to trigger other operations which are described in the following subsections. Similarly, a write access to the NVM module has no effect and the data is lost when a protected sector is addressed (see Section 8.4.7). Depending on the settings of NVMPROG, an automatic verify is performed (see Section 8.4.6). In case of a one-shot write, write mode is automatically left. In case of continuous write mode, further write operations to new addresses can follow, until the write mode is explicitly left. Continuous write operations can target blocks within the complete memory without any restriction regarding sector or page borders. 8.4.4 Memory Erase Only whole pages can be physically erased, i.e. all bits of the addressed page are physically set to ‘1’. To erase a page in the memory field, the NVM module has to be set to one-shot or continuous page erase mode by setting the SFR NVMPROG to the corresponding value. A write access to a memory location specifies the address of the page to be erased and triggers the erase. A write access to the NVM when not in page erase mode does not trigger an exception or interrupt because they are also used to trigger other operations; as described in this section. Similarly, no erase is triggered when a protected sector is addressed (see Section 8.4.7). In case of a one-shot page erase, page erase mode is automatically left. In case of continuous page erase mode, further page erase operations can follow, until the page erase mode is explicitly left. 8.4.5 Sector Erase Additionally, whole sectors consisting of 16 pages can be physically erased in parallel, i.e. all bits of the addressed sector are physically set to ‘1’. Reference Manual NVM, V1.3 8-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture To erase a sector in the memory array, the NVM module has to be set to one-shot or continuous sector erase mode by setting the SFR NVMPROG to the corresponding value. Writing arbitrary data to a memory location specifies the address of the sector to be erased. A write access to the NVM when not in sector erase mode does not trigger an exception or interrupt because it is also used to trigger other operations; as described in this section. Similarly, no erase is triggered when a protected sector is addressed (see Chapter 8.4.7). In case of a one-shot sector erase, sector erase mode is automatically left. In case of continuous sector erase mode, further sector erase operations can follow, until the sector erase mode is explicitly left. 8.4.6 Verify The data written as described in Section 8.4.3 can be verified automatically. The written data in the cell array can be automatically compared to the data still available in the module internal buffer. This is automatically performed two times with hardread written and hardread erased. These hardread levels provide some margin compared to the normal read level to ensure that the data is really programmed with suitably distinct levels for written and erased bits. The verification result can be read at SFR NVMSTATUS. Stand-alone verify operations can also be started by setting the SFR NVMPROG to the corresponding value. In this case, data written to a memory location is compared with the content of the memory field at the specified address. The comparison here is performed just once with a read level chosen before from normal read, hardread written and hardread erased. A write access to the NVM when not in verification mode does not trigger an exception or interrupt because it is also used to trigger other operations; as described in this section. Similarly, a write access to the NVM module has no effect, when a protected sector is addressed (see Section 8.4.7). In case of a one-shot verify, verify mode is automatically left. In case of continuous verify mode, further verify operations can follow, until the verify mode is explicitly left. Note: A continuous write operation without automatic verification, followed by two standalone verifications with ‘hardread written’ and ‘hardread erased’, is faster than a write operation with continuous automatic verification, since in the second case for every block write the hardread level has to be changed twice, whereas in the first case this change is performed only two times for the complete write data. On the other hand, for the continuous automatic verification the reference data for the verification is directly available within the NVM module, whereas for the standalone verification the reference data needs to be provided again by the CPU. Reference Manual NVM, V1.3 8-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.4.7 Erase-Protection and Write-Protection By setting NVMCONF.SECPROT, a configurable number of sectors can be selected to be protected from any modification, i.e. a range of sectors starting with sector 0 can be defined to be erase-protected and write-protected. 8.5 Redundancy To increase the production yield, the NVM module contains redundancy. Redundancy is transparent to the user. 8.6 Properties and Implementation of Error Correcting Code (ECC) The error correcting code (ECC) for the data blocks is a one-bit error correction and a (partial) double-bit error detection for every data block of 128 bit, which uses 4 parity bits and 6 ECC bits in addition to the protected 128 data bits. The correct ECC bits for every block are generated automatically when the data is written. 8.7 Service Request Generation The NVM module supports immediate error and status information to the user by interrupt generation. A NVM interrupt can be issued because of the following events: • • Completion of: – NVM operations started through NVMPROG.ACTION (except for verify-only sequence) – NVM wake-up sequence NVM ECC double-bit error The NVM interrupt request is generated to the CPU through the SCU. Therefore, related interrupt control bits are located in the SCU but with the following exceptions: • • • There are two sets of NVM ECC double-bit error status flag and clear status bit: – NVMSTATUS.ECC2READ and NVMPROG.RSTECC in NVM module – SCU_RAWSR.FLECC2I and SCU_SRCLR.FLECC2I in SCU module It is sufficient to use just one of the two sets and ignore the other. The interrupt enable bit for the NVM operation complete interrupt is located only in the NVMCONF register. 8.8 Power, Reset and Clock The following sections describe the power, reset and clock sources of the NVM module. Reference Manual NVM, V1.3 8-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.8.1 Power Supply The NVM module sources all voltages required for read, program and erase operations from the on-chip Embedded Voltage Regulator (EVR). The standard VDDC is used for all digital control functions. 8.8.2 Power Saving Modes The NVM module supports the following power saving modes. The modes differ in power consumption and in the time to restart the memory. 8.8.2.1 NVM Idle Mode Idle mode is entered after reset after charging the pumps. In idle mode the power consumption is less than during a memory read access or write access. Any operation of the NVM module (SFR access or memory access) can be started from idle mode without time delay. 8.8.2.2 NVM Sleep Mode Entering and leaving NVM sleep mode requires special state machine sequences, which need some time. Therefore, besides SFR accesses, the NVM module cannot be used immediately after wake-up from sleep mode, as indicated by NVMSTATUS.BUSY. NVM sleep mode is entered via WFE/WFI when Flash Power down is activeted, see SCU chapter. Alternatively, sleep mode for the NVM module can be triggered by writing the respective bit in SFR NVMCONF. In NVM sleep mode only the SFR NVMCONF can be read and written, all other SFRs can only be read. No memory access is possible in sleep mode. 8.8.3 Reset The NVM module is reset with the system reset. 8.8.4 Clock The NVM module is operating at the same clock speed as main clock, MCLK. Reference Manual NVM, V1.3 8-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.9 Registers Table 8-3 shows a complete list of the NVM special function registers. Table 8-2 Registers Address Space Module Base Address End Address NVM 4005 0000H 4005 00FFH Table 8-3 Note Registers Overview Register Short Name Register Long Name Offset Address Page Number NVMSTATUS NVM Status Register 0000H Page 8-11 NVMPROG NVM Programming Control Register 0004H Page 8-13 NVMCONF NVM Configuration Register 0008H Page 8-15 The register is addressed wordwise. Reading an SFR is not blocked, while the NVM module is busy. If the SFR value depends on the completion of an NVM sequence, NVMSTATUS.BUSY must be polled for 0B, before the SFR is read. Otherwise, reading the SFR might yield a value that is not updated yet. Reference Manual NVM, V1.3 8-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.9.1 NVM Registers NVM Status Register NVMSTATUS NVM Status Register 15 14 13 12 (0000H) 11 10 9 8 7 Reset Value: 0002H 6 5 4 ECC ECC WRP 2RE 1RE ERR AD AD r r r 0 r 3 2 VERR r 1 0 SLE BUS EP Y r r Field Bits Type Description 0 15:7 r Reserved Read as 0. WRPERR 6 r Write Protocol Error The flag accumulates write protocol violations during the last 4-word write operations (for write or verify). It is also set when a triggered operation was ignored because of write protection. The correct protocol is defined in Section 8.4.3. It is reset by hardware when NVMPROG.RSTECC is written. WRPROTOK, No write protocol failure occurred. 0B 1B WRPROTFAIL, At least one write protocol failure was detected. ECC2READ 5 r ECC2 Read1) The flag accumulates ECC two bit failure during memory read operations. It is reset by hardware when NVMPROG.RSTECC is written. ECC2RDOK, No ECC two bit failure during memory 0B read operations. ECC2RDFAIL, At least one ECC two bit failure was 1B detected. Reference Manual NVM, V1.3 8-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture Field Bits Type Description ECC1READ 4 r ECC1 Read1) The flag accumulates ECC single bit failure during the last memory read operations. It is reset by hardware when NVMPROG.RSTECC is written. ECC1RDOK, No ECC single bit failure occurred. 0B ECC1RDFAIL, At least one ECC single bit failure 1B was detected and corrected. VERR 3:2 r Verify Error The flag is reset by hardware, when NVMPROG.RSTVERR is written. The flag is also reset, when write mode or verify-only mode are entered, i.e. NVMPROG.ACTION.OPTYPE = 0001B or NVMPROG.ACTION.VERIFY = 11B. The flag accumulates, i.e. VERR is updated every time a value higher than the current value is required, until write mode or verify-only mode are left (automatically in case of a one-shot write operation). Information on number of fail bits during verify procedure(s): 00B NOFAIL, No fail bit. 01B ONEFAIL, One fail bit in one data block. 10B TWOFAIL, Two fail bits in two different data blocks. 11B MOREFAIL, Two or more fail bits in one data block, or three or more fail bits overall. SLEEP 1 r Sleep Mode 0B READY, NVM not in sleep mode, and no sleep or wake up procedure in progress. SLEEP, NVM in sleep mode, or busy due to a sleep 1B or wake up procedure. BUSY 0 r Busy 0B READY, The NVM is not busy. Memory reads from the cell array and register write accesses are possible. BUSY, The NVM is busy. Memory reads and register 1B write accesses are not possible. 1) If a block is read from the field that contains two or more parity errors ECC1 and ECC2 errors may be flagged simultaneously. NVM Programming Control Register Reference Manual NVM, V1.3 8-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture NVMPROG NVM Programming Control Register (0004H) 15 14 0 r 13 12 RST RST VER ECC R rw rw 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 0 ACTION r rw 2 1 Field Bits Type Description 0 15:1 r 4 Reserved Read as 0; should by written with 0. RSTECC 13 rw Reset ECC Can only be set by software, is reset automatically by hardware. 0B NOP, No action. RESET, Reset of NVMSTATUS.ECCxREAD and 1B NVMSTATUS.WRPERR. RSTVERR 12 rw Reset Verify Error Can only be set by software, is reset automatically by hardware. 0B NOP, No action. 1B RESET, Reset of NVMSTATUS.VERR. 0 11:8 r Reference Manual NVM, V1.3 0 Reserved Read as 0; should be written with 0. 8-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture Field Bits Type Description ACTION 7:0 Reference Manual NVM, V1.3 rw ACTION: [VERIFY, ONE_SHOT, OPTYPE] This field selects an erase, write, or verify operation. See also More details on ACTION. ACTION is a concatenation of three bit fields: ACTION[7:6] = VERIFY, ACTION[5:4] = ONE_SHOT and ACTION[3:0] = OPTYPE. OPTYPE defines the following operations: 0000B: idle or verify-only, that depends on the setting of VERIFY; 0001B: write; 0010B: page erase. 0100B: sector erase. ONE_SHOT is a parameter of OPTYPE with the following values: 01B: once or 10B: continuously. In case of 01B, ACTION is automatically reset to idle mode after operation has been performed. VERIFY defines a second parameter of OPTYPE: 01B: verification of written data with hardread levels after every write operation, 10B: no verification, 11B: verification of array content. The following operations are defined, other values are interpreted as 00H 00H , Idle state, no action triggered. Writing 00H exits current mode. 51H , Start one-shot write operation with automatic verify. 91H , Start one-shot write operation without verify. 61H , Start continuous write operation with automatic verify of every write. A1H , Start continuous write operation without verify. 92H , Start one-shot page erase operation. 94H , Start one-shot sector erase operation. A4H , Start continuous sector erase operation. A2H , Start continuous page erase operation. D0H , Start one-shot verify-only: Written data is compared to array content. E0H , Start continuous verify-only: Written data is compared to array content. 8-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture More details on ACTION The operation selected by ACTION is performed, when a write to the NVM address range is performed, which defines the address (and block data) for the operation. Afterwards, in case of a one-shot operation, ACTION is automatically reset. Verification results can be read at NVMSTATUS.VERR. ACTION can only be changed when the current value of ACTION is 00H, otherwise ACTION is set to 00H. Once ACTION is not idle, ACTION can only be written again with its current value; any other value leads to a reset of ACTION. Only write operations can be automatically verified. Page erase operations cannot use automatic verify, they must be started with ACTION.VERIFY = 10B. If the correct erasing of a page or sector is to be verified, a separate sequence using ACTION.VERIFY = 11B has to be started. A verify operation requires the provision of the data for a complete block and always includes the ECC bits. The ECC bits for every block are generated automatically when the data is written. A verify operation started with ACTION.VERIFY = 01B is automatically performed with both hardread written and hardread erased levels. A verify operation started with ACTION.VERIFY = 11B is performed with the single hardread level defined by NVMCONF.HRLEV at this starting time. A sequence started by setting ACTION will set NVMSTATUS.BUSY only after the transfer of the address (and block data) is performed. The end of the sequence can be detected either by polling NVMSTATUS.BUSY or by waiting for an NVM interrupt (not for verify-only sequence). Entering sleep mode resets ACTION. NVM Configuration Register NVMCONF is the only SFR that can be written while the module is in sleep mode. This is necessary to enable the use of NVM_ON = 0B to go to sleep mode and of NVM_ON = 1B to wake-up again. NVMCONF NVM Configuration Register 15 14 NVM INT_ _ON ON rw rw 13 12 0 1 rw rw Reference Manual NVM, V1.3 11 10 (0008H) 9 8 7 Reset Value: 9000H 3 2 1 0 SECPROT 0 HRLEV 0 rw r rw rw 8-15 6 5 4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture Field Bits Type Description NVM_ON 15 rw NVM On When cleared, no software code can be executed anymore from the NVM, until it is set again. I.e., already the software code that initiates the change in NVM_ON itself may not reside in the NVM, otherwise the software is stalled forever. SLEEP, NVM is switched to or stays in sleep mode. 0B 1B NORM, NVM is switched to or stays in normal mode. INT_ON 14 rw Interrupt On When enabled the completion of a sequence started by setting NVMPROG.ACTION (write or erase sequence) will be indicated by NVM interrupt. The same is true for the wake-up sequence. INTOFF, No NVM ready interrupts are generated. 0B 1B INTON, NVM ready interrupts are generated. 0 13 rw Reserved for Future Use Must be written with 0 to allow correct operation. 1 12 rw Reserved for Future Use Must be written with 1 to allow correct operation. SECPROT 11:4 rw Sector Protection1) This field defines the number of write, erase, verify protected sectors, starting with physical sector 0. 0 3 r Reserved Read as 0; should be written with 0. HRLEV 2:1 rw Hardread Level2) Defines single hardread level for verification with NVMPROG.ACTION.VERIFY = 11B: 00B NR, Normal read 01B HRW, Hardread written 10B HRE, Hardread erased 11B RFU, Reserved for Future Use 0 0 rw Reserved for Future Use Must be written with 0 to allow correct operation. 1) For SECPROT > 0, SECPROT defines the number of protected sectors. The sectors 0 to SECPROT-1 cannot be written, erased, or verified. All writes that target the protected sectors are accepted, but are internally ignored. 2) HRLEV defines the hardread level for a stand-alone verification sequence started with NVMPROG.ACTION.VERIFY = 11B. This hardread level is used until the end of the verification sequence. HRLEV may not be changed in between. Reference Manual NVM, V1.3 8-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.10 Example Sequences This section presents some low-level programming examples. In all following operations the protection defined by NVMCONF.SECPROT needs to be taken into account. 8.10.1 Writing to Memory 8.10.1.1 Writing a Single Block This sequence requires that the target block is already erased. Additional assumption: NVMPROG.ACTION = 00H. 1. Start a one-shot write operation: Write NVMPROG.ACTION = 51H or 91H, respectively, if an automatic verification of the written data is to be performed or not. 2. Write data for one block to the physical address. 3. Poll flag NVMSTATUS.BUSY until write sequence has finished, or wait for NVMready interrupt (if enabled). 4. If an automatic verification of the written data was requested in the first step, read NVMSTATUS.VERR for the verification result. If no verification of the written data was requested in step 1, and thus no read access to the NVM SFR is required in step 4, step 3 may be omitted. The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 8.10.1.2 Writing Blocks This sequence requires the target blocks are already erased. Additional assumption: NVMPROG.ACTION = 00H. 1. Start a continuous write operation: Write NVMPROG.ACTION = 61H or A1H, respectively, if an automatic verification of the written data is to be performed or not. 2. Write data for one block to the physical address. 3. Poll flag NVMSTATUS.BUSY until write sequence has finished, or wait for NVMready interrupt (if enabled). Optionally, step 3 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 4. Jump to step 2 unless all data is written. Reference Manual NVM, V1.3 8-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 5. Stop continuous write operation: Write NVMPROG.ACTION = 00H. 6. If an automatic verification of the written data was requested in the first step, read NVMSTATUS.VERR for the verification result. 8.10.2 Erasing Memory 8.10.2.1 Erasing a Single Page Assumption: NVMPROG.ACTION = 00H. 1. Start a one-shot page erase operation: Write NVMPROG.ACTION = 92H. 2. Write dummy data for one word to one arbitrary word-aligned physical address of the page to be erased. 3. Poll flag NVMSTATUS.BUSY until page erase sequence has finished, or wait for NVMready interrupt (if enabled). Optionally, step 3 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 8.10.2.2 Erasing Pages Assumption: NVMPROG.ACTION = 00H. 1. Start a continuous page erase operation: Write NVMPROG.ACTION = A2H. 2. Write dummy data for one word to one arbitrary word-aligned physical address of the page to be erased. 3. Poll flag NVMSTATUS.BUSY until page erase sequence has finished, or wait for NVMready interrupt (if enabled). Optionally, step 3 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 4. Jump to step 2 unless all pages are erased. 5. Stop continuous page erase operation: Write NVMPROG.ACTION = 00H. 8.10.2.3 Erasing a Single Sector Assumption: NVMPROG.ACTION = 00H. 1. Start a one-shot sector erase operation: Write NVMPROG.ACTION = 94H. Reference Manual NVM, V1.3 8-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 2. Write dummy data for one word to one arbitrary word-aligned physical address of the sector to be erased. 3. Poll flag NVMSTATUS.BUSY until sector erase sequence has finished, or wait for NVMready interrupt (if enabled). Optionally, step 3 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 8.10.2.4 Erasing Sectors Assumption: NVMPROG.ACTION = 00H. 1. Start a continuous sector erase operation: Write NVMPROG.ACTION = A4H. 2. Write dummy data for one word to one arbitrary word-aligned physical address of the sector to be erased. 3. Poll flag NVMSTATUS.BUSY until sector erase sequence has finished, or wait for NVMready interrupt (if enabled). Optionally, step 3 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 2 is finished. 4. Jump to step 2 unless all sectors are erased. 5. Stop continuous sector erase operation: Write NVMPROG.ACTION = 00H. 8.10.3 Verifying Memory 8.10.3.1 Verifying a Single Block Assumption: NVMPROG.ACTION = 00H. 1. Choose desired hardread level by setting NVMCONF.HRLEV. 2. Start a one-shot verify operation: Write NVMPROG.ACTION = D0H. 3. Write reference data for one block to the physical address. 4. Poll flag NVMSTATUS.BUSY until verify sequence has finished. 5. Read NVMSTATUS.VERR for the verification result. 8.10.3.2 Verifying Blocks Assumption: NVMPROG.ACTION = 00H. 1. Choose desired hardread level by setting NVMCONF.HRLEV. Reference Manual NVM, V1.3 8-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 2. Start a continuous verify operation: Write NVMPROG.ACTION = E0H. 3. Write reference data for one block to the physical address. 4. Poll flag NVMSTATUS.BUSY until verify sequence has finished. Optionally, step 4 may be omitted: The next access to the NVM module or the next write access to an NVM SFR (which ever comes first) will be automatically stalled, until the operation started in step 3 is finished. 5. Jump to step 3 unless all blocks are verified. 6. Stop continuous verify operation: Write NVMPROG.ACTION = 00H. 7. Read NVMSTATUS.VERR for the verification result. 8.10.4 Writing to an Already Written Block Normally, writing additional bits in an already written block is not feasible, since the already written ECC bits and the parity bits would need an update, too, which in most cases would require to erase some bits, which is not possible. The result would be an ECC-faulty block. For special purposes a repeated update of specially constructed data is possible, e.g. to store some marker bits for use in a power loss recovery SW implementation. Starting with an erased block, and making use of the special structure of the ECC, it is possible to repeatedly add two newly written bits in identical bit positions to two arbitrary words of the block. This principle is shown in the exemplary writing scheme of Table 8-4, where a block is updated 32 times without corruption of the ECC, i.e. the data stays ECC protected throughout the procedure. Table 8-4 Operatio n Incremental Update of a Block with Specially Constructed Data Resulting Block Content1) Block Write Data Erase block FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF Add 1st value FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC Add 2nd value FFFFFFFF FFFFFFF3 FFFFFFFF FFFFFFF3 FFFFFFFF FFFFFFF0 FFFFFFFF FFFFFFF0 Add 3rd value FFFFFFFF FFFFFFCF FFFFFFFF FFFFFFCF FFFFFFFF FFFFFFC0 FFFFFFFF FFFFFFC0 Add 4th value FFFFFFFF FFFFFF3F FFFFFFFF FFFFFF3F FFFFFFFF FFFFFF00 FFFFFFFF FFFFFF00 Reference Manual NVM, V1.3 8-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture Table 8-4 Incremental Update of a Block with Specially Constructed Data Operatio n Block Write Data Resulting Block Content1) Add 5th value FFFFFFFF FFFFFCFF FFFFFFFF FFFFFCFF FFFFFFFF FFFFFC00 FFFFFFFF FFFFFC00 Add 6th value FFFFFFFF FFFFF3FF FFFFFFFF FFFFF3FF FFFFFFFF FFFFF000 FFFFFFFF FFFFF000 ... ... ... 15th value FFFFFFFF CFFFFFFF FFFFFFFF CFFFFFFF FFFFFFFF C0000000 FFFFFFFF C0000000 16th value FFFFFFFF 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF 00000000 FFFFFFFF 00000000 17th value FFFFFFFC FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC 00000000 FFFFFFFC 00000000 ... ... ... 30 value F3FFFFFF FFFFFFFF F3FFFFFF FFFFFFFF F0000000 00000000 F0000000 00000000 31st value CFFFFFFF FFFFFFFF CFFFFFFF FFFFFFFF C0000000 00000000 C0000000 00000000 32nd value 3FFFFFFF FFFFFFFF 3FFFFFFF FFFFFFFF 00000000 00000000 00000000 00000000 Add to invalidate written values2) Same as before, but ECC2-faulty th FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFE 1) ECC-clean and parity-clean (ECC bits and parity bits all stay erased), except where indicated otherwise. 2) This write data can be written on any of the states above (except the completely erased state), always resulting in an unchanged data content, but now with an ECC2 error (three ECC bits and one parity bit are written). Other combinations of write values are possible, too, as long as the basic “add two identical bits in each of two words” is adhered to. In Table 8-4 it is also shown that an invalidation of the data by deliberately creating an ECC2 error is possible. To minimize the write times and also to minimize the cycle load of the block, it is important to only write the new bits of the block as shown in Table 8-4. In principle it is possible to repeatedly write also the already written bits again, but this would unnecessarily increase the writing times and would also increase the cycle load. Reference Manual NVM, V1.3 8-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.10.5 Sleep Mode Assumption: Active mode (NVMSTATUS.SLEEP = 0B) and NVMSTATUS.BUSY = 0B. To Enter Sleep Mode 1. Execute WFE/WFI or NVMCONF.NVM_ON = 0B. 2. NVMSTATUS.BUSY = 1B and NVMSTATUS.SLEEP = 1B until sleep mode is reached. 3. NVMSTATUS.BUSY = 0B and NVMSTATUS.SLEEP = 1B while in sleep mode. To Wake-up from Sleep Mode 1. Any wake-up event and NVMCONF.NVM_ON = 1B. 2. NVMSTATUS.BUSY = 1B and NVMSTATUS.SLEEP = 1B until active mode is reached. 3. Poll flag NVMSTATUS.BUSY until wake-up sequence has finished, or wait for NVMready interrupt (if enabled). 4. NVMSTATUS.BUSY = 0B and NVMSTATUS.SLEEP = 0B while in active mode. A wake-up event while the goto sleep sequence has not finished yet, does not shorten this sequence, but only directly starts the wake-up sequence afterwards. Reference Manual NVM, V1.3 8-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Flash Architecture 8.10.6 Timing This state diagram shows the transitions and timings of all possible sequences. block write complete Erase GotoSleep sleep_req=1 or new NVM_ON=0 VerifyWait VerifyBlock VERIFY=3, BUSY=0 BUSY=1 memory write erase operation done T EraseWait block write complete sleep_req=1 or new NVM_ON=0 9 10 sleep_req=1 or new NVM_ON=0 VERIFY=3, BUSY=0 ONE_SHOT=1 or new ACTION=0 new VERIFY=3 memory write 11 (block verify done and ONE_SHOT=1) or new ACTION=0 or memory read RIdleV GotoSleep OPTYPE =[2, 4], BUSY=0 BUSY=1 block verify done 8 GotoSleep (block verify done and ONE_SHOT=1) or new ACTION=0 3 Read ACTION=0, BUSY=0 new OPTYPE=2 memory read read done and no new memory read ReadIdle (write done and ONE_SHOT=1) or new ACTION=0 read done and new memory read T pump charge done ACTION=0 BUSY=0 / SLEEP=0 sleep_req=1 or new NVM_ON=0 WakeUp BUSY=1 / SLEEP=1 2 new OPTYPE=1 sleep_req=0 and (new) NVM_ON=1 Reset Sleep RIdleW ACTION=0, BUSY=0 / SLEEP=1 sleep_req=1 or new NVM_ON=0 OPTYPE=1, BUSY=0 pump discharge done block write done and VERIFY≠1 block verify done 4 T T from RIdleV GotoSleep BUSY=1 / SLEEP=1 1 VerifyBlockHR BUSY=1 5 block write complete block write done and VERIFY=1 7 from EraseWait WriteBits from VerifyWait BUSY=1 6 ReadIns ACTION unchanged BUSY=0 3 read done and no new memory read read done and new memory read back to RIdleV, RIdleW, or EraseWait ACTION: OPTYPE: VERIFY: ONE_SHOT: NVMPROG.ACTION NVMPROG.ACTION.OPTYPE NVMPROG.ACTION.VERIFY NVMPROG.ACTION.ONE_SHOT NVM_ON: NVMCONF.NVM_ON BUSY: SLEEP: NVMSTATUS.BUSY NVMSTATUS.SLEEP T : trigger interrupt, if enabled x : time required for operation or state transition (see list Æ) Figure 8-4 memory read from RIdleV, RIdleW, or EraseWait Time required for operation / state transition 1: 10 µs 2: 30 µs 3: ~65 ns per ECC-clean word *) 4: 20 µs 5: 20 µs 6: 10...130 µs per block, depending on data 7: 40 µs 8: 10 ms 9: 0 or 10 µs, depending on verify read level 10: 0 or 10 µs, depending on verify read level 11: 1 µs *) *) : @ fsys = 32 MHz State Diagram of the NVM Module Timings are preliminary Reference Manual NVM, V1.3 8-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) 9 Peripheral Access Unit (PAU) This chapter describes Peripheral Access Unit (PAU) in XMC1100. 9.1 Overview The PAU supports access control of memories and peripherals in a central place. 9.1.1 Features The PAU provides the following features: • • • Allows user application to enable/disable the access to the registers of a peripheral Generates a HardFault exception when there is an access to a disabled or unassigned address location Provides information on availability of peripherals and size of memories 9.2 Peripheral Privilege Access Control The user application can use the Peripheral Privilege Access Registers, PRIVDISn, to disable access to a peripheral. When the PDISx bit corresponding to the peripheral is set, the memory address space mapped to the peripheral is rendered invalid. An access to such an invalid address causes a HardFault exception. The application can clear the same bit to enable accesses to the peripheral again. Table 9-1 shows the peripherals and their assigned PDISx bits. Peripherals without a PDISx bit are accessible at all times. Table 9-1 Peripherals Availability and Privilege Access Control Peripheral Address Grouping AVAILn.AVAILx bit PRIVDIS.PDISx bit Flash Flash SFRs - PRIVDIS0.2 SRAM RAM Block 1 AVAIL0.5 PRIVDIS0.5 RAM Block 2 AVAIL0.6 PRIVDIS0.6 RAM Block 3 AVAIL0.7 PRIVDIS0.7 WDT WDT - PRIVDIS0.19 Ports Port 0 AVAIL0.22 PRIVDIS0.22 Port 1 AVAIL0.23 PRIVDIS0.23 USIC0 PRNG Port 2 AVAIL0.24 PRIVDIS0.24 USIC0_CH0 AVAIL1.0 PRIVDIS1.0 USIC0_CH1 AVAIL1.1 PRIVDIS1.1 PRNG AVAIL1.4 - Reference Manual PAU, V1.12 9-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Table 9-1 Peripherals Availability and Privilege Access Control Peripheral Address Grouping AVAILn.AVAILx bit PRIVDIS.PDISx bit VADC0 VADC0 Basic SFRs AVAIL1.5 PRIVDIS1.5 SHS0 SHS0 AVAIL1.8 PRIVDIS1.8 CCU4 CC40 and CCU40 Kernel AVAIL1.9 SFRs PRIVDIS1.9 CC41 AVAIL1.10 PRIVDIS1.10 CC42 AVAIL1.11 PRIVDIS1.11 CC43 AVAIL1.12 PRIVDIS1.12 9.3 Peripheral Availability and Memory Size The availability of peripherals and memory sizes varies according to product variants. The user application can read the Peripheral Availability Registers, AVAILn, to check for the availability of peripherals in a product variant. Refer to Table 9-1 for the bit assignement. Similarly, the Memory Size Registers (e.g. FLSIZE for Flash memory) can be used to check for the size of the available memories. 9.4 Service Request Generation The PAU generates a hard fault exception when there is an access to an invalid address. 9.5 Debug Behaviour The PAU does not support a suspend mode while the system is halted by the debugger. That means that the PAU continues its operation during debug halt. 9.6 Power, Reset and Clock The PAU is located in the core power domain. The module can be reset to its default state by a system reset. The PAU module is clocked by the main clock, MCLK, from SCU 9.7 Initialization and System Dependencies The PAU is always available after reset. 9.8 PAU Registers Registers Overview The absolute register address is calculated by adding: Reference Manual PAU, V1.12 9-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Module Base Address + Offset Address Table 9-2 Registers Address Space Module Base Address End Address PAU 4000 0000H 4000 FFFFH Table 9-3 Note Register Overview Short Name Description Offset Addr. Access Mode Description Write See Read Reserved Reserved 0000H - nBE 003CH nBE AVAIL0 Peripheral Availability Register 0 0040H U, PV BE Page 9-6 AVAIL1 Peripheral Availability Register 1 0044H U, PV BE Page 9-7 AVAIL2 Peripheral Availability Register 2 0048H U, PV BE Page 9-9 Reserved Reserved 004CH - nBE 007CH nBE PRIVDIS0 Peripheral Privilege Access Register 0 0080H U, PV U, PV Page 9-4 PRIVDIS1 Peripheral Privilege Access Register 1 0084H U, PV U, PV Page 9-5 Reserved Reserved 0088H - nBE 03FCH nBE ROMSIZE ROM Size Register 0400H U, PV BE Page 9-9 FLSIZE Flash Size Register 0404H U, PV BE Page 9-10 RAM0SIZE RAM0 Size Register 0410H U, PV BE Page 9-11 9.8.1 Peripheral Privilege Access Registers (PRIVDISn) The PRIVDISn registers provide the bit to enable and disable access to a peripheral during runtime. When disabled, an access to the peripheral throws a BusFault. Reference Manual PAU, V1.12 9-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) PRIVDIS0 Peripheral Privilege Access Register 0 (0080H) 31 30 29 28 27 26 25 r 14 13 23 22 21 PDIS PDIS PDIS 24 23 22 0 15 24 Reset Value: 0000 0000H 12 11 10 9 rw rw rw 8 7 6 20 r rw rw 18 PDIS 19 0 r rw r 5 4 rw 3 2 1 0 PDIS 2 0 r rw r Bits Type Description PDIS2 2 rw Flash SFRs Privilege Disable Flag Flash SFRs are accessible. 0B 1B Flash SFRs are not accessible. PDIS5 5 rw RAM Block 1 Privilege Disable Flag 0B RAM Block 1 is accessible. 1B RAM Block 1 is not accessible. PDIS6 6 rw RAM Block 2 Privilege Disable Flag 0B RAM Block 2 is accessible. RAM Block 2 is not accessible. 1B PDIS7 7 rw RAM Block 3 Privilege Disable Flag RAM Block 3 is accessible. 0B 1B RAM Block 3 is not accessible. PDIS19 19 rw WDT Privilege Disable Flag 0B WDT is accessible. 1B WDT is not accessible. PDIS22 22 rw Port 0 Privilege Disable Flag 0B Port 0 is accessible. Port 0 is not accessible. 1B PDIS23 23 rw Port 1 Privilege Disable Flag Port 1 is accessible. 0B 1B Port 1 is not accessible. PDIS24 24 rw Port 2 Privilege Disable Flag 0B Port 2 is accessible. Port 2 is not accessible. 1B 9-4 16 0 Field Reference Manual PAU, V1.12 17 0 PDIS PDIS PDIS 7 6 5 0 19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Field Bits 0 [31:25] r , [21:20] , [18:8], [4:3], [1:0] Type Description Reserved PRIVDIS1 Peripheral Privilege Access Register 1 (0084H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 0 r 12 11 10 9 8 PDIS PDIS PDIS PDIS PDIS 12 11 10 9 8 rw rw rw rw rw 0 PDIS 5 0 r rw r PDIS PDIS 1 0 rw Field Bits Type Description PDIS0 0 rw USIC0 Channel 0 Privilege Disable Flag USIC0 Channel 0 is accessible. 0B 1B USIC0 Channel 0 is not accessible. PDIS1 1 rw USIC0 Channel 1 Privilege Disable Flag 0B USIC0 Channel 1 is accessible. 1B USIC0 Channel 1 is not accessible. PDIS5 5 rw VADC0 Basic SFRs Privilege Disable Flag 0B VADC0 Basic SFRs are accessible. VADC0 Basic SFRs are not accessible. 1B PDIS8 8 rw SHS0 Privilege Disable Flag SHS0 is accessible. 0B 1B SHS0 is not accessible. Reference Manual PAU, V1.12 9-5 rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Field Bits Type Description PDIS9 9 rw CC40 and CCU40 Kernel SFRs Privilege Disable Flag CC40 and CCU40 Kernel SFRs are 0B accessible. 1B CC40 and CCU40 Kernel SFRs are not accessible. PDIS10 10 rw CC41 Privilege Disable Flag CC41 is accessible. 0B 1B CC41 is not accessible. PDIS11 11 rw CC42 Privilege Disable Flag 0B CC42 is accessible. 1B CC42 is not accessible. PDIS12 12 rw CC43 Privilege Disable Flag 0B CC43 is accessible. CC43 is not accessible. 1B 0 [31:13] r , [7:6], [4:2] 9.8.2 Reserved Peripheral Availability Registers (AVAILn) The AVAILn registers indicate the available peripherals for the particular device variant. Note: The reset values of AVAILn registers show the configuration with all peripherals available. Actual values might differ depending on the product variant. AVAIL0 Peripheral Availability Register 0 31 30 29 28 27 26 25 r 14 13 24 23 12 11 0 22 10 9 r r r 8 7 6 21 20 r 9-6 r 18 1 r r 5 r 19 0 AVAI AVAI AVAI L7 L6 L5 r Reference Manual PAU, V1.12 Reset Value: 01CF 00FFH AVAI AVAI AVAI L24 L23 L22 0 15 (0040H) 4 3 2 17 16 1 0 1 r V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Field Bits Type Description AVAIL5 5 r RAM Block 1 Availability Flag RAM block 1 is not available. 0B 1B RAM block 1 is available. AVAIL6 6 r RAM Block 2 Availability Flag 0B RAM block 2 is not available. 1B RAM block 2 is available. AVAIL7 7 r RAM Block 3 Availability Flag 0B RAM block 3 is not available. RAM block 3 is available. 1B AVAIL22 22 r Port 0 Availability Flag Port 0 is not available. 0B 1B Port 0 is available. AVAIL23 23 r Port 1 Availability Flag 0B Port 1 is not available. 1B Port 1 is available. AVAIL24 24 r Port 2 Availability Flag 0B Port 2 is not available. Port 2 is available. 1B 1 [19:16] r , [4:0] Reserved 0 [31:25] r , [21:20] , [15:8] Reserved AVAIL1 Peripheral Availability Register 1 31 30 29 28 27 26 25 (0044H) 24 Reset Value: 0000 1F37H 23 22 7 6 21 20 19 18 5 4 3 2 17 16 1 0 0 r 15 14 13 0 r Reference Manual PAU, V1.12 12 11 10 9 8 AVAI AVAI AVAI AVAI AVAI L12 L11 L10 L9 L8 r r r r r 0 r 9-7 AVAI AVAI L5 L4 r r 0 1 r r AVAI AVAI L1 L0 r r V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Field Bits Type Description AVAIL0 0 r USIC0 Channel 0 Availability Flag USIC0 Channel 0 is not available. 0B 1B USIC0 Channel 0 is available. AVAIL1 1 r USIC0 Channel 1 Availability Flag 0B USIC0 Channel 1 is not available. 1B USIC0 Channel 1 is available. AVAIL4 4 r PRNG Availability Flag 0B PRNG is not available. PRNG is available. 1B AVAIL5 5 r VADC0 Basic SFRs Availability Flag VADC0 Basic SFRs are not available. 0B 1B VADC0 Basic SFRs are available. AVAIL8 8 r SHS0 Availability Flag 0B SHS0 is not available. 1B SHS0 is available. AVAIL9 9 r CC40 Availability Flag 0B CC40 is not available. CC40 is available. 1B AVAIL10 10 r CC41 Availability Flag CC41 is not available. 0B 1B CC41 is available. AVAIL11 11 r CC42 Availability Flag 0B CC42 is not available. 1B CC42 is available. AVAIL12 12 r CC43 Availability Flag 0B CC43 is not available. CC43 is available. 1B 1 2 r Reserved 0 [31:13] r , [7:6], 3 Reserved Reference Manual PAU, V1.12 9-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) AVAIL2 Peripheral Availability Register 2 31 30 29 28 27 26 25 (0048H) 24 23 Reset Value: 0000 0000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved r 15 14 13 12 11 10 9 8 7 Reserved r Field Bits Type Description Reserved [31:0] r 9.8.3 Reserved Read as 0. Memory Size Registers Memory size registers are available for the ROM, SRAM and Flash memories. They are used to indicate the available size of these memories in the device. Note: The reset values of the size registers show the configuration of the superset device. Actual values might differ depending on the product variant. ROMSIZE ROM Size Register 31 30 29 28 (0400H) 27 26 25 24 Reset Value: 0000 0B00H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 ADDR 0 r r r Reference Manual PAU, V1.12 9-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) Field Bits Type Description ADDR [13:8] r 0 [31:14] r , [7:0] ROM Size Size of user-readable ROM in bytes = ADDR * 256 Reserved FLSIZE Flash Size Register 31 15 30 29 14 13 28 12 (0404H) 27 26 11 10 25 9 24 23 Reset Value: 0001 1000H 22 21 20 19 18 17 16 0 ADDR r r 8 7 6 5 ADDR 0 r r 4 3 2 1 0 Field Bits ADDR [17:12] r Flash Size Size of the Flash (excluding Flash sector 0) in Kbytes = (ADDR - 1) * 4 0 [31:18] r , [11:0] Reserved Reference Manual PAU, V1.12 Type Description 9-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Peripheral Access Unit (PAU) RAM0SIZE RAM0 Size Register 31 30 29 28 (0410H) 27 26 25 24 Reset Value: 0000 1000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 ADDR 0 r r r Field Bits Type Description ADDR [12:8] r 0 [31:13] r , [7:0] Reference Manual PAU, V1.12 RAM0 Size Size of RAM block 0 in bytes = ADDR * 256 For total RAM size, RAM blocks 1 to 3 have to be also taken into consideration. Reserved 9-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family On-chip Peripherals On-chip Peripherals Reference Manual V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) 10 Window Watchdog Timer (WDT) Purpose of the Window Watchdog Timer module is improvement of system integrity. WDT triggers the system reset or other corrective action like e.g. an interrupt if the main program, due to some fault condition, neglects to regularly service the watchdog (also referred to as “kicking the dog”, “petting the dog”, “feeding the watchdog” or “waking the watchdog”). The intention is to bring the system back from the unresponsive state into normal operation. References [6] Cortex-M0 User Guide, ARM DUI 0467B (ID081709) 10.1 Overview A successful servicing of the WDT results in a pulse on the signal wdt_service. The signal is offered also as an alternate function output can be used to show to an external watchdog that the system is alive. The WDT timer is a 32-bit counter, which counts up from 0H. It can be serviced while the counter value is within the window boundary, i.e. between the lower and the upper boundary value. Correct servicing results in a reset of the counter to 0H. A so called “Bad Service” attempt results in the system reset request. The timer block is running on the fWDT clock which is independent from the bus clock. The timer value is updated in the corresponding AHB register TIM. This mechanism enables immediate response on a read access from the bus. 10.1.1 Features The watchdog timer (WDT) is an independent window watchdog timer. The features are: • • • • • • Triggers system reset when not serviced on time or serviced in a wrong way Servicing restricted to be within boundaries of refresh window Can run from an independent clock Provides service indication to an external pin Can be suspended in halting mode Provides optional pre-warning alarm before reset Reference Manual WDT, V1.0 10-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) Table 10-1 Application Features Feature Purpose/Application System reset upon Bad Servicing Triggered to restore system stable operation and ensure system integrity Servicing restricted to be within defined boundaries of refresh window Allows to consider minimum and maximum software timing Independent clocks To ensure that WDT counts even in case of the system clock failure Service indication on external pin For dual-channel watchdog solution, additional external control of system integrity Suspending in HALT mode Enables safe debugging with productive code Pre-warning alarm Software recovery to allow corrective action via software recovery routine bringing system back from the unresponsive state into normal operation 10.1.2 Block Diagram The WDT block diagram is shown in Figure 10-1. Bus Interface wdt_service PORTS WDT CPU external watchdog WDT Registers HALTED wdt_alarm wdt_rst_req SCU.GCU SCU.RCU Timer SCU.CCU fWDT Figure 10-1 Watchdog Timer Block Diagram Reference Manual WDT, V1.0 10-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) 10.2 Time-Out Mode An overflow results in an immediate reset request going to the RCU of the SCU via the signal wdt_rst_req whenever the counter crosses the upper boundary it triggers an overflow event pre-warning is not enabled with CTR register. A successful servicing performed with writing a unique value, referred to as “Magic Word” to the SRV register of the WDT within the valid servicing window, results in a pulse on the signal wdt_service and reset of the timer counter. WDT serviced WDT serviced First overflow Window Upper Bound Window Lower Bound 0H No servicing allowed Servicing allowed wdt_service wdt_alarm wdt_rst_req Figure 10-2 Reset without pre-warning The example scenario depicted in Figure 10-2 shows two consecutive service pulses generated from WDT module as the result of successful servicing within valid time windows. The situation where no service has been performed immediately triggers generation of reset request on the wdt_rst_req output after the counter value has exceeded window upper bound value. 10.3 Pre-warning Mode While in pre-warning mode the effect of the overflow event is different with and without pre-warning enabled. The first crossing of the upper bound triggers the outgoing alarm signal wdt_alarm when pre-warning is enabled. Only the next overflow results a reset request. The alarm status is shown via register WDTSTS and can be cleared via register WDTCLR. A clear of the alarm status will bring the WDT back to normal state. Reference Manual WDT, V1.0 10-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) WDT serviced First overflow Second overflow Window Upper Bound Window Lower Bound 0H No servicing allowed Servicing allowed wdt_service wdt_alarm wdt_rst_req Figure 10-3 Reset after pre-warning The example scenario depicted in Figure 10-3 shows service pulse generated from WDT module as the result of successful servicing within valid time window. WDT generates alarm pulse on wdt_alarm upon first missing servicing. The alarm signal is routed as interrupt request to the SCU. Within this alarm service request the user can clear the WDT status bit and give a proper WDT service before it overflows next time. Otherwise WDT generates reset request on wdt_rstn upon the second missing service. 10.4 Bad Service Operation A bad service attempt results in a reset request. A bad service attempt can be due to servicing outside the window boundaries or servicing with an invalid Magic Word. Reference Manual WDT, V1.0 10-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) WDT serviced serviced in wrong window Window Upper Bound Window Lower Bound 0H No servicing allowed Servicing allowed wdt_service wdt_alarm wdt_rst_req Figure 10-4 Reset upon servicing in a wrong window The example in Figure 10-4 shows servicing performed outside of valid servicing window. Attempt to service WDT while counter value remains below the window lower bound results in immediate reset request on wdt_rst_req signal. WDT serviced serviced with invalid magic word Window Upper Bound Window Lower Bound 0H No servicing allowed Servicing allowed wdt_service wdt_alarm wdt_rst_req Figure 10-5 Reset upon servicing with a wrong magic word Reference Manual WDT, V1.0 10-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) The example in Figure 10-5 shows servicing performed within a valid servicing window but with an invalid Magic Word. Attempt to write a wrong word to the SRV register results in immediate reset request on wdt_rst_req signal. 10.5 Service Request Processing The WDT generates watchdog alarm service requests via wdt_alarm output signal upon first counter overflow over watchdog upper bound when pre-warning mode is enabled. The alarm service request is serviced in SCU. Service requests can be disabled respectively by service request mask register in SCU. 10.6 Debug Behavior The WDT function can be suspended when the CPU enters HALT mode. WDT debug function is controlled with DSP bit field in CTR register and it is set to be suspended by default. 10.7 Power, Reset and Clock The WDT module is a part of the core domain and supplied with VDDC voltage. All WDT registers get reset with the system reset. A sticky bit in the Reset Status Register, RSTSTAT, of SCU/RCU module indicates whether the last system reset has been triggered by the WDT module. This bit does not get reset with system reset. The input clock of the WDT counter is provided by the internal 32kHz standby clock from SCU/CCU module, independently from the AHB interface clock. The WDT module clock is default disabled and can be enabled via the SCU_CGATCLR0 register. Enabling and disabling the module clock could cause load change and clock blanking could happen as explained in the CCU (Clock Gating Control) section of the SCU chapter. It is strongly recommended to setup the module clock in the user initialisation code to avoid clock blanking during runtime. 10.8 Initialization and Control Sequence Programming model of the WDT module assumes several scenarios where different control sequences apply. Note: Some of the scenarios described in this chapter require operations on system level the that are not in the scope of the WDT module description, therefore for detailed information please refer to relevant chapters of this document. 10.8.1 Initialization & Start of Operation Complete WDT module initialization is required upon system reset. Reference Manual WDT, V1.0 10-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) • • • • check reason for last system reset in order to determine power state – read out SCU_RSTSTAT.RSTSTAT register bit field to determine last system reset cause and clear this bit using bit SCU_RSTCLR.RSCLR – perform appropriate operations dependent on the last system reset cause WDT software initialization sequence – enable WDT clock with SCU_CGATCLR0.WDT register bit field – set lower window bound with WDT_WLB register – set upper window bound with WDT_WUB register – configure external watchdog service indication (optional, please refer to PORT chapter) – enable interrupt for pre-warning alarm on system level with SCU_SRMSK register (optional, used in WDT pre-warning mode only) software start sequence – select mode (Time-Out or Pre-warning) and enable WDT module with WDT_CTR register service the watchdog – write magic word to WDT_SRV register within valid time window 10.8.2 Software Stop & Resume Operation The WDT module can be stopped and re-started at any point of time for e.g. debug purpose using software sequence. • • • • software stop sequence – disable WDT module with WDT_CTR register perform any user operations software start (resume) sequence – enable WDT module with WDT_CTR register with WDT_CTR register service the watchdog – write magic word to WDT_SRV register within valid time window 10.8.3 Enter Sleep/Deep-Sleep & Resume Operation The WDT counter clock can be configured to stop while in sleep or deep-sleep mode. No direct software interaction with the WDT is required in those modes and no watchdog time-out will fire if the WDT clock is configured to stop while CPU is sleeping. • • software configuration sequence for sleep/deep-sleep mode – configure WDT behavior with SCU_CGATx register enter sleep/deep-sleep mode software sequence Reference Manual WDT, V1.0 10-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) • • • – select sleep or deep-sleep mode in CPU (for details please refer to Cortex-M0 documentation [6]) – enter selected mode (for details please refer to Cortex-M0 documentation [6]) wait for a wake-up event (no software interaction, CPU stopped) resume operation (CPU clock restarted automatically on an event) service the watchdog – write magic word to WDT_SRV register within valid time window 10.8.4 Pre-warning Alarm Handling The WDT will fire pre-warning alarm before requesting system reset while in pre-warning mode and not serviced within valid time window. The WDT status register indicating alarm must be cleared before the timer counter value crosses the upper bound for the second time after firing the alarm. After clearing of the alarm status regular watchdog servicing must be performed within valid time window. • • alarm event – exception routine (service request) clearing WDT_WDTSTAT register with WDT_WDTCLR register service the watchdog – write magic word to WDT_SRV register within valid time window Reference Manual WDT, V1.0 10-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) 10.9 WDT Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 10-2 Registers Address Space Module Base Address End Address Note WDT 4002 0000H 4002 FFFFH Watchdog Timer Registers Table 10-3 Register Overview Short Name Description Offset Addr. Read Access Mode Description Write See WDT Kernel Registers ID Module ID Register 00H U, PV PV Page 10-9 CTR Control Register 04H U, PV PV Page 10-10 SRV Service Register 08H BE PV Page 10-11 TIM Timer Register 0CH U, PV BE Page 10-13 WLB Window Lower Bound 10H U, PV PV Page 10-13 WUB Window Upper Bound 14H U, PV PV Page 10-14 WDTSTS Watchdog Status Register 18H U, PV PV Page 10-14 WDTCLR Watchdog Status Clear Register 1CH U, PV PV Page 10-15 10.9.1 Registers Description ID The module unique ID register. Reference Manual WDT, V1.0 10-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) ID WDT Module ID Register (0000H) 31 30 29 28 27 26 25 24 23 Reset Value: 00AD C0XXH 22 21 20 19 18 17 16 5 4 3 2 1 0 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV [7:0] r Module Revision Number Indicates the revision number of the implementation. The value of a module revision starts with 01H (first revision). MOD_TYPE [15:8] r Module Type This bit field is fixed to C0H. r Module Number Value This bit field defines the module identification number. MOD_NUMBER [31:16] CTR The operation mode control register. Reference Manual WDT, V1.0 10-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) CTR WDT Control Register 31 30 29 28 (04H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 SPW 0 DSP 0 rw r rw r PRE ENB rw rw Field Bits Type Description ENB 0 rw Enable 0B disables watchdog timer, 1B enables watchdog timer PRE 1 rw Pre-warning 0B disables pre-warning 1B enables pre-warning, DSP 4 rw Debug Suspend 0B watchdog timer is stopped during debug halting mode 1B watchdog timer is not stopped during debug halting mode SPW [15:8] rw Service Indication Pulse Width Pulse width (SPW+1) of service indication in clk_wdt cycles 0 [3:2], r [7:5], [31:16] reserved SRV The WDT service register. Software must write a magic word while the timer value is within the valid window boundary. Writing the magic word while the timer value is within the window boundary will service the watchdog and result a reload of the timer with 0H. Reference Manual WDT, V1.0 10-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) Upon writing data different than the magic word within valid time window or writing even correct Magic Word but outside of the valid time window no servicing will be performed. Instead will request an immediate system reset request. SRV WDT Service Register 31 30 29 28 (08H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SRV w 15 14 13 12 11 10 9 8 7 SRV w Field Bits Type Description SRV [31:0] w Reference Manual WDT, V1.0 Service Writing the magic word ABADCAFEH while the timer value is within the window boundary will service the watchdog. 10-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) TIM The actual watchdog timer register count value. This register can be read by software in order to determine current position in the WDT time window. TIM WDT Timer Register 31 30 29 28 (0CH) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 TIM rh 15 14 13 12 11 10 9 8 7 TIM rh Field Bits Type Description TIM [31:0] rh Timer Value Actual value of watchdog timer value. WLB The Window Lower Bound register defines the lower bound for servicing window. Servicing of the watchdog has only effect within the window boundary WLB WDT Window Lower Bound Register (10H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 WLB rw 15 14 13 12 11 10 9 8 7 WLB rw Reference Manual WDT, V1.0 10-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) Field Bits Type Description WLB [31:0] rw Window Lower Bound Lower bound for servicing window. Setting the lower bound to 0H disables the window mechanism. WUB The Window Upper Bound register defines the upper bound for servicing window. Servicing of the watchdog has only effect within the window boundary. WUB WDT Window Upper Bound Register (14H) 31 30 29 28 27 26 25 24 Reset Value: FFFF FFFFH 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 WUB rw 15 14 13 12 11 10 9 8 7 WUB rw Field Bits Type Description WUB [31:0] rw Window Upper Bound Upper Bound for servicing window. The WDT triggers an reset request when the timer is crossing the upper bound value without pre-warning enabled. With pre-warning enabled the first crossing triggers a watchdog alarm and the second crossing triggers a system reset. WDTSTS The status register contains sticky bit indicating occurrence of alarm condition. Reference Manual WDT, V1.0 10-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) WDTSTS WDT Status Register 31 30 29 28 (0018H) 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 ALM S r rh Field Bits Type Description ALMS 0 rh Pre-warning Alarm 1B pre-warning alarm occurred, 0B no pre-warning alarm occurred 0 [31:1] r reserved WDTCLR The status register contains sticky bitfield indicating occurrence of alarm condition. WDTCLR WDT Clear Register 31 30 29 28 (001CH ) 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 Reference Manual WDT, V1.0 12 11 10 9 8 0 ALM C r w 10-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Window Watchdog Timer (WDT) Field Bits Type Description ALMC 0 w Pre-warning Alarm 1B clears pre-warning alarm 0B no-action 0 [31:1] r reserved 10.10 Interconnects Table 10-4 Pin Table Input/Output I/O Connected To Description I SCU.CCU timer clock wdt_service O PORTS service indication to external watchdog HALTED I CPU In halting mode debug. HALTED remains asserted while the core is in debug. Clock and Reset Signals fWDT Timer Signals Service Request Connectivity wdt_alarm O SCU.GCU pre-warning alarm wdt_rst_req O SCU.RCU reset request Reference Manual WDT, V1.0 10-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) 11 Real Time Clock (RTC) Real-time clock (RTC) is a clock that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time in a digital format for clock displays and computer systems. 11.1 Overview The RTC module tracks time with separate registers for hours, minutes, and seconds. The calendar registers track date, day of the week, month and year with automatic leap year correction1). The clock of RTC is selectable via bit SCU_CLKCR.RTCCLKSEL. The timer may remains operational during sleep or deep sleep mode. 11.1.1 Features The features of the Real Time Clock (RTC) module are: • • • • Real time keeping with – 32.768 kHz internal clock Periodic time-based interrupt Programmable alarm interrupt on time match Supports wake-up mechanism from sleep or deep sleep mode Table 11-1 Application Features Feature Purpose/Application Precise real time keeping Reduced need for time adjustments Periodic time-based interrupt Scheduling of operations performed on precisely defined intervals Programmable alarm interrupt on time match Scheduling of operations performed on precisely defined times Supports wake-up mechanism from sleep Autonomous wakeups from sleep or deep or deep sleep mode sleep mode for system state control and maintaintenance routine operations 11.1.2 Block Diagram The RTC block diagram is shown in Figure 11-1. The main building blocks of the RTC is Time Counter implementing real time counter and RTC Registers containing multi-field registers for the time counter and alarm 1) The automatic leap year correction is performed when the year is divisible by 4. Reference Manual RTC, V2.3 11-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) programming register where dedicated fields represent a separate values for elapsing second, minutes, hours, days, days of week, months and years. The RTC module is controlled directly from SCU module and shares system bus interface with other sub-modulesof SCU. Access to the RTC registers is performed via Register Mirror updated over serial interface. Time Counter RTC alarm periodic_event Prescaler 32.768 kHz clock RTC Registers SCU Serial Interface Figure 11-1 Real Time Clock Block Diagram Structure 11.2 RTC Operation The RTC timer counts seconds, minutes, hours, days, days of week, months and years the time in separate fields (see Figure 11-2). Individual bit fields of the RTC counter can be programmed and read with software over serial interface via mirror registers in SCU module. Reference Manual RTC, V2.3 11-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) seconds minutes days hours months years Alarm Time (ATIM0 & ATIM1) = Real Time (TIM0 & TIM1) alarm days of week Prescaler 1 second tick seconds minutes days hours Periodic Service Request Logic months years periodic_event Figure 11-2 Block Diagram of RTC Time Counter Occurrence of an internal timer event is stored in the service request raw status register RAWSTAT. The values of the status register RAWSTAT drive the outgoing service request lines alarm and periodic_event. 11.3 Register Access Operations The RTC module is a part of SCU from programmming model perepcetive and shares register address space for configuration with other sub-modules of SCU. RTC registers are instantiated in the RTC module and mirrored in SCU. The registers get updated in both clock domains over serial interface running at 32kHz clock rate. Any update of the registers is performed with some delay required for data to propagate to and from the mirror registers over serial interface. Accesses to the RTC registers in core domain must not block the bus interface of SCU module. For details of the register mirror and serial communication handling please refer to SCU chapter. For consistent write to the timer registers TIM0 and TIM1, the register TIM0 has to be written before the register TIM1. Transfer of the new values from the register mirror starts only after both registers have been written. For consistent read-out of the timer registers TIM0 and TIM1, the register TIM0 has to be read before the register TIM1. The value of TIM1 is stored in a shadow register upon each read of TIM0 before they get copied to the mirror register in core domain. Reference Manual RTC, V2.3 11-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) 11.4 Service Request Processing The RTC generates service requests upon: • • periodic timer events configured alarm condition The service requests can be processed in the core domain as regular service requests or as wake-up triggers from sleep or deep sleep mode. 11.4.1 Periodic Service Request The periodic timer service request is raised whenever a non-masked field of the timer counter gets updated. Masking of the bits is performed using MSKSR register. Periodic Service requests can be disabled with MSKSR. 11.4.2 Timer Alarm Service Request The alarm interrupt is triggered when TIM0 and TIM1 bit fields values match all corresponding bit fields values of ATIM0, ATIM1 registers. The Timer Alarm Service requests can be enabled/disabled with the MSKSR register . 11.5 Debug Behavior The RTC function can be suspended when the CPU enters HALT mode. RTC debug function is controlled with SUS bit field in CTR register. Note: In XMC1100, bit CTR.SUS is reset to its default value by any reset. Hence, if suspend function is required during debugging, it is recommended to enable the debug suspend function in the user initialisation code. Before programming the register, the module clock has to be enabled and special care need to be handled while enabling the module clock as described in the CCU (Clock Gating Control) section of the SCU chapter. 11.6 Power, Reset and Clock RTC can be programmed to remains powered up in sleep and deep sleep mode. The RTC module remains in reset state after initial power up until reset released. The RTC timer is running from an internal 32.768 kHz clock. The prescaler setting of 7FFFH results in an once per second update of the RTC timer. The RTC module clock is default disabled and can be enabled via the SCU_CGATCLR0 register. Reference Manual RTC, V2.3 11-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) 11.7 Initialization and Control Sequence Programming model of the RTC module assumes several scenarios where different control sequences apply. Note: Some of the scenarios described in this chapter require operations on system level the that are not in the scope of the RTC module description, therefore for detailed information please refer to relevant chapters of this document. 11.7.1 Initialization & Start of Operation Complete RTC module initialization is required upon reset. Accesses to RTC registers are performed via dedicated mirror registers (for more details please refer to SCU chapter) • • • enable the clock to RTC module – write one to SCU_CGATCLR0.RTC program RTC_TIM0 and RTC_TIM1 registers with current time – check SCU_MIRRSTS to ensure that no transfer over serial interface is pending to the RTC_TIM0 and RTC_TIM1 registers – write a new value to the RTC_TIM0 and RTC_TIM1 registers enable RTC module to start counting time – write one to RTC_CTR.ENB Note: To ensure a successful transfer over serial interface, RTC_TIM0 and RTC_TIM1 can only be written once for each transfer. In addition, these registers must be written in 32-bit data width. Individual bit access will not start the serial transfer operation. 11.7.2 Configure and Enable Periodic Event The RTC periodic event configuration require programming in order to enable interrupt request generation out upon a change of value in the corresponding bit fields. • enable service request for periodic timer events in RTC module – set respective bit field (MPSE, MPMI, MPHO, MPDA, MPMO, MPYE) in RTC_MSKSR register to enable the individual periodic timer events 11.7.3 Configure and Enable Timer Event The RTC alarm event configuration require programming in order to enable interrupt request generation out upon compare match of values in the corresponding bit fields of TIM0 and TIM1 against ATIM0 and ATIM1 respectively. • program compare values in individual bit fields of ATIM0 and ATIM1 in RTC module – check SCU_MIRRSTS to ensure that no transfer over serial interface is pending to the RTC_ATIM0 and RTC_ATIM1 registers – write to RTC_ATIM0 and RTC_ATIM1 registers Reference Manual RTC, V2.3 11-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) • enable service request for timer alarm events in RTC module – set MAI bit field of RTC_MSKSR register in order enable individual periodic timer events Note: To ensure a successful transfer over serial interface, RTC_ATIM0 and RTC_ATIM1 can only be written once for each transfer. In addition, these registers must be written in 32-bit data width. Individual bit access will not start the serial transfer operation. 11.8 RTC Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 11-2 Registers Address Space Module Base Address End Address RTC 4001 0A00H 4001 0AFFH Table 11-3 Short Name Note Register Overview Description Offset Addr. Access Mode Description Read Write See RTC Kernel Registers ID ID Register 0000H U, PV BE Page 11-7 CTR Control Register 0004H U, PV PV Page 11-8 RAWSTAT Raw Service Request Register 0008H U, PV BE Page 11-8 STSSR Status Service Request Register 000CH U, PV BE Page 11-9 MSKSR Mask Service Request Register 0010H U, PV PV Page 11-10 CLRSR Clear Service Request Register 0014H U, PV PV Page 11-12 ATIM0 Alarm Time Register 0 0018H U, PV PV Page 11-13 ATIM1 Alarm Time Register 1 001CH U, PV PV Page 11-14 Reference Manual RTC, V2.3 11-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Table 11-3 Register Overview (cont’d) Short Name Description Offset Addr. Read Access Mode Description Write See TIM0 Time Register 0 0020H U, PV PV Page 11-15 TIM1 Time Register 1 0024H U, PV PV Page 11-16 11.8.1 Registers Description ID Read-only ID register of the RTC module containing unique identification code of the RTC module. ID RTC Module ID Register (00H) 31 30 29 28 27 26 25 24 Reset Value: 00A3 C0XXH 23 22 21 20 19 18 17 16 5 4 3 2 1 0 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV [7:0] r Module Revision Number Indicates the revision number of the implementation. The value of a module revision starts with 01H (first revision). MOD_TYPE [15:8] r Module Type This bit field is fixed to C0H. r Module Number Value This bit field defines the module identification number. MOD_NUMBER [31:16] Reference Manual RTC, V2.3 11-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) CTR RTC Control Register providing control means of the operation mode of the module. CTR RTC Control Register 31 30 29 28 (04H) 27 26 25 24 Reset Value: 7FFF 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DIV rw 15 14 13 0 r 12 11 10 9 8 7 0 r r r 0 r r r r r SUS ENB r rw rw Field Bits Type Description ENB 0 rw RTC Module Enable 0B disables RTC module 1B enables RTC module SUS 1 rw Debug Suspend Control 0B RTC is not stopped during halting mode debug 1B RTC is stopped during halting mode debug DIV [31:16] rw Divider Value reload value of RTC prescaler. Clock is divided by DIV+1. 7FFFH is default value for RTC mode with 32.768 kHz clock 0 [15:2] r Reserved Read as 0; should be written with 0 RAWSTAT RTC Raw Service Request Register contains raw status info i.e. before status mask takes effect on generation of service requests or iterrupts. This register serves debug purpose but can be aslo used for polling of the status withou generating serice requests. Reference Manual RTC, V2.3 11-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) RAWSTAT RTC Raw Service Request Register 31 30 29 28 27 26 25 (08H) 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 0 RAI 0 r rh r 0 r 15 14 13 12 11 10 9 RPY RPM E O rh rh 0 r RPD RPH RPM RPS A O I E rh rh rh rh Field Bits Type Description RPSE 0 rh Raw Periodic Seconds Service Request Set whenever seconds count increments RPMI 1 rh Raw Periodic Minutes Service Request Set whenever minutes count increments RPHO 2 rh Raw Periodic Hours Service Request Set whenever hours count increments RPDA 3 rh Raw Periodic Days Service Request Set whenever days count increments RPMO 5 rh Raw Periodic Months Service Request Set whenever months count increments RPYE 6 rh Raw Periodic Years Service Request Set whenever years count increments RAI 8 rh Alarm Service Request Set whenever count value matches compare value 0 4, 7, [31:9] r Reserved STSSR RTC Service Request Status Register contains status info reflecting status mask effect on generation of service requests or iterrupts. This register needs to be accessed by software in order to determine the actual cause of an event. Reference Manual RTC, V2.3 11-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) STSSR RTC Service Request Status Register (0CH) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 0 SAI 0 r rh r 0 r 15 14 13 12 11 10 9 SPY SPM E O rh rh 0 r SPS SPD SPH SPMI E A O rh rh rh rh Field Bits Type Description SPSE 0 rh Periodic Seconds Service Request Status after masking SPMI 1 rh Periodic Minutes Service Request Status after masking SPHO 2 rh Periodic Hours Service Request Status after masking SPDA 3 rh Periodic Days Service Request Status after masking SPMO 5 rh Periodic Months Service Request Status after masking SPYE 6 rh Periodic Years Service Request Status after masking SAI 8 rh Alarm Service Request Status after masking 0 4, 7, [31:9] r reserved MSKSR RTC Service Request Mask Register contains masking value for generation control of service requests or iterrupts. Reference Manual RTC, V2.3 11-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) MSKSR RTC Service Request Mask Register (10H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 0 MAI 0 r rw r 0 r 15 14 13 12 11 10 9 MPY MPM E O rw rw 0 MPD MPH MPM MPS A O I E r rw Field Bits Type Description MPSE 0 rw Periodic Seconds Interrupt Mask 0B disable interrupt 1B enable interrupt MPMI 1 rw Periodic Minutes Interrupt Mask 0B disable interrupt 1B enable interrupt MPHO 2 rw Periodic Hours Interrupt Mask 0B disable interrupt 1B enable interrupt MPDA 3 rw Periodic Days Interrupt Mask 0B disable interrupt 1B enable interrupt MPMO 5 rw Periodic Months Interrupt Mask 0B disable interrupt 1B enable interrupt MPYE 6 rw Periodic Years Interrupt Mask 0B disable interrupt 1B enable interrupt MAI 8 rw Alarm Interrupt Mask 0B disable interrupt 1B enable interrupt 0 4, 7, [31:9] r Reserved Reference Manual RTC, V2.3 11-11 rw rw rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) CLRSR RTC Clear Service Request Register serves purpose of clearing sticky bits of RAWSTAT and STSSR registers. Write one to a bit in order to clear the status bit. Writing zero has no effect on the set nor reset bits. CLRSR RTC Clear Service Request Register (14H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 8 7 6 5 4 3 2 1 0 0 RAI 0 r w r 0 r 15 14 13 12 11 10 9 RPY RPM E O w w 0 r RPD RPH RPM RPS A O I E w w w Field Bits Type Description RPSE 0 w Raw Periodic Seconds Interrupt Clear 0B no effect 1B clear status bit RPMI 1 w Raw Periodic Minutes Interrupt Clear 0B no effect 1B clear status bit RPHO 2 w Raw Periodic Hours Interrupt Clear 0B no effect 1B clear status bit RPDA 3 w Raw Periodic Days Interrupt Clear 0B no effect 1B clear status bit RPMO 5 w Raw Periodic Months Interrupt Clear 0B no effect 1B clear status bit RPYE 6 w Raw Periodic Years Interrupt Clear 0B no effect 1B clear status bit Reference Manual RTC, V2.3 11-12 w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Field Bits Type Description RAI 8 w Raw Alarm Interrupt Clear 0B no effect 1B clear status bit 0 4, 7, [31:9] r Reserved ATIM0 RTC Alarm Time Register 0 serves purpose of programming single alarm time at a desired point of time reflecting comparison against TIM0 register. The ATM0 register contains portion of bit fields for seconds, minutes, hours and days. Upon attempts to write an invalid value to a bit bield e.g. exceeding maximum value a default value gets programmed as described for each individual bit fields. ATIM0 RTC Alarm Time Register 0 31 30 15 29 28 27 26 (18H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 0 ADA 0 AHO r rw r rw 14 13 12 11 10 9 8 7 6 5 4 3 2 0 AMI 0 ASE r rw r rw 17 16 1 0 Field Bits Type Description ASE [5:0] rw Alarm Seconds Compare Value Match of seconds timer count to this value triggers alarm seconds interrupt. Setting value equal or above 3CH results in setting the field value to 0H AMI [13:8] rw Alarm Minutes Compare Value Match of minutes timer count to this value triggers alarm minutes interrupt. Setting value equal or above 3CH results in setting the field value to 0H Reference Manual RTC, V2.3 11-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Field Bits Type Description AHO [20:16] rw Alarm Hours Compare Value Match of hours timer count to this value triggers alarm hours interrupt. Setting value equal or above 18H results in setting the field value to 0H ADA [28:24] rw Alarm Days Compare Value Match of days timer count to this value triggers alarm days interrupt. Setting valueequal above 1FH results in setting the field value to 0H 0 [7:6], [15:14], [23:21], [31:29] r Reserved ATIM1 RTC Alarm Time Register 1 serves purpose of programming single alarm time at a desired point of time reflecting comparison against TIM1 register. The ATM1 register contains portion of bit fields for months and years. Upon attempts to write an invalid value to a bit bield e.g. exceeding maximum value a default value gets programmed as described for each individual bit fields. ATIM1 RTC Alarm Time Register 1 31 30 29 28 27 (1CH) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 AYE rw 15 14 13 12 11 10 9 8 7 0 AMO 0 r rw r Reference Manual RTC, V2.3 11-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Field Bits Type Description AMO [11:8] rw AYE [31:16] rw Alarm Year Compare Value Match of years timer count to this value triggers alarm years interrupt. 0 [7:0], r [15:12] Reserved Alarm Month Compare Value Match of months timer count to this value triggers alarm month interrupt. Setting value equal or above the number of days of the actual month count results in setting the field value to 0H TIM0 RTC Time Register 0 contains current time value for seconds, minutes, hours and days. The bit fields get updated in intervals corresponding with their meaning accordingly. The register needs to be programmed to reflect actual time after initial power up and will continue counting time also while in sleep or deep sleep mode if enabled. Upon attempts to write an invalid value to a bit bield e.g. exceeding maximum value a default value gets programmed as described for each individual bit fields. TIM0 RTC Time Register 0 31 30 15 29 28 (20H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 0 DA 0 HO r rwh r rwh 14 13 12 11 10 9 8 7 6 5 4 3 2 0 MI 0 SE r rwh r rwh Reference Manual RTC, V2.3 11-15 17 16 1 0 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Field Bits Type Description SE [5:0] rwh Seconds Time Value Setting value equal or above 3CH results in setting the field value to 0H. Value can only be written, when RTC is disabled via bit CTR.ENB. MI [13:8] rwh Minutes Time Value Setting value equal or above 3CH results in setting the field value to 0H. Value can only be written, when RTC is disabled via bit CTR.ENB. HO [20:16] rwh Hours Time Value Setting value equal or above 18H results in setting the field value to 0H Value can only be written, when RTC is disabled via bit CTR.ENB. DA [28:24] rwh Days Time Value Setting value equal or above the number of days of the actual month count results in setting the field value to 0H Value can only be written, when RTC is disabled via bit CTR.ENB. Days counter starts with value 0 for the first day of month. 0 [7:6], r [15:14], [23:21], [31:29] Reserved TIM1 RTC Time Register 1 contains current time value for days of week, months and years. The bit fields get updated in intervals corresponding with their meaning accordingly. The register needs to be programmed to reflect actual time after initial power up and will continue counting time also while in sleep or deep sleep if enabled. Upon attempts to write an invalid value to a bit bield e.g. exceeding maximum value a default value gets programmed as described for each individual bit fields. Reference Manual RTC, V2.3 11-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) TIM1 RTC Time Register 1 31 30 29 28 (24H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 YE rwh 15 14 13 12 11 10 9 8 7 0 MO 0 DAWE r rwh r rwh Field Bits Type Description DAWE [2:0] rwh Days of Week Time Value Setting value above 6H results in setting the field value to 0H Value can only be written, when RTC is disabled via bit CTR.ENB. Days counter starts with value 0 for the first day of week. MO [11:8] rwh Month Time Value Setting value equal or above CH results in setting the field value to 0H. Value can only be written, when RTC is disabled via bit CTR.ENB. Months counter starts with value 0 for the first month of year. YE [31:16] rwh Year Time Value Value can only be written, when RTC is disabled. 0 [7:3], [15:12] r Reserved 11.9 Interconnects Reference Manual RTC, V2.3 11-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Real Time Clock (RTC) Table 11-4 Pin Connections Input/Output I/O Connected To Description I SCU.CCU 32.768 kHz clock selected I CPU Indicates the processor is in debug state and halted Clock Signals fRTC Debug Signals HALTED Service Request Connectivity periodic_event O SCU.GCU Timer periodic service request alarm O SCU.GCU Alarm service request Reference Manual RTC, V2.3 11-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12 System Control Unit (SCU) The SCU is the SoC power, reset and a clock manager with additional responsibility of providing system stability protection and other auxiliary functions. 12.1 Overview The functionality of the SCU described in this chapter is organized in the following subchapters, representing different aspects of system control: • • • • Miscellaneous control functions, GCU Chapter 12.2 Power control, PCU Chapter 12.3 Reset operation, RCU Chapter 12.4 Clock Control, CCU Chapter 12.5 12.1.1 Features The following features are provided for monitoring and controlling the system: • • • • General Control – Start-up Software (SSW) and Boot Mode Support – Memory Content Protection – Interrupt Handling Power control – On-chip core supply generation via EVR – Power Validation – Supply Watchdog – Voltage Monitoring – Load Change Handling Reset Control – Reset assertion on various reset request sources – System Reset Generation – Inspection of reset sources after reset Clock Control – Clock Generation – Clock Supervision – Individual Peripheral Clock Gating – Clock Blanking Support Reference Manual SCU, V1.1 12-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.1.2 Block Diagram Figure 12-1 shows the following sub-units: • • • • Power Control Unit (PCU) Reset Control Unit (RCU) Clock Control Unit (CCU) General Control Unit (GCU) All the SFRs in SCU module are accessible via the AHB and the 16-bit APB bus interface as shown in Figure 12-1.The APB bus interface is used to access the group of SFR called ANACTRL register. These registers are used to configure the analog modules in the system, namely, the embedded voltage regulator (EVR) and the digitally controlled oscillators (DCO1 and DCO2). The other group of SFR called SCU register are accesible via the AHB bus interface. Bus Interface AHB Interface APB Interface SCU Register ANACTRL Register Parity Error Service Requests RTC Interface GCU Interrupt Signals to NVIC EVR Module RTC Module PCU I/O Control DCOx Module Clock Signals Reset Requests CCU RCU Reset Signals Figure 12-1 SCU Block Diagram Reference Manual SCU, V1.1 12-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Interface of General Control Unit The General Control Unit GCU has a memory fault interface to the memory validation logic of each on-chip SRAM and the Flash to receive memory fault events, as parity errors. Interface of Power Control Unit The Power Control Unit PCU has an interface to the Embedded Voltage Regulator (EVR) and an interface to the CCU module. The PCU related signals are described in more detail in Chapter 12.3. Interface of Reset Control Unit The Reset Control Unit RCU has an interface to the Embedded Voltage Regulator (EVR). The RCU receives the power-on reset and the brownout reset information from the EVR. Reset requests are coming to the unit from the watchdog, the CPU, the GCU and the clock control unit (CCU). The RCU is providing the reset signals to all other units of the chip in the core power domain. The RCU related signals are described in more detail in Chapter 12.4. Interface of Clock Control Unit The Clock Control Unit (CCU) receives the clock source from the on-chip Digitally Controlled Oscillator (DCO). The CCU provides the clock signals to all other units of the chip. Interface of RTC Access to the RTC module is served over a serial interface. The interface provides mirror registers updated via the serial interface to the RTC module registers. Update of the mirror registers over the serial is controlled using MIRRSTS registers. End of update can also trigger service requests via SRRAW register. Refresh of the registers in the register mirror are performed continuously, as fast as possible in order to instantly reflect any register state change on both sides. The RTC module functionality is described in separate RTC chapter. Reference Manual SCU, V1.1 12-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.2 Miscellaneous Control Functions (GCU) System Control implements system management functions accessible via GCU registers. General system control including various auxillary function is performed in the General Control Unit (GCU). 12.2.1 Service Requests Handling Service request events listed in Table 12-1 can result in assertion of an interrupt. Please refer to SRMSK a register description. The interrupt structure is shown in Figure 12-2. The interrupt request or the corresponding interrupt set bit (in register SRSET) can trigger the interrupt generation at the selected interrupt node x. The service request pulse is generated independently from the interrupt flag in register SRRAW. The interrupt flag can be cleared by software by writing to the corresponding bit in register SRCLR. SRCLR.x SRSET.x SRMSK.x clear SRRAW.x Service Request Event x set set 1 raw request & request to IRQ request combined output Figure 12-2 Service Request Handling The flag in register SRRAW can be cleared by software by writing to the corresponding bit in register SRCLR. All trap requests are combined to one common line and connected to a regular interrupt node of NVIC. Note: When servicing an SCU service request, make sure that all related request flags are cleared after the identified request has been handled. 12.2.1.1 Service Request Sources The SCU supports service request sources listed in Table 12-1 and reflected in the SRRAW, SRMSK, SRCLR and SRSET registers. The events that trigger these service Reference Manual SCU, V1.1 12-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) requests are described in the respective module chapters or in the various sections within SCU. Table 12-1 Service Requests Modules Service Request Name Service Request Short Name SCU.SRx NVM Flash Double Bit ECC Event FLECC2I SR0 Flash Operation Complete Event FLCMPLTI 16kbytes SRAM Parity Error Event PESRAMI SCU:CCU SCU:PCU SCU:GCU WDT RTC 12.2.2 USIC0 SRAM Parity Error Event PEU0I Loss of Clock Event LOCI Standby Clock Failure Event SBYCLKFI VDDP Pre-warning Event VDDPI VDROP Event VDROPI VCLIP Event VCLIPI Temperature Sensor Done Event TSE_DONE Temperature Sensor Compare High Event TSE_HIGH Temperature Sensor Compare Low Event TSE_LOW WDT pre-warning PRWARN RTC Periodic Event PI RTC Alarm AI RTC CTR Mirror Register Updated RTC_CTR RTC ATIM0 Mirror Register Updated RTC_ATIM0 RTC ATIM1 Mirror Register Updated RTC_ATIM1 RTC TIM0 Mirror Register Updated RTC_TIM0 RTC TIM1 Mirror Register Updated RTC_TIM1 SR1 SRAM Memory Content Protection For supervising the content of the on-chip SRAM memories, the following mechanism is provided: All on-chip SRAMs provide protection of content via parity checking. The parity logic generates additional parity bits which are stored along with each data word at a write operation. A read operation implies checking of the previous stored parity information. Reference Manual SCU, V1.1 12-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) An occurrence of a parity error is observable at the SRRAW status register. It is configurable via SRMSK whether a memory error should trigger an interrupt. It can also trigger a system reset when RSTCON.SPERSTEN or RSTCON.U0PERSTEN is set to 1. A parity control software test, such as to support in-system testing to fulfill Class B requirements, can be enabled with bit PMTSR.MTENS for the 16 kbytes SRAM memory individually. Once this bit is set, an inverted parity bit is generated during a write operation. When a read operation is performed on this SRAM address, a parity error shall be detected. Note: Test software should be located in a different memory space. 12.2.3 Summary of ID This section describes the various ID in XMC1100. Module Identification The module identification register indicates the function and the design step of each peripherals. Register SCU_ID is used for SCU module. System ROM Table ID The PID values in the system ROM table are defined in the Table 12-2. The XMC1100 system ROM table is located at F000 0000H. Cortex-M0 ROM table is described in the debug chapter. Table 12-2 PID Values of XMC1100 System ROM Table Name Offset Reference Values PID0 FE0H XMC1100 Part Number [7:0] EDH PID1 FE4H bits [7:4] JEP106 ID code [3:0] bits [3:0] XMC1100 Part Number [11:8] 11H PID2 FE8H bits [7:4] XMC1100 Revision bit [3] == 1: JEDEC assigned ID fields bits [2:0] JEP106 ID code [6:4] 1CH PID3 FECH bits [7:4] RevAnd, minor revision field bits [3:0] if non-zero indicate a customer-modified block 00H PID4 FD0H bits [7:4] 4KB count bits [3:0] JEP106 continuation code 00H Reference Manual SCU, V1.1 12-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Chip Identification Number The chip identification number is a 8 word length number. It consists of the values in register DBGROMID, IDCHIP, register PAU_FLSIZE, register PAU_RAM0SIZE and register PAU_AVAILn(n=0-2) respectively. This number is for easy identification of product variants information of the device, example, package type, the temperature profile, flash size, RAM size and the peripheral availability. Reference Manual SCU, V1.1 12-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.3 Power Management (PCU) Power management control is performed in the Power Control Unit (PCU). 12.3.1 Functional Description The XMC1100 is running from a single external power supply of 1.8 - 5.5V (VDDP). The main supply voltage is supervised by a supply watchdog. The I/Os is running directly from the external supply voltage. The core voltage (VDDC) is generated by an on-chip Embedded Voltage Regulator (EVR). The safe voltage range of the core voltage is supervised by a power validation circuit, which is part of the EVR. 12.3.2 System States The system has the following general system states: • • • • Off Active Sleep Deep-Sleep Figure 12-3 shows the state diagram and the transitions between the states. Sleep Wake-up Event Sleep Request Deep Sleep Request Off Cold/Warm startup Active Deep Sleep Wake-up Event Figure 12-3 System States Diagram Reference Manual SCU, V1.1 12-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Active State The active state is the normal operation state. The system is fully powered. The CPU is usually running from a high-speed clock. Depending on the application, the system clock might be slowed down. Unused peripherals might be stopped by gating the clock to these peripherals. Sleep State The sleep state of the system corresponds to the sleep state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state, the clock to the CPU is stopped. To save power, the clock of the peripherals that are not needed during sleep state can be gated by register CGATSET0 before entering sleep state. The Flash can be put into shutdown mode during active state to achieve a further power reduction before entering sleep state via bit NVMCONF.NVM_ON. However, user code would have to be executed in SRAM before entering sleep state and after waking up from sleep state. To avoid the switching of code execution to SRAM due to the shutdown of flash, register PWRSVCR can be used. When FPD bit is set, flash is shutdown only when the device has entered sleep state. The shut down operation is performed after the core has executed WFI/WFE instruction. After a wake-up event is detected, the system will resumed to the previous state i.e. the flash is operable again before the CPU can continue to fetch and execute the code. In this case, user code can be executed in Flash and no switching to SRAM in needed. In his approach, the wake-up time is longer because of the time needed for flash to reach the active state. Peripherals can continue to operate unaffected and eventually generate an event to wake-up the CPU. In User with Debug mode (UMD) or User with Debug mode and HAR (UMHAR), a Debug HALT request is also able to wake-up the CPU. Any accordingly configured interrupt will bring the CPU back to operation via the NVIC or the M0 debug system. Deep-Sleep State The deep-sleep state is entered on the same mechanism as the sleep state with the addition that user code has enabled the deep-sleep state in system control register. This state is similiar to sleep state, except that in deep-sleep state, the PCLK and MCLK will be switched to a slow standby clock and DCO1 will be put into power-down mode. The shutting down of flash via NVMCONF.NVM_ON or PWRSVCR.FPD as explained in above section is applicable for deep-sleep mode. Peripherals that continue to operate will run using the slow standby clock and can eventually generate an event to wake-up the CPU. In User with Debug mode (UMD) or User with Debug mode and HAR (UMHAR), a Debug HALT request is also able to wakeup the CPU. Any accordingly configured interrupt will bring the CPU back to operation Reference Manual SCU, V1.1 12-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) via the NVIC or the M0 debug system. The clock system is restored to the previous configuration for active state upon wake-up. Peripherals that are active will run with restored clock configuration. The SRAM content is preserved in the deep-sleep state. Note: It is recommended to slow down the PCLK and MCLK before entering deep sleep mode to prevent a sudden load change that could cause a brownout reset. 12.3.3 Embedded Voltage Regulator (EVR) The EVR generates the core voltage VDDC out of the external supplied voltage VDDP. The EVR provides 2 supply monitoring detectors for the input voltage VDDP. The generated core voltage VDDC is monitored by a power validation circuit (PV). 12.3.4 Power-on Reset The EVR starts operation as soon as VDDP is above defined minimum level. It releases the reset, when the external voltage VDDP and the generated voltage VDDC are above the reset thresholds and reaching the nominal values. 12.3.5 Power Validation A power validation circuit monitors the internal core supply voltage,VDDC. It monitors that the core voltage is above the voltage threshold VDDCBO which guarantees safe operation. Whenever the voltage falls below the threshold level, a brownout reset is generated. 12.3.6 Supply Voltage Monitoring There are 2 detectors, namely, External voltage detector (VDEL) and External brownout detector (BDE) in the EVR that are used to monitor the VDDP. VDEL detector compares the supply voltage against a pre-warning threshold voltage. The threshold level is programmable via register ANAVDEL.VDEL_SELECT. An interrupt if enabled, will be triggered if a level below this threshold is detected and the flag, VDDPI, in SRRAW register bit is set. An indication bit, VDESR.VDDPPW, shows the output of the detector. During power-up, this indication bit can be polled to ensure that the external supply has reached the pre-warning voltage before starting the application code. BDE detector is used to trigger a brownout reset when the VDDP supply voltage drops below the defined threshold. Similiarly, it is also used to ensure a proper startup during the power-up phase. The Data Sheet defines the nominal value and applied hysteresis Reference Manual SCU, V1.1 12-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.3.7 VDDC Response During Load Change In XMC1100, the core voltage level, VDDC, drops below the typical threshold when there is an increase in the load and rises when there is a decrease in the load. 2 detectors, VDROP and VCLIP detectors are used to montior the lower limits and the upper limits of the core voltage level respectively (detectors details are described in the next section). A VDROP event happens when VDDC drops below the VDROP threshold voltage. A VCLIP event happens when VDDC rises above the VCLIP threshold voltage. Each of these events can triggered it’s dedicated interrupt if enabled via SRMSK register and the event status can be monitior via SRRAW register. In XMC1100, the following scenarios may trigger a VDROP/VCLIP event due to load change: • • Changing the MCLK and PCLK frequency via CLKCR register Enabling/Gating the peripheral clock via the CGATSET0/CGATCLR0 registers When a sudden load change happens (< 4*baseload or > 0.25*baseload), irregardless of an increase or decrease in load, the EVR needs time (15 usec) to regulate the core voltage back to a stable nominal voltage. During this period of time, the system is expected to maintain in the current load and no load change is allowed. Status bit VDDC2LOW and VDDC2HIGH in CRCLK register are used to indicate whether the voltage is stable. Note: It is not recommended to increase the load more than 4 times of the baseload or decrease the load to less than 0.25 times of the baseload. If a bigger than the specified load change is required, the recommendation is to change the load in steps that each steps are within the limits. For example, a final load of 16mA from the current baseload of 1mA needs at least 2 steps. A step from 1mA to 4mA followed by another step from 4mA to 16mA The VDDC2LOW and VDDC2HIGH status bit is generated by a 10-bit counter using DCO1, 64MHz clock as the clock input. It is implemented to count the 16 usec (default) that is needed to have a stable VDDC after a VDROP or VCLIP event happens. The length of this counter can be changed depending on the amount of load change via bit CLKCR.CNTADJ. The larger is the load change, the more is the time that user need to wait for a stable clock. Refer to datasheet for a guideline of the current consumption of each modules. Using the example above, after programming some configuration that causes a change in load from 1mA to 4mA, user can poll for VDDC2LOW (CNTADJ=3FFH) to ensure the 16 usec(max) needed to regulate EVR. After VDDC2LOW is set to 0, another load change from 4mA to 16mA can be performed and the cycle repeats for each step of load change. During a VDROP event, clock blanking happens and the detail description is documented in “Clock Blanking” on Page 12-17. CPU clock and peripheral clocks continue to run during VCLIP event. Reference Manual SCU, V1.1 12-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Note: When overflow event happens while the VDROP=1 (time to overflow based on the CNTADJ value is shorter than the time the device stays in a vdrop event), the 10bit counter will automatically be restarted with the CNTADJ value. Note: VDROP and VCLIP detectors are disabled during deep sleep mode. 12.3.8 Flash Power Control The Flash module can be switched off to reduce static power. In sleep or deep-sleep state, it is dependent on the setting of register PWRSVCR whether the Flash module will be put to sleep or not in this state. The user has to evaluate the reduced leakage current against the longer startup time. In addition, the Flash can also be put to sleep using NVMCONF.NVM_ON before entering these power save modes. Reference Manual SCU, V1.1 12-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.4 Reset Control (RCU) Reset Control Unit performs control of all reset related functionality including: • • • Reset assertion on various reset request sources Inspection of reset sources after reset Selective reset of peripheral 12.4.1 Functional Description The XMC1100 has the following reset types for the system: • • Master Reset, MRESET System Reset, SYSRESET Master Reset, MRESET Master reset is triggered by: • • • Power-on reset (PORST) VDDP or VDDC undervoltage reset (also known as brownout reset) SW master reset via setting bit RSTCON.MRSTEN to 1 A complete reset to the device is executed by a master reset. Master reset is triggered by a power-on reset upon power-up. Whenever the supply VDDP is ramped-up and crossing the VDDP and VDDC voltage threshold, the power-on reset is released. A poweron reset (also known as brown-out reset) is asserted again whenever the VDDP voltage or the VDDC voltage falls below reset thresholds. In additional, a master reset can be triggered by setting bit RSTCON.MRSTEN. The sources that trigger a master reset also triggers a system reset SYSRESET. System Reset, SYSRESET System reset is triggered by: • • • • • • • SW reset via Cortex M0 Application Interrupt and Reset Control Register (AIRCR) Lockup signal from Cortex M0 when enabled at RCU Watchdog reset Memory parity error when enabled Flash ECC double bit error when enabled Loss of clock when enabled sources that trigger a master reset A system reset affects almost all logics. The only exceptions are RCU registers and Debug system when debug probe is present. The reset gets extended to the length defined by implementation requirements. The debug system is reset by System Reset in normal operation mode when debug probe is not present. When debug probe is present, System Reset must not affect the Debug system. Reference Manual SCU, V1.1 12-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.4.2 Reset Status The EVR provides the cause of a power on reset to the RCU. The reset cause can be inspected after resuming operation by reading register RSTSTAT. This register also indicates the source of event that causes the triggering of a system reset. All registers of the RCU undergo reset only by a master reset except for RSTSTAT and RSTCON register. RSTSTAT register is only reset by a power-on reset and RSTCON is reset by any reset type. Note: Clearing of the reset status via register bit RSTCLR.RSCLR is strongly recommended to ensure a clear indication of the cause of next reset. Table 12-3 shows an overview of the reset signals their source and effects on the various parts of the system. Table 12-3 Reset Overview Module/Function Power-on Reset Master Reset by System Reset SW bit CPU Core yes yes yes SCU yes yes yes, except reset indication bit Peripherals yes yes yes Debug System yes yes see footnote1)2) Port Control yes yes yes SRAM Affected,unreliable Not affected Not affected Flash yes yes yes EVR yes no3) no Clock System yes yes yes 1) Debug system will be reset only if debug probe is not present. 2) Access to debug interface is disabled after every reset even when debug probe is present. See Warm Reset section of Debug System chapter for more details. 3) The supply to EVR will not be affected and hence a complete reset to EVR is not possible. However, it will be partially affected by the reset in the ANACTRL module. Reference Manual SCU, V1.1 12-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.5 Clock Control (CCU) 12.5.1 Features The clock control unit CCU has the following functionality: • • • • Dedicated RTC and standby clock Clock Supervisory – Oscillator watchdog Wide range of frequency scaling of system frequencies Individual peripheral clock gating 12.5.2 Clock System and Control Figure 12-4 shows the block diagram of the clock system in XMC1100. It consists of two oscillator (DCO11) and DCO2) and a clock control unit (CCU). DCO1 has a clock output, dco1_dclk running at 64MHz. DCO2 is used to generate the standby clock running at 32.768kHz. The main clock, MCLK, and fast peripherial clock, PCLK, are generated from dco1_dclk. PCLK is running in either the same frequency as MCLK or double the frequency of MCLK. It is selectable via CLKCR.PCLKSEL. Figure 12-4 shows the list of peripherals that are running in the PCLK domain. The rest of the peripherals except RTC and WDT are clocked by MCLK which is the same as the core and bus system. RTC and WDT is running at a frequency of 32.768kHz from the standby clock which is asychronous to the MCLK and PCLK clock. 1) The accuracy of the DCO1 clock output can be improved by calibrating it based on the die temperatue given by the temperature sensor. Refer to Section 12.5.4 for detailed description Reference Manual SCU, V1.1 12-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) EVR Clock blanking SCU CCU CLKCR.PCLKSEL 64MHz DCO1 dco1_dclk Clock blanking Fractional divider n:256 PCLK CCU40 Divide by 2 Oscillator Watchdog MCLK Divider by 2 Reserved Reserved DCO2 32.768 kHz Standby Clock CPU & rest of the IPs SHS0 (ADC) rtc_clock RTC wdt_clock WDT CLKCR.RTCCLKSEL Figure 12-4 Clock System Block Diagram Note: SHS(ADC) clock will not switched to standby clock source when there is a loss of clock event. Reference Manual SCU, V1.1 12-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Fractional Divider The frequency of MCLK and PCLK are programmable through a fractional divider. PCLK has a range of frequency from 125kHz to 64MHz and MCLK has a range from 125kHz to 32MHz. The following formula calculate the MCLK clock frequency. (12.1) ⎛ ⎞ ⎜ ⎟ dco_dclk ⎜ MCLK = -------------------------------------------------------⎟ for IDIV > 0 FDIV ⎜ ( 2 ) × ⎛ IDIV + ---------------⎞ ⎟⎠ ⎝ ⎝ 256 ⎠ The following formula calculate the PCLK clock frequency when CLKCR.PCLKSEL is set to 1 and it is double the frequency of MCLK. (12.2) ⎛ ⎞ ⎜ ⎟ dco_dclk ⎜ PCLK = ----------------------------------------⎟ for IDIV > 0 ⎜ ⎛ IDIV + FDIV ---------------⎞ ⎟⎠ ⎝ ⎝ 256 ⎠ IDIV represents an unsigned 8-bit integer from the bit field CLKCR.IDIV and FDIV/256 defines the fractional divider selection in CLKCR.FDIV. Changing of the MCLK and PCLK can be done within 2 clock cycles. While changing the frequency of MCLK clock and PCLK clock, it is recommended to disable all interrupts to prevent any access to flash that may results in an unsuccessful flash operation. Note: Changing the MCLK and PCLK frequency may result in a load change that causes clock blanking to happen. Refer to Clock Blanking and VDDC Response During Load Change for more details. Clock Blanking To prevent a brown-out reset in case of a sudden positive load change, the clock blanking circuitry is used. It freezed the clock input to the fractional divider to regulate the Reference Manual SCU, V1.1 12-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) load change. The clock blanking only causes a small jitter if it is considered over a longer time period. The clock blanking is activated when VDDC is detected to be below the VDROP threshold. Once the VDDC is above this threshold, the enabled clocking is resume. This voltage drop detector is part of the EVR and it is activated by default upon any reset. To monitor clock blanking activities, user can enable interrupt but can only enter ISR after the clock resume. In addition to the use of clock blanking function to prevent a brown-out reset, the system is also expected to maintain in the current load and no further load change is allowed for 16 usec (max). Detail description of the core voltage behaviors during load change are described in “VDDC Response During Load Change” on Page 12-11. As described in “VDDC Response During Load Change” on Page 12-11, the status bit CLKCR.VDDC2LOW is used to indicate to user that the core voltage, VDDC, is below the nominal voltage and EVR is in the process of regulating it. During this period, the clock could be also not running in the selected speed and it is recommended to poll this bit before continuing with any large change to the current load. Note: It is recommended to slow down the PCLK and MCLK before entering deep sleep mode to prevent a sudden load change that could cause a brownout reset when entering . 12.5.2.1 Oscillator Watchdog The oscillator watchdog (OWD) monitors the DCO1 clock frequency using the standby clock as the reference clock. It can be disabled via OSCCSR.OWDEN. By setting bit OSCCSR.OWDRES1), the detection for DCO1 clock frequency can be restarted. The detection status output is only valid after some cycles of the standby clock frequency. When the OWD is disabled, the detection status will be reset and no detection is possible. If the OWD is enabled before entering deep sleep mode, it will be disabled automatically by hardware when it enters deep sleep mode and re-enabled again after exiting deep sleep mode. The detection is reset and restarted after device wake-up from deep sleep mode. 12.5.2.2 Loss of Clock Detection and Recovery Loss of clock happens when the oscillator watchdog (OWD) detects a DCO1 frequency that is less than 50 MHz or more than 68.5 MHz during normal operation. In this case, 1) It is recommended to clear the status bit SRRAW.LOCI and SRRAW.SBYCLKFI before restarting the detection. Reference Manual SCU, V1.1 12-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) an interrupt will be generated if it is enabled. Concurrently, the oscillator status flag, OSCCSR.OSC2L or OSCCSR.OSC2H, is set to 1 and the system clock will be provided by the standby clock of 32.768kHz. Emergency routines can be executed to safely shut down the system. Beside triggering an interrupt when the loss of clock happens, a system reset can also be triggered if it is enabled by RSTCON.LOCRSTEN. Note: Switching to standby clock during loss of clock event happens only if DCO2 is still running (>0MHz). Bit SRRAW.SBYCLKFI indicates the fail status of the standby clock. The XMC1100 remains in this loss of clock state until the next reset or after a successful clock recovery has been performed. A clock recovery could be carried out by restarting the detection by setting bit OSCCSR.OWDRES. Upon detecting a stable oscillator frequency of more than 50 MHz and lower than 68.5MHz, OSC2L and OSC2H will be set to 0 and the MCLK will switched automatically to the DCO1 clock source. 12.5.2.3 Standby Clock Failure The standby clock failure event happens when the OWD detects a failure in standby clock where the clock stops running (~0kHz). Bit SRRAW.SBYCLKFI is set to 1 and trigger an interrupt via SCU_SR1 service request if the interrupt is enabled in register SRMSK. 12.5.2.4 Startup Control for System Clock When the XMC1100 starts up after reset, system frequency is provided by the DCO1 oscillator. After reset, CPU runs in 8MHz, default frequency. User can change the clock frequency that is used to execute the SSW and the user application code by defining it in the flash memory location 1000 1010H. This feature allows the fexibility of device performance e.g. speed vs power consumption optimisation during start-up. For details, please refer to the section “Clock system handling by SSW” in the “Boot and Startup” chapter. 12.5.3 Clock Gating Control The clock to peripherals can be individually gated and parts of the system can be stopped by registers CGATSET0. After a master reset, only core, memories, SCU and PORT peripheral are not clock gated. The rest of the peripherals are default clock gated. User can select the clock of individual modules to be enabled by SSW after reset by defining it in the flash memory location 1000 1014H. Refer to Boot and Startup chapter for more details. Load change during module clock enabling or gating Enabling or gating the clock to peripherals could result in a load change that could cause clock blanking to happen. In addition, a load change of more than 4 times the current Reference Manual SCU, V1.1 12-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) load would required the system to maintain in the current load and no further load change is allowed for 16 usec (max). See VDDC Response During Load Change for more details. Module clock gating in Sleep and Deep-Sleep modes It is recommended to gate the clock using registers CGATSET0 for module that is not needed during sleep mode or deep-sleep mode. These modules must be disabled before entering sleep or deep-sleep mode. In addition, the PCLK and MCLK will be switched to a slow standby clock and DCO1 will be put into power-down mode in deepsleep mode. 12.5.4 Calibrating DCO based on Temperature In XMC1100, DCO1 clock frequency can be calibrated during runtime to achieve a better accuracy. Based on the measured temperature using the on-chip temperature sensor(TSE), an offset value can be obtained using the formulae as shown below: (12.3) (a – b)(c – d) OFFSET [ steps ] = b + --------------------------------(e – d) where : OFFSET value is range from 0 to 8 c is the measured temperature [°C] a is constant DCO_ADJLO_T2 b is constant DCO_ADJLO_T1 d is constant ANA_TSE_T1 e is constant ANA_TSE_T2 The 4 constants in the formulae are stored in flash configuration page shown in Table 12-4. Table 12-4 Address DCO calibration data in Flash sector 0 (CS0) Length Function DCO calibration data: 1000’0F30H 1B ANA_TSE_T1 1000’0F31H 1B ANA_TSE_T2 Reference Manual SCU, V1.1 12-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Table 12-4 DCO calibration data in Flash sector 0 (CS0) Address Length Function 1000’0F32H 1B DCO_ADJLO_T1 1000’0F33H 1B DCO_ADJLO_T2 Input the offset value (rounded to the nearest integer) to register bit ANAOFFSET.ADJL_OFFSET to start the DCO1 calibration. The offset value must be within the range of 0 to 8. This bit field is bit protected. DCO1 will take about 5 usec(max) for clock to be adjusted to the new frequency. An example code is provided in the Osciilator Handling Device Guide. 12.6 Service Request Generation The SCU module provides 2 service request outputs SR[1:0]. SR0 is for system critical request, such as loss of clock event. SR1 is for the common SCU request such as WDT pre-warning request. The service request outputs SR[1:0] are connected to interrupt nodes in the Nested Vectored Interrupt Controller (NVIC). Refer to Section 12.2.1 for more details. 12.7 Debug Behavior The SCU module does not get affected with the HALTED signal from SCU upon debug activities performed using external debug probe. 12.8 Power, Reset and Clock The SCU module implements functions that involve varoius types of modules controlled directly or via dedicated interfaces that are instantiated in different power, clock and reset domains. These modules are functionally considered parts of the SCU and therefore SCU is also considered a multi domain circuit in this sense. Power domains: Power domains get separated with appropriate power separation cells. • • Core domain supplied with VDDC voltage Pad domain supplied with VDDP voltage Clock domains: All cross-domain interfaces implement signal synchchronization. • • internal SCU clock is MCLK, always identical to the CPU clock RTC and register mirror interface clock is 32.786 kHz clock generated from DCO2 oscillator Reference Manual SCU, V1.1 12-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Reset domains: All resets get internally synchronized to respective clocks. • • System Reset (SYSRESET) resets most of the logics in SCU and can be triggered from various sources (please refer to Reset Control (RCU) section for more details) Master Reset (MRESET) contributes in generation of the System Reset and gets triggered upon power-up sequence of the Core domain Reference Manual SCU, V1.1 12-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.9 Registers This section describes the registers of SCU which some of them resides in the ANACTRL module. Most of the registers are reset by SYSRESET reset signal but some of the registers can be reset only with power-on reset. SCU registers are accessible via the AHB-lite bus. ANACTRL registers are accessible via the APB bus. ANACTRL registers have name starting with “ANA”. Table 12-5 Base Addresses of sub-sections of SCU registers Short Name Description Offset Addr.1) GCU Registers Offset address of General Control Unit 0000H PCU Registers Offset address of Power Control Unit 0200H CCU Registers Offset address of Clock Control Unit 0300H RCU Registers Offset address of Reset Control Unit 0400H RTC Registers Offset address of Real Time Clock Module 0A00H ANACTRL Registers Offset address of ANACTRL registers 1000H 1) The absolute register address is calculated as follows: Module Base Address + Sub-Module Offset Address (shown in this column) + Register Offset Address Following access to SCU/ANACTRL SFRs result in an AHB/APB error response: • • • Read or write access to undefined address Write access to read-only registers Write access to startup protected registers Table 12-6 Registers Address Space Module Base Address End Address Note SCU 4001 0000H 4001 FFFFH System Control Unit Registers Reference Manual SCU, V1.1 12-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Table 12-7 Registers Overview Short Name Description Offset Access Mode Description Addr.1) Read Write See PCU Registers (ANACTRL) ANAVDEL Voltage Detector Control register 1050H U, PV U, PV Page 12-25 0000H U, PV U, PV Page 12-26 PCU Registers (SCU) VDESR Voltage Detector Status Register CCU Registers (SCU) CLKCR Clock Control 0000H U, PV U, PV, Page 12-27 BP PWRSVCR Power Save Control Register 0004H U, PV U, PV Page 12-29 CGATSTAT0 Clock Gating Status for Peripherals 0 0008H U, PV U, PV Page 12-30 CGATSET0 Clock Gating Set for Peripherals 0 000CH U, PV U, PV, Page 12-31 BP CGATCLR0 Clock Gating Clear for Peripherals 0 0010H U, PV U, PV, Page 12-32 BP OSCCSR Oscillator Control and Status Register 0014H U, PV U, PV 106CH U, PV U, PV, Page 12-34 BP Page 12-33 CCU Registers (ANACTRL) ANAOFFSET DCO1 Offset Register RCU Registers (SCU) RSTSTAT Reset Status 0000H U, PV BE Page 12-35 RSTSET Reset Set Register 0004H U, PV U, PV Page 12-36 RSTCLR Reset Clear Register 0008H U, PV U, PV Page 12-37 RSTCON Reset Control Register 000CH U, PV U, PV Page 12-38 GCU Registers (SCU) ID Module Identification Register 0008H U, PV BE Page 12-39 IDCHIP Chip ID 0004H U, PV SP Page 12-40 Reference Manual SCU, V1.1 12-24 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Table 12-7 Registers Overview (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See DBGROMID DBGROMID 0000H U, PV SP Page 12-41 SSW0 SSW Support Register 0014H U, PV U, PV Page 12-41 CCUCON CCUx Global Start Control Register 0030H U, PV U, PV Page 12-42 SRRAW RAW Service Request Status 0038H U, PV BE Page 12-43 SRMSK Service Request Mask 003CH U, PV U, PV Page 12-45 SRCLR Service Request Clear 0040H U, PV U, PV Page 12-47 SRSET Service Request Set 0044H U, PV U, PV Page 12-50 PASSWD Bit protection Register 0024H U, PV U, PV Page 12-52 MIRRSTS Mirror Update Status Register 0048H U, PV BE Page 12-54 PMTSR Parity Memory Test Select Register 0054H U, PV U, PV Page 12-55 1) The absolute register address is calculated as follows: Module Base Address + Sub-Module Offset Address + Offset Address (shown in this column) 12.9.1 PCU Registers (ANACTRL) ANAVDEL Voltage Detector Control register. ANAVDEL Voltage Detector Control Register 15 14 13 12 11 10 9 (1050H) 8 7 6 5 4 3 2 1 0 VDE VDEL_TIM VDEL_SE L_E _ADJ LECT N rw rw rw 0 r Reference Manual SCU, V1.1 Reset Value:001CH 12-25 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description VDEL_SELECT 1:0 rw VDEL Range Select With these bits the VDDP range is set. 00B 2.25V 01B 3.0V 10B 4.4V VDEL_TIM_ADJ 3:2 rw VDEL Timing Setting These bits control the reaction speed of the VDEL. The value is determined by characterisation. 00B typ 1µs - slowest response time 01B typ 500n 10B typ 250n 11B no delay - fastest response time. VDEL_EN 4 rw VDEL unit Enable 0B VDEL is disabled 1B VDEL is active 0 15:5 r Reserved Read as 0; should be written with 0. 12.9.2 PCU Registers (SCU) VDESR Voltage Detector status register. VDESR Voltage Detector Status Register 31 30 29 28 27 26 (0200H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 VDD VCLI PPW P 0 r Reference Manual SCU, V1.1 rh 12-26 rh V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description VCLIP 0 rh VCLIP Indication VCLIP monitoring bit. 0B VCLIP is not active 1B VCLIP is active VDDPPW 1 rh VDDPPW Indication 0B VDDP is above pre-warning threshold VDDP is below pre-warningthreshold 1B 0 [31:2] r Reserved Read as 0; should be written with 0. 12.9.3 CCU Registers (SCU) CLKCR Clock control register. CLKCR Clock Control Register 31 30 29 28 27 (0300H) 26 VDD VDD C2HI C2L GH OW rh rh 15 14 13 Reference Manual SCU, V1.1 12 11 10 25 24 23 Reset Value: 3FF0 0400H 22 21 20 19 18 17 CNTADJ RTCCLKSEL rw rw 9 8 7 6 5 4 3 IDIV FDIV rw rw 12-27 2 1 16 PCL KSE L rw 0 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Function FDIV [7:0] rw Fractional Divider Selection Selects the fractional divider to be n/256, where n is the value of FDIV and is in the range of 0 to 255. For example, writing 0001B to FDIV selects the fractional divider to be 1/256. This bit is protected by the bit protection scheme as described in Memory Organization chapter Note: Fractional divider has no effect if IDIV = 00H . IDIV [15:8] rw Divider Selection 00H Divider is bypassed. 01H 1; MCLK = 32 MHz 02H 2; MCLK = 16 MHz 03H 3; MCLK = 10.67 MHz 04H 4; MCLK = 8 MHz FEH 254; MCLK = 126 kHz FFH 255; MCLK = 125.5 kHz This bit is protected by the bit protection scheme as described in Memory Organization chapter PCLKSEL 16 rw PCLK Clock Select 0B PCLK = MCLK PCLK = 2 x MCLK 1B This bit is protected by the bit protection scheme as described in Memory Organization chapter RTCCLKSEL [19:17] rw RTC Clock Select 000B 32.768kHz standby clock Others Reserved This bit is protected by the bit protection scheme as described in Memory Organization chapter CNTADJ rw Counter Adjustment 000H 1 clock cycles of the DCO1, 64MHz clock 001H 2 clock cycles of the DCO1, 64MHz clock 002H 3 clock cycles of the DCO1, 64MHz clock 003H 4 clock cycles of the DCO1, 64MHz clock 004H 5 clock cycles of the DCO1, 64MHz clock 3FEH 1023 clock cycles of the DCO1, 64MHz clock 3FFH 1024 clock cycles of the DCO1, 64MHz clock [29:20] Reference Manual SCU, V1.1 12-28 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Function VDDC2LOW 30 rh VDDC too low 0B VDDC is not too low and the fractional divider input clock is running at the targeted frequency VDDC is too low and the fractional divider input 1B clock is not running at the targeted frequency VDDC2HIGH 31 rh VDDC too high 0B VDDC is not too high VDDC is too high 1B PWRSVCR Configuration register that defines some system behaviour aspects while in deep-sleep mode or sleep mode. The original system state gets restored upon wakeup from sleep mode or deep-sleep mode. PWRSVCR Power Save Control Register 31 30 29 28 27 26 (0304H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 FPD r rw Field Bits Type Description FPD 0 rw Flash Power Down 0B no effect Flash power down when entering power save 1B mode. Upon wake-up, CPU is able to fetch code from flash. 0 [31:1] r Reserved Read as 0. Reference Manual SCU, V1.1 12-29 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) CGATSTAT0 Clock gating status for XMC1100 peripherals. After reset, all peripherals as listed in the registers are not running. Their module clock are gated. Every bit in this register is protected by the bit protection scheme as described in Memory Organization chapter. CGATSTAT0 Peripheral 0 Clock Gating Status 31 30 29 28 27 26 25 (0308H) 24 Reset Value: 0000 07FFH 23 22 21 20 7 6 5 4 19 18 17 16 3 2 1 0 1 VAD C r r 0 r 15 14 13 12 0 11 10 9 8 RTC WDT r r 1 r USIC CCU 0 40 r Field Bits Type Description VADC 0 r VADC and SHS Gating Status 0B gating de-asserted 1B gating asserted CCU40 2 r CCU40 Gating Status 0B gating de-asserted 1B gating asserted USIC0 3 r USIC0 Gating Status 0B gating de-asserted gating asserted 1B WDT 9 r WDT Gating Status 0B gating de-asserted 1B gating asserted RTC 10 r RTC Gating Status 0B gating de-asserted 1B gating asserted 0 [31:11] r Reserved 1 1, [8:4] r Reserved Reference Manual SCU, V1.1 12-30 r r V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) CGATSET0 Clock gating enable for XMC1100 peripherals. Write one to selected bit to enable gating of corresponding clock, writing zeros has no effect. Every bit in this register is protected by the bit protection scheme as described in Memory Organization chapter. CGATSET0 Peripheral 0 Clock Gating Set 31 30 29 28 27 26 (030CH) 25 24 Reset Value: 0000 0000H 23 22 21 20 7 6 5 4 19 18 17 16 3 2 1 0 0 VAD C r w 0 r 15 14 13 12 0 11 10 9 8 RTC WDT r w 0 w r Field Bits Type Description VADC 0 w VADC and SHS Gating Set 0B no effect 1B enable gating CCU40 2 w CCU40 Gating Set 0B no effect enable gating 1B USIC0 3 w USIC0 Gating Set 0B no effect 1B enable gating WDT 9 w WDT Gating Set 0B no effect 1B enable gating RTC 10 w RTC Gating Set 0B no effect enable gating 1B 0 1, [8:4], r [31:11] Reference Manual SCU, V1.1 USIC CCU 0 40 w w Reserved 12-31 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) CGATCLR0 Clock gating disable for XMC1100 peripherals. Write one to selected bit to disable gating of corresponding clock, writing zeros has no effect. CGATCLR0 Peripheral 0 Clock Gating Clear 31 30 29 28 27 26 (0310H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 VAD C r w 0 r 15 14 13 12 0 11 10 9 8 RTC WDT r w 0 w r Field Bits Type Description VADC 0 w VADC and SHS Gating Clear 0B no effect disable gating 1B CCU40 2 w CCU40 Gating Clear 0B no effect 1B disable gating USIC0 3 w USIC0 Gating Clear 0B no effect 1B disable gating WDT 9 w WDT Gating Clear 0B no effect disable gating 1B RTC 10 w RTC Gating Clear 0B no effect 1B disable gating 0 1, [8:4], r [31:11] Reference Manual SCU, V1.1 USIC CCU 0 40 w w Reserved 12-32 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) OSCCSR Oscillator Control and Status Register. OSCCSR Oscillator Control and Status Register (0314H) 31 30 29 28 27 26 25 24 23 Reset Value: 0000 000XH 22 21 20 19 18 r 14 13 12 11 10 9 16 OWD OWD EN RES 0 15 17 8 7 6 5 4 3 2 rw rwh 1 0 OSC OSC 2H 2L 0 r rh rh Field Bits Type Description OSC2L 0 rh Oscillator Valid Low Status Bit This bit indicates if the frequency output of OSC is usable. This is checked by the Oscillator Watchdog The OSC frequency is usable 0B 1B The OSC frequency is not usable. Frequency is too low. OSC2H 1 rh Oscillator Valid High Status Bit This bit indicates if the frequency output of OSC is usable. This is checked by the Oscillator Watchdog. The OSC frequency is usable 0B 1B The OSC frequency is not usable. Frequency is too high. Reference Manual SCU, V1.1 12-33 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description OWDRES 16 rwh Oscillator Watchdog Reset Setting this bit will restart the oscillator detection. This bit will be automatically reset to 0 after OWD is reset which takes 2 standby clock cycles due to synchronisation. The Oscillator Watchdog is not cleared and 0B remains active 1B The Oscillator Watchdog is cleared and restarted. The OSC2L and OSC2H flag will be held in the last value until it is updated after 3 standby clock cycles. OWDEN 17 rw Oscillator Watchdog Enable 0B The Oscillator Watchdog is disabled The Oscillator Watchdog is enabled 1B Note: OSC2H and OSC2L will be cleared to 0 when OWD is disabled. 0 Reserved Read as 0. [15:2], r [31:18] 12.9.4 CCU Registers (ANACTRL) ANAOFFSET DCO1 Offset register. ANAOFFSET DCO1 Offset Register 15 14 13 Reference Manual SCU, V1.1 12 (106CH) 11 10 9 8 7 Reset Value: 0004H 6 5 4 3 2 1 0 ADJL_OFFSET r rw 12-34 0 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description ADJL_OFFSET 3:0 rw ADJL Offset register The adjusted oscillator frequency can be varied according to the steps programmed. This bit is protected by the bit protection scheme as described in Memory Organization chapter - 3.75%, typ. 0H 1H - 2.85%, typ. ... 4H 0, default 5H + 0.95%, typ. ... 8H + 3.75%, typ. 0 15:4 r Reserved Read as 0; should be written with 0. 12.9.5 RCU Registers (SCU) RSTSTAT Reset status register. This register needs to be checked after system startup in order to determine last reset reason. User should clear this register after reading it to ensure a clear status when the next reset happen. This register is reset by a power-on reset. RSTSTAT RCU Reset Status 31 30 29 28 (0400H) 27 26 25 24 Reset Value: 0000 0XXXH 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 LCK EN RSTSTAT r r rh Reference Manual SCU, V1.1 12-35 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description RSTSTAT [9:0] rh Reset Status Information Provides reason of last reset 0000000001B Power on reset or Brownout reset XXXXXXXX1XB Master reset via bit RSTCON.MRSTEN XXXXXXX1XXB CPU system reset request XXXXXX1XXXB CPU lockup reset XXXXX1XXXXB Flash ECC reset XXXX1XXXXXB WDT reset XXX1XXXXXXB Loss of clock reset XX1XXXXXXXB Parity Error reset LCKEN 10 r Enable Lockup Status 0B Reset by Lockup disabled Reset by Lockup enabled 1B 0 [31:11] r Reserved RSTSET Selective configuration of reset behaviour in the system. Write one to set selected bit, writing zeros has no effect. RSTSET RCU Reset Set Register 31 30 29 28 27 (0404H) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 LCK EN 0 r w r Field Bits Type Description LCKEN 10 w Reference Manual SCU, V1.1 Enable Lockup Reset 0B no effect Enable reset when Lockup gets asserted 1B 12-36 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits 0 [9:0], r [31:11] Type Description Reserved RSTCLR Selective configuration of reset behaviour in the system. Write one to clear selected bit, writing zeros has no effect. RSTCLR RCU Reset Clear Register 31 30 29 28 (0408H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 7 6 5 4 3 2 1 16 0 r 15 14 13 12 11 10 9 8 0 0 LCK EN 0 RSC LR r w r w Field Bits Type Description RSCLR 0 w Clear Reset Status 0B no effect 1B Clears field RSTSTAT.RSTSTAT LCKEN 10 w Enable Lockup Reset 0B no effect 1B Disable reset when Lockup gets asserted 0 [9:1], r [31:11] Reserved RSTCON Enabling of reset triggered by critical events. It is reset by any reset type. Reference Manual SCU, V1.1 12-37 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) RSTCON RCU Reset Control Register 31 15 30 14 29 28 13 12 27 11 (040CH) 26 25 10 9 24 23 Reset Value: 0000 0000H 22 21 20 19 18 17 16 0 MRS TEN r w 8 7 6 5 4 3 2 1 0 U0P SPE LOC ECC ERS RST RST RST TEN EN EN EN rw rw rw rw 0 r Field Bits Type Description ECCRSTEN 0 rw Enable ECC Error Reset 0B No reset when ECC double bit error occur 1B Reset when ECC double bit error occur LOCRSTEN 1 rw Enable Loss of Clock Reset 0B No reset when loss of clock occur 1B Reset when loss of clock occur SPERSTEN 2 rw Enable 16kbytes SRAM Parity Error Reset 0B No reset when SRAM parity error occur Reset when SRAM parity error occur 1B U0PERSTEN 3 rw Enable USIC0 SRAM Parity Error Reset 0B No reset when USIC0 memory parity error occur 1B Reset when USIC0 memory parity error occur MRSTEN 16 w Enable Master Reset 0B No effect 1B Triggered Master reset 0 [15:4], r [31:17] Reference Manual SCU, V1.1 Reserved 12-38 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) 12.9.6 GCU Registers (SCU) ID Register containing uniques ID of the module. ID SCU Module ID Register (0008H) 31 30 29 28 27 26 25 24 23 Reset Value: 00F1 C0XXH 22 21 20 19 18 17 16 5 4 3 2 1 0 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV [7:0] r Module Revision Number MOD_REV defines the revision number. The value of a module revision starts with 01H (first revision). MOD_TYPE [15:8] r Module Type This bit field is C0H. It defines the module as a 32-bit module. r Module Number Value This bit field defines the module identification number. MOD_NUMBER [31:16] IDCHIP Register containing a unique ID of the chip in the XMC family. The value of this register formed part of the chip identification number as described in Chip Identification Number. Reference Manual SCU, V1.1 12-39 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) IDCHIP Chip ID Register 31 30 29 (0004H) 28 27 26 25 24 23 Reset Value: 0000 0000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 IDCHIP r 15 14 13 12 11 10 9 8 7 IDCHIP r Field Bits Type Description IDCHIP [31:0] r CHIP ID 0001 1XXXH XMC1100 0001 XXX2H temperature : -40 - 85° C 0001 XXX3H temperature : -40 - 105° C 0001 XX1XH TSSOP38 pin package 0001 XX2XH TSSOP28 pin package 0001 XX3XH TSSOP16 pin package 0001 XX4XH VQFN40 pin package 0001 XX6XH VQFN24 pin package Others Reserved DBGROMID Register containing unique manufactory ID, part number and the design stepping code of the chip. Reference Manual SCU, V1.1 12-40 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) DBGROMID Debug System ROM ID Register 31 30 29 28 27 26 (0000H) 25 24 23 Reset Value: 201E D083H 22 21 VERSION PARTNO r r 15 14 13 12 11 10 9 8 7 6 5 20 19 18 17 16 4 3 2 1 0 PARTNO MANUFID 1 r r r Field Bits Type Description MANUFID [11:1] r PARTNO [27:12] r Part Number VERSION [31:28] r Product version 1 0 Reserved Read as 1; should be written with 1. Manufactory Identity r SSW0 Software support registers. SSW0 is used to change the BMI value. SSW0 SSW Register 0 31 30 29 (0014H) 28 27 26 25 24 23 Reset Value: 0000 0000H 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DAT rw 15 14 13 12 11 10 9 8 7 DAT rw Reference Manual SCU, V1.1 12-41 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description DAT [31:0] rw SSW Data Note: SSW registers can be reset with master reset only CCUCON CAPCOM module control register. CCUCON CCU Control Register 31 30 29 28 (0030H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 GSC 40 r rw Field Bits Type Description GSC40 0 rw Global Start Control CCU40 This register can be used to control a synchronous start of multiple timers of CCU40. It also can be used to control additional functions that are available in the timers, e.g. Count or Capture. For a complete description of the available set of functions, please address the specific section of the CCU4 chapters. Writing 1 or 0 into this field will not by itself trigger a synchronous start of multiple timers and one must before configure the specific peripheral function accordingly. 0 [31:1] r Reserved Read as 0; should be written with 0. Reference Manual SCU, V1.1 12-42 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) SRRAW Service request status without masking. Write one to a bit in SRCLR register to clear a bit or SRSET to set a bit. Writing zero has no effect. SRRAW SCU Raw Service Request Status 31 30 29 28 27 26 25 (0038H) 24 TSE TSE TSE RTC RTC RTC RTC RTC _LO _HIG _DO _TIM _TIM _ATI _ATI _CT W H NE 1 0 M1 M0 R rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 23 0 r 7 Reset Value: 0000 0000H 22 21 20 19 18 17 16 SBY FLC PES VCLI FLE PEU CLK MPL RAM LOCI PI CC2I 0I FI TI I rh rh rh rh rh rh rh 6 5 4 3 2 1 0 0 VDR OPI 0 VDD PI AI PI PRW ARN r rh r rh rh rh rh Field Bits Type Description PRWARN 0 rh WDT pre-warning Event Status Before Masking 0B Event has not occurred 1B Event has occurred PI 1 rh RTC Raw Periodic Event Status Before Masking 0B Event has not occurred 1B Event has occurred AI 2 rh RTC Raw Alarm Event Status Before Masking 0B Event has not occurred 1B Event has occurred VDDPI 3 rh VDDP pre-warning Event Status Before Masking 0B Event has not occurred 1B Event has occurred VDROPI 7 rh VDROP Event Status Before Masking 0B Event has not occurred 1B Event has occurred LOCI 16 rh Loss of Clock Event Status Before Masking 0B Event has not occurred 1B Event has occurred Reference Manual SCU, V1.1 12-43 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description PESRAMI 17 rh 16kbytes SRAM Parity Error Event Status Before Masking 0B Event has not occurred 1B Event has occurred PEU0I 18 rh USIC0 SRAM Parity Error Event Status Before Masking 0B Event has not occurred 1B Event has occurred FLECC2I 19 rh Flash Double Bit ECC Event Status Before Masking 0B Event has not occurred 1B Event has occurred FLCMPLTI 20 rh Flash Operation Complete Event Status Before Masking 0B Event has not occurred 1B Event has occurred VCLIPI 21 rh VCLIP Event Status Before Masking 0B Event has not occurred 1B Event has occurred SBYCLKFI 22 rh Standby Clock Failure Event Status Before Masking 0B No standby clock failure has occurred 1B Standby clock failure has occurred RTC_CTR 24 rh RTC CTR Mirror Register Update Status Before Masking 0B not updated 1B update completed RTC_ATIM0 25 rh RTC ATIM0 Mirror Register Update Status Before Masking 0B not updated 1B update completed RTC_ATIM1 26 rh RTC ATIM1 Mirror Register Update Status Before Masking 0B not updated 1B update completed Reference Manual SCU, V1.1 12-44 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description RTC_TIM0 27 rh RTC TIM0 Mirror Register Update Before Masking 0B not updated 1B update completed RTC_TIM1 28 rh RTC TIM1 Mirror Register Update Status Before Masking 0B not updated 1B update completed TSE_DONE 29 rh TSE Measurement Done Event Status Before Masking 0B Event has not occurred 1B Event has occurred TSE_HIGH 30 rh TSE Compare High Temperature Event Status Before Masking 0B Event has not occurred 1B Event has occurred TSE_LOW 31 rh TSE Compare Low Temperature Event Status Before Masking 0B Event has not occurred 1B Event has occurred 0 [6:4], [15:8], 23 r Reserved SRMSK Service request mask used to mask outputs of RAW register. When the bit is set to 1, an interrupt or service request will be triggered when the event happens. Reference Manual SCU, V1.1 12-45 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) SRMSK SCU Service Request Mask 31 30 29 28 27 26 (003CH) 25 24 TSE TSE TSE RTC RTC RTC RTC RTC _LO _HIG _DO _TIM _TIM _ATI _ATI _CT W H NE 1 0 M1 M0 R rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 23 0 r 7 Reset Value: 0000 0000H 22 21 SBY VCLI CLK PI FI rw rw 6 5 20 0 r 19 18 17 4 3 2 1 0 0 PRW ARN r rw r rw 0 r rw Field Bits Type Description PRWARN 0 rw WDT pre-warning Interrupt Mask 0B disable interrupt 1B enable interrupt VDDPI 3 rw VDDP pre-warning Interrupt Mask 0B disable interrupt 1B enable interrupt VDROPI 7 rw VDROP Interrupt Mask 0B disable interrupt 1B enable interrupt LOCI 16 rw Loss of Clock Interrupt Mask 0B disable interrupt 1B enable interrupt PESRAMI 17 rw 16kbytes SRAM Parity Error Interrupt Mask 0B disable interrupt 1B enable interrupt PEU0I 18 rw USIC0 SRAM Parity Error Interrupt Mask 0B disable interrupt 1B enable interrupt FLECC2I 19 rw Flash Double Bit ECC Interrupt Mask 0B disable interrupt 1B enable interrupt VCLIPI 21 rw VCLIP Interrupt Mask 0B disable interrupt 1B enable interrupt 12-46 0 VDD PI VDR OPI Reference Manual SCU, V1.1 16 PES FLE PEU RAM LOCI CC2I 0I I rw rw rw rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description SBYCLKFI 22 rw Standby Clock Failure Interrupt Mask 0B disable interrupt 1B enable interrupt RTC_CTR 24 rw RTC CTR Mirror Register Update Mask 0B disable interrupt 1B enable interrupt RTC_ATIM0 25 rw RTC ATIM0 Mirror Register Update Mask 0B disable interrupt 1B enable interrupt RTC_ATIM1 26 rw RTC ATIM1 Mirror Register Update Mask 0B disable interrupt 1B enable interrupt RTC_TIM0 27 rw RTC TIM0 Mirror Register Update Mask 0B disable interrupt 1B enable interrupt RTC_TIM1 28 rw RTC TIM1 Mirror Register Update Mask 0B disable interrupt 1B enable interrupt TSE_DONE 29 rw TSE Measurement Done Interrupt Mask 0B disable interrupt 1B enable interrupt TSE_HIGH 30 rw TSE Compare High Temperature Interrupt Mask 0B disable interrupt 1B enable interrupt TSE_LOW 31 rw TSE Compare Low Temperature Interrupt Mask 0B disable interrupt 1B enable interrupt 0 [2:1], [6:4], [15:8], 20, 23 r Reserved SRCLR Clear service request bits of register SRRAW. Write one to clear corresponding bits. Writing zeros has no effect. Reference Manual SCU, V1.1 12-47 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) SRCLR SCU Service Request Clear 31 30 29 28 27 26 (0040H) 25 24 TSE TSE TSE RTC RTC RTC RTC RTC _LO _HIG _DO _TIM _TIM _ATI _ATI _CT W H NE 1 0 M1 M0 R w w w w w w w w 15 14 13 12 11 10 9 8 23 0 r 7 Reset Value: 0000 0000H 22 21 20 19 18 17 6 5 4 3 0 VDD PI r w 2 1 0 AI PI PRW ARN w w w 0 VDR OPI r w Field Bits Type Description PRWARN 0 w WDT pre-warning Interrupt Clear 0B no effect 1B clear status bit in the raw status register PI 1 w RTC Periodic Interrupt Clear 0B no effect 1B clear status bit in the raw status register AI 2 w RTC Alarm Interrupt Clear 0B no effect 1B clear status bit in the raw status register VDDPI 3 w VDDP pre-warning Interrupt Clear 0B no effect 1B clear status bit in the raw status register VDROPI 7 w VDROP Interrupt Clear 0B no effect 1B clear status bit in the raw status register LOCI 16 w Loss of Clock Interrupt Clear 0B no effect 1B clear status bit in the raw status register PESRAMI 17 w 16kbytes SRAM Parity Error Interrupt Clear 0B no effect 1B clear status bit in the raw status register PEU0I 18 w USIC0 SRAM Parity Error Interrupt Clear 0B no effect 1B clear status bit in the raw status register Reference Manual SCU, V1.1 12-48 16 SBY FLC PES VCLI FLE PEU CLK MPL RAM LOCI PI CC2I 0I FI TI I w w w w w w w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description FLECC2I 19 w Flash Double Bit ECC Interrupt Clear 0B no effect 1B clear status bit in the raw status register FLCMPLTI 20 w Flash Operation Complete Interrupt Clear 0B no effect 1B clear status bit in the raw status register VCLIPI 21 w VCLIP Interrupt Clear 0B no effect 1B clear status bit in the raw status register SBYCLKFI 22 w Standby Clock Failure Interrupt Clear 0B no effect 1B clear status bit in the raw status register RTC_CTR 24 w RTC CTR Mirror Register Update Clear 0B no effect 1B clear status bit in the raw status register RTC_ATIM0 25 w RTC ATIM0 Mirror Register Update Clear 0B no effect 1B clear status bit in the raw status register RTC_ATIM1 26 w RTC ATIM1 Mirror Register Update Clear 0B no effect 1B clear status bit in the raw status register RTC_TIM0 27 w RTC TIM0 Mirror Register Update Clear 0B no effect 1B clear status bit in the raw status register RTC_TIM1 28 w RTC TIM1 Mirror Register Update Clear 0B no effect 1B clear status bit in the raw status register TSE_DONE 29 w TSE Measurement Done Interrupt Clear 0B no effect 1B clear status bit in the raw status register TSE_HIGH 30 w TSE Compare High Temperature Interrupt Clear 0B no effect 1B clear status bit in the raw status register TSE_LOW 31 w TSE Compare Low Temperature Interrupt Clear 0B no effect 1B clear status bit in the raw status register Reference Manual SCU, V1.1 12-49 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description 0 [6:4], [15:8], 23 r Reserved SRSET Set service request fits of register SRRAW. Write one to set corresponding bits. Writing zeros has no effect. SRSET SCU Service Request Set 31 30 29 28 27 (0044H) 26 25 24 TSE TSE TSE RTC RTC RTC RTC RTC _LO _HIG _DO _TIM _TIM _ATI _ATI _CT W H NE 1 0 M1 M0 R w w w w w w w w 15 14 13 12 11 10 9 8 23 0 r 7 Reset Value: 0000 0000H 22 21 20 19 18 6 5 4 3 16 r w 1 0 AI PI PRW ARN w w w 0 r w Field Bits Type Description PRWARN 0 w WDT pre-warning Interrupt Set 0B no effect 1B set status bit in the raw status register PI 1 w RTC Periodic Interrupt Set 0B no effect 1B set status bit in the raw status register AI 2 w RTC Alarm Interrupt Set 0B no effect 1B set status bit in the raw status register VDDPI 3 w VDDP pre-warning Interrupt Set 0B no effect 1B set status bit in the raw status register VDROPI 7 w VDROP Interrupt Set 0B no effect 1B set status bit in the raw status register 12-50 0 VDD PI 2 VDR OPI Reference Manual SCU, V1.1 17 SBY FLC PES VCLI FLE PEU CLK MPL RAM LOCI PI CC2I 0I FI TI I w w w w w w w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description LOCI 16 w Loss of Clock Interrupt Set 0B no effect 1B set status bit in the raw status register PESRAMI 17 w 16kbytes SRAM Parity Error Interrupt Set 0B no effect 1B set status bit in the raw status register PEU0I 18 w USIC0 SRAM Parity Error Interrupt Set 0B no effect 1B set status bit in the raw status register FLECC2I 19 w Flash Double Bit ECC Interrupt Set 0B no effect 1B set status bit in the raw status register FLCMPLTI 20 w Flash Operation Complete Interrupt Set 0B no effect 1B set status bit in the raw status register VCLIPI 21 w VCLIP Interrupt Set 0B no effect 1B set status bit in the raw status register SBYCLKFI 22 w Standby Clock Failure Interrupt Set 0B no effect 1B set status bit in the raw status register RTC_CTR 24 w RTC CTR Mirror Register Update Set 0B no effect 1B set status bit in the raw status register RTC_ATIM0 25 w RTC ATIM0 Mirror Register Update Set 0B no effect 1B set status bit in the raw status register RTC_ATIM1 26 w RTC ATIM1 Mirror Register Update Set 0B no effect 1B set status bit in the raw status register RTC_TIM0 27 w RTC TIM0 Mirror Register Update Set 0B no effect 1B set status bit in the raw status register RTC_TIM1 28 w RTC TIM1 Mirror Register Update Set 0B no effect 1B set status bit in the raw status register Reference Manual SCU, V1.1 12-51 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description TSE_DONE 29 w TSE Measurement Done Interrupt Set 0B no effect 1B set status bit in the raw status register TSE_HIGH 30 w TSE Compare High Temperature Interrupt Set 0B no effect 1B set status bit in the raw status register TSE_LOW 31 w TSE Compare Low Temperature Interrupt Set 0B no effect 1B set status bit in the raw status register 0 [6:4], [15:8], 23 r Reserved PASSWD The PASSWD register is used to control the bit protection scheme. PASSWD Password Register 31 30 29 (0024H) 28 27 26 25 24 Reset Value: 0000 0007H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 Reference Manual SCU, V1.1 12 11 10 9 8 0 PASS PRO TS MODE r w rh rw 12-52 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control Bits 00B Scheme disabled - direct access to the protected bits is allowed. 11B Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default) Others: Scheme enabled, similar to the setting for MODE = 11B. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B. Only then will the MODE bit field be registered. PROTS 2 rh Bit Protection Signal Status Bit This bit shows the status of the protection. 0B Software is able to write to all protected bits. Software is unable to write to any of the 1B protected bits. PASS [7:3] w Password Bits This bit protection scheme only recognizes the following three passwords: 11000BEnables writing of the bit field MODE. 10011BOpens access to writing of all protected bits. 10101BCloses access to writing of all protected bits. 0 [31:8] r Reserved MIRRSTS Mirror status register for control of communication between SCU and RTC. Reference Manual SCU, V1.1 12-53 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) MIRRSTS Mirror Update Status Register 31 30 29 28 27 26 (0048H) 25 24 Reset Value: 0000 0000H 23 22 21 7 6 5 20 19 18 17 16 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 RTC RTC RTC RTC RTC _TIM _TIM _ATI _ATI _CT 1 0 M1 M0 R rh rh rh rh rh 0 r Field Bits Type Function RTC_CTR 0 rh RTC CTR Mirror Register Update Status 0B no update pending 1B update pending RTC_ATIM0 1 rh RTC ATIM0 Mirror Register Update Status 0B no update pending 1B update pending RTC_ATIM1 2 rh RTC ATIM1 Mirror Register Update Status 0B no update pending 1B update pending RTC_TIM0 3 rh RTC TIM0 Mirror Register Update Status 0B no update pending 1B update pending RTC_TIM1 4 rh RTC TIM1 Mirror Register Update Status 0B no update pending 1B update pending 0 [31:14] r Reserved Read as 0; should be written with 0. PMTSR This register selects parity test output from a memory instance. Reference Manual SCU, V1.1 12-54 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family System Control Unit (SCU) PMTSR Parity Memory Test Select Register (0054H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 MTE NS r rw Field Bits Type Description MTENS 0 rw Parity Test Enable Control for 16kbytes SRAM Controls the test multiplexer for the 16kbytes SRAM. 0B standard operation 1B generate an inverted parity bit during a write operation 0 [31:1] r Reserved Should be written with 0. Reference Manual SCU, V1.1 12-55 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) 13 Pseudo Random Number Generator (PRNG) 13.1 Overview The pseudo random bit generator (PRNG) provides random data with fast generation times. 13.1.1 Features The PRNG includes the following features: • • Fast random data generation times: – 17 to 18 clock cycles generation time for 16-bit random data – 9 to 10 clock cycles generation time for 8-bit random data Fulfills statistical tests according to NIST-800 13.2 Description of Operation Modes 13.2.1 Key Loading Mode Before the PRNG can be used it has to be initialized by the user software. The key (seed) k of the PRNG is a bit string k = (kn-1, kn-2, ..., k2, k1, k0) of length n. A key length of 80 bits is recommended, although smaller or larger key lengths are possible. It is recommended to use chip individual seed values. The initialization of the PRNG consists of two basic phases: 1. Key loading 2. Warm-up Key loading is initialized by setting the bit PRNG_CTRL.KLD to "1". In the key loading mode, PRNG_WORD acts always as a 16 bit destination register. The p partial words Wi (0 <= i < p) of the key k = (Wp-1, ..., W1, W0), with Wi = (k15, ..., k1, k0), are sequentially written to PRNG_WORD in the order W0, W1, ..., Wp-1. A useful seed size is 80 bits (i.e., 5 data words, p=5). Because the bits of the partial key word are sequentially loaded into the internal state of the PRNG, loading of a key word will take 16 clock cycles. The PRNG_CHK.RDV flag is set to "0" while loading is in progress. A flag value of "1" indicates that the next partial key word can be written to PRNG_WORD. After the complete key has been loaded, the PRNG_CTRL.KLD flag must be set to "0" to prepare the following warm-up phase. This operation takes one clock cycle. The warm-up phase provides a thorough diffusion of the key bits. For this purpose the user must read and discard 64 random bits from the register PRNG_WORD. The Reference Manual PRNG, V1.1 13-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) random data output block must be set to either b = 8 or 16 bits. This is achieved by setting the corresponding value of the PRNG_CTRL.RDBS field. The flag PRNG_CHK.RDV set to "1" indicates that the next random data block of width b can be read from PRNG_WORD. If, for any reason, PRNG_CTRL.RDBS is reset to the default value of 00B, the PRNG must be initialized once more – i.e., a key must be loaded and a warm-up phase carried out. 13.2.2 Streaming Mode The flag PRNG_CHK.RDV set to 1B indicates that the next random data block can be read from PRNG_WORD. After a word has been read the flag PRNG_CHK.RDV is reset to 0B by the hardware and generation of new random bits starts. The PRNG requires 17– 18 clock cycles to generate a 16 random bits and 9–10 clock cycles to generate eight random bits. From a software point of view it is not necessary to poll the PRNG_CHK.RDV flag. Consecutive read accesses to PRNG_WORD will be delayed automatically by hardware as long as PRNG_CHK.RDV is "0". The width of the output data block is changed by setting the value of PRNG_CTRL.RDBS. This should be done before entering streaming mode, otherwise if the change is made during streaming, the new setting will not come into effect until the next generation cycle is started. The hardware checks that the selected number of bits are available and the flag PRNG_CHK.RDV is set when this condition is true. In order to avoid reading a duplicate random byte when switching from 8-bit to 16-bit operation mode the last byte generated in the 8-bit mode should first be discarded before switching to 16-bit mode. Note: PRNG_WORD should be accessed as 16 bit register, the upper 16 bits (of a 32 bit access) are ignored on a write and zeroes on a read and therefore contains no random data. 13.2.3 Refreshing and Restarting a Random Bit Stream The random bit sequence can be refreshed with a new key. In this case the entropy contained in the last internal state is not cleared, but instead the new key is mixed into the current PRNG state. This is referred to as refreshing. Refreshing is a means of introducing additional entropy into the generation of the random bit sequence. Without refreshing, the entire entropy rests in the inital key (or seed) that was used for initializing the PRNG during first key loading. Thereafter, the generation of the random bit sequence is purely deterministic. The deterministic process is broken whenever refreshing is performed. Refreshing implies that it is not possible to reproduce the same random result using the same key for data generation. Since the internal state of the PRNG cannot be read and set directly, a sequence cannot be restored from any given state. A random bit sequence based on a certain initial key Reference Manual PRNG, V1.1 13-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) can, however, be continued. To this means, a segment s of the output sequence is stored and this segment is used as a initial key later on. The segment s = (sn-1, sn-2, ..., s2, s1, s0) of length n should be fresh – i.e., generated after the last bits used in the application. The length of s should be at least n = 80 bits. This way a pseudorandom bit sequence can be continued after a system reset without requiring new key material. This process is known as restarting. Note: Integration in a multi-application/multitasking environment together with the requirement to obtain a reproducible pseudorandom bit sequence would necessitate a state saving and restoring feature. Hence the OS must be able to save the PRNG state before giving control to application 2 and restore the state before returning control to application 1. This is not possible with the PRNG module. 13.3 Service Request Generation The PRNG does not generate any service request. 13.4 Debug Behavior The PRNG does not support a suspend mode while the system is halted by the debugger. That means that the PRNG continues its operation during debug halt. 13.5 Power, Reset and Clock The PRNG module is located in the core power domain. The module can be reset to its default state by a system reset. The PRNG module is clocked by the main clock, MCLK, from SCU. 13.6 Initialization and System Dependencies The PRNG is always available after reset. Refer to Section 13.2.1 for the initialization steps. 13.7 Registers The interface of the PRNG comprises the registers PRNG_WORD, PRNG_CHK and PRNG_CTRL. Table 13-1 Registers Address Space Module Base Address End Address PRNG 4802 0000H 4802 000FH Reference Manual PRNG, V1.1 13-3 Note V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) Table 13-2 Registers Overview Register Short Name Register Long Name Offset Address Page Number PRNG_WORD PRNG word register 00H Page 13-4 PRNG_CHK PRNG status check register 04H Page 13-5 PRNG control register 0CH Page 13-6 Data Registers Control Registers PRNG_CTRL The register is addressed wordwise. 13.7.1 Data Registers Pseudo RNG Word Register PRNG_WORD PRNG Word Register 15 14 13 12 (00H) 11 10 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 RDATA rw Field Bits Type Description RDATA 15:0 rw Reference Manual PRNG, V1.1 Random Data Random bit block or key to load. In the streaming mode the range of valid random bits is defined by the settings given by PRNG_CTRL.RDSB and the value of the flag PRNG_CHK.RDV. In the key loading mode the seed value (key) is written via this register. In this case, the key is written in units of 16 bits. 13-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) Additional Information Notes 1. Reading PRNG_WORD while the PRNG is running in key loading mode (configured by setting PRNG_CTRL.KLD) will return the last value written to the register, whereas write accesses to the register while the PRNG is running in streaming mode (PRNG_CTRL.KLD = ’0’) will be ignored. 2. Write access to SFR PRNG_WORD: It is strongly recommended to wait until the SFR bit PRNG_CHK.RDV indicates that the register PRNG_WORD is ready to receive (new) data (which will be used to seed the PRNG.) 3. Read access to SFR PRNG_WORD: It is strongly recommended to check the SFR bit PRNG_CHK.RDV before reading SFR PRNG_WORD. Pseudo RNG Status Check Register PRNG_CHK PRNG Status Check Register 15 14 13 12 11 10 (04H) 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 0 RDV r r Field Bits Type Description RDV 0 r Random Data / Key Valid Flag 0B INV, New random data block is not yet ready to be read. In “Key Loading Mode” on Page 13-1) this flag is set to 0B while loading is in progress. VAL, Random data block is valid. In key loading mode 1B this value indicates that the next partial key word can be written to PRNG_WORD. 0 15:1 r Reserved Additional Information Note: If a word or byte is read from PRNG_WORD although the data is not ready (PRNG_CHK.RDV = 0B), the system stalls until the data becomes ready. Reference Manual PRNG, V1.1 13-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Pseudo Random Number Generator (PRNG) 13.7.2 Control Registers Pseudo RNG Control Register PRNG_CTRL PRNG Control Register 15 14 13 12 11 (0CH) 10 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 0 KLD RDBS 0 r rw rw r Field Bits Type Description KLD 3 rw Key Load Operation Mode 0B STRM, Streaming mode (default) 1B KLD, Key loading mode RDBS 2:1 rw Random Data Block Size Set random data block size for read access (16 bits always used for key loading) 00B RES, Reset state (no random data block size defined)1), value of PRNG_WORD is undefined. 01B BYTE, 8 bits in PRNG_WORD.RDATA[7:0] 10B WORD, 16 bits in PRNG_WORD.RDATA[15:0] 11B RFU, Reserved for future use, value of PRNG_WORD is undefined. 0 0 r Reserved 0 15:4 r Reserved 1) Once the reset value for RDBS (00B) is set, the PRNG must be fully initialized before the functionality can be used. Initialization requires key loading, followed by a warm-up phase. Additional Information Note: It is recommended not to change the PRNG_CTRL.KLD flag during key load. Otherwise the distribution of the bits of the PRNG will not be equal. Reference Manual PRNG, V1.1 13-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14 Universal Serial Interface Channel (USIC) The Universal Serial Interface Channel module (USIC) is a flexible interface module covering several serial communication protocols. A USIC module contains two independent communication channels named USICx_CH0 and USICx_CH1, with x being the number of the USIC module (e.g. channel 0 of USIC module 0 is referenced as USIC0_CH0). The user can program during run-time which protocol will be handled by each communication channel and which pins are used. References The following documents are referenced for further information [7] IIC Bus Specification (Philips Semiconductors v2.1) [8] IIS Bus Specification (Philips Semiconductors June 5 1996 revision) Table 14-1 Abbreviations CTQ Time Quanta Counter DSU Data Shift Unit fPERIPH fPIN USIC module clock frequency MCLK Master Clock Input frequency to baud rate generator Note: In the USIC chapter, the module clock is referred to as fPERIPH PPP Protocol Pre-Processor RSR Receive Shift Register SCLK Shift Clock TSR Transmit Shift Register 14.1 Overview This section gives an overview about the feature set of the USIC. 14.1.1 Features Each USIC channel can be individually configured to match the application needs, e.g. the protocol can be selected or changed during run time without the need for a reset. The following protocols are supported: • UART (ASC, asynchronous serial channel) – Module capability: receiver/transmitter with max. baud rate fPERIPH / 4 Reference Manual USIC, V2.14 14-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • – Wide baud rate range down to single-digit baud rates – Number of data bits per data frame: 1 to 63 – MSB or LSB first LIN Support by hardware (Local Interconnect Network) – Data transfers based on ASC protocol – Baud rate detection possible by built-in capture event of baud rate generator – Checksum generation under software control for higher flexibility SSC/SPI (synchronous serial channel with or without slave select lines) – Standard, Dual and Quad SPI format supported – Module capability: maximum baud rate fPERIPH / 2, limited by loop delay – Number of data bits per data frame 1 to 63, more with explicit stop condition – Parity bit generation supported – MSB or LSB first IIC (Inter-IC Bus) – Application baud rate 100 kbit/s to 400 kbit/s – 7-bit and 10-bit addressing supported – Full master and slave device capability IIS (infotainment audio bus) – Module capability: maximum baud rate fPERIPH / 2 Note: The real baud rates that can be achieved in a real application depend on the operating frequency of the device, timing parameters as described in the Data Sheet, signal delays on the PCB and timings of the peer device. In addition to the flexible choice of the communication protocol, the USIC structure has been designed to reduce the system load (CPU load) allowing efficient data handling. The following aspects have been considered: • • • Data buffer capability The standard buffer capability includes a double word buffer for receive data and a single word buffer for transmit data. This allows longer CPU reaction times (e.g. interrupt latency). Additional FIFO buffer capability In addition to the standard buffer capability, the received data and the data to be transmitted can be buffered in a FIFO buffer structure. The size of the receive and the transmit FIFO buffer can be programmed independently. Depending on the application needs, a total buffer capability of 64 data words can be assigned to the receive and transmit FIFO buffers of a USIC module (the two channels of the USIC module share the 64 data word buffer). In addition to the FIFO buffer, a bypass mechanism allows the introduction of highpriority data without flushing the FIFO buffer. Transmit control information For each data word to be transmitted, a 5-bit transmit control information has been added to automatically control some transmission parameters, such as word length, frame length, or the slave select control for the SPI protocol. The transmit control Reference Manual USIC, V2.14 14-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • • • • information is generated automatically by analyzing the address where the user software has written the data word to be transmitted (32 input locations = 25 = 5 bit transmit control information). This feature allows individual handling of each data word, e.g. the transmit control information associated to the data words stored in a transmit FIFO can automatically modify the slave select outputs to select different communication targets (slave devices) without CPU load. Alternatively, it can be used to control the frame length. Flexible frame length control The number of bits to be transferred within a data frame is independent of the data word length and can be handled in two different ways. The first option allows automatic generation of frames up to 63 bits with a known length. The second option supports longer frames (even unlimited length) or frames with a dynamically controlled length. Interrupt capability The events of each USIC channel can be individually routed to one of 6 service request outputs SR[5:0] available for each USIC module, depending on the application needs. Furthermore, specific start and end of frame indications are supported in addition to protocol-specific events. Flexible interface routing Each USIC channel offers the choice between several possible input and output pins connections for the communications signals. This allows a flexible assignment of USIC signals to pins that can be changed without resetting the device. Input conditioning Each input signal is handled by a programmable input conditioning stage with programmable filtering and synchronization capability. Baud rate generation Each USIC channel contains its own baud rate generator. The baud rate generation can be based either on the internal module clock or on an external frequency input. This structure allows data transfers with a frequency that can not be generated internally, e.g. to synchronize several communication partners. Transfer trigger capability In master mode, data transfers can be triggered by events generated outside the USIC module, e.g. by an input pin or a timer unit (transmit data validation). This feature allows time base related data transmission. Debugger support The USIC offers specific addresses to read out received data without interaction with the FIFO buffer mechanism. This feature allows debugger accesses without the risk of a corrupted receive data sequence. To reach a desired baud rate, two criteria have to be respected, the module capability and the application environment. The module capability is defined with respect to the module’s input clock frequency, being the base for the module operation. Although the module’s capability being much higher (depending on the module clock and the number Reference Manual USIC, V2.14 14-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) of module clock cycles needed to represent a data bit), the reachable baud rate is generally limited by the application environment. In most cases, the application environment limits the maximum reachable baud rate due to driver delays, signal propagation times, or due to EMI reasons. Note: Depending on the selected additional functions (such as digital filters, input synchronization stages, sample point adjustment, data structure, etc.), the maximum reachable baud rate can be limited. Please also take care about additional delays, such as (internal or external) propagation delays and driver delays (e.g. for collision detection in ASC mode, for IIC, etc.). Reference Manual USIC, V2.14 14-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) A block diagram of the USIC module/channel structure is shown in Figure 14-1. SRx User Interface PPP Data Shift Unit Input Stages ( ASC, SSC. ..) Channel 0 USICx fPER IPH _C1 Baud Rate Generator Data Buffer Data Shift Unit Pins USICx fPER IPH_C0 Baud Rate Generator Data Buffer To Interrupt Registers PPP Signal Distribution Interrupt Generation Input Stages ( ASC, SSC. ..) Channel 1 Optional : FIFO Data Buffer shared between U SICx_C0 and USICx_C1 USIC Module x Figure 14-1 USIC Module/Channel Structure Reference Manual USIC, V2.14 14-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2 Operating the USIC This section describes how to operate the USIC communication channel. 14.2.1 USIC Structure Overview This section introduces the USIC structure. 14.2.1.1 Channel Structure The USIC module contains two independent communication channels, with a structure as shown in Figure 14-1. The data shift unit and the data buffering of each channel support full-duplex data transfers. The protocol-specific actions are handled by the protocol pre-processors (PPP). In order to simplify data handling, an additional FIFO data buffer is optionally available for each USIC module to store transmit and receive data for each channel. Due to the independent channel control and baud rate generation, the communication protocol, baud rate and the data format can be independently programmed for each communication channel. 14.2.1.2 Input Stages For each protocol, the number of input signals used depends on the selected protocol. Each input signal is handled by an input stage (called DXn, where n=0-5) for signal conditioning, such as input selection, polarity control, or a digital input filter. They can be classified according to their meaning for the protocols, see Table 14-2. The inputs marked as “optional” are not needed for the standard function of a protocol and may be used for enhancements. The descriptions of protocol-specific items are given in the related protocol chapters. For the external frequency input, please refer to the baud rate generator section, and for the transmit data validation, to the data handling section. Reference Manual USIC, V2.14 14-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-2 Input Signals for Different Protocols Selected Protocol Shift Data Input(s) (handled by DX0, DX3, DX4 and DX5)1) Shift Clock Input (handled by DX1) Shift Control Input (handled by DX2) ASC, LIN RXD optional: external frequency input or TXD collision detection optional: transmit data validation Standard SSC, SPI (Master) DIN0 (MRST, MISO) optional: external frequency input or delay compensation optional: transmit data validation or delay compensation Standard SSC, SPI (Slave) DIN0 (MTSR, MOSI) SCLKIN SELIN DualSSC, SPI (Master) DIN[1:0] (MRST[1:0], MISO[1:0]) optional: external frequency input or delay compensation optional: transmit data validation or delay compensation DualSSC, SPI (Slave) DIN[1:0] (MTSR[1:0], MOSI[1:0]) SCLKIN SELIN QuadSSC, SPI (Master) DIN[3:0] (MRST[3:0], MISO[3:0]) optional: external frequency input or delay compensation optional: transmit data validation or delay compensation QuadSSC, SPI (Slave) DIN[3:0] (MTSR[3:0], MOSI[3:0]) SCLKIN SELIN IIC SDA SCL optional: transmit data validation IIS (Master) DIN0 optional: external frequency input or delay compensation optional: transmit data validation or delay compensation IIS (Slave) DIN0 SCLKIN WAIN 1) ASC, IIC, IIS and standard SSC protocols use only DX0 as the shift data input. Reference Manual USIC, V2.14 14-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Note: To allow a certain flexibility in assigning required USIC input functions to port pins of the device, each input stage can select the desired input location among several possibilities. The available USIC signals and their port locations are listed in the interconnects section, see Page 14-226. 14.2.1.3 Output Signals For each protocol, up to 14 protocol-related output signals are available. The number of actually used outputs depends on the selected protocol. They can be classified according to their meaning for the protocols, see Table 14-3. The outputs marked as “optional” are not needed for the standard function of a protocol and may be used for enhancements. The descriptions of protocol-specific items are given in the related protocol chapters. The MCLKOUT output signal has a stable frequency relation to the shift clock output (the frequency of MCLKOUT can be higher than for SCLKOUT) for synchronization purposes of a slave device to a master device. If the baud rate generator is not needed for a specific protocol (e.g. in SSC slave mode), the SCLKOUT and MCLKOUT signals can be used as clock outputs with 50% duty cycle with a frequency that can be independent from the communication baud rate. Table 14-3 Output Signals for Different Protocols Selected Shift Data Protocol Output(s) DOUT[3:0]1) Shift Clock Output SCLKOUT Shift Control Outputs SELO[7:0] Master Clock Output MCLKOUT ASC, LIN TXD not used not used optional: master time base Standard DOUT0 SSC, SPI (MTSR, MOSI) (Master) master shift clock slave select, chip select optional: master time base Standard DOUT0 SSC, SPI (MRST, MISO) (Slave) optional: independent clock output optional: independent clock output DualDOUT[1:0] SSC, SPI (MTSR[1:0], (Master) MOSI[1:0]) master shift clock slave select, chip select optional: master time base DualDOUT[1:0] SSC, SPI (MRST[1:0], (Slave) MISO[1:0]) optional: independent clock output optional: independent clock output Reference Manual USIC, V2.14 14-8 not used not used V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-3 Output Signals for Different Protocols (cont’d) Shift Control Outputs SELO[7:0] Master Clock Output MCLKOUT Selected Shift Data Protocol Output(s) DOUT[3:0]1) Shift Clock Output SCLKOUT QuadDOUT[3:0] SSC, SPI (MTSR[3:0], (Master) MOSI[3:0]) master shift clock slave select, chip select optional: master time base QuadDOUT[3:0] SSC, SPI (MRST[3:0], (Slave) MISO[3:0]) optional: independent clock output not used optional: independent clock output IIC SDA SCL not used optional: master time base IIS (master) DOUT0 master shift clock WA optional: master time base IIS (slave) DOUT0 optional: independent clock output optional: independent clock output not used 1) ASC, IIC, IIS and standard SSC protocols use only DOUT0 as the shift data output. Note: To allow a certain flexibility in assigning required USIC output functions to port pins of the device, most output signals are made available on several port pins. The port control itself defines pin-by-pin which signal is used as output signal for a port pin (see port chapter). The available USIC signals and their port locations are listed in the interconnects section, see Page 14-226. 14.2.1.4 Baud Rate Generator Each USIC Channel contains a baud rate generator structured as shown in Figure 14-2. It is based on coupled divider stages, providing the frequencies needed for the different protocols. It contains: • • • • A fractional divider to generate the input frequency fPIN = fFD for baud rate generation based on the internal system frequency fPERIPH. The DX1 input to generate the input frequency fPIN = fDX1 for baud rate generation based on an external signal. Two protocol-related counters: the divider mode counter to provide the master clock signal MCLK, the shift clock signal SCLK, and other protocol-related signals; and the capture mode timer for time interval measurement, e.g. baud rate detection. A time quanta counter associated to the protocol pre-processor defining protocolspecific timings, such shift control signals or bit timings, based on the input frequency fCTQIN. Reference Manual USIC, V2.14 14-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • The output signals MCLKOUT and SCLKOUT of the protocol-related divider that can be made available on pins. In order to adapt to different applications, some output characteristics of these signals can be configured. For device-specific details about availability of USIC signals on pins please refer to the interconnects section. BRG DX1 Input Protocol Pre-Processor 2 Enable fD X1 fPIN fFD fCTQIN CLKSEL Protocol SCLK Related Counter s Output Configration SCLKOUT Enable fPERIPH Fractional Divider Output Configration MCLK MCLKOUT Figure 14-2 Baud Rate Generator 14.2.1.5 Channel Events and Interrupts The notification of the user about events occurring during data traffic and data handling is based on: • • • Data transfer events related to the transmission or reception of a data word, independent of the selected protocol. Protocol-specific events depending on the selected protocol. Data buffer events related to data handling by the optional FIFO data buffers. 14.2.1.6 Data Shifting and Handling The data handling of the USIC module is based on an independent data shift unit (DSU) and a buffer structure that is similar for the supported protocols. The data shift and buffer registers are 16-bit wide (maximum data word length), but several data words can be concatenated to achieve longer data frames. The DSU inputs are the shift data (handled by input stage DX0, DX3, DX4 and DX5), the shift clock (handled by the input stage DX1), and the shift control (handled by the input stage DX2). The signal DOUT[3:0] represents the shift data outputs. Reference Manual USIC, V2.14 14-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Bypass Bypass Data FIFO 4 TBUF Buffered Transmit Data Transmit Data Optional Receive Data Buffer Buffered Receive Data RBUF0 RSR0[3:0] RBUF1 RSR1[3:0] DX0, DX[5:3] Inputs Shift Data Output(s) 4 DOUT[3:0] Shift Clock Input DX1 Input Shift Control Input In FIFO TSR s Data Shift Unit (DSU) TBUFx Out User Interface In INx OUTR Shift Data Input(s) Basic Data Buffer Out BYP Optional Transmit Data Buffer RBUF DX2 Input Receive Data Figure 14-3 Principle of Data Buffering The principle of data handling comprises: • • • A transmitter with transmit shift registers (TSR and TSR[3:0]) in the DSU and a transmit data buffer (TBUF). A data validation scheme allows triggering and gating of data transfers by external events under certain conditions. A receiver with two alternating sets of receive shift registers (RSR0[3:0] and RSR1[3:0]) in the DSU and a double receive buffer structure (RBUF0, RBUF1). The alternating receive shift registers support the reception of data streams and data frames longer than one data word. A user interface to handle data, interrupts, and status and control information. Basic Data Buffer Structure The read access to received data and the write access of data to be transmitted can be handled by a basic data buffer structure. The received data stored in the receiver buffers RBUF0/RBUF1 can be read directly from these registers. In this case, the user has to take care about the reception sequence to read these registers in the correct order. To simplify the use of the receive buffer structure, register RBUF has been introduced. A read action from this register delivers the data word received first (oldest data) to respect the reception sequence. With a read access from at least the low byte of RBUF, the data is automatically declared to be no longer new and the next received data word becomes visible in RBUF and can be read out next. Reference Manual USIC, V2.14 14-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Control Info TCI RBUF01SR RBUF01SR TBUF RBUF0 RBUF1 16 5 Location Data TBUF31 DS .. .. TBUF01 RBUFSR TBUF00 RBUF RBUFD Mirror Data Write Access Data Read Access Debug Read Access Figure 14-4 Data Access Structure without additional Data Buffer It is recommended to read the received data words by accesses to RBUF and to avoid handling of RBUF0 and RBUF1. The USIC module also supports the use of debug accesses to receive data words. Debugger read accesses should not disturb the receive data sequence and, as a consequence, should not target RBUF. Therefore, register RBUFD has been introduced. It contains the same value as RBUF, but a read access from RBUFD does not change the status of the data (same data can be read several times). In addition to the received data, some additional status information about each received data word is available in the receiver buffer status register RBUF01SR (related to data in RBUF0 and RBUF1) and RBUFSR (related to data in RBUF). Transmit data can be loaded to TBUF by software by writing to the transmit buffer input locations TBUFx (x = 00-31), consisting of 32 consecutive addresses. The data written to one of these input locations is stored in the transmit buffer TBUF. Additionally, the address of the written location is evaluated and can be used for additional control purposes. This 5-bit wide information (named Transmit Control Information TCI) can be used for different purposes in different protocols. FIFO Buffer Structure To allow easier data setup and handling, an additional data buffering mechanism can be optionally supported. The data buffer is based on the first-in-first-out principle (FIFO) that ensures that the sequence of transferred data words is respected. If a FIFO buffer structure is used, the data handling scheme (data with associated control information) is similar to the one without FIFO. The additional FIFO buffer can be Reference Manual USIC, V2.14 14-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) independently enabled/disabled for transmission and reception (e.g. if data FIFO buffers are available for a specific USIC channel, it is possible to configure the transmit data path without and the receive data path with FIFO buffering). The transmit FIFO buffer is addressed by using 32 consecutive address locations for INx instead of TBUFx (x=00-31) regardless of the FIFO depth. The 32 addresses are used to store the 5-bit TCI (together with the written data) associated with each FIFO entry. The receive FIFO can be read out at two independent addresses, OUTR and OUTDR instead of RBUF and RBUFD. A read from the OUTR location triggers the next data packet to be available for the next read (general FIFO mechanism). In order to allow nonintrusive debugging (without risk of data loss), a second address location (OUTDR) has been introduced. A read at this location delivers the same value as OUTR, but without modifying the FIFO contents. The transmit FIFO also has the capability to bypass the data stream and to load bypass data to TBUF. This can be used to generate high-priority messages or to send an emergency message if the transmit FIFO runs empty. The transmission control of the FIFO buffer can also use the transfer trigger and transfer gating scheme of the transmission logic for data validation (e.g. to trigger data transfers by events). Note: The available size of a FIFO data buffer for a USIC channel depends on the specific device. Please refer to the implementation chapter for details about available FIFO buffer capability. Reference Manual USIC, V2.14 14-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Control Info TCI RBUF01SR RBUF01SR TBUF RBUF0 RBUF1 Transmit FIFO Receive FIFO 5-bit IN31 TCI= 11111 16-bit TX Data . . . . IN01 TCI= 00001 TX Data IN00 TCI= 00000 TX Data OUTR OUTDR Mirror Data Write Access OUTR OUTDR Data Read Access Debug Read Access Figure 14-5 Data Access Structure with FIFO 14.2.2 Operating the USIC Communication Channel This section describes how to operate a USIC communication channel, including protocol control and status, mode control and interrupt handling. The following aspects have to be taken into account: • • • • • Enable the USIC module for operation and configure the behavior for the different device operation modes (see Page 14-16). Configure the pinning (refer to description in the corresponding protocol section). Configure the data structure (shift direction, word length, frame length, polarity, etc.). Configure the data buffer structure of the optional FIFO buffer area. A FIFO buffer can only be enabled if the related bit in register CCFG is set. Select a protocol by CCR.MODE. A protocol can only be selected if the related bit in register CCFG is set. Reference Manual USIC, V2.14 14-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.2.1 Protocol Control and Status The protocol-related control and status information are located in the protocol control register PCR and in the protocol status register PSR. These registers are shared between the available protocols. As a consequence, the meaning of the bit positions in these registers is different within the protocols. Use of PCR Bits The signification of the bits in register PCR is indicated by the protocol-related alias names for the different protocols. • • • • PCR for the ASC protocol (see Page 14-66) PCR for the SSC protocol (see Page 14-98) PCR for the IIC protocol (see Page 14-129) PCR for the IIS protocol (see Page 14-147) Use of PSR Flags The signification of the flags in register PSR is indicated by the protocol-related alias names for the different protocols. • • • • PSR flags for the ASC protocol (see Page 14-69) PSR flags for the SSC protocol (see Page 14-102) PSR flags for the IIC protocol (see Page 14-132) PSR flags for the IIS protocol (see Page 14-150) Reference Manual USIC, V2.14 14-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.2.2 Mode Control The mode control concept for system control tasks, such as suspend request for debugging, allows to program the module behavior under different device operating conditions. The behavior of a communication channel can be programmed for each of the device operating modes (normal operation, suspend mode). Therefore, each communication channel has an associated kernel state configuration register KSCFG defining its behavior in the following operating modes: • • Normal operation: This operating mode is the default operating mode when no suspend request is pending. The module clock is not switched off and the USIC registers can be read or written. The channel behavior is defined by KSCFG.NOMCFG. Suspend mode: This operating mode is requested when a suspend request is pending in the device. The module clock is not switched off and the USIC registers can be read or written. The channel behavior is defined by KSCFG.SUMCFG. The four kernel modes defined by the register KSCFG are shown in Table 14-4. Table 14-4 USIC Communication Channel Behavior Kernel Mode Channel Behavior KSCFG. NOMCFG Run mode 0 Channel operation as specified, no impact on data transfer 00B Run mode 1 01B Stop mode 0 Explicit stop condition as described in the protocol chapters 10B Stop mode 1 11B Generally, bit field KSCFG.NOMCFG should be configured for run mode 0 as default setting for standard operation. If a communication channel should not react to a suspend request (and to continue its operation as in normal mode), bit field KSCFG.SUMCFG has to be configured with the same value as KSCFG.NOMCFG. If the communication channel should show a different behavior and stop operation when a specific stop condition is reached, the code for stop mode 0 or stop mode 1 have to be written to KSCFG.SUMCFG. The stop conditions are defined for the selected protocol (see mode control description in the protocol section). Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG. Do not mix stop mode 0 and stop mode 1 and avoid transitions Reference Manual USIC, V2.14 14-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) from stop mode 0 to stop mode 1 (or vice versa) for the same communication channel. Note: In XMC1100, bit field KSCFG.SUMCFG is reset to its default value by any reset. If the suspend function is required during debugging, it is recommended that it is enabled in the user initialization code. Before programming the bit field, the module clock has to be enabled and special care needs to be taken while enabling the module clock as described in the CCU (Clock Gating Control) section of the SCU chapter. 14.2.2.3 General Channel Events and Interrupts The general event and interrupt structure is shown in Figure 14-6. If a defined condition is met, an event is detected and an event indication flag becomes automatically set. The flag stays set until it is cleared by software. If enabled, an interrupt can be generated if an event is detected. The actual status of the event indication flag has no influence on the interrupt generation. As a consequence, the event indication flag does not need to be cleared to generate further interrupts. Additionally, the service request output SRx of the USIC channel that becomes activated in case of an event condition can be selected by an interrupt node pointer. This structure allows to assign events to interrupts, e.g. depending on the application, several events can share the same interrupt routine (several events activate the same SRx output) or can be handled individually (only one event activates one SRx output). The SRx outputs are connected to interrupt control registers to handle the CPU reaction to the service requests. This assignment is described in the implementation section on Page 14-153. Clear Event Indication Flag Clear Event Indication Flag Interrupt Enable Interrupt Node Pointer 2 Set To SR0 Event Condition is met . . . .. . To SR5 Figure 14-6 General Event and Interrupt Structure Reference Manual USIC, V2.14 14-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.2.4 Data Transfer Events and Interrupts The data transfer events are based on the transmission or reception of a data word. The related indication flags are located in register PSR. All events can be individually enabled for interrupt generation. • • • • • • Receive event to indicate that a data word has been received: If a new received word becomes available in the receive buffer RBUF0 or RBUF1, either a receive event or an alternative receive event occurs. The receive event occurs if bit RBUFSR.PERR = 0. It is indicated by flag PSR.RIF and, if enabled, leads to receive interrupt. Receiver start event to indicate that a data word reception has started: When the receive clock edge that shifts in the first bit of a new data word is detected and reception is enabled, a receiver start event occurs. It is indicated by flag PSR.RSIF and, if enabled, leads to transmit buffer interrupt. In full duplex mode, this event follows half a shift clock cycle after the transmit buffer event and indicates when the shift control settings are internally “frozen” for the current data word reception and a new setting can be programmed. In SSC and IIS mode, the transmit data valid flag TCSR.TDV is cleared in single shot mode with the receiver start event. Alternative receive event to indicate that a specific data word has been received: If a new received word becomes available in the receive buffer RBUF0 or RBUF1, either a receive event or an alternative receive event occurs. The alternative receive event occurs if bit RBUFSR.PERR = 1. It is indicated by flag PSR.AIF and, if enabled, leads to alternative receive interrupt. Depending on the selected protocol, bit RBUFSR.PERR is set to indicate a parity error in ASC mode, the reception of the first byte of a new frame in IIC mode, and the WA information about right/left channel in IIS mode. In SSC mode, it is used as indication if the received word is the first data word, and is set if first and reset if not. Transmit shift event to indicate that a data word has been transmitted: A transmit shift event occurs with the last shift clock edge of a data word. It is indicated by flag PSR.TSIF and, if enabled, leads to transmit shift interrupt. Transmit buffer event to indicate that a data word transmission has been started: When a data word from the transmit buffer TBUF has been loaded to the shift register and a new data word can be written to TBUF, a transmit buffer event occurs. This happens with the transmit clock edge that shifts out the first bit of a new data word and transmission is enabled. It is indicated by flag PSR.TBIF and, if enabled, leads to transmit buffer interrupt. This event also indicates when the shift control settings (word length, shift direction, etc.) are internally “frozen” for the current data word transmission. In ASC and IIC mode, the transmit data valid flag TCSR.TDV is cleared in single shot mode with the transmit buffer event. Data lost event to indicate a loss of the oldest received data word: If the data word available in register RBUF (oldest data word from RBUF0 or RBUF1) Reference Manual USIC, V2.14 14-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) has not been read out before it becomes overwritten with new incoming data, this event occurs. It is indicated by flag PSR.DLIF and, if enabled, leads to a protocol interrupt. Table 14-5 shows the registers, bits and bit fields indicating the data transfer events and controlling the interrupts of a USIC channel. Table 14-5 Data Transfer Events and Interrupt Handling Event Indication Flag Indication cleared by Interrupt enabled by SRx Output selected by Standard receive event PSR.RIF PSCR.CRIF CCR.RIEN INPR.RINP Receive start event PSR.RSIF PSCR.CRSIF CCR.RSIEN INPR.TBINP Alternative receive event PSR.AIF PSCR.CAIF Transmit shift event PSR.TSIF PSCR.CTSIF CCR.TSIEN INPR.TSINP Transmit buffer event PSR.TBIF PSCR.CTBIF CCR.TBIEN INPR.TBINP Data lost event PSR.DLIF PSCR.CDLIF CCR.DLIEN INPR.PINP CCR.AIEN INPR.AINP Figure 14-7 shows the two transmit events and interrupts. PSCR CTSIF Clear PSR CCR TSIF INPR TSIEN TSINP 2 Set Transmit Shift Interrupt Transmit Shift Event .. . SR0 . . . SR5 (End of last transmit shift clock period of data word) PSCR CTBIF PSR Clear CCR TBIF INPR TBIEN Set TBINP Transmit Buffer Interrupt Transmit Buffer Event 2 . . . SR0 . . . SR5 (First transmit shift clock of data word) Figure 14-7 Transmit Events and Interrupts Reference Manual USIC, V2.14 14-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Figure 14-8 shows the receive events and interrupts. RBUFSR PERR PSCR CRIF Clear PSR CCR RIF Standard Receive Event INPR RIEN RINP 2 Set Standard Receive Interrupt .. . SR0 .. . SR5 New Data in RBUF Event 0 1 Alternate Receive Event Alternate Receive Interrupt . . . SR0 . . . SR5 Set CAIF Clear PSCR PSCR CRSIF Clear 2 AIF AIEN AINP PSR CCR INPR PSR CCR INPR RSIF RSIEN TBINP 2 Set Receive Start Interrupt Receive Start Event . . . SR0 . . . SR5 (First receive shift clock of data world) PSCR CDLIF Clear PSR CCR DLIF INPR DLIEN Set PINP Data Lost Interrupt Data Lost Event 2 . . . SR0 . . . SR5 (RBUF becomes overwritten without having been read out) Figure 14-8 Receive Events and Interrupts 14.2.2.5 Baud Rate Generator Event and Interrupt The baud rate generator event is based on the capture mode timer reaching its maximum value. It is indicated by flag PSR.BRGIF and, if enabled, leads to a protocol interrupt. Reference Manual USIC, V2.14 14-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-6 shows the registers, bits and bit fields indicating the baud rate generator event and controlling the interrupt of a USIC channel. Table 14-6 Baud Rate Generator Event and Interrupt Handling Event Indication Flag Indication cleared by Interrupt enabled by SRx Output selected by Baud rate generator event PSR. BRGIF PSCR. CBRGIF CCR. BRGIEN INPR.PINP Figure 14-9 shows the baud rate generator event and interrupt. PSCR CBRGIF Clear PSR CCR BRGIF BRGIEN Set Baud Rate Generator Event INPR PINP Baud Rate Generator Interrupt 2 .. . SR0 . . . SR5 (Capture mode timer reaches its maximum value) Figure 14-9 Baud Rate Generator Event and Interrupt Reference Manual USIC, V2.14 14-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.2.6 Protocol-specific Events and Interrupts These events are related to protocol-specific actions that are described in the corresponding protocol chapters. The related indication flags are located in register PSR. All events can be individually enabled for the generation of the common protocol interrupt. • • • • Protocol-specific events in ASC mode: Synchronization break, data collision on the transmit line, receiver noise, format error in stop bits, receiver frame finished, transmitter frame finished Protocol-specific events in SSC mode: MSLS event (start-end of frame in master mode), DX2T event (start/end of frame in slave mode), both based on slave select signals, parity error Protocol-specific events in IIC mode: Wrong transmit code (error in frame sequence), start condition received, repeated start condition received, stop condition received, non-acknowledge received, arbitration lost, slave read request, other general errors Protocol-specific events in IIS mode: DX2T event (change on WA line), WA falling edge or rising edge detected, WA generation finished Table 14-7 Protocol-specific Events and Interrupt Handling Event Indication Flag Indication cleared by Interrupt enabled by SRx Output selected by Protocol-specific PSR.ST[8:2] PSCR.CST[8:2] PCR.CTR[7:3]] events in ASC mode INPR.PINP Protocol-specific PSR.ST[3:2] PSCR.CST[3:2] PCR.CTR[15:14] events in SSC mode INPR.PINP Protocol-specific PSR.ST[8:1] PSCR.CST[8:1] PCR.CTR[24:18] events in IIC mode INPR.PINP Protocol-specific PSR.ST[6:3] PSCR.CST[6:3] PCR.CTR[6:4], events in PCR.CTR[15] IIS mode INPR.PINP 14.2.3 Operating the Input Stages All input stages offer the same feature set. They are used for all protocols, because the signal conditioning can be adapted in a very flexible way and the digital filters can be switched on and off separately. Reference Manual USIC, V2.14 14-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.3.1 General Input Structure There are generally two types of input stages, one for the data input stages DX0, DX[5:3] and the other for non-data input stages DX[2:1], as shown in Figure 14-10 and Figure 14-11. The difference is that for the data input stages, the input signal can be additionally selected from the port signal HWINn if hardware port control is enabled through CCR.HPCEN bit. All other enable/disable functions and selections are controlled independently for each input stage by bits in the registers DXnCR. The desired input signal can be selected among the input lines DXnA to DXnG and a permanent 1-level by programming bit field DSEL (for the data input stages, hardware port control must be disabled for DSEL to take effect). Please refer to the interconnects section (Section 14.12) for the device-specific input signal assignment. Bit DPOL allows a polarity inversion of the selected input signal to adapt the input signal polarity to the internal polarity of the data shift unit and the protocol state machine. For some protocols, the input signals can be directly forwarded to the data shift unit for the data transfers (DSEN = 0, INSW = 1) without any further signal conditioning. In this case, the data path does not contain any delay due to synchronization or filtering. In the case of noise on the input signals, there is the possibility to synchronize the input signal (signal DXnS is synchronized to fPERIPH) and additionally to enable a digital noise filter in the signal path. The synchronized input signal (and optionally filtered if DFEN = 1) is taken into account by DSEN = 1. Please note that the synchronization leads to a delay in the signal path of 2-3 times the period of fPERIPH. DXnCR DSEL DXnA DXnB HPCEN DXnCR DXnCR DPOL DXnCR DSEN INSW 000 001 0 ... ... DXnG 1 CCR 0 110 1 0 1 1 1 0 111 DXnS HWINn DXnINS Data Shift Unit Protocol Pre-Processor Digital Filter Edge Detection DFEN CM DXnT DXnCR DXnCR Figure 14-10 Input Conditioning for DX0 and DX[5:3] Reference Manual USIC, V2.14 14-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) DXnCR DSEL ... DXnG 1 DXnCR DPOL 000 001 0 ... DXnA DXnB DXnCR 1 DXnCR DSEN INSW 0 1 1 110 Data Shift Unit 0 111 DXnS Protocol Pre-Processor DXnINS Digital Filter Edge Detection DFEN CM DXnT DXnCR DXnCR Figure 14-11 Input Conditioning for DX[2:1] If the input signals are handled by a protocol pre-processor, the data shift unit is directly connected to the protocol pre-processor by INSW = 0. The protocol pre-processor is connected to the synchronized input signal DXnS and, depending on the selected protocol, also evaluates the edges. To support delay compensation in SSC and IIS protocols, the DX1 input stage additionally allows the receive shift clock to be controlled independently from the transmit shift clock through the bit DCEN. When DCEN = 0, the shift clock source is selected by INSW and is the same for both receive and transmit. When DCEN = 1, the receive shift clock is derived from the selected input line as shown in Figure 14-12. Reference Manual USIC, V2.14 14-24 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) DX1CR DSEN Similar to structure of DX2 DX1CR DX1CR INSW DCEN 1 0 1 0 1 Receive shift clock (DSU) 0 Transmit shift clock (DSU) 1 0 Signal from Protocol Pre-processor Figure 14-12 Delay Compensation Enable in DX1 14.2.3.2 Digital Filter The digital filter can be enabled to reduce noise on the input signals. Before being filtered, the input signal becomes synchronized to fPERIPH. If the filter is disabled, signal DXnS corresponds to the synchronized input signal. If the filter is enabled, pulses shorter than one filter sampling period are suppressed in signal DXnS. After an edge of the synchronized input signal, signal DXnS changes to the new value if two consecutive samples of the new value have been detected. In order to adapt the filter sampling period to different applications, it can be programmed. The first possibility is the system frequency fPERIPH. Longer pulses can be suppressed if the fractional divider output frequency fFD is selected. This frequency is programmable in a wide range and can also be used to determine the baud rate of the data transfers. In addition to the synchronization delay of 2-3 periods of fPERIPH, an enabled filter adds a delay of up to two filter sampling periods between the selected input and signal DXnS. 14.2.3.3 Edge Detection The synchronized (and optionally filtered) signal DXnS can be used as input to the data shift unit and is also an input to the selected protocol pre-processor. If the protocol preprocessor does not use the DXnS signal for protocol-specific handling, DXnS can be Reference Manual USIC, V2.14 14-25 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) used for other tasks, e.g. to control data transmissions in master mode (a data word can be tagged valid for transmission, see chapter about data buffering). A programmable edge detection indicates that the desired event has occurred by activating the trigger signal DXnT (introducing a delay of one period of fPERIPH before a reaction to this event can take place). 14.2.3.4 Selected Input Monitoring The selected input signal of each input stage has been made available with the signals DXnINS. These signals can be used in the system to trigger other actions, e.g. to generate interrupts. 14.2.3.5 Loop Back Mode The USIC transmitter output signals can be connected to the corresponding receiver inputs of the same communication channel in loop back mode. Therefore, the input “G” of the input stages that are needed for the selected protocol have to be selected. In this case, drivers for ASC, SSC, and IIS can be evaluated on-chip without the connections to port pins. Data transferred by the transmitter can be received by the receiver as if it would have been sent by another communication partner. 14.2.4 Operating the Baud Rate Generator The following blocks can be configured to operate the baud rate generator, see also Figure 14-2. 14.2.4.1 Fractional Divider The fractional divider generates its output frequency fFD by either dividing the input frequency fPERIPH by an integer factor n or by multiplication of n/1024. It has two operating modes: • Normal divider mode (FDR.DM = 01B): In this mode, the output frequency fFD is derived from the input clock fPERIPH by an integer division by a value between 1 and 1024. The division is based on a counter FDR.RESULT that is incremented by 1 with fPERIPH. After reaching the value 3FFH, the counter is loaded with FDR.STEP and then continues counting. In order to achieve fFD = fPERIPH, the value of STEP has to be programmed with 3FFH. The output frequency in normal divider mode is defined by the equation: (14.1) 1 f FD = f PERIPH × --n Reference Manual USIC, V2.14 with n = 1024 - STEP 14-26 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • Fractional divider mode (FDR.DM = 10B): In this mode, the output frequency fFD is derived from the input clock fPERIPH by a fractional multiplication of n/1024 for a value of n between 0 and 1023. In general, the fractional divider mode allows to program the average output clock frequency with a finer granularity than in normal divider mode. Please note that in fractional divider mode fFD can have a maximum period jitter of one fPERIPH period. This jitter is not accumulated over several cycles. The frequency fFD is generated by an addition of FDR.STEP to FDR.RESULT with fPERIPH. The frequency fFD is based on the overflow of the addition result over 3FFH. The output frequency in fractional divider mode is defined by the equation: (14.2) f FD n = f PERIPH × ------------1024 with n = STEP The output frequency fFD of the fractional divider is selected for baud rate generation by BRG.CLKSEL = 00B. 14.2.4.2 External Frequency Input The baud rate can be generated referring to an external frequency input (instead of to fPERIPH) if in the selected protocol the input stage DX1 is not needed (DX1CTR.INSW = 0). In this case, an external frequency input signal at the DX1 input stage can be synchronized and sampled with the system frequency fPERIPH. It can be optionally filtered by the digital filter in the input stage. This feature allows data transfers with frequencies that can not be generated by the device itself, e.g. for specific audio frequencies. If BRG.CLKSEL = 10B, the trigger signal DX1T determines fDX1. In this mode, either the rising edge, the falling edge, or both edges of the input signal can be used for baud rate generation, depending on the configuration of the DX1T trigger event by bit field DX1CTR.CM. The signal MCLK toggles with each trigger event of DX1T. If BRG.CLKSEL = 11B, the rising edges of the input signal can be used for baud rate generation. The signal MCLK represents the synchronized input signal DX1S. Both, the high time and the low time of external input signal must each have a length of minimum 2 periods of fPERIPH to be used for baud rate generation. 14.2.4.3 Divider Mode Counter The divider mode counter is used for an integer division delivering the output frequency fPDIV. Additionally, two divider stages with a fixed division by 2 provide the output signals MCLK and SCLK with 50% duty cycle. If the fractional divider mode is used, the maximum fractional jitter of 1 period of fPERIPH can also appear in these signals. The output frequencies of this divider is controlled by register BRG. Reference Manual USIC, V2.14 14-27 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) In order to define a frequency ratio between the master clock MCLK and the shift clock SCLK, the divider stage for MCLK is located in front of the divider by PDIV+1, whereas the divider stage for SCLK is located at the output of this divider. fMCLK = fSCLK = fPIN (14.3) 2 fPDIV (14.4) 2 In the case that the master clock is used as reference for external devices (e.g. for IIS components) and a fixed phase relation to SCLK and other timing signals is required, it is recommended to use the MCLK signal as input for the PDIV divider. If the MCLK signal is not used or a fixed phase relation is not necessary, the faster frequency fPIN can be selected as input frequency. 1 PDIV + 1 1 fPDIV = fMCLK × PDIV + 1 fPDIV = fPIN × if PPPEN = 0 (14.5) if PPPEN = 1 11 10 01 fCTQIN 00 fPIN Divide by 2 0 1 fMCLK fPPP Divide by PDIV + 1 fPDIV Divide by 2 fSC LK SCLK MCLK PPPEN CTQSEL BRG BRG Figure 14-13 Divider Mode Counter 14.2.4.4 Capture Mode Timer The capture mode timer is used for time interval measurement and is enabled by BRG.TMEN = 1. The timer works independently from the divider mode counter. Therefore, any serial data reception or transmission can continue while the timer is performing timing measurements. The timer counts fPPP periods and stops counting Reference Manual USIC, V2.14 14-28 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) when it reaches its maximum value. Additionally, a baud rate generator interrupt event is generated (bit PSR.BRGIF becomes set). If an event is indicated by DX0T or DX1T, the actual timer value is captured into bit field CMTR.CTV and the timer restarts from 0. Additionally, a transmit shift interrupt event is generated (bit PSR.TSIF becomes set). ≥1 DX0T DX1T Clear Divide by 2 fPIN 0 fPPP 1 fMC L K Capture Up-Counter Capture in CTV MCLK PPPEN BRG TMEN = 1 BRG Figure 14-14 Protocol-Related Counter (Capture Mode) The capture mode timer can be used to measure the baud rate in slave mode before starting or during data transfers, e.g. to measure the time between two edges of a data signal (by DX0T) or of a shift clock signal (by DX1T). The conditions to activate the DXnT trigger signals can be configured in each input stage. 14.2.4.5 Time Quanta Counter The time quanta counter CTQ associated to the protocol pre-processor allows to generate time intervals for protocol-specific purposes. The length of a time quantum tq is given by the selected input frequency fCTQIN and the programmed pre-divider value. The meaning of the time quanta depend on the selected protocol, please refer to the corresponding chapters for more protocol-specific information. fC TQIN Pre-Divider tq PCTQ BRG Time Quanta Counter CTQ Protocol Pre-Processor DCTQ BRG Figure 14-15 Time Quanta Counter Reference Manual USIC, V2.14 14-29 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.4.6 Master and Shift Clock Output Configuration The master clock output signal MCLKOUT available at the corresponding output pin can be configured in polarity. The MCLK signal can be generated for each protocol in order to provide a kind of higher frequency time base compared to the shift clock. The configuration mechanism of the master clock output signal MCLKOUT ensures that no shortened pulses can occur. Each MCLK period consists of two phases, an active phase, followed by a passive phase. The polarity of the MCLKOUT signal during the active phase is defined by the inverted level of bit BRG.MCLKCFG, evaluated at the start of the active phase. The polarity of the MCLKOUT signal during the passive phase is defined by bit BRG.MCLKCFG, evaluated at the start of the passive phase. If bit BRG.MCLKCFG is programmed with another value, the change is taken into account with the next change between the phases. This mechanism ensures that no shorter pulses than the length of a phase occur at the MCLKOUT output. In the example shown in Figure 14-16, the value of BRG.MCLKCFG is changed from 0 to 1 during the passive phase of MCLK period 2. The generation of the MCLKOUT signal is enabled/disabled by the protocol preprocessor, based on bit PCR.MCLK. After this bit has become set, signal MCLKOUT is generated with the next active phase of the MCLK period. If PCR.MCLK = 0 (MCLKOUT generation disabled), the level for the passive phase is also applied for active phase. MCLK Period 1 MCLK Period 2 MCLK Period 3 MCLK Period 4 MCLKOUT Active Passive Active Passive Active Passive Active Passive Phase Phase Phase Phase Phase Phase Phase Phase Bit BRG. MCLKCFG 0 1 Figure 14-16 Master Clock Output Configuration The shift clock output signal SCLKOUT available at the corresponding output pin can be configured in polarity and additionally, a delay of one period of fPDIV (= half SCLK period) can be introduced. The delay allows to adapt the order of the shift clock edges to the application requirements. If the delay is used, it has to be taken into account for the calculation of the signal propagation times and loop delays. The mechanism for the polarity control of the SCLKOUT signal is similar to the one for MCLKOUT, but based on bit field BRG.SCLKCFG. The generation of the SCLKOUT Reference Manual USIC, V2.14 14-30 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) signal is enabled/disabled by the protocol pre-processor. Depending on the selected protocol, the protocol pre-processor can control the generation of the SCLKOUT signal independently of the divider chain, e.g. for protocols without the need of a shift clock available at a pin, the SCLKOUT generation is disabled. 14.2.5 Operating the Transmit Data Path The transmit data path is based on 16-bit wide transmit shift registers (TSR and TSR[3:0]) and a transmit buffer TBUF. The data transfer parameters like data word length, data frame length, or the shift direction are controlled commonly for transmission and reception by the shift control register SCTR. The transmit control and status register TCSR controls the transmit data handling and monitors the transmit status. A change of the value of the data shift output signal DOUTx only happens at the corresponding edge of the shift clock input signal. The level of the last data bit of a data word/frame is held constant at DOUTx until the next data word begins with the next corresponding edge of the shift clock. 14.2.5.1 Transmit Buffering The transmit shift registers can not be directly accessed by software, because they are automatically updated with the value stored in the transmit buffer TBUF if a currently transmitted data word is finished and new data is valid for transmission. Data words can be loaded directly into TBUF by writing to one of the transmit buffer input locations TBUFx (see Page 14-33) or, optionally, by a FIFO buffer stage (see Page 14-39). Reference Manual USIC, V2.14 14-31 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Shift Clock Domain TSR3 Shift Data Output 3 Shift Data Output 2 TSR2 Shift Data Output 1 TSR1 TSR0 Shift Data Output 0 Shift Clock Input Shift Control Input 8 TSR Shift Clock Domain Control Shift and Status Control & of TSR Status 16 8 4 4 16 16 Data TCSR SCTR TBUF Transmit Control Optional FIFO System Clock Domain TBUFx Figure 14-17 Transmit Data Path 14.2.5.2 Transmit Data Shift Mode The transmit shift data can be selected to be shifted out one, two or four bits at a time through the corresponding number of output lines. This option allows the USIC to support protocols such as the Dual- and Quad-SSC. The selection is done through the bit field DSM in the shift control register SCTR. Note: The bit field SCTR.DSM controls the data shift mode for both the transmit and receive paths to allow the transmission and reception of data through one to four data lines. For the shift mode with two or four parallel data outputs, the data word and frame length must be in multiples of two or four respectively. The number of data shifts required to output a specific data word or data frame length is thus reduced by the factor of the number of parallel data output lines. For example, to transmit a 16-bit data word through four output lines, only four shifts are required. Reference Manual USIC, V2.14 14-32 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Depending on the shift mode, different transmit shift registers with different bit composition are used as shown in Table 14-8. Note that the ‘n’ in the table denotes the shift number less one, i.e. for the first data shift n = 0, the second data shift n = 1 and continues until the total number of shifts less one is reached. For all transmit shift registers, whether the first bit shifted out is the MSB or LSB depends on the setting of SCTR.SDIR. Table 14-8 Transmit Shift Register Composition Transmit Shift Registers Single Data Output (SCTR.DSM = 00B) Two Data Outputs (SCTR.DSM = 10B) Four Data Outputs (SCTR.DSM = 11B) TSR All data bits Not used Not used TSR0 Not used Bit n*2 Bit n*4 TSR1 Not used Bit n*2 + 1 Bit n*4 + 1 TSR2 Not used Not used Bit n*4 + 2 TSR3 Not used Not used Bit n*4 + 3 14.2.5.3 Transmit Control Information The transmit control information TCI is a 5-bit value derived from the address x of the written TBUFx or INx input location. For example, writing to TBUF31 generates a TCI of 11111B. The TCI can be used as an additional control parameter for data transfers to dynamically change the data word length, the data frame length, or other protocol-specific functions (for more details about this topic, please refer to the corresponding protocol chapters). The way how the TCI is used in different applications can be programmed by the bits WLEMD, FLEMD, SELMD, WAMD and HPCMD in register TCSR. Please note that not all possible settings lead to useful system behavior. • • Word length control: If TCSR.WLEMD = 1, bit field SCTR.WLE is updated with TCI[3:0] if a transmit buffer input location TBUFx is written. This function can be used in all protocols to dynamically change the data word length between 1 and 16 data bits per data word. Additionally, bit TCSR.EOF is updated with TCI[4]. This function can be used in SSC master mode to control the slave select generation to finish data frames. It is recommended to program TCSR.FLEMD = TCSR.SELMD = TCSR.WAMD = TCSR.HPCMD = 0. Frame length control: If TCSR.FLEMD = 1, bit field SCTR.FLE[4:0] is updated with TCI[4:0] and SCTR.FLE[5] becomes 0 if a transmit buffer input location TBUFx is written. This function can be used in all protocols to dynamically change the data frame length Reference Manual USIC, V2.14 14-33 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • between 1 and 32 data bits per data frame. It is recommended to program TCSR.SELMD = TCSR.WLEMD = TCSR.WAMD = TCSR.HPCMD = 0. Select output control: If TCSR.SELMD = 1, bit field PCR.CTR[20:16] is updated with TCI[4:0] and PCR.CTR[23:21] becomes 0 if a transmit buffer input location TBUFx is written. This function can be used in SSC master mode to define the targeted slave device(s). It is recommended to program TCSR.WLEMD = TCSR.FLEMD = TCSR.WAMD = TCSR.HPCMD = 0. Word address control: If TCSR.WAMD = 1, bit TCSR.WA is updated with TCI[4] if a transmit buffer input location TBUFx is written. This function can be used in IIS mode to define if the data word is transmitted on the right or the left channel. It is recommended to program TCSR.WLEMD = TCSR.FLEMD = TCSR.SELMD = TCSR.HPCMD = 0. Hardware Port control: If TCSR.HPCMD = 1, bit field SCTR.DSM is updated with TCI[1:0] if a transmit buffer input location TBUFx is written. This function can be used in SSC protocols to dynamically change the number of data input and output lines to set up for standard, dual and quad SSC formats. Additionally, bit TCSR.HPCDIR is updated with TCI[2]. This function can be used in SSC protocols to control the pin(s) direction when the hardware port control function is enabled through CCR.HPCEN = 1. It is recommended to program TCSR.FLEMD = TCSR.WLEMD = TCSR.SELMD = TCSR.WAMD = 0. 14.2.5.4 Transmit Data Validation The data word in the transmit buffer TBUF can be tagged valid or invalid for transmission by bit TCSR.TDV (transmit data valid). A combination of data flow related and event related criteria define whether the data word is considered valid for transmission. A data validation logic checks the start conditions for each data word. Depending on the result of the check, the transmit shift register is loaded with different values, according to the following rules: • • If a USIC channel is the communication master (it defines the start of each data word transfer), a data word transfer can only be started with valid data in the transmit buffer TBUF. In this case, the transmit shift register is loaded with the content of TBUF, that is not changed due to this action. If a USIC channel is a communication slave (it can not define the start itself, but has to react), a data word transfer requested by the communication master has to be started independently of the status of the data word in TBUF. If a data word transfer is requested and started by the master, the transmit shift register is loaded at the first corresponding shift clock edge either with the data word in TBUF (if it is valid for transmission) or with the level defined by bit SCTR.PDL (if the content of TBUF has not been valid at the transmission start). In both cases, the content of TBUF is not changed. Reference Manual USIC, V2.14 14-34 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The control and status bits for the data validation are located in register TCSR. The data validation is based on the logic blocks shown in Figure 14-18. Data Shift Unit DSU TCSR TDVTR TCSR DX2T TE Transfer Trigger TDV Shift Control Input DX2 DX2S Transfer Gating TDEN TCSR TBUF Data Validation TDSSM TCSR Figure 14-18 Transmit Data Validation • • • A transfer gating logic enables or disables the data word transfer from TBUF under software or under hardware control. If the input stage DX2 is not needed for data shifting, signal DX2S can be used for gating purposes. The transfer gating logic is controlled by bit field TCSR.TDEN. A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin. If the input stage DX2 is not needed for data shifting, signal DX2T can be used for trigger purposes. The transfer trigger logic is controlled by bit TCSR.TDVTR and the occurrence of a trigger event is indicated by bit TCSR.TE. For example, this can be used for triggering the data transfer upon receiving the Clear to Send (CTS) signal at DX2 in the RS-232 protocol. A data validation logic combining the inputs from the gating logic, the triggering logic and DSU signals. A transmission of the data word located in TBUF can only be started if the gating enables the start, bit TCSR.TDV = 1, and bit TCSR.TE = 1. The content of the transmit buffer TBUF should not be overwritten with new data while it is valid for transmission and a new transmission can start. If the content of TBUF has to be changed, it is recommended to clear bit TCSR.TDV by writing FMR.MTDV = 10B before updating the data. Bit TCSR.TDV becomes automatically set when TBUF is updated with new data. Another possibility are the interrupts TBI (for ASC and IIC) or RSI (for SSC and IIS) indicating that a transmission has started. While a transmission is in progress, TBUF can be loaded with new data. In this case the user has to take care that an update of the TBUF content takes place before a new transmission starts. With this structure, the following data transfer functionality can be achieved: Reference Manual USIC, V2.14 14-35 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • If bit TCSR.TDSSM = 0, the content of the transmit buffer TBUF is always considered as valid for transmission. The transfer trigger mechanism can be used to start the transfer of the same data word based on the selected event (e.g. on a timer base or an edge at a pin) to realize a kind of life-sign mechanism. Furthermore, in slave mode, it is ensured that always a correct data word is transmitted instead of the passive data level. Bit TCSR.TDSSM = 1 has to be programmed to allow word-by-word data transmission with a kind of single-shot mechanism. After each transmission start, a new data word has to be loaded into the transmit buffer TBUF, either by software write actions to one of the transmit buffer input locations TBUFx or by an optional data buffer (e.g. FIFO buffer). To avoid that data words are sent out several times or to allow data handling with an additional data buffer (e.g. FIFO), bit TCSR.TDSSM has to be 1. Bit TCSR.TDV becoming automatically set when a new data word is loaded into the transmit buffer TBUF, a transmission start can be requested by a write action of the data to be transmitted to at least the low byte of one of the transmit buffer input locations TBUFx. The additional information TCI can be used to control the data word length or other parameters independently for each data word by a single write access. Bit field FMR.MTDV allows software driven modification (set or clear) of bit TCSR.TDV. Together with the gating control bit field TCSR.TDEN, the user can set up the transmit data word without starting the transmission. A possible program sequence could be: clear TCSR.TDEN = 00B, write data to TBUFx, clear TCSR.TDV by writing FMR.MTDV = 10B, re-enable the gating with TCSR.TDEN = 01B and then set TCSR.TDV under software control by writing FMR.MTDV = 01B. 14.2.6 Operating the Receive Data Path The receive data path is based on two sets of 16-bit wide receive shift registers RSR0[3:0] and RSR1[3:0] and a receive buffer for each of the set (RBUF0 and RBUF1). The data transfer parameters like data word length, data frame length, or the shift direction are controlled commonly for transmission and reception by the shift control registers. Register RBUF01SR monitors the status of RBUF0 and RBUF1. 14.2.6.1 Receive Buffering The receive shift registers cannot be directly accessed by software, but their contents are automatically loaded into the receive buffer registers RBUF0 (or RBUF1 respectively) if a complete data word has been received or the frame is finished. The received data words in RBUF0 or RBUF1 can be read out in the correct order directly from register RBUF or, optionally, from a FIFO buffer stage (see Page 14-39). Reference Manual USIC, V2.14 14-36 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Shift Clock Domain RSR13 Shift Data Input 3 RSR03 RSR12 Shift Data Input 2 RSR02 RSR11 Shift Data Input 1 RSR01 8 8 4 4 4 4 RSR10 Shift Data Input 0 4 RSR00 Shift Control & Status Shift Clock Input Shift Control Input 4 4 8 4 Status of RSR0 Status of RSR1 RBUF01 RBUF01 SR (Lower SR (Upper 16-bit) 16-bit) 8 16 16 16 16 16 16 Data Data RBUF0 RBUF1 SCTR Receive Control RBUFSR RBUF System Clock Domain Figure 14-19 Receive Data Path 14.2.6.2 Receive Data Shift Mode Receive data can be selected to be shifted in one, two or four bits at a time through the corresponding number of input stages and data input lines. This option allows the USIC to support protocols such as the Dual- and Quad-SSC. The selection is done through the bit field DSM in the shift control register SCTR. Note: The bit field SCTR.DSM controls the data shift mode for both the transmit and receive paths to allow the transmission and reception of data through one to four data lines. For the shift mode with two or four parallel data inputs, the data word and frame length must be in multiples of two or four respectively. The number of data shifts required to input a specific data word or data frame length is thus reduced by the factor of the Reference Manual USIC, V2.14 14-37 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) number of parallel data input lines. For example, to receive a 16-bit data word through four input lines, only four shifts are required. Depending on the shift mode, different receive shift registers with different bit composition are used as shown in Table 14-8. Note that the ‘n’ in the table denotes the shift number less one, i.e. for the first data shift n = 0, the second data shift n = 1 and continues until the total number of shifts less one is reached. For all receive shift registers, whether the first bit shifted in is the MSB or LSB depends on the setting of SCTR.SDIR. Table 14-9 Receive Shift Register Composition Receive Shift Registers Input stage Single Data Input Two Data Inputs used (SCTR.DSM = (SCTR.DSM = 00B) 10B) Four Data Inputs (SCTR.DSM = 11B) RSRx0 DX0 All data bits Bit n*2 Bit n*4 RSRx1 DX3 Not used Bit n*2 + 1 Bit n*4 + 1 RSRx2 DX4 Not used Not used Bit n*4 + 2 RSRx3 DX5 Not used Not used Bit n*4 + 3 14.2.6.3 Baud Rate Constraints The following baud rate constraints have to be respected to ensure correct data reception and buffering. The user has to take care about these restrictions when selecting the baud rate and the data word length with respect to the module clock frequency fPERIPH. • • • • A received data word in a receiver shift registers RSRx[3:0] must be held constant for at least 4 periods of fPERIPH in order to ensure correct loading of the related receiver buffer register RBUFx. The shift control signal has to be constant inactive for at least 5 periods of fPERIPH between two consecutive frames in order to correctly detect the end of a frame. The shift control signal has to be constant active for at least 1 period of fPERIPH in order to correctly detect a frame (shortest frame). A minimum setup and hold time of the shift control signal with respect to the shift clock signal has to be ensured. 14.2.7 Hardware Port Control Hardware port control is intended for SSC protocols with half-duplex configurations, where a single port pin is used for both input and output data functions, to control the pin direction through a dedicated hardware interface. All settings in Pn_IOCRy.PCx, except for the input pull device selection and output driver type (open drain or push-pull), are overruled by the hardware port control. Reference Manual USIC, V2.14 14-38 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Input pull device selection is done through the Pn_IOCRy.PCx as before, while the output driver is fixed to push-pull-only in this mode. One, two or four port pins can be selected with the hardware port control to support SSC protocols with multiple bi-directional data lines, such as dual- and quad-SSC. This selection and the enable/disable of the hardware port control is done through CCR.HPCEN. The direction of all selected pins is controlled through a single bit SCTR.HPCDIR. SCTR.HPCDIR is automatically shadowed with the start of each data word to prevent changing of the pin direction in the middle of a data word transfer. 14.2.8 Operating the FIFO Data Buffer The FIFO data buffers of a USIC module are built in a similar way, with transmit buffer and receive buffer capability for each channel. Depending on the device, the amount of available FIFO buffer area can vary. In the XMC1100, totally 64 buffer entries can be distributed among the transmit or receive FIFO buffers of both channels of the USIC module. Buffered Receive Data OUTR Transmit Data INx User Interface USICx_C0 Buffered Receive Data OUTR Transmit Data INx USICx_C1 Receive FIFO Transmit FIFO Receive Data RBUF Buffered Transmit Data Data Shift Unit (DSU) TBUF Shift Data Input (s) Shift Data Output (s) Bypass Receive FIFO Transmit FIFO Receive Data RBUF Buffered Transmit Data TBUF Data Shift Unit (DSU) Shift Data Input (s) Shift Data Output (s) Bypass Figure 14-20 FIFO Buffer Overview In order to operate the FIFO data buffers, the following issues have to be considered: Reference Manual USIC, V2.14 14-39 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • FIFO buffer available and selected: The transmit FIFO buffer and the bypass structure are only available if CCFG.TB = 1, whereas the receive FIFO buffer is only available if CCFG.RB = 1. It is recommended to configure all buffer parameters while there is no data traffic for this USIC channel and the FIFO mechanism is disabled by TBCTR.SIZE = 0 (for transmit buffer) or RBCTR.SIZE = 0 (for receive buffer). The allocation of a buffer area by writing TBCTR or RBCTR has to be done while the corresponding FIFO buffer is disabled. The FIFO buffer interrupt control bits can be modified independently of data traffic. FIFO buffer setup: The total amount of available FIFO buffer entries limits the length of the transmit and receive buffers for each USIC channel. Bypass setup: In addition to the transmit FIFO buffer, a bypass can be configured as described on Page 14-50. 14.2.8.1 FIFO Buffer Partitioning If available, the FIFO buffer area consists of a defined number of FIFO buffer entries, each containing a data part and the associated control information (RCI for receive data, TCI for transmit data). One FIFO buffer entry represents the finest granularity that can be allocated to a receive FIFO buffer or a transmit FIFO buffer. All available FIFO buffer entries of a USIC module are located one after the other in the FIFO buffer area. The overall counting starts with FIFO entry 0, followed by 1, 2, etc. For each USIC module, a certain number of FIFO entries is available, that can be allocated to the channels of the same USIC module. It is not possible to assign FIFO buffer area to USIC channels that are not located within the same USIC module. For each USIC channel, the size of the transmit and the receive FIFO buffer can be chosen independently. For example, it is possible to allocate the full amount of available FIFO entries as transmit buffer for one USIC channel. Some possible scenarios of FIFO buffer partitioning are shown in Figure 14-21. Each FIFO buffer consists of a set of consecutive FIFO entries. The size of a FIFO data buffer can only be programmed as a power of 2, starting with 2 entries, then 4 entries, then 8 entries, etc. A FIFO data buffer can only start at a FIFO entry aligned to its size. For example, a FIFO buffer containing n entries can only start with FIFO entry 0, n, 2*n, 3*n, etc. and consists of the FIFO entries [x*n, (x+1)*n-1], with x being an integer number (incl. 0). It is not possible to have “holes” with unused FIFO entries within a FIFO buffer, whereas there can be unused FIFO entries between two FIFO buffers. Reference Manual USIC, V2.14 14-40 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Available Buffer Area Available Buffer Area Transmit Data Area for CH0 Transmit Data Area for CH1 Receive Data Area for CH0 Receive Data Area for CH0 Transmit Data Area for CH0 Scenario 2 Scenario 3 Scenario 4 Available Buffer Area Available Buffer Area Transmit Data Area for CH1 Transmit Data Area for CH1 Receive Data Area for CH1 Unused Entries Transmit Data Area for CH0 Receive Data Area for CH0 Scenario 1 Figure 14-21 FIFO Buffer Partitioning The data storage inside the FIFO buffers is based on pointers, that are internally updated whenever the data contents of the FIFO buffers have been modified. This happens automatically when new data is put into a FIFO buffer or the oldest data is taken from a FIFO buffer. As a consequence, the user program does not need to modify the pointers for data handling. Only during the initialization phase, the start entry of a FIFO buffer has to be defined by writing the number of the first FIFO buffer entry in the FIFO buffer to the corresponding bit field DPTR in register RBCTR (for a receive FIFO buffer) or TBCTR (for a transmit FIFO buffer) while the related bit field RBCTR.SIZE=0 (or TBCTR.SIZE = 0, respectively). The assignment of buffer entries to a FIFO buffer (regarding to size and pointers) must not be changed by software while the related USIC channel is taking part in data traffic. 14.2.8.2 Transmit Buffer Events and Interrupts The transmit FIFO buffer mechanism detects the following events, that can lead to interrupts (if enabled): • • Standard transmit buffer event Transmit buffer error event Standard Transmit Buffer Event The standard transmit buffer event is triggered by the filling level of the transmit buffer (given by TRBSR.TBFLVL) exceeding (TBCTR.LOF = 1) or falling below (TBCTR.LOF = 0)1) a programmed limit (TBCTR.LIMIT). 1) If the standard transmit buffer event is used to indicate that new data has to be written to one of the INx locations, TBCTR.LOF = 0 should be programmed. Reference Manual USIC, V2.14 14-41 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) If the event trigger with TRBSR.STBT feature is disabled (TBCTR.STBTEN = 0), the trigger of the standard transmit buffer event is based on the transition of the fill level from equal to below or above the limit, not the fact of being below or above. If TBCTR.STBTEN = 1, the transition of the fill level below or above the programmed limit additionally sets TRBSR.STBT. This bit triggers also the standard transmit buffer event whenever there is a transfer data to TBUF event or write data to INx event, depending on TBCTR.LOF setting. The way TRBSR.STBT is cleared depends on the trigger mode (selected by TBCTR.STBTM). If TBCTR.STBTM = 0, TRBSR.STBT is cleared by hardware when the buffer fill level equals the programmed limit again (TRBSR.TBFLVL = TBCTR.LIMIT). If TBCTR.STBTM = 1, TRBSR.STBT is cleared by hardware when the buffer fill level equals the buffer size (TRBSR.TBFLVL = TBCTR.SIZE). Note: The flag TRBSR.STBI is set only when the transmit buffer fill level exceeds or falls below the programmed limit (depending on TBCTR.LOF setting). Standard transmit buffer events triggered by TRBSR.STBT does not set the flag. Figure 14-22 shows examples of the standard transmit buffer event with the different TBCTR.STBTEN and TBCTR.STBTM settings. These examples are meant to illustrate the hardware behaviour and might not always represent real application use cases. Reference Manual USIC, V2.14 14-42 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) An interrupt is generated due to the transition of TBFLVL from 3 to 2. STBI is set. The interrupt is serviced and it is used to fill up the FIFO with the next 2 data words. Example 1: TBCTR settings: SIZE = 8 LIMIT = 3 LOF = 0 STBTEN = 0 STBTM = 0 2 data words are written to FIFO per standard buffer event interrupt … ... D1 D0 D0 D1 D1 D2 D2 TBFLVL = 3 STBI = 0 STBT = 0 TBFLVL = 2 STBI = 1 STBT = 0 TBUF D1 D2 D2 INx D3 D4 TBFLVL = 4 STBI = 0 STBT = 0 TBFLVL = 3 STBI = 0 STBT = 0 An interrupt is generated due to the transition of TBFLVL from 3 to 2. STBI and STBT are set. … ... D3 INx The interrupt is serviced and it is used to fill up the FIFO with the next 2 data words. As interrupt is still pending, a second interrupt due to TBUF load while STBT=1, has no effect. When TBFLVL = LIMIT, STBT is cleared. Example 2: TBCTR settings: SIZE = 8 LIMIT = 3 LOF = 0 STBTEN = 1 STBTM = 0 2 data words are written to FIFO per standard buffer event interrupt … ... D0 D0 D1 D1 D1 TBUF D2 D2 D2 D2 D2 INx D3 TBFLVL = 3 STBI = 0 STBT = 0 TBFLVL = 2 STBI = 1 STBT = 1 TBFLVL = 1 STBI = 1 STBT = 1 TBUF TBFLVL = 2 STBI = 0 STBT = 1 D4 TBFLVL = 3 STBI = 0 STBT = 0 The interrupt is serviced and it is used to fill up the FIFO with the next 6 data words. An interrupt is generated due to the transition of TBFLVL from 3 to 2. STBI and STBT are set. … ... D3 INx When TBFLVL = SIZE, STBT is cleared. D1 Example 3: TBCTR settings: SIZE = 8 LIMIT = 3 LOF = 0 STBTEN = 1 STBTM = 1 6 data words are written to FIFO per standard buffer event interrupt … ... D0 D0 D1 D1 D2 D2 TBFLVL = 3 STBI = 0 STBT = 0 TBFLVL = 2 STBI = 1 STBT = 1 TBUF D1 D2 INx D3 TBFLVL = 3 STBI = 0 STBT = 1 … ... D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 INx D7 TBFLVL = 7 STBI = 0 STBT = 1 D7 INx … ... … ... D8 TBFLVL = SIZE STBI = 0 STBT = 0 Figure 14-22 Standard Transmit Buffer Event Examples Transmit Buffer Error Event The transmit buffer error event is triggered when software has written to a full buffer. The written value is ignored. Reference Manual USIC, V2.14 14-43 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Transmit Buffer Events and Interrupt Handling Figure 14-23 shows the transmit buffer events and interrupts. TBCTR TRBSCR LOF CSTBI Clear TRBSR TBCTR TBCTR STBIEN STBINP STBI Set 2 ≥1 Transfer Data to TBUF Event Write Data to INx Event LIMIT equal to TBFLVL TBCTR 0 & 1 . . . & TRBSR Set . . . SR5 Standard Transmit Buffer Event STBTEN SR0 Standard Transmit Buffer Interrupt STBT Clear 0 TBFLVL equal to SIZE 1 TBCTR STBTM TRBSCR CTBERI TRBSR Clear TBCTR TBERI TBCTR TBERIEN Set ATBINP Transmit Buffer Error Interrupt Transmit Buffer Error Event 2 (Write to full transmit buffer) . . . SR0 . . . SR5 Figure 14-23 Transmit Buffer Events Table 14-10 shows the registers, bits and bit fields to indicate the transmit buffer events and to control the interrupts related to the transmit FIFO buffers of a USIC channel. Table 14-10 Transmit Buffer Events and Interrupt Handling Event Indication Indication Flag cleared by Standard transmit buffer event TRBSR. STBI Transmit buffer error event Reference Manual USIC, V2.14 TRBSCR. CSTBI TRBSR. STBT Cleared by hardware TRBSR. TBERI TRBSCR. CTBERI 14-44 Interrupt enabled by SRx Output selected by TBCTR. STBIEN TBCTR. STBINP TBCTR. TBERIEN TBCTR. ATBINP V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.2.8.3 Receive Buffer Events and Interrupts The receive FIFO buffer mechanism detects the following events, that can lead to an interrupt (if enabled): • • • Standard receive buffer event Alternative receive buffer event Receive buffer error event The standard receive buffer event and the alternative receive buffer event can be programmed to two different modes, one referring to the filling level of the receive buffer, the other one related to a bit position in the receive control information RCI of the data word that becomes available in OUTR. If the interrupt generation refers to the filling level of the receive FIFO buffer, only the standard receive buffer event is used, whereas the alternative receive buffer event is not used. This mode can be selected to indicate that a certain amount of data has been received, without regarding the content of the associated RCI. If the interrupt generation refers to RCI, the filling level is not taken into account. Each time a new data word becomes available in OUTR, an event is detected. If bit RCI[4] = 0, a standard receive buffer event is signaled, otherwise an alternative receive buffer device (RCI[4] = 1). Depending on the selected protocol and the setting of RBCTR.RCIM, the value of RCI[4] can hold different information that can be used for protocol-specific interrupt handling (see protocol sections for more details). Standard Receive Buffer Event in Filling Level Mode In filling level mode (RBCTR.RNM = 0), the standard receive buffer event is triggered by the filling level of the receive buffer (given by TRBSR.RBFLVL) exceeding (RBCTR.LOF = 1) or falling below (RBCTR.LOF = 0) a programmed limit (RBCTR.LIMIT).1) If the event trigger with bit TRBSR.SRBT feature is disabled (RBCTR.SRBTEN = 0), the trigger of the standard receive buffer event is based on the transition of the fill level from equal to below or above the limit, not the fact of being below or above. If RBCTR.SRBTEN = 1, the transition of the fill level below or above the programmed limit additionally sets the bit TRBSR.SRBT. This bit also triggers the standard receive buffer event each time there is a data read out event or new data received event, depending on RBCTR.LOF setting. The way TRBSR.SRBT is cleared depends on the trigger mode (selected by RBCTR.SRBTM). If RBCTR.SRBTM = 0, TRBSR.SRBT is cleared by hardware when the buffer fill level equals the programmed limit again (TRBSR.RBFLVL = 1) If the standard receive buffer event is used to indicate that new data has to be read from OUTR, RBCTR.LOF = 1 should be programmed. Reference Manual USIC, V2.14 14-45 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) RBCTR.LIMIT). If RBCTR.SRBTM = 1, TRBSR.SRBT is cleared by hardware when the buffer fill level equals 0 (TRBSR.RBFLVL = 0). Note: The flag TRBSR.SRBI is set only when the receive buffer fill level exceeds or falls below the programmed limit (depending on RBCTR.LOF setting). Standard receive buffer events triggered by TRBSR.SRBT does not set the flag. Reference Manual USIC, V2.14 14-46 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Figure 14-24 shows examples of the standard receive buffer event with the different RBCTR.SRBTEN and RBCTR.SRBTM settings. These examples are meant to illustrate the hardware behaviour and might not always represent real application use cases. An interrupt is generated due to the transition of RBFLVL from 1 to 2. SRBI is set. Example 1: RBCTR settings: SIZE = 8 LIMIT = 1 LOF = 1 SRBTEN = 0 SRBTM = 0 Interrupt is serviced and 2 data read outs from OUTR take place. D0 D3 D2 D1 D2 D1 D2 D1 D2 D1 D3 D0 D3 D0 RBFLVL = 1 SRBI = 0 SRBT = 0 RBFLVL = 2 SRBI = 1 SRBT = 0 RBFLVL = 1 SRBI = 0 SRBT = 0 RBFLVL = 0 SRBI = 0 SRBT = 0 An interrupt is generated due to the transition of RBFLVL from 1 to 2. SRBI and SRBT are set. FIFO continues to receive data while the interrupt is pending. Interrupt is serviced and 2 data reads from OUTR take place. RBUF D3 D2 D4 D3 D1 D1 D0 Example 2: RBCTR settings: SIZE = 8 LIMIT = 1 LOF = 1 SRBTEN = 1 SRBTM = 0 D4 D3 D0 D3 D0 RBUF D1 D2 D1 D2 D1 D2 RBUF D2 D1 D2 D1 D3 D0 D3 D0 D3 D0 RBFLVL = 1 SRBI = 0 SRBT = 0 RBFLVL = 2 SRBI = 1 SRBT = 1 RBFLVL = 4 SRBI = 1 SRBT = 1 RBUF Interrupt is serviced and 2 data reads from OUTR take place. Since now RBFLVL=LIMIT, SRBT is cleared D7 D0 D7 D0 D1 D6 D1 D6 D2 D5 D7 D0 D2 D5 D7 D0 D3 D4 D7 D0 D5 D2 D3 D4 D7 D0 D5 D2 D4 D2 D1 D1 D3 D1 D3 D2 D2 RBFLVL = 2 SRBI = 0 SRBT = 1 RBFLVL = 3 SRBI = 0 SRBT = 1 D0, D1 An interrupt is generated due to the transition of RBFLVL from 1 to 2. SRBI and SRBT are set. A new interrupt is generated due to the FIFO data receive event while SRBT=1 … ... RBUF … ... Interrupt is serviced and 2 data reads from OUTR take place. SRBT is also cleared due to RBFLVL=LIMIT. … ... D7 D0 D1 D6 … ... D2, D3 D2 D5 D1 D5 RBUF D3 D4 D2 D4 D4 RBFLVL = 1 SRBI = 0 SRBT = 0 RBFLVL = 2 SRBI = 1 SRBT = 1 D5 RBFLVL = 0 SRBI = 0 SRBT = 0 D5 RBFLVL = 0 SRBI = 0 SRBT = 0 For the case SRBTM = 1, SRBT remains set until the condition RBFLVL=0 is reached. While SRBT=1, a standard receive interrupt will be generated with each FIFO received data(LOF=1). Figure 14-24 Standard Receive Buffer Event Examples Reference Manual USIC, V2.14 14-47 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Standard and Alternate Receive Buffer Events in RCI Mode In RCI mode (RBCTR.RNM = 1), the standard receive buffer event is triggered when the OUTR stage is updated with a new data value with RCI[4] = 0. If the OUTR stage is updated with a new data value with RCI[4] = 1, an alternate receive buffer event is triggered instead. Receive Buffer Error Event The receive buffer error event is triggered if the software reads from an empty buffer, regardless of RBCTR.RNM value. The read data is invalid. Receive Buffer Events and Interrupt Handling Figure 14-25 shows the receiver buffer events and interrupts in filling level mode. RBCTR TRBSCR LOF CSRBI Clear TRBSR SRBI RBCTR RBCTR STBIEN SRBINP 2 Set ≥1 Data Read Out Event New Data Received Event LIMIT equal to RBFLVL .. . & RBCTR 0 & TRBSR Set . . SR5 Standard Receive Buffer Event SRBTEN 1 SR0 . Standard Receive Buffer Interrupt SRBT Clear 0 RBFLVL equal to 0 1 RBCTR SRBTM TRBSCR CRBERI Clear TRBSR RBCTR RBCTR RBERI RBERIEN ARBINP Set Receive Buffer Error Event 2 Receive Buffer Error Interrupt (Read from empty receive buffer) . . . SR0 . . . SR5 Figure 14-25 Receiver Buffer Events in Filling Level Mode Reference Manual USIC, V2.14 14-48 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Figure 14-26 shows the receiver buffer events and interrupts in RCI mode. OUTR RCI[4] TRBSCR CSRBI Clear TRBSR SRBI RBCTR RBCTR SRBIEN SRBINP 2 Set .. . New Data in OUTR Event 0 1 Standard Receive Buffer Event Standard Receive Buffer Interrupt Alternate Receive Buffer Event Alternate Receive Buffer Interrupt SR0 .. . SR5 . . . SR0 . . . SR5 Set CARBI Clear TRBSCR TRBSCR CRBERI Clear 2 ARBI ARBIEN TRBSR RBCTR TRBSR RBCTR RBERI RBERIEN ARBINP RBCTR 2 Set Receive Buffer Error Interrupt Receive Buffer Error Event (Read from empty receive buffer) . . . SR0 . . . SR5 Figure 14-26 Receiver Buffer Events in RCI Mode Table 14-11 shows the registers, bits and bit fields to indicate the receive buffer events and to control the interrupts related to the receive FIFO buffers of a USIC channel. Table 14-11 Receive Buffer Events and Interrupt Handling Event Indication Indication Flag cleared by Interrupt enabled by SRx Output selected by Standard receive buffer event TRBSR. SRBI TRBSCR. CSRBI RBCTR. SRBIEN RBCTR. SRBINP TRBSR. SRBT Cleared by hardware Reference Manual USIC, V2.14 14-49 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-11 Receive Buffer Events and Interrupt Handling (cont’d) Event Indication Indication Flag cleared by Interrupt enabled by SRx Output selected by Alternative receive buffer event TRBSR. ARBI TRBSCR. CARBI RBCTR. ARBIEN RBCTR. ARBINP Receive buffer error event TRBSCR. CRBERI RBCTR. RBERIEN RBCTR. ARBINTXDP TRBSR. RBERI 14.2.8.4 FIFO Buffer Bypass The data bypass mechanism is part of the transmit FIFO control block. It allows to introduce a data word in the data stream without modifying the transmit FIFO buffer contents, e.g. to send a high-priority message. The bypass structure consists of a bypass data word of maximum 16 bits in register BYP and some associated control information in register BYPCR. For example, these bits define the word length of the bypass data word and configure a transfer trigger and gating mechanism similar to the one for the transmit buffer TBUF. The bypass data word can be tagged valid or invalid for transmission by bit BYRCR.BDV (bypass data valid). A combination of data flow related and event related criteria define whether the bypass data word is considered valid for transmission. A data validation logic checks the start conditions for this data word. Depending on the result of the check, the transmit buffer register TBUF is loaded with different values, according to the following rules: • • • • • • Data from the transmit FIFO buffer or the bypass data can only be transferred to TBUF if TCSR.TDV = 0 (TBUF is empty). Bypass data can only be transferred to TBUF if the bypass is enabled by BYPCR.BDEN or the selecting gating condition is met. If the bypass data is valid for transmission and has either a higher transmit priority than the FIFO data or if the transmit FIFO is empty, the bypass data is transferred to TBUF. If the bypass data is valid for transmission and has a lower transmit priority than the FIFO buffer that contains valid data, the oldest transmit FIFO data is transferred to TBUF. If the bypass data is not valid for transmission and the FIFO buffer contains valid data, the oldest FIFO data is transferred to TBUF. If neither the bypass data is valid for transmission nor the transmit FIFO buffer contains valid data, TBUF is unchanged. The bypass data validation is based on the logic blocks shown in Figure 14-27. • A transfer gating logic enables or disables the bypass data word transfer to TBUF under software or under hardware control. If the input stage DX2 is not needed for Reference Manual USIC, V2.14 14-50 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • data shifting, signal DX2S can be used for gating purposes. The transfer gating logic is controlled by bit field BYPCR.BDEN. A transfer trigger logic supports data word transfers related to events, e.g. timer based or related to an input pin. If the input stage DX2 is not needed for data shifting, signal DX2T can be used for trigger purposes. The transfer trigger logic is controlled by bit BYPCR.BDVTR. A bypass data validation logic combining the inputs from the gating logic, the triggering logic and TCSR.TDV. TBUF TDV BYPCR BDVTR BYPCR DX2T Transfer Trigger BDV Bypass Data Validation Shift Control Input DX2 DX2S Transfer Gating BDEN BDSSM BYPCR BYPCR Figure 14-27 Bypass Data Validation With this structure, the following bypass data transfer functionality can be achieved: • • Bit BYPCR.BDSSM = 1 has to be programmed for a single-shot mechanism. After each transfer of the bypass data word to TBUF, the bypass data word has to be tagged valid again. This can be achieved either by writing a new bypass data word to BYP or by DX2T if BDVTR = 1 (e.g. trigger on a timer base or an edge at a pin). Bit BYPCR.BDSSM = 0 has to be programmed if the bypass data is permanently valid for transmission (e.g. as alternative data if the data FIFO runs empty). 14.2.8.5 FIFO Access Constraints The data in the shared FIFO buffer area is accessed by the hardware mechanisms for data transfer of each communication channel (for transmission and reception) and by software to read out received data or to write data to be transmitted. As a consequence, the data delivery rate can be limited by the FIFO mechanism. Each access by hardware to the FIFO buffer area has priority over a software access, that is delayed in case of an access collision. In order to avoid data loss and stalling of the CPU due to delayed software accesses, the Reference Manual USIC, V2.14 14-51 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) baud rate, the word length and the software access mechanism have to be taken into account. Each access to the FIFO data buffer area by software or by hardware takes one period of fPERIPH. Especially a continuous flow of very short, consecutive data words can lead to an access limitation. 14.2.8.6 Handling of FIFO Transmit Control Information In addition to the transmit data, the transmit control information TCI can be transferred from the transmit FIFO or bypass structure to the USIC channel. Depending on the selected protocol and the enabled update mechanism, some settings of the USIC channel parameters can be modified. The modifications are based on the TCI of the FIFO data word loaded to TBUF or by the bypass control information if the bypass data is loaded into TBUF. • • • • • TCSR.SELMD = 1: update of PCR.CTR[20:16] by FIFO TCI or BYPCR.BSELO with additional clear of PCR.CTR[23:21] TCSR.WLEMD = 1: update of SCTR.WLE and TCSR.EOF by FIFO TCI or BYPCR.BWLE (if the WLE information is overwritten by TCI or BWLE, the user has to take care that FLE is set accordingly) TCSR.FLEMD = 1: update of SCTR.FLE[4:0] by FIFO TCI or BYPCR.BWLE with additional clear of SCTR.FLE[5] TCSR.HPCMD = 1: update of SCTR.DSM and SCTR.HPCDIR by FIFO TCI or BYPCR.BHPC TCSR.WAMD = 1: update of TCSR.WA by FIFO TCI[4] See Section 14.2.5.3 for more details on TCI. Reference Manual USIC, V2.14 14-52 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) FIFO / Bypass USIC Channel BDATA 16 TBUF 16 Transmit FIFO 5 SELMD TCI CTR[20:16] 5 BSEL0 0 Bypass Control CTR[23:21] WLEMD BWLE WLE , EOF 4+ 1 FLEMD FLE[4:0] 0 HPCMD TCI[2:0] BHPC FLE[5] DSM 3 HPCDIR WAMD TCI[4] WA Figure 14-28 TCI Handling with FIFO / Bypass Reference Manual USIC, V2.14 14-53 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.3 Asynchronous Serial Channel (ASC = UART) The asynchronous serial channel ASC covers the reception and the transmission of asynchronous data frames and provides a hardware LIN support. The receiver and transmitter being independent, frames can start at different points in time for transmission and reception. The ASC mode is selected by CCR.MODE = 0010B with CCFG.ASC = 1 (ASC mode available). 14.3.1 Signal Description An ASC connection is characterized by the use of a single connection line between a transmitter and a receiver. The receiver input RXD signal is handled by the input stage DX0. ASC Module A ASC Module B DIN0 RBUF DX0 RXD RXD DOUT0 TBUF fPER IPH (ASC A) DIN0 DX0 RBUF DOUT0 TXD TBUF TXD Transfer Control Transfer Control Baud Rate Generator Baud Rate Generator fPER IPH (ASC B) Figure 14-29 ASC Signal Connections for Full-Duplex Communication For full-duplex communication, an independent communication line is needed for each transfer direction. Figure 14-29 shows an example with a point-to-point full-duplex connection between two communication partners ASC A and ASC B. For half-duplex or multi-transmitter communication, a single communication line is shared between the communication partners. Figure 14-30 shows an example with a point-to-point half-duplex connection between ASC A and ASC B. In this case, the user has to take care that only one transmitter is active at a time. In order to support transmitter collision detection, the input stage DX1 can be used to monitor the level of the transmit line and to check if the line is in the idle state or if a collision occurred. There are two possibilities to connect the receiver input DIN0 to the transmitter output Reference Manual USIC, V2.14 14-54 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) DOUT0. Communication partner ASC A uses an internal connection with only the transmit pin TXD, that is delivering its input value as RXD to the DX0 input stage for reception and to DX1 to check for transmitter collisions. Communication partner ASC B uses an external connection between the two pins TXD and RXD. ASC Module A ASC Module B DIN0 RBUF TBUF DX0 RBUF DOUT0 DOUT0 DX1 fPER IPH (ASC A) RXD DX0 DIN0 TBUF TXD TXD DX1 Transfer Control Transfer Control Baud Rate Generator Baud Rate Generator fPER IPH (ASC B) Figure 14-30 ASC Signal Connections for Half-Duplex Communication 14.3.2 Frame Format A standard ASC frame is shown in Figure 14-31. It consists of: • • • • • An idle time with the signal level 1. One start of frame bit (SOF) with the signal level 0. A data field containing a programmable number of data bits (1-63). A parity bit (P), programmable for either even or odd parity. It is optionally possible to handle frames without parity bit. One or two stop bits with the signal level 1. Reference Manual USIC, V2.14 14-55 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 1 IDLE SOF DATA 1 Bit 1-63 Bit P STOP IDLE 0 0-1 Bit 1-2 Bits Figure 14-31 Standard ASC Frame Format The protocol specific bits (SOF, P, STOP) are automatically handled by the ASC protocol state machine and do not appear in the data flow via the receive and transmit buffers. 14.3.2.1 Idle Time The receiver and the transmitter independently check the respective data input lines (DX0, DX1) for being idle. The idle detection ensures that an SOF bit of a recently enabled ASC module does not collide with an already running frame of another ASC module. In order to start the idle detection, the user software has to clear bits PSR.RXIDLE and/or PSR.TXIDLE, e.g. before selecting the ASC mode or during operation. If a bit is cleared by software while a data transfer is in progress, the currently running frame transfer is finished normally before starting the idle detection again. Frame reception is only possible if PSR.RXIDLE = 1 and frame transmission is only possible if PSR.TXIDLE = 1. The duration of the idle detection depends on the setting of bit PCR.IDM. In the case that a collision is not possible, the duration can be shortened and the bus can be declared as being idle by setting PCR.IDM = 0. In the case that the complete idle detection is enabled by PCR.IDM = 1, the data input of DX0 is considered as idle (PSR.RXIDLE becomes set) if a certain number of consecutive passive bit times has been detected. The same scheme applies for the transmitter’s data input of DX1. Here, bit PSR.TXIDLE becomes set if the idle condition of this input signal has been detected. The duration of the complete idle detection is given by the number of programmed data bits per frame plus 2 (in the case without parity) or plus 3 (in the case with parity). The counting of consecutive bit times with 1 level restarts from the beginning each time an edge is found, after leaving a stop mode or if ASC mode becomes enabled. If the idle detection bits PSR.RXIDLE and/or TXIDLE are cleared by software, the counting scheme is not stopped (no re-start from the beginning). As a result, the cleared bit(s) can become set immediately again if the respective input line still meets the idle criterion. Please note that the idle time check is based on bit times, so the maximum time can be up to 1 bit time more than programmed value (but not less). Reference Manual USIC, V2.14 14-56 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.3.2.2 Start Bit Detection The receiver input signal DIN0 (selected signal of input stage DX0) is checked for a falling edge. An SOF bit is detected when a falling edge occurs while the receiver is idle or after the sampling point of the last stop bit. To increase noise immunity, the SOF bit timing starts with the first falling edge that is detected. If the sampled bit value of the SOF is 1, the previous falling edge is considered to be due to noise and the receiver is considered to be idle again. 14.3.2.3 Data Field The length of the data field (number of data bits) can be programmed by bit field SCTR.FLE. It can vary between 1 and 63 data bits, corresponding to values of SCTR.FLE = 0 to 62 (the value of 63 is reserved and must not be programmed in ASC mode). The data field can consist of several data words, e.g. a transfer of 12 data bits can be composed of two 8-bit words, with the 12 bits being split into 8-bits of the first word and 4 bits of the second word. The user software has to take care that the transmit data is available in-time, once a frame has been started. If the transmit buffer runs empty during a running data frame, the passive data level (SCTR.PDL) is sent out. The shift direction can be programmed by SCTR.SDIR. The standard setting for ASC frames with LSB first is achieved with the default setting SDIR = 0. 14.3.2.4 Parity Bit The ASC allows parity generation for transmission and parity check for reception on frame base. The type of parity can be selected by bit field CCR.PM, common for transmission and reception (no parity, even or odd parity). If the parity handling is disabled, the ASC frame does not contain any parity bit. For consistency reasons, all communication partners have to be programmed to the same parity mode. After the last data bit of the data field, the transmitter automatically sends out its calculated parity bit if parity generation has been enabled. The receiver interprets this bit as received parity and compares it to its internally calculated one. The received parity bit value and the result of the parity check are monitored in the receiver buffer status registers, RBUFSR and RBUF01SR, as receiver buffer status information. These registers contain bits to monitor a protocol-related argument (PAR) and protocol-related error indication (PERR). 14.3.2.5 Stop Bit(s) Each ASC frame is completed by 1 or 2 of stop bits with the signal level 1 (same level as the idle level). The number of stop bits is programmable by bit PSR.STPB. A new start bit can be transferred directly after the last stop bit. Reference Manual USIC, V2.14 14-57 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.3.3 Operating the ASC In order to operate the ASC protocol, the following issues have to be considered: • • • • Select ASC mode: It is recommended to configure all parameters of the ASC that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 01B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the ASC mode can be enabled by CCR.MODE = 0010B afterwards. Pin connections: Establish a connection of input stage DX0 with the selected receive data input pin (signal DIN0) with DX0CR.INSW = 0 and configure a transmit data output pin (signal DOUT0). For collision or idle detection of the transmitter, the input stage DX1 has to be connected to the selected transmit output pin, also with DX1CR.INSW = 0. Additionally, program DX2CR.INSW = 0. Due to the handling of the input data stream by the synchronous protocol handler, the propagation delay of the synchronization in the input stage has to be considered. Note that the step to enable the alternate output port functions should only be done after the ASC mode is enabled, to avoided unintended spikes on the output. Bit timing configuration: The desired baud rate setting has to be selected, comprising the fractional divider, the baud rate generator and the bit timing. Please note that not all feature combinations can be supported by the application at the same time, e.g. due to propagation delays. For example, the length of a frame is limited by the frequency difference of the transmitter and the receiver device. Furthermore, in order to use the average of samples (SMD = 1), the sampling point has to be chosen to respect the signal settling and data propagation times. Data format configuration: The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the register SCTR. If required by the application, the data input and output signals can be inverted. Additionally, the parity mode has to be configured (CCR.PM). 14.3.3.1 Bit Timing In ASC mode, each bit (incl. protocol bits) is divided into time quanta in order to provide granularity in the sub-bit range to adjust the sample point to the application requirements. The number of time quanta per bit is defined by bit fields BRG.DCTQ and the length of a time quantum is given by BRG.PCTQ. In the example given in Figure 14-32, one bit time is composed of 16 time quanta (BRG.DCTQ = 15). It is not recommended to program less than 4 time quanta per bit time. Reference Manual USIC, V2.14 14-58 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Bit field PCR.SP determines the position of the sampling point for the bit value. The value of PCR.SP must not be set to a value greater than BRG.DCTQ. It is possible to sample the bit value only once per bit time or to take the average of samples. Depending on bit PCR.SMD, either the current input value is directly sampled as bit value, or a majority decision over the input values sampled at the latest three time quanta is taken into account. The standard ASC bit timing consists of 16 time quanta with sampling after 8 or 9 time quanta with majority decision. The bit timing setup (number of time quanta and the sampling point definition) is common for the transmitter and the receiver. Due to independent bit timing blocks, the receiver and the transmitter can be in different time quanta or bit positions inside their frames. The transmission of a frame is aligned to the time quanta generation. 1 Bit Time PCR.SP = 15 PCR.SP = 8 Time Quanta 0 1 2 3 4 5 6 = sample taken if SMD= 0 7 8 9 10 11 12 13 14 15 = sample taken if SMD= 1 Figure 14-32 ASC Bit Timing The sample point setting has to be adjusted carefully if collision or idle detection is enabled (via DX1 input signal), because the driver delay and some external delays have to be taken into account. The sample point for the transmit line has to be set to a value where the bit level is stable enough to be evaluated. If the sample point is located late in the bit time, the signal itself has more time to become stable, but the robustness against differences in the clock frequency of transmitter and receiver decreases. 14.3.3.2 Baud Rate Generation The baud rate fASC in ASC mode depends on the number of time quanta per bit time and their timing. The baud rate setting should only be changed while the transmitter and the receiver are idle. The bits in register BRG define the baud rate setting: • BRG.CTQSEL to define the input frequency fCTQIN for the time quanta generation Reference Manual USIC, V2.14 14-59 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • BRG.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) BRG.DCTQ to define the number of time quanta per bit time The standard setting is given by CTQSEL = 00B (fCTQIN = fPDIV) and PPPEN = 0 (fPPP = fPIN). Under these conditions, the baud rate is given by: fASC = fPIN × 1 1 1 × × DCTQ +1 PCTQ + 1 PDIV + 1 (14.6) In order to generate slower frequencies, two additional divide-by-2 stages can be selected by CTQSEL = 10B (fCTQIN = fSCLK) and PPPEN = 1 (fPPP = fMCLK), leading to: fASC = fPIN 2×2 × 1 1 1 × × PCTQ + 1 PDIV + 1 DCTQ + 1 (14.7) 14.3.3.3 Noise Detection The ASC receiver permanently checks the data input line of the DX0 stage for noise (the check is independent from the setting of bit PCR.SMD). Bit PSR.RNS (receiver noise) becomes set if the three input samples of the majority decision are not identical at the sample point for the bit value. The information about receiver noise gets accumulated over several bits in bit PSR.RNS (it has to be cleared by software) and can trigger a protocol interrupt each time noise is detected if enabled by PCR.RNIEN. 14.3.3.4 Collision Detection In some applications, such as data transfer over a single data line shared by several sending devices (see Figure 14-30), several transmitters have the possibility to send on the same data output line TXD. In order to avoid collisions of transmitters being active at the same time or to allow a kind of arbitration, a collision detection has been implemented. The data value read at the TXD input at the DX1 stage and the transmitted data bit value are compared after the sampling of each bit value. If enabled by PCR.CDEN = 1 and a bit sent is not equal to the bit read back, a collision is detected and bit PSR.COL is set. If enabled, bit PSR.COL = 1 disables the transmitter (the data output lines become 1) and generates a protocol interrupt. The content of the transmit shift register is considered as invalid, so the transmit buffer has to be programmed again. 14.3.3.5 Pulse Shaping For some applications, the 0 level of transmitted bits with the bit value 0 is not applied at the transmit output during the complete bit time. Instead of driving the original 0 level, Reference Manual USIC, V2.14 14-60 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) only a 0 pulse is generated and the remaining time quanta of the bit time are driven with 1 level. The length of a bit time is not changed by the pulse shaping, only the signalling is changed. In the standard ASC signalling scheme, the 0 level is signalled during the complete bit time with bit value 0 (ensured by programming PCR.PL = 000B). In the case PCR.PL > 000B, the transmit output signal becomes 0 for the number of time quanta defined by PCR.PL. In order to support correct reception with pulse shaping by the transmitter, the sample point has to be adjusted in the receiver according to the applied pulse length. 0-Pulse for PL = 001 B 0-Pulse for PL = 010 B 0-Pulse for PL = 111 B 0-Pulse for PL = 000 B Time Quanta 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Figure 14-33 Transmitter Pulse Length Control Figure 14-34 shows an example for the transmission of an 8-bit data word with LSB first and one stop bit (e.g. like for IrDA). The polarity of the transmit output signal has been inverted by SCTR.DOCFG = 01B. Reference Manual USIC, V2.14 14-61 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Idle STOP D7 D6 D5 D4 D3 D2 D1 D0 SOF ASC Frame Idle Bit Value DOUT Pulse Figure 14-34 Pulse Output Example 14.3.3.6 Automatic Shadow Mechanism The contents of the protocol control register PCR, as well as bit field SCTR.FLE are internally kept constant while a data frame is transferred by an automatic shadow mechanism (shadowing takes place with each frame start). The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. Bit fields SCTR.WLE and SCTR.SDIR are shadowed automatically with the start of each data word. As a result, a data frame can consist of data words with a different length. It is recommended to change SCTR.SDIR only when no data frame is running to avoid interference between hardware and software. Please note that the starting point of a data word can be different for a transmitter and a receiver. In order to ensure correct handling, it is recommended to modify SCTR.WLE only while transmitter and receiver are both idle. If the transmitter and the receiver are referring to the same data signal (e.g. in a LIN bus system), SCTR.WLE can be modified while a data transfer is in progress after the RSI event has been detected. 14.3.3.7 End of Frame Control The number of bits per ASC frame is defined by bit field SCTR.FLE. In order to support different frame length settings for consecutively transmitted frames, this bit field can be modified by hardware. The automatic update mechanism is enabled by TCSR.FLEMD = 1 (in this case, bits TCSR.WLEMD, SELMD, WAMD and HPCMD have to be written with 0). If enabled, the transmit control information TCI automatically overwrites the bit field TCSR.FLEMD when the ASC frame is started (leading to frames with 1 to 32 data bits). The TCI value represents the written address location of TBUFxx (without additional data Reference Manual USIC, V2.14 14-62 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) buffer) or INxx (with additional data buffer). With this mechanism, an ASC with 8 data bits is generated by writing a data word to TBUF07 (IN07, respectively). 14.3.3.8 Mode Control Behavior In ASC mode, the following kernel modes are supported: • • • Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0: Bit PSR.TXIDLE is cleared. A new transmission is not started. A current transmission is finished normally. Bit PSR.RXIDLE is not modified. Reception is still possible. When leaving stop mode 0, bit TXIDLE is set according to PCR.IDM. Stop Mode 1: Bit PSR.TXIDLE is cleared. A new transmission is not started. A current transmission is finished normally. Bit PSR.RXIDLE is cleared. A new reception is not possible. A current reception is finished normally. When leaving stop mode 1, bits TXIDLE and RXIDLE are set according to PCR.IDM. 14.3.3.9 Disabling ASC Mode In order to switch off ASC mode without any data corruption, the receiver and the transmitter have to be both idle. This is ensured by requesting Stop Mode 1 in register KSCFG. After waiting for the end of the frame, the ASC mode can be disabled. 14.3.3.10 Protocol Interrupt Events The following protocol-related events are generated in ASC mode and can lead to a protocol interrupt. The collision detection and the transmitter frame finished events are related to the transmitter, whereas the receiver events are given by the synchronization break detection, the receiver noise detection, the format error checks and the end of the received frame. Please note that the bits in register PSR are not automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • • Collision detection: This interrupt indicates that the transmitted value (DOUT0) does not match with the input value of the DX1 input stage at the sample point of a bit. For more details refer to Page 14-60. Transmitter frame finished: This interrupt indicates that the transmitter has completely finished a frame. Bit PSR.TFF becomes set at the end of the last stop bit. The DOUT0 signal assignment to port pins can be changed while no transmission is in progress. Receiver frame finished: This interrupt indicates that the receiver has completely finished a frame. Bit Reference Manual USIC, V2.14 14-63 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • PSR.RFF becomes set at the end of the last stop bit. The DIN0 signal assignment to port pins can be changed while no reception is in progress. Synchronization break detection: This interrupt can be used in LIN networks to indicate the reception of the synchronization break symbol (at the beginning of a LIN frame). Receiver noise detection: This interrupt indicates that the input value at the sample point of a bit and at the two time quanta before are not identical. Format error: The bit value of the stop bit(s) is defined as 1 level for the ASC protocol. A format error is signalled if the sampled bit value of a stop bit is 0. 14.3.3.11 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to ASC frame handling. • • • • Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. This is the earliest point in time when a new data word can be written to TBUF. With this event, bit TCSR.TDV is cleared and new data can be loaded to the transmit buffer. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Receiver start interrupt RSI: Bit PSR.RSIF is set after the sample point of the first data bit of a data word. Receiver interrupt RI and alternative interrupt AI: Bit PSR.RIF is set after the sampling point of the last data bit of a data word if this data word is not directly followed by a parity bit (parity generation disabled or not the last word of a data frame). If the data word is directly followed by a parity bit (last data word of a data frame and parity generation enabled), bit PSR.RIF is set after the sampling point of the parity bit if no parity error has been detected. If a parity error has been detected, bit PSR.AIF is set instead of bit PSR.RIF. The first data word of a data frame is indicated by RBUFSR.SOF = 1 for the received word. Bit PSR.RIF is set for a receiver interrupt RI with WA = 0. Bit PSR.AIF is set for a alternative interrupt AI with WA = 1. 14.3.3.12 Baud Rate Generator Interrupt Handling The baud rate generator interrupt indicate that the capture mode timer has reached its maximum value. With this event, the bit PSR.BRGIF is set. Reference Manual USIC, V2.14 14-64 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.3.3.13 Protocol-Related Argument and Error The protocol-related argument (RBUFSR.PAR) and the protocol-related error (RBUFSR.PERR) are two flags that are assigned to each received data word in the corresponding receiver buffer status registers. In ASC mode, the received parity bit is monitored by the protocol-related argument and the result of the parity check by the protocol-related error indication (0 = received parity bit equal to calculated parity value). This information being elaborated only for the last received data word of each data frame, both bit positions are 0 for data words that are not the last data word of a data frame or if the parity generation is disabled. 14.3.3.14 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTR.SIZE > 0), it is recommended to set RBCTR.RCIM = 11B in ASC mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTR.RCI[0] = 1, a parity error is indicated by OUTR.RCI[4] = 1, and the received parity bit value is given by OUTR.RCI[3]. The standard receive buffer event and the alternative receive buffer event can be used for the following operations in RCI mode (RBCTR.RNM = 1): • • A standard receive buffer event indicates that a data word can be read from OUTR that has been received without parity error. An alternative receive buffer event indicates that a data word can be read from OUTR that has been received with parity error. 14.3.3.15 Sync-Break Detection The receiver permanently checks the DIN0 signal for a certain number of consecutive bit times with 0 level. The number is given by the number of programmed bits per frame (SCTR.FLE) plus 2 (in the case without parity) or plus 3 (in the case with parity). If a 0 level is detected at a sample point of a bit after this event has been found, bit PSR.SBD is set and additionally, a protocol interrupt can be generated (if enabled by PCR.SBIEN = 1). The counting restarts from 0 each time a falling edge is found at input DIN0. This feature can be used for the detection of a synchronization break for slave devices in a LIN bus system (the master does not check for sync break). For example, in a configuration for 8 data bits without parity generation, bit PCR.SBD is set after at the next sample point at 0 level after 10 complete bit times have elapsed (representing the sample point of the 11th bit time since the first falling edge). 14.3.3.16 Transfer Status Indication The receiver status can be monitored by flag PSR[9] = BUSY if bit PCR.CTR[16] (receiver status enable RSTEN) is set. In this case, bit BUSY is set during a complete frame reception from the beginning of the start of frame bit to the end of the last stop bit. Reference Manual USIC, V2.14 14-65 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The transmitter status can be monitored by flag PSR[9] = BUSY if bit PCR.CTR[17] (transmitter status enable TSTEN) is set. In this case, bit BUSY is set during a complete frame reception from the beginning of the start of frame bit to the end of the last stop bit. If both bits RSTEN and TSTEN are set, flag BUSY indicates the logical OR-combination of the receiver and the transmitter status. If both bits are cleared, flag BUSY is not modified depending on the transfer status (status changes are ignored). 14.3.4 ASC Protocol Registers In ASC mode, the registers PCR and PSR handle ASC related information. 14.3.4.1 ASC Protocol Control Register In ASC mode, the PCR register bits or bit fields are defined as described in this section. PCR Protocol Control Register [ASC Mode] (3CH) 31 30 29 28 27 26 25 24 MCL K 0 rw r 15 14 13 12 11 10 PL SP rw rw 9 8 23 22 21 20 19 18 17 16 TST RST EN EN 7 6 5 4 3 2 rw rw 1 0 FFIE FEIE RNIE CDE SBIE STP IDM SMD N N N N N B rw Field Bits Type Description SMD 0 rw Reference Manual USIC, V2.14 Reset Value: 0000 0000H rw rw rw rw rw rw rw Sample Mode This bit field defines the sample mode of the ASC receiver. The selected data input signal can be sampled only once per bit time or three times (in consecutive time quanta). When sampling three times, the bit value shifted in the receiver shift register is given by a majority decision among the three sampled values. Only one sample is taken per bit time. The current 0B input value is sampled. Three samples are taken per bit time and a majority 1B decision is made. 14-66 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description STPB 1 rw Stop Bits This bit defines the number of stop bits in an ASC frame. The number of stop bits is 1. 0B 1B The number of stop bits is 2. IDM 2 rw Idle Detection Mode This bit defines if the idle detection is switched off or based on the frame length. The bus idle detection is switched off and bits 0B PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before. The bus is considered as idle after a number of 1B consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit). SBIEN 3 rw Synchronization Break Interrupt Enable This bit enables the generation of a protocol interrupt if a synchronization break is detected. The automatic detection is always active, so bit SBD can be set independently of SBIEN. The interrupt generation is disabled. 0B The interrupt generation is enabled. 1B CDEN 4 rw Collision Detection Enable This bit enables the reaction of a transmitter to the collision detection. 0B The collision detection is disabled. If a collision is detected, the transmitter stops its 1B data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software. RNIEN 5 rw Receiver Noise Detection Interrupt Enable This bit enables the generation of a protocol interrupt if receiver noise is detected. The automatic detection is always active, so bit PSR.RNS can be set independently of PCR.RNIEN. The interrupt generation is disabled. 0B The interrupt generation is enabled. 1B Reference Manual USIC, V2.14 14-67 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description FEIEN 6 rw Format Error Interrupt Enable This bit enables the generation of a protocol interrupt if a format error is detected. The automatic detection is always active, so bits PSR.FER0/FER1 can be set independently of PCR.FEIEN. The interrupt generation is disabled. 0B 1B The interrupt generation is enabled. FFIEN 7 rw Frame Finished Interrupt Enable This bit enables the generation of a protocol interrupt if the receiver or the transmitter reach the end of a frame. The automatic detection is always active, so bits PSR.RFF or PSR.TFF can be set independently of PCR.FFIEN. The interrupt generation is disabled. 0B The interrupt generation is enabled. 1B SP [12:8] rw Sample Point This bit field defines the sample point of the bit value. The sample point must not be located outside the programmed bit timing (PCR.SP ≤ BRG.DCTQ). PL [15:13] rw Pulse Length This bit field defines the length of a 0 data bit, counted in time quanta, starting with the time quantum 0 of each bit time. Each bit value that is a 0 can lead to a 0 pulse that is shorter than a bit time, e.g. for IrDA applications. The length of a bit time is not changed by PL, only the length of the 0 at the output signal. The pulse length must not be longer than the programmed bit timing (PCR.PL ≤ BRG.DCTQ). This bit field is only taken into account by the transmitter and is ignored by the receiver. 000B The pulse length is equal to the bit length (no shortened 0). 001B The pulse length of a 0 bit is 2 time quanta. 010B The pulse length of a 0 bit is 3 time quanta. ... 111B The pulse length of a 0 bit is 8 time quanta. Reference Manual USIC, V2.14 14-68 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RSTEN 16 rw Receiver Status Enable This bit enables the modification of flag PSR[9] = BUSY according to the receiver status. Flag PSR[9] is not modified depending on the 0B receiver status. Flag PSR[9] is set during the complete reception of 1B a frame. TSTEN 17 rw Transmitter Status Enable This bit enables the modification of flag PSR[9] = BUSY according to the transmitter status. Flag PSR[9] is not modified depending on the 0B transmitter status. 1B Flag PSR[9] is set during the complete transmission of a frame. MCLK 31 rw Master Clock Enable This bit enables the generation of the master clock MCLK. 0B The MCLK generation is disabled and the MCLK signal is 0. The MCLK generation is enabled. 1B 0 [30:18] r Reserved Returns 0 if read; should be written with 0. 14.3.4.2 ASC Protocol Status Register In ASC mode, the PSR register bits or bit fields are defined as described in this section. The bits and bit fields in register PSR are not cleared by hardware. The flags in the PSR register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but does not lead to further actions (no interrupt generation). Writing a 0 has no effect. The PSR flags should be cleared by software before enabling a new protocol. Reference Manual USIC, V2.14 14-69 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) PSR Protocol Status Register [ASC Mode] (48H) 31 30 29 28 13 14 AIF RIF TBIF TSIF DLIF RSIF rwh rwh rwh 11 26 15 rwh 12 27 rwh 10 rwh 25 9 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 0 BRG IF r rwh 8 7 6 5 4 3 2 1 0 RXID TXID BUS FER FER TFF RFF RNS COL SBD LE LE Y 1 0 r rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description TXIDLE 0 rwh Transmission Idle This bit shows if the transmit line (DX1) has been idle. A frame transmission can only be started if TXIDLE is set. 0B The transmitter line has not yet been idle. The transmitter line has been idle and frame 1B transmission is possible. RXIDLE 1 rwh Reception Idle This bit shows if the receive line (DX0) has been idle. A frame reception can only be started if RXIDLE is set. The receiver line has not yet been idle. 0B 1B The receiver line has been idle and frame reception is possible. SBD 2 rwh Synchronization Break Detected1) This bit is set if a programmed number of consecutive bit values with level 0 has been detected (called synchronization break, e.g. in a LIN bus system). A synchronization break has not yet been detected. 0B A synchronization break has been detected. 1B COL 3 rwh Collision Detected1) This bit is set if a collision has been detected (with PCR.CDEN = 1). 0B A collision has not yet been detected and frame transmission is possible. A collision has been detected and frame 1B transmission is not possible. Reference Manual USIC, V2.14 14-70 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RNS 4 rwh Receiver Noise Detected1) This bit is set if receiver noise has been detected. Receiver noise has not been detected. 0B 1B Receiver noise has been detected. FER0 5 rwh Format Error in Stop Bit 01) This bit is set if a 0 has been sampled in the stop bit 0 (called format error 0). A format error 0 has not been detected. 0B 1B A format error 0 has been detected. FER1 6 rwh Format Error in Stop Bit 11) This bit is set if a 0 has been sampled in the stop bit 1 (called format error 1). A format error 1 has not been detected. 0B 1B A format error 1 has been detected. RFF 7 rwh Receive Frame Finished1) This bit is set if the receiver has finished the last stop bit. 0B The received frame is not yet finished. The received frame is finished. 1B TFF 8 rwh Transmitter Frame Finished1) This bit is set if the transmitter has finished the last stop bit. 0B The transmitter frame is not yet finished. 1B The transmitter frame is finished. BUSY 9 r Transfer Status BUSY This bit indicates the receiver status (if PCR.RSTEN = 1) or the transmitter status (if PCR.TSTEN = 1) or the logical OR combination of both (if PCR.RSTEN = PCR.TSTEN = 1). A data transfer does not take place. 0B 1B A data transfer currently takes place. RSIF 10 rwh Receiver Start Indication Flag 0B A receiver start event has not occurred. 1B A receiver start event has occurred. DLIF 11 rwh Data Lost Indication Flag 0B A data lost event has not occurred. 1B A data lost event has occurred. TSIF 12 rwh Transmit Shift Indication Flag 0B A transmit shift event has not occurred. 1B A transmit shift event has occurred. Reference Manual USIC, V2.14 14-71 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TBIF 13 rwh Transmit Buffer Indication Flag 0B A transmit buffer event has not occurred. A transmit buffer event has occurred. 1B RIF 14 rwh Receive Indication Flag 0B A receive event has not occurred. 1B A receive event has occurred. AIF 15 rwh Alternative Receive Indication Flag 0B An alternative receive event has not occurred. 1B An alternative receive event has occurred. BRGIF 16 rwh Baud Rate Generator Indication Flag 0B A baud rate generator event has not occurred. A baud rate generator event has occurred. 1B 0 [31:17 r ] Reserved Returns 0 if read; should be written with 0. 1) This status bit can generate a protocol interrupt (see Page 14-22). The general interrupt status flags are described in the general interrupt chapter. 14.3.5 Hardware LIN Support In order to support the LIN protocol, bit TCSR.FLEMD = 1 should be set for the master. For slave devices, it can be cleared and the fixed number of 8 data bits has to be set (SCTR.FLE = 7H). For both, master and slave devices, the parity generation has to be switched off (CCR.PM = 00B) and transfers take place with LSB first (SCTR.SDIR = 0) and 1 stop bit (PCR.STPB = 0). The Local Interconnect Network (LIN) data exchange protocol contains several symbols that can all be handled in ASC mode. Each single LIN symbol represents a complete ASC frame. The LIN bus is a master-slave bus system with a single master and multiple slaves (for the exact definition please refer to the official LIN specification). A complete LIN frame contains the following symbols: • Synchronization break: The master sends a synchronization break to signal the beginning of a new frame. It contains at least 13 consecutive bit times at 0 level, followed by at least one bit time at 1 level (corresponding to 1 stop bit). Therefore, TBUF11 if the transmit buffer is used, (or IN11 if the FIFO buffer is used) has to be written with 0 (leading to a frame with SOF followed by 12 data bits at 0 level). A slave device shall detect 11 consecutive bit times at 0 level, which done by the synchronization break detection. Bit PSR.SBD is set if such an event is detected and a protocol interrupt can be generated. Additionally, the received data value of 0 appears in the receive buffer and a format error is signaled. Reference Manual USIC, V2.14 14-72 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • If the baud rate of the slave has to be adapted to the master, the baud rate measurement has to be enabled for falling edges by setting BRG.TMEN = 1, DX0CR.CM = 10H and DX1CR.CM = 00H before the next symbol starts. Synchronization byte: The master sends this symbol after writing the data value 55H to TBUF07 (or IN07). A slave device can either receive this symbol without any further action (and can discard it) or it can use the falling edges for baud rate measurement. Bit PSR.TSIF = 1 (with optionally the corresponding interrupt) indicates the detection of a falling edge and the capturing of the elapsed time since the last falling edge in CMTR.CTV. Valid captured values can be read out after the second, third, fourth and fifth activation of TSIF. After the fifth activation of TSIF within this symbol, the baud rate detection can be disabled (BRG.TMEN = 0) and BRG.PDIV can be programmed with the captured CMTR.CTV value divided by twice the number of time quanta per bit (assuming BRG.PCTQ = 00B). Other symbols: The other symbols of a LIN frame can be handled with ASC data frames without specific actions. If LIN frames should be sent out on a frame base by the LIN master, the input DX2 can be connected to external timers to trigger the transmit actions (e.g. the synchronization break symbol has been prepared but is started if a trigger occurs). Please note that during the baud rate measurement of the ASC receiver, the ASC transmitter of the same USIC channel can still perform a transmission. Reference Manual USIC, V2.14 14-73 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4 Synchronous Serial Channel (SSC) The synchronous serial channel SSC covers the data transfer function of an SPI-like module. It can handle reception and transmission of synchronous data frames between a device operating in master mode and at least one device in slave mode. Besides the standard SSC protocol consisting of one input and one output data line, SSC protocols with two (Dual-SSC) or four (Quad-SSC) input/output data lines are also supported. The SSC mode is selected by CCR.MODE = 0001B with CCFG.SSC = 1 (SSC mode is available). 14.4.1 Signal Description A synchronous SSC data transfer is characterized by a simultaneous transfer of a shift clock signal together with the transmit and/or receive data signal(s) to determine when the data is valid (definition of transmit and sample point). SSC Communication Master DOUT0 TBUF DIN0 RBUF DX0 Baud Rate Generator Slave Select Generator SCLKOUT SELOx SSC Communication Slave Master Transmit / Slave Receive DIN0 Master Receive / Slave Transmit DOUT0 Slave Clock Slave Select fPER IPH (Master) DX0 RBUF TBUF SCLKIN DX1 SELIN DX2 fPER IPH (Slave) Figure 14-35 SSC Signals for Standard Full-Duplex Communication In order to explicitly indicate the start and the end of a data transfer and to address more than one slave devices individually, the SSC module supports the handling of slave select signals. They are optional and are not necessarily needed for SSC data transfers. The SSC module supports up to 8 different slave select output signals for master mode operation (named SELOx, with x = 0-7) and 1 slave select input SELIN for slave mode. In most applications, the slave select signals are active low. Reference Manual USIC, V2.14 14-74 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) A device operating in master mode controls the start and end of a data frame, as well as the generation of the shift clock and slave select signals. This comprises the baud rate setting for the shift clock and the delays between the shift clock and the slave select output signals. If several SSC modules are connected together, there can be only one SSC master at a time, but several slaves. Slave devices receive the shift clock and optionally a slave select signal(s). For the programming of the input stages DXn please refer to Page 14-22. Table 14-12 SSC Communication Signals SSC Mode Receive Data Shift Clock Slave Select(s) Standard SSC Master MRST1), MTSR2), input DIN0, Output DOUT0 handled by DX0 Transmit Data Output SCLKOUT Output(s) SELOx Standard SSC Slave MTSR, MRST, input DIN0, Output DOUT0 handled by DX0 Input SCLKIN, input SELIN, handled by DX1 handled by DX2 Dual-SSC Master MRST[1:0], MTSR[1:0], input DIN[1:0], Output handled by DX0 DOUT[1:0] and DX3 Output SCLKOUT Dual-SSC Slave MTSR[1:0], MRST[1:0], input DIN[1:0], Output handled by DX0 DOUT[1:0] and DX3 Output(s) SELOx Input SCLKIN, input SELIN, handled by DX1 handled by DX2 Quad-SSC Master MTSR[3:0], MRST[3:0], input DIN[3:0], Output handled by DOUT[3:0] DX0, DX3, DX4 and DX5 Output SCLKOUT Output(s) SELOx Quad-SSC Slave MTSR[3:0], MRST[3:0], input DIN[3:0], Output DOUT[3:0] handled by DX0, DX3, DX4 and DX5 Input SCLKIN, input SELIN, handled by DX1 handled by DX2 1) MRST = master receive slave transmit, also known as MISO = master in slave out 2) MTSR = master transmit slave receive, also known as MOSI = master out slave in Reference Manual USIC, V2.14 14-75 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Shift Clock Transmit Data Receive Data D0 D1 Dn D0 D1 D0 D1 Dn Dn D0 D1 Dn Data Word x Data Word 0 Data Frame Slave Select Figure 14-36 4-Wire SSC Standard Communication Signals 14.4.1.1 Transmit and Receive Data Signals In standard SSC half-duplex mode, a single data line is used, either for data transfer from the master to a slave or from a slave to the master. In this case, MRST and MTSR are connected together, one signal as input, the other one as output, depending on the data direction. The user software has to take care about the data direction to avoid data collision (e.g. by preparing dummy data of all 1s for transmission in case of a wired AND connection with open-drain drivers, by enabling/disabling push/pull output drivers or by switching pin direction with hardware port control enabled). In full-duplex mode, data transfers take place in parallel between the master device and a slave device via two independent data signals MTSR and MRST, as shown in Figure 14-35. The receive data input signal DIN0 is handled by the input stage DX0. In master mode (referring to MRST) as well as in slave mode (referring to MTSR), the data input signal DIN0 is taken from an input pin. The signal polarity of DOUT0 (data output) with respect to the data bit value can be configured in block DOCFG (data output configuration) by bit field SCTR.DOCFG. MRST Master Mode MTSR Slave Mode DIN0 Input Stage DX0 Data Shift Unit SCTR DOCFG DOUT0 MTSR Master Mode MRST Slave Mode Figure 14-37 SSC Data Signals Reference Manual USIC, V2.14 14-76 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) For dual- and quad-SSC modes that require multiple input and output data lines to be used, additional input stages, DINx and DOUTx signals need to be set up. 14.4.1.2 Shift Clock Signals The shift clock signal is handled by the input stage DX1. In slave mode, the signal SCLKIN is received from an external master, so the DX1 stage has to be connected to an input pin. The input stage can invert the received input signal to adapt to the polarity of SCLKIN to the function of the data shift unit (data transmission on rising edges, data reception on falling edges). In master mode, the shift clock is generated by the internal baud rate generator. The output signal SCLK of the baud rate generator is taken as shift clock input for the data shift unit. The internal signal SCLK is made available for external slave devices by signal SCLKOUT. For complete closed loop delay compensation in a slave mode, SCLKOUT can also take the transmit shift clock from the input stage DX1. The selection is done through the bit BRG.SCLKOSEL. See Section 14.4.6.3. SSC in Slave Mode SSC in Master Mode SCLKIN SCLKOUT Delay of ½ Bit Time SCLKCFG Input Stage DX1 SCLK Data Shift Unit Transfer Control Logic Baud Rate Generator Figure 14-38 SSC Shift Clock Signals Due to the multitude of different SSC applications, in master mode, there are different ways to configure the shift clock output signal SCLKOUT with respect to SCLK. This is done in the block SCLKCFG (shift clock configuration) by bit field BRG.SCLKCFG, allowing 4 possible settings, as shown in Figure 14-39. • No delay, no polarity inversion (SCLKCFG = 00B, SCLKOUT equals SCLK): The inactive level of SCLKOUT is 0, while no data frame is transferred. The first data bit of a new data frame is transmitted with the first rising edge of SCLKOUT and the first data bit is received in with the first falling edge of SCLKOUT. The last data bit of a data frame is transmitted with the last rising clock edge of SCLKOUT and the last Reference Manual USIC, V2.14 14-77 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • data bit is received in with the last falling edge of SCLKOUT. This setting can be used in master and in slave mode. It corresponds to the behavior of the internal data shift unit. No delay, polarity inversion (SCLKCFG = 01B): The inactive level of SCLKOUT is 1, while no data frame is transferred. The first data bit of a new data frame is transmitted with the first falling clock edge of SCLKOUT and the first data bit is received with the first rising edge of SCLKOUT. The last data bit of a data frame is transmitted with the last falling edge of SCLKOUT and the last data bit is received with the last rising edge of SCLKOUT. This setting can be used in master and in slave mode. For slave mode, bit field DX1CR.DPOL = 1B has to be programmed. SCLKOUT is delayed by 1/2 shift clock period, no polarity inversion (SCLKCFG = 10B): The inactive level of SCLKOUT is 0, while no data frame is transferred. The first data bit of a new data frame is transmitted 1/2 shift clock period before the first rising clock edge of SCLKOUT. Due to the delay, the next data bits seem to be transmitted with the falling edges of SCLKOUT. The last data bit of a data frame is transmitted 1/2 period of SCLKOUT before the last rising clock edge of SCLKOUT. The first data bit is received 1/2 shift clock period before the first falling edge of SCLKOUT. Due to the delay, the next data bits seem to be received with the rising edges of SCLKOUT. The last data bit is received 1/2 period of SCLKOUT before the last falling clock edge of SCLKOUT. This setting can be used only in master mode and not in slave mode (the connected slave has to provide the first data bit before the first SCLKOUT edge, e.g. as soon as it is addressed by its slave select). SCLKOUT is delayed by 1/2 shift clock period, polarity inversion (SCLKCFG = 11B): The inactive level of SCLKOUT is 1, while no data frame is transferred. The first data bit of a new data frame is transmitted 1/2 shift clock period before the first falling clock edge of SCLKOUT. Due to the delay, the next data bits seem to be transmitted with the rising edges of SCLKOUT. The last data bit of a data frame is transmitted 1/2 period of SCLKOUT before the last falling clock edge of SCLKOUT. The first data bit is received 1/2 shift clock period before the first rising edge of SCLKOUT. Due to the delay, the next data bits seem to be received with the falling edges of SCLKOUT. The last data bit is received 1/2 period of SCLKOUT before the last rising clock edge of SCLKOUT. This setting can be used only in master mode and not in slave mode (the connected slave has to provide the first data bit before the first SCLKOUT edge, e.g. as soon as it is addressed by its slave select). Reference Manual USIC, V2.14 14-78 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Data Bit x transmitted (x = 1-n) 1 n 2 Bit 1 Bit n SCK SCLKOUT (SCLKCFG = 00B) SCLKOUT (SCLKCFG = 01B) SCLKOUT (SCLKCFG = 10B) SCLKOUT (SCLKCFG = 11B) Data Bit x received (x = 1-n) 1 2 n Figure 14-39 SCLKOUT Configuration in SSC Master Mode Note: If a configuration with delay is selected and a slave select line is used, the slave select delays have to be set up accordingly. In SSC slave mode, the bit PCR.SLPHSEL can be used to configure the clock phase of the data shift. • • When SLPHSEL = 0B, the slave SSC transmits data bits with each leading edge of the selected shift clock input (SCLKIN) and receives data bits with each trailing edge of SCLKIN When SLPHSEL = 1B, the slave SSC transmits the first data bit once the selected slave select input (SELIN) becomes active. If SELIN is not used, the DX2 stage has to deliver a 1-level to the data shift unit to shift out the first bit. Subsequent data bits are then transmitted with each trailing edge of SCLKIN. The SSC slave receives all data bits with each leading edge of SCLKIN. For both settings, the clock polarity is determined by bit 0 of SCLKCFG. Reference Manual USIC, V2.14 14-79 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) SELIN SCLKIN (SCLKCFG = 00B ) SCLKIN (SCLKCFG = 01B ) MRST D0 (SLPHSEL =0B ) MRST (SLPHSEL =1B ) D0 D1 Dn D1 Dn Figure 14-40 SLPHSEL Configuration in SSC Slave Mode 14.4.1.3 Slave Select Signals The slave select signal is handled by the input stage DX2. In slave mode, the input signal SELIN is received from an external master via an input pin. The input stage can invert the received input signal to adapt the polarity of signal SELIN to the function of the data shift unit (the module internal signals are considered as high active, so a data transfer is only possible while the slave select input of the data shift unit is at 1-level, otherwise, shift clock pulses are ignored and do not lead to data transfers). If an input signal SELIN is low active, it should be inverted in the DX2 input stage. In master mode, a master slave select signal MSLS is generated by the internal slave select generator. In order to address different external slave devices independently, the internal MSLS signal is made available externally via up to 8 SELOx output signals that can be configured by the block SELCFG (select configuration). Reference Manual USIC, V2.14 14-80 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) SSC in Slave Mode SSC in Master Mode .. ... . SELIN SELOx x = 0-7 SELCFG Input Stage DX2 MSLS Data Shift Unit Transfer Control Logic Slave Select Generator Figure 14-41 SSC Slave Select Signals The control of the SELCFG block is based on protocol specific bits and bit fields in the protocol control register PCR. For the generation of the MSLS signal please refer to Section 14.4.3.2. • • • PCR.SELCTR to chose between direct and coded select mode PCR.SELINV to invert the SELOx outputs PCR.SELO[7:0] as individual value for each SELOx line The SELCFG block supports the following configurations of the SELOx output signals: • • Direct Select Mode (SELCTR = 1): Each SELOx line (with x = 0-7) can be directly connected to an external slave device. If bit x in bit field SELO is 0, the SELOx output is permanently inactive. A SELOx output becomes active while the internal signal MSLS is active (see Section 14.4.3.2) and bit x in bit field SELO is 1. Several external slave devices can be addressed in parallel if more than one bit in bit field SELO are set during a data frame. The number of external slave devices that can be addressed individually is limited to the number of available SELOx outputs. Coded Select Mode (SELCTR = 0): The SELOx lines (with x = 1-7) can be used as addresses for an external address decoder to increase the number of external slave devices. These lines only change with the start of a new data frame and have no other relation to MSLS. Signal SELO0 can be used as enable signal for the external address decoder. It is active while MSLS is active (during a data frame) and bit 0 in bit field SELO is 1. Furthermore, in coded select mode, this output line is delayed by one cycle of fPERIPH compared to MSLS to allow the other SELOx lines to stabilize before enabling the address decoder. Reference Manual USIC, V2.14 14-81 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.2 Operating the SSC This chapter contains SSC issues, that are of general interest and not directly linked to either master mode or slave mode. 14.4.2.1 Automatic Shadow Mechanism The contents of the baud rate control register BRG, bit fields SCTR.FLE as well as the protocol control register PCR are internally kept constant while a data frame is transferred (= while MSLS is active) by an automatic shadow mechanism. The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. Bit fields SCTR.WLE, SCTR.DSM, SCTR.HPCDIR and SCTR.SDIR are shadowed automatically with the start of each data word. As a result, a data frame can consist of data words with a different length, or data words that are transmitted or received through different number of data lines. It is recommended to change SCTR.SDIR only when no data frame is running to avoid interference between hardware and software. Please note that the starting point of a data word are different for a transmitter (first bit transmitted) and a receiver (first bit received). In order to ensure correct handling, it is recommended to refer to the receive start interrupt RSI before modifying SCTR.WLE. If TCSR.WLEMD = 1, it is recommended to update TCSR and TBUFxx after the receiver start interrupt has been generated. 14.4.2.2 Mode Control Behavior In SSC mode, the following kernel modes are supported: • • Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0/1: The content of the transmit buffer is considered as not valid for transmission. Although being considered as 0, bit TCSR.TDV it is not modified by the stop mode condition. In master mode, a currently running word transfer is finished normally, but no new data word is started (the stop condition is not considered as end-of-frame condition). In slave mode, a currently running word transfer is finished normally. Passive data will be sent out instead of a valid data word if a data word transfer is started by the external master while the slave device is in stop mode. In order to avoid passive slave transmit data, it is recommended not to program stop mode for an SSC slave device if the master device does not respect the slave device’s stop mode. Reference Manual USIC, V2.14 14-82 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.2.3 Disabling SSC Mode In order to disable SSC mode without any data corruption, the receiver and the transmitter have to be both idle. This is ensured by requesting Stop Mode 1 in register KSCFG. After Stop Mode 1 has been acknowledged by KSCFG.2 = 1, the SSC mode can be disabled. 14.4.2.4 Data Frame Control An SSC data frame can consist of several consecutive data words that may be separated by an inter-word delay. Without inter-word delay, the data words seem to form a longer data word, being equivalent to a data frame. The length of the data words are most commonly identical within a data frame, but may also differ from one word to another. The data word length information (defined by SCTR.WLE) is evaluated for each new data word, whereas the frame length information (defined by SCTR.FLE) is evaluated at the beginning at each start of a new frame. The length of an SSC data frame can be defined in two different ways: • • By the number of bits per frame: If the number of bits per data frame is defined (frame length FLE), a slave select signal is not necessarily required to indicate the start and the end of a data frame. If the programmed number of bits per frame is reached within a data word, the frame is considered as finished and remaining data bits in the last data word are ignored and are not transferred. This method can be applied for data frames with up to 63 data bits. By the slave select signal: If the number of bits per data frame is not known, the start/end information of a data frame is given by a slave select signal. If a deactivation of the slave select signal is detected within a data word, the frame is considered as finished and remaining data bits in the last data word are ignored and are not transferred. This method has to be applied for frames with more than 63 data bits (programming limit of FLE). The advantage of slave select signals is the clearly defined start and end condition of data frames in a data stream. Furthermore, slave select signals allow to address slave devices individually. 14.4.2.5 Parity Mode The SSC allows parity generation for transmission and parity check for reception on frame base. The type of parity can be selected by bit field CCR.PM, common for transmission and reception (no parity, even or odd parity). If the parity handling is disabled, the SSC frame does not contain any parity bit. For consistency reasons, all communication partners have to be programmed to the same parity mode. Reference Manual USIC, V2.14 14-83 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) If parity generation has been enabled, the transmitter automatically extends the clock by one cycle after the last data word of the data frame, and sends out its calculated parity bit in this cycle. Figure 14-42 shows how a parity bit is added to the transmitted data bits of a frame. The number of the transmitted bits of a complete frame with parity is always one more than that without parity. The parity bit is transmitted as the last bit of a frame, following the data bits, independent of the shift direction (SCTR.SDIR). Note: For dual and quad SSC protocols, the parity bit will be transmitted and received only on DOUT0 and DX0 respectively in the extended clock cycle. Data Frame with LSB First (SCTR.SDIR = 0) Bit 0 Bit 1 Bit 2 Bit 3 Bit FLE-1 Bit FLE Bit FLE-1 Bit FLE Parity Mode Disabled (FLE+ 1) Bits Bit 0 Bit 1 Bit 2 Bit 3 Parity Bit Parity Mode Enabled (FLE+ 1) + Parity Time Data Frame with MSB First (SCTR.SDIR = 1) Bit FLE Bit FLE-1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 Parity Mode Disabled (FLE+ 1) Bits Bit FLE Bit FLE-1 Bit 3 Parity Bit Parity Mode Enabled (FLE+1) + Parity Time Figure 14-42 Data Frames without/with Parity Reference Manual USIC, V2.14 14-84 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Similarly, after the receiver receives the last word of a data frame as defined by FLE, it expects an additional one clock cycle, which will contain the parity bit. The receiver interprets this bit as received parity and separates it from the received data. The received parity bit value is instead monitored in the protocol-related argument (PAR) of the receiver buffer status registers as receiver buffer status information. The receiver compares the bit to its internally calculated parity and the result of the parity check is indicated by the flag PSR.PARERR. The parity error event generates a protocol interrupt if PCR.PARIEN = 1. Parity bit generation and detection is not supported for the following cases: • • When frame length is 64 data bits or greater, i.e. FLE = 63H; When in slave mode, the end of frame occurs before the number of data bits defined by FLE is reached. 14.4.2.6 Transfer Mode In SSC mode, bit field SCTR.TRM = 01B has to be programmed to allow data transfers. Setting SCTR.TRM = 00B disables and stops the data transfer immediately. 14.4.2.7 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to SSC frame handling. • • • • • Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Receiver start interrupt RSI: Bit PSR.RSIF is set after the reception of the first data bit of a data word. With this event, bit TCSR.TDV is cleared and new data can be loaded to the transmit buffer. Receiver interrupt RI: The reception of the second, third, and all subsequent words in a multi-word frame is always indicated by RBUFSR.SOF = 0. Bit PSR.RIF is set after the reception of the last data bit of a data word if RBUFSR.SOF = 0. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a multi-word frame or some subsequent word. In SSC mode, it decides if alternative interrupt or receive interrupt is generated. Alternative interrupt AI: The reception of the first word in a frame is always indicated by RBUFSR.SOF = 1. This is true both in case of reception of multi-word frames and single-word frames. In SSC mode, this results in setting PSR.AIF. Reference Manual USIC, V2.14 14-85 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.2.8 Baud Rate Generator Interrupt Handling The baud rate generator interrupt indicate that the capture mode timer has reached its maximum value. With this event, the bit PSR.BRGIF is set. 14.4.2.9 Protocol-Related Argument and Error The protocol-related argument (RBUFSR.PAR) and the protocol-related error (RBUFSR.PERR) are two flags that are assigned to each received data word in the corresponding receiver buffer status registers. In SSC mode, the received parity bit is monitored by the protocol-related argument. The received start of frame indication is monitored by the protocol-related error indication (0 = received word is not the first word of a frame, 1 = received word is the first word of a new frame). Note: For SSC, the parity error event indication bit is located in the PSR register. 14.4.2.10 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTR.SIZE > 0), it is recommended to set RBCTR.RCIM = 01B in SSC mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTR.RCI[4] = 1, and the word length of the received data is given by OUTR.RCI[3:0]. The standard receive buffer event and the alternative receive buffer event can be used for the following operation in RCI mode (RBCTR.RNM = 1): • • A standard receive buffer event indicates that a data word can be read from OUTR that has not been the first word of a data frame. An alternative receive buffer event indicates that the first data word of a new data frame can be read from OUTR. 14.4.2.11 Multi-IO SSC Protocols The SSC implements the following three features to support multiple data input/output SSC protocols, such as the dual- and quad-SSC: 1. Data Shift Mode (Section 14.2.5.2) Configures the data for transmission and reception using one, two or four data lines in parallel, through the bit field SCTR.DSM. 2. Hardware Port Control (Section 14.2.7) Sets up a dedicated hardware interface to control the direction of the pins overlaid with both DINx and DOUTx functions, through the bit SCTR.HPCDIR. 3. Transmit Control Information (Section 14.2.5.3) Allows the dynamic control of both the shift mode and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR with TCI. Reference Manual USIC, V2.14 14-86 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Figure 14-43 shows an example of a Quad-SSC protocol, which requires the master SSC to first transmit a command byte (to request a quad output read from the slave) and a dummy byte through a single data line. At the end of the dummy byte, both master and slave SSC switches to quad data lines, and with the roles of transmitter and receiver reversed. The master SSC then receives the data four bits per shift clock from the slave through the MRST[3:0] lines. Slave Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4 0 4 0 MRST1 5 1 5 1 MRST2 6 2 6 2 MRST3 7 3 7 3 SCLKOUT MTSR/ MRST0 Command Byte Dummy Byte Data Byte 0 Shadowed SCTR.DSM 00B Data Byte 1 11B Shadowed SCTR.HPCDIR (Master) Figure 14-43 Quad-SSC Example To work with the quad-SSC protocol in the given example, the following issues have to be additionally considered on top of those defined in Section 14.4.3 and Section 14.4.4: • • • During the initialization phase: – Set CCR.HPCEN to 11B to enable the dedicated hardware interface to the DX0/DOUT0, DX3/DOUT1, DX4/DOUT2 and DX5/DOUT3 pins. – Set TCSR.[4:0] to 10H to enable hardware port control in TCI To start the data transfer: – For the master SSC, write the command and dummy bytes into TBUF04 to select a single data line in output mode and initiate the data transfer. – For the slave SSC, dummy data can be preloaded into TBUF00 to select a single data line in input mode. To switch to quad data lines and pin direction: Reference Manual USIC, V2.14 14-87 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) – For the master SSC, write subsequent dummy data to TBUF03 to select quad data lines in input mode to read in valid slave data. – For the slave SSC, write valid data to TBUF07 for transmission through quad data lines in output mode. Note: If DOUT[1:0] or DOUT[3:0] pins are already enabled with CCR.HPCEN but SCTR.DSM does not use all pins, the unused DOUTx pins output the passive data level defined by SCTR.PDL. Figure 14-44 shows the connections for the Quad-SSC example. USIC Master USIC Slave DX5 DOUT3 DX5 MTSR3/MRST3 DX4 DOUT2 DX4 MTSR2/MRST2 DX3 DOUT1 SCLKOUT SELO DOUT2 DX3 MTSR1/MRST1 DX0 DOUT0 DOUT3 DOUT1 DX0 MTSR0/MRST0 DOUT0 clock DX1 SCLK DX2 SELO Slave_select Figure 14-44 Connections for Quad-SSC Example 14.4.3 Operating the SSC in Master Mode In order to operate the SSC in master mode, the following issues have to be considered: • Select SSC mode: It is recommended to configure all parameters of the SSC that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 01B has to be programmed. The configuration of the input stages has to be done while Reference Manual USIC, V2.14 14-88 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • CCR.MODE = 0000B to avoid unintended edges of the input signals and the SSC mode can be enabled by CCR.MODE = 0001B afterwards. Pin connections: Establish a connection of the input stage (DX0, DX3, DX4, DX5) with the selected receive data input pin (DIN[3:0]) with DXnCR.INSW = 1 and configure the transmit data output pin (DOUT[3:0]). One, two or four such connections may be needed depending on the protocol. For half-duplex configurations, hardware port control can be also used to establish the required connections. Baud rate generation: The desired baud rate setting has to be selected, comprising the fractional divider and the baud rate generator. Bit DX1CR.INSW = 0 has to be programmed to use the baud rate generator output SCLK directly as input for the data shift unit. Configure a shift clock output pin (signal SCLKOUT). Slave select generation: The slave select delay generation has to be enabled by setting PCR.MSLSEN = 1 and the programming of the time quanta counter setting. Bit DX2CR.INSW = 0 has to be programmed to use the slave select generator output MSLS as input for the data shift unit. Configure slave select output pins (signals SELOx) if needed. Data format configuration: The word length, the frame length, the shift direction and shift mode have to be set up according to the application requirements by programming the register SCTR. Note: The USIC can only receive in master mode if it is transmitting, because the master frame handling refers to bit TDV of the transmitter part. Note: The step to enable the alternate output port functions should only be done after the SSC mode is enabled, to avoided unintended spikes on the output. 14.4.3.1 Baud Rate Generation The baud rate (determining the length of one data bit) of the SSC is defined by the frequency of the SCLK signal (one period of fSCLK represents one data bit). The SSC baud rate generation does not imply any time quanta counter. In a standard SSC application, the phase relation between the optional MCLK output signal and SCLK is not relevant and can be disabled (BRG.PPPEN = 0). In this case, the SCLK signal directly derives from the protocol input frequency fPIN. In the exceptional case that a fixed phase relation between the MCLK signal and SCLK is required (e.g. when using MCLK as clock reference for external devices), the additional divider by 2 stage has to be taken into account (BRG.PPPEN = 1). Reference Manual USIC, V2.14 14-89 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The adjustable divider factor is defined by bit field BRG.PDIV. fPIN 1 PDIV + 1 fPIN 1 × fSCLK = 2×2 PDIV + 1 fSCLK = 2 × if PPPEN = 0 (14.8) if PPPEN = 1 14.4.3.2 MSLS Generation The slave select signals indicate the start and the end of a data frame and are also used by the communication master to individually select the desired slave device. A slave select output of the communication master becomes active a programmable time before a data part of the frame is started (leading delay Tld), necessary to prepare the slave device for the following communication. After the transfer of a data part of the frame, it becomes inactive again a programmable time after the end of the last bit (trailing delay Ttd) to respect the slave hold time requirements. If data frames are transferred back-toback one after the other, the minimum time between the deactivation of the slave select and the next activation of a slave select is programmable (next-frame delay Tnf). If a data frame consists of more than one data word, an optional delay between the data words can also be programmed (inter-word delay Tiw). Data Frame Data Word 0 Data Word 1 Shift Clock Transmit Data D0 D1 Receive Data D0 D1 Tld Dn D0 D1 Dn Dn D0 D1 Tiw Dn Ttd Tn f Active MSLS Inactive SELOx (SELINV = 1) Figure 14-45 MSLS Generation in SSC Master Mode In SSC master mode, the slave select delays are defined as follows: Reference Manual USIC, V2.14 14-90 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • Leading delay Tld: The leading delay starts if valid data is available for transmission. The internal signal MSLS becomes active with the start of the leading delay. The first shift clock edge (rising edge) of SCLK is generated by the baud rate generator after the leading delay has elapsed. Trailing delay Ttd The trailing delay starts at the end of the last SCLK cycle of a data frame. The internal signal MSLS becomes inactive with the end of the trailing delay. Inter-word delay Tiw: This delay is optional and can be enabled/disabled by PCR.TIWEN. If the inter-word delay is disabled (TIWEN = 0), the last data bit of a data word is directly followed by the first data bit of the next data word of the same data frame. If enabled (TIWEN = 1), the inter-word delay starts at the end of the last SCLK cycle of a data word. The first SCLK cycle of the following data word of the same data frame is started when the inter-word delay has elapsed. During this time, no shift clock pulses are generated and signal MSLS stays active. The communication partner has time to “digest” the previous data word or to prepare for the next one. Next-frame delay Tnf: The next-frame delay starts at the end of the trailing delay. During this time, no shift clock pulses are generated and signal MSLS stays inactive. A frame is considered as finished after the next-frame delay has elapsed. 14.4.3.3 Automatic Slave Select Update If the number of bits per SSC frame and the word length are defined by bit fields SCTR.FLE and SCTR.WLE, the transmit control information TCI can be used to update the slave select setting PCR.CTR[23:16] to control the SELOx select outputs. The automatic update mechanism is enabled by TCSR.SELMD = 1 (bits TCSR.WLEMD, FLEMD, and WAMD have to be cleared). In this case, the TCI of the first data word of a frame defines the slave select setting of the complete frame due to the automatic shadow mechanism (see Page 14-62). Reference Manual USIC, V2.14 14-91 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.3.4 Slave Select Delay Generation The slave select delay generation is based on time quanta. The length of a time quantum (defined by the period of the fCTQIN) and the number of time quanta per delay can be programmed. In standard SSC applications, the leading delay Tld and the trailing delay Ttd are mainly used to ensure stability on the input and output lines as well as to respect setup and hold times of the input stages. These two delays have the same length (in most cases shorter than a bit time) and can be programmed with the same set of bit fields. • • • BRG.CTQSEL to define the input frequency fCTQIN for the time quanta generation for Tld and Ttd BRG.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) for Tld and Ttd BRG.DCTQ to define the number of time quanta for the delay generation for Tld and Ttd The inter-word delay Tiw and the next-frame delay Tnf are used to handle received data or to prepare data for the next word or frame. These two delays have the same length (in most cases in the bit time range) and can be programmed with a second, independent set of bit fields. • • • • PCR.CTQSEL1 to define the input frequency fCTQIN for the time quanta generation for Tnf and Tiw PCR.PCTQ1 to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) for Tnf and Tiw PCR.DCTQ1 to define the number of time quanta for the delay generation for Tnf and Tiw PCR.TIWEN to enable/disable the inter-word delay Tiw Each delay depends on the length of a time quantum and the programmed number of time quanta given by the bit fields CTQSEL/CTQSEL1, PCTQ/DCTQ and PCTQ1/DCTQ1 (the coding of CTQSEL1 is similar to CTQSEL, etc.). To provide a high flexibility in programming the delay length, the input frequencies can be selected between several possibilities (e.g. based on bit times or on the faster inputs of the protocol-related divider). The delay times are defined as follows: Tld = Ttd = Tiw = Tnf = Reference Manual USIC, V2.14 (PCTQ + 1) × (DCTQ + 1) fCTQIN (PCTQ1 + 1) × (DCTQ1 + 1) (14.9) fCTQIN 14-92 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.3.5 Protocol Interrupt Events The following protocol-related events generated in SSC mode and can lead to a protocol interrupt. They are related to the start and the end of a data frame. After the start of a data frame a new setting could be programmed for the next data frame and after the end of a data frame the SSC connections to pins can be changed. Please note that the bits in register PSR are not all automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • • MSLS Interrupt: This interrupt indicates in master mode (MSLS generation enabled) that a data frame has started (activation of MSLS) and has been finished (deactivation of MSLS). Any change of the internal MSLS signal sets bit PSR.MSLSEV and additionally, a protocol interrupt can be generated if PCR.MSLSIEN = 1. The actual state of the internal MSLS signal can be read out at PSR.MSLS to take appropriate actions when this interrupt has been detected. DX2T Interrupt: This interrupt monitors edges of the input signal of the DX2 stage (although this signal is not used as slave select input for data transfers). A programmable edge detection for the DX2 input signal sets bit PSR.DX2TEV and additionally, a protocol interrupt can be generated if PCR.DX2TIEN = 1. The actual state of the selected input signal can be read out at PSR.DX2S to take appropriate actions when this interrupt has been detected. Parity Error Interrupt: This interrupt indicates that there is a mismatch in the received parity bit (in RBUFSR.PAR) with the calculated parity bit of the last received word of a data frame. Reference Manual USIC, V2.14 14-93 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.3.6 End-of-Frame Control The information about the frame length is required for the MSLS generator of the master device. In addition to the mechanism based on the number of bits per frame (selected with SCTR.FLE < 63), the following alternative mechanisms for end of frame handling are supported. It is recommended to set SCTRFLE = 63 (if several end of frame mechanisms are activated in parallel, the first end condition being found finishes the frame). • • • • Software-based start of frame indication TCSR.SOF: This mechanism can be used if software handles the TBUF data without data FIFO. If bit SOF is set, a valid content of TBUF is considered as first word of a new frame. Bit SOF has to be set before the content of TBUF is transferred to the transmit shift register, so it is recommended to write it before writing data to TBUF. A current data word transfer is finished completely and the slave select delays Ttd and Tnf are applied before starting a new data frame with Tld and the content of TBUF. For software-handling of bit SOF, bit TCSR.WLEMD = 0 has to be programmed. In this case, all TBUF[31:0] address locations show an identical behavior (TCI not taken into account for data handling). Software-based end of frame indication TCSR.EOF: This mechanism can be used if software handles the TBUF data without data FIFO. If bit EOF is set, a valid content of TBUF is considered as last word of a new frame. Bit EOF has to be set before the content of TBUF is transferred to the transmit shift register, so it is recommended to write it before writing data to TBUF. The data word in TBUF is sent out completely and the slave select delays Ttd and Tnf are applied. A new data frame can start with Tld with the next valid TBUF value. For software-handling of bit EOF, bit TCSR.WLEMD = 0 has to be programmed. In this case, all TBUF[31:0] address locations show an identical behavior (TCI not taken into account for data handling). Software-based address related end of frame handling: This mechanism can be used if software handles the TBUF data without data FIFO. If bit TCSR.WLEMD = 1, the address of the written TBUF[31:0] is used as transmit control information TCI[4:0] to update SCTR.WLE (= TCI[3:0]) and TCSR.EOF (= TCI[4]) for each data word. The written TBUF[31:0] address location defines the word length and the end of a frame (locations TBUF[31:16] lead to a frame end). For example, writing transmit data to TBUF[07] results in a data word of 8-bit length without finishing the frame, whereas writing transmit data to TBUF[31] leads to a data word length of 16 bits, followed by Ttd, the deactivation of MSLS and Tnf. If TCSR.WLEMD = 1, bits TCSR.EOF and SOF, as well as SCTR.WLE must not be written by software after writing data to a TBUF location. Furthermore, it is recommended to clear bits TCSR.SELMD, FLEMD and WAMD. FIFO-based address related end of frame handling: This mechanism can be used if a data FIFO is used to store the transmit data. The general behavior is similar to the software-based address related end of frame Reference Manual USIC, V2.14 14-94 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • handling, except that transmit data is not written to the locations TBUF[31:0], but to the FIFO input locations IN[31:0] instead. In this case, software must not write to any of the TBUF locations. TBUF related end of frame handling: If bit PCR.FEM = 0, an end of frame is assumed if the transmit buffer TBUF does not contain valid transmit data at the end of a data word transmission (TCSR.TDV = 0 or in Stop Mode). In this case, the software has to take care that TBUF does not run empty during a data frame in Run Mode. If bit PCR.FEM = 1, signal MSLS stays active while the transmit buffer is waiting for new data (TCSR.TDV = 1 again) or until Stop Mode is left. Explicit end of frame by software: The software can explicitly stop a frame by clearing bit PSR.MSLS by writing a 1 to the related bit position in register PSCR. This write action immediately clears bit PSR.MSLS, whereas the internal MSLS signal becomes inactive after finishing a currently running word transfer and respecting the slave select delays Ttd and Tnf. Reference Manual USIC, V2.14 14-95 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.4 Operating the SSC in Slave Mode In order to operate the SSC in slave mode, the following issues have to be considered: • • • • • Select SSC mode: It is recommended to configure all parameters of the SSC that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 01B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the SSC mode can be enabled afterwards by CCR.MODE = 0001B. Pin connections: Establish the connection of the input stage (DX0, DX3, DX4, DX5) with the selected receive data input pin (DIN[3:0]) with DXnCR.INSW = 1 and configure the transmit data output pin (DOUT[3:0]). One, two or four such connections may be needed depending on the protocol. For half-duplex configurations, hardware port control can be also used to establish the required connections. Establish a connection of input stage DX1 with the selected shift clock input pin (signal SCLKIN) with DX1CR.INSW = 1. Establish a connection of input stage DX2 with the selected slave select input pin (signal SELIN) with DX2CR.INSW = 1. If no slave select input signal is used, the DX2 stage has to deliver a 1-level to the data shift unit to allow data reception and transmission. If a slave device is not selected (DX2 stage delivers a 0 to the data shift unit) and a shift clock pulse are received, the incoming data is not received and the DOUTx signal outputs the passive data level defined by SCTR.PDL. Note that the step to enable the alternate output port functions should only be done after the SSC mode is enabled, to avoided unintended spikes on the output. Baud rate generation: The baud rate generator is not needed and can be switched off by the fractional divider. Data format configuration: If required, the shift mode can be set up for reception and/or transmission of two or four data bits at one time by programming the register SCTR. Slave select generation: The slave select delay generation is not needed and can be switched off. The bits and bit fields MSLSEN, SELCTR, SELINV, CTQSEL1, PCTQ1, DCTQ1, MSLSIEN, SELO[7:0], and TIWEN in register PCR are not necessary and can be programmed to 0. 14.4.4.1 Protocol Interrupts The following protocol-related events generated in SSC mode and can lead to a protocol interrupt. They are related to the start and the end of a data frame. After the start of a data frame a new setting could be programmed for the next data frame and after the end of a data frame the SSC connections to pins can be changed. Reference Manual USIC, V2.14 14-96 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Please note that the bits in register PSR are not all automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • • MSLS event: The MSLS generation being switched off, this event is not available. DX2T event: The slave select input signal SELIN is handled by the DX2 stage and the edges of the selected signal can generate a protocol interrupt. This interrupt allows to indicate that a data frame has started and/or that a data frame has been completely finished. A programmable edge detection for the DX2 input signal activates DX2T, sets bit PSR.DX2TEV and additionally, a protocol interrupt can be generated if PCR.DX2TIEN = 1. The actual state of the selected input signal can be read out at PSR.DX2S to take appropriate actions when this interrupt has been detected. Parity Error Interrupt: This interrupt indicates that there is a mismatch in the received parity bit (in RBUFSR.PAR) with the calculated parity bit of the last received word of a data frame. 14.4.4.2 End-of-Frame Control In slave mode, the following possibilities exist to determine the frame length. The slave device either has to refer to an external slave select signal, or to the number of received data bits. • • • Frame length known in advance by the slave device, no slave select: In this case bit field SCTR.FLE can be programmed to the known value (if it does not exceed 63 bits). A currently running data word transfer is considered as finished if the programmed frame length is reached. Frame length not known by the slave, no slave select: In this case, the slave device’s software has to decide on data word base if a frame is finished. Bit field SCTR.FLE can be either programmed to the word length SCTR.WLE, or to its maximum value to disable the slave internal frame length evaluation by counting received bits. Slave device addressed via slave select signal SELIN: If the slave device is addressed by a slave select signal delivered by the communication master, the frame start and end information are given by this signal. In this case, bit field SCTR.FLE should be programmed to its maximum value to disable the slave internal frame length evaluation. Reference Manual USIC, V2.14 14-97 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.5 SSC Protocol Registers In SSC mode, the registers PCR and PSR handle SSC related information. 14.4.5.1 SSC Protocol Control Registers In SSC mode, the PCR register bits or bit fields are defined as described in this section. PCR Protocol Control Register [SSC Mode] (3CH) 31 30 29 28 MCL K 0 rw rw 15 14 13 12 27 rw 25 24 23 22 21 20 SLP TIW HSE EN L rw rw 11 DX2 MSL PARI TIEN SIEN EN rw 26 Reset Value: 0000 0000H rw 10 9 8 19 18 17 16 2 1 0 SELO rw 7 6 DCTQ1 PCTQ1 rw rw 5 4 3 CTQSEL1 FEM rw rw SELI SEL MSL NV CTR SEN rw rw rw Field Bits Type Description MSLSEN 0 rw MSLS Enable This bit enables/disables the generation of the master slave select signal MSLS. If the SSC is a transfer slave, the SLS information is read from a pin and the internal generation is not needed. If the SSC is a transfer master, it has to provide the MSLS signal. The MSLS generation is disabled (MSLS = 0). 0B This is the setting for SSC slave mode. The MSLS generation is enabled. 1B This is the setting for SSC master mode. SELCTR 1 rw Select Control This bit selects the operating mode for the SELO[7:0] outputs. The coded select mode is enabled. 0B 1B The direct select mode is enabled. Reference Manual USIC, V2.14 14-98 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SELINV 2 rw Select Inversion This bit defines if the polarity of the SELO[7:0] outputs in relation to the master slave select signal MSLS. The SELO outputs have the same polarity as the 0B MSLS signal (active high). The SELO outputs have the inverted polarity to the 1B MSLS signal (active low). FEM 3 rw Frame End Mode This bit defines if a transmit buffer content that is not valid for transmission is considered as an end of frame condition for the slave select generation. The current data frame is considered as finished 0B when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). The MSLS signal is kept active also while no new 1B data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. CTQSEL1 [5:4] rw Input Frequency Selection This bit field defines the input frequency fCTQIN for the generation of the slave select delays Tiw and Tnf. 00B fCTQIN = fPDIV 01B fCTQIN = fPPP 10B fCTQIN = fSCLK 11B fCTQIN = fMCLK PCTQ1 [7:6] rw Divider Factor PCTQ1 for Tiw and Tnf This bit field represents the divider factor PCTQ1 (range = 0 - 3) for the generation of the inter-word delay and the next-frame delay. Tiw = Tnf = 1/fCTQIN x (PCTQ1 + 1) x (DCTQ1 + 1) DCTQ1 [12:8] rw Divider Factor DCTQ1 for Tiw and Tnf This bit field represents the divider factor DCTQ1 (range = 0 - 31) for the generation of the inter-word delay and the next-frame delay. Tiw = Tnf = 1/fCTQIN x (PCTQ1 + 1) x (DCTQ1 + 1) Reference Manual USIC, V2.14 14-99 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description PARIEN 13 rw Parity Error Interrupt Enable This bit enables/disables the generation of a protocol interrupt with the detection of a parity error. A protocol interrupt is not generated with the 0B detection of a parity error. A protocol interrupt is generated with the detection 1B of a parity error. MSLSIEN 14 rw MSLS Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the state of the MSLS signal changes (indicated by PSR.MSLSEV = 1). A protocol interrupt is not generated if a change of 0B signal MSLS is detected. A protocol interrupt is generated if a change of 1B signal MSLS is detected. DX2TIEN 15 rw DX2T Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the DX2T signal becomes activated (indicated by PSR.DX2TEV = 1). A protocol interrupt is not generated if DX2T is 0B activated. A protocol interrupt is generated if DX2T is 1B activated. SELO [23:16] rw Select Output This bit field defines the setting of the SELO[7:0] output lines. The corresponding SELOx line cannot be activated. 0B 1B The corresponding SELOx line can be activated (according to the mode selected by SELCTR). TIWEN 24 rw Enable Inter-Word Delay Tiw This bit enables/disables the inter-word delay Tiw after the transmission of a data word. No delay between data words of the same frame. 0B 1B The inter-word delay Tiw is enabled and introduced between data words of the same frame. Reference Manual USIC, V2.14 14-100 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SLPHSEL 25 rw Slave Mode Clock Phase Select This bit selects the clock phase for the data shifting in slave mode. Data bits are shifted out with the leading edge of the 0B shift clock signal and latched in with the trailing edge. The first data bit is shifted out when the data shift 1B unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge. MCLK 31 rw Master Clock Enable This bit enables/disables the generation of the master clock output signal MCLK, independent from master or slave mode. The MCLK generation is disabled and output 0B MCLK = 0. The MCLK generation is enabled. 1B 0 [30:26] rw Reserved Returns 0 if read; should be written with 0. Reference Manual USIC, V2.14 14-101 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.5.2 SSC Protocol Status Register In SSC mode, the PSR register bits or bit fields are defined as described in this section. The bits and bit fields in register PSR are not cleared by hardware. The flags in the PSR register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but does not lead to further actions (no interrupt generation). Writing a 0 has no effect. The PSR flags should be cleared by software before enabling a new protocol. PSR Protocol Status Register [SSC Mode] (48H) 31 15 30 14 29 28 13 12 27 11 26 10 25 9 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 0 BRG IF r rwh 8 7 6 5 4 3 2 1 0 AIF RIF TBIF TSIF DLIF RSIF 0 PAR DX2 MSL DX2 MSL ERR TEV SEV S S rwh rwh r rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description MSLS 0 rwh MSLS Status This bit indicates the current status of the MSLS signal. It must be cleared by software to stop a running frame. The internal signal MSLS is inactive (0). 0B 1B The internal signal MSLS is active (1). DX2S 1 rwh DX2S Status This bit indicates the current status of the DX2S signal that can be used as slave select input SELIN. DX2S is 0. 0B 1B DX2S is 1. MSLSEV 2 rwh MSLS Event Detected1) This bit indicates that the MSLS signal has changed its state since MSLSEV has been cleared. Together with the MSLS status bit, the activation/deactivation of the MSLS signal can be monitored. The MSLS signal has not changed its state. 0B 1B The MSLS signal has changed its state. Reference Manual USIC, V2.14 14-102 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DX2TEV 3 rwh DX2T Event Detected1) This bit indicates that the DX2T trigger signal has been activated since DX2TEV has been cleared. The DX2T signal has not been activated. 0B 1B The DX2T signal has been activated. PARERR 4 rwh Parity Error Event Detected1) This bit indicates that there is a mismatch in the received parity bit (in RBUFSR.PAR) with the calculated parity bit of the last received word of the data frame. A parity error event has not been activated. 0B 1B A parity error event has been activated. RSIF 10 rwh Receiver Start Indication Flag 0B A receiver start event has not occurred. 1B A receiver start event has occurred. DLIF 11 rwh Data Lost Indication Flag 0B A data lost event has not occurred. A data lost event has occurred. 1B TSIF 12 rwh Transmit Shift Indication Flag 0B A transmit shift event has not occurred. 1B A transmit shift event has occurred. TBIF 13 rwh Transmit Buffer Indication Flag 0B A transmit buffer event has not occurred. 1B A transmit buffer event has occurred. RIF 14 rwh Receive Indication Flag 0B A receive event has not occurred. A receive event has occurred. 1B AIF 15 rwh Alternative Receive Indication Flag 0B An alternative receive event has not occurred. 1B An alternative receive event has occurred. BRGIF 16 rwh Baud Rate Generator Indication Flag 0B A baud rate generator event has not occurred. 1B A baud rate generator event has occurred. 0 [9:5], [31:17] r Reserved Returns 0 if read; not modified in SSC mode. 1) This status bit can generate a protocol interrupt in SSC mode (see Page 14-22). The general interrupt status flags are described in the general interrupt chapter. Reference Manual USIC, V2.14 14-103 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.6 SSC Timing Considerations The input and output signals have to respect certain timings in order to ensure correct data reception and transmission. In addition to module internal timings (due to input filters, reaction times on events, etc.), also the timings from the input pin via the input stage (Tin) to the module and from the module via the output driver stage to the pin (Tout), as well as the signal propagation on the wires (Tprop) have to be taken into account. Please note that there might be additional delays in the DXn input stages, because the digital filter and the synchronization stages lead to systematic delays, that have to be considered if these functions are used. 14.4.6.1 Closed-loop Delay A system-inherent limiting factor for the baud rate of an SSC connection is the closedloop delay. In a typical application setup, a communication master device is connected to a slave device in full-duplex mode with independent lines for transmit and receive data. In a general case, all transmitters refer to one shift clock edge for transmission and all receivers refer to the other shift clock edge for reception. The master device’s SSC module sends out the transmit data, the shift clock and optionally the slave select signal. Therefore, the baud rate generation (BRG) and slave select generation (SSG) are part of the master device. The frame control is similar for SSC modules in master and slave mode, the main difference is the fact which module generates the shift clock and optionally, the slave select signals. SSC Slave Device SSC Master Device SSC Master Module To u t TBUF Tin RBUF MTSR Tp ro p MRST Tp ro p Tin RBUF To u t TBUF Frame Control Frame Control To u t BRG To u t SSG SSC Slave Module Shift Clock Tp ro p Slave Select Tp ro p Tin Tin Figure 14-46 SSC Closed-loop Delay Reference Manual USIC, V2.14 14-104 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The signal path between the SSC modules of the master and the slave device includes the master’s output driver, the wiring to the slave device and the slave device’s input stage. With the received shift clock edges, the slave device receives the master’s transmit data and transmits its own data back to the master device, passing by a similar signal path in the other direction. The master module receives the slave’s transmit data related to its internal shift clock edges. In order to ensure correct data reception in the master device, the slave’s transmit data has to be stable (respecting setup and hold times) as master receive data with the next shift clock edge of the master (generally 1/2 shift clock period). To avoid data corruption, the accumulated delays of the input and output stages, the signal propagation on the wiring and the reaction times of the transmitter/receiver have to be carefully considered, especially at high baud rates. In the given example, the time between the generation of the shift clock signal and the evaluation of the receive data by the master SSC module is given by the sum of Tout_master + 2 x Tprop + Tin_slave + Tout_slave + Tin_master + module reaction times + input setup times. The input path is characterized by an input delay depending mainly on the input stage characteristics of the pads. The output path delay is determined by the output driver delay and its slew rate, the external load and current capability of the driver. The device specific values for the input/output driver are given in the Data Sheet. Reference Manual USIC, V2.14 14-105 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Figure 14-47 describes graphically the closed-loop delay and the effect of two delay compensation options discussed in Section 14.4.6.2 and Section 14.4.6.3. 1) Without any delay compensation SCLK at master (Output driver stage ) MTSR at master (Output driver stage ) Master Data Tout_master + Tprop + Tin_slave SCLK at slave (input driver stage ) MRST at slave (Output driver stage ) Slave Data Delay may lead to a wrong slave data being latched in MRST at master (Input driver stage ) Slave Data Tout_slave+ Tprop + Tin_master 2) With master mode delay compensation SCLK at master (Receive data path ) For both cases with delay compensation , slave data is latched in correctly 3) With complete closed loop delay compensation SCLK at master (Receive data path) Figure 14-47 SSC Closed-loop Delay Timing Waveform Reference Manual USIC, V2.14 14-106 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.6.2 Delay Compensation in Master Mode A higher baud rate can be reached by delay compensation in master mode. This compensation is possible if (at least) the shift clock pin is bidirectional. SSC Master Device SSC Master Module To u t TBUF Tin RBUF SSC Slave Device MTSR Tp ro p MRST Tp ro p Tin RBUF To u t TBUF Frame Control BRG SSG SSC Slave Module Frame Control Shift Clock Tp ro p Slave Select Tp ro p Tin Tin Figure 14-48 SSC Master Mode with Delay Compensation If the receive shift clock signal in master mode is directly taken from the input function in parallel to the output signal, the output delay of the master device’s shift clock output is compensated and only the difference between the input delays of the master and the slave devices have to be taken into account instead of the complete master’s output delay and the slave’s input delay of the shift clock path. The delay compensation is enabled with DX1CR.DCEN = 1 while DX1CR.INSW = 0 (transmit shift clock is taken from the baud-rate generator). In the given example, the time between the evaluation of the shift clock signal and the receive data by the master SSC module is reduced by Tin_master + Tout_master. Although being a master mode, the shift clock input and optionally the slave select signal are not directly connected internally to the data shift unit, but are taken as external signals from input pins. The delay compensation does not lead to additional pins for the SSC communication if the shift clock output pin (slave select output pin, respectively) is/are bidirectional. In this case, the input signal is decoupled from other internal signals, because it is related to the signal level at the pin itself. Reference Manual USIC, V2.14 14-107 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.4.6.3 Complete Closed-loop Delay Compensation Alternatively, the complete closed-loop delay can be compensated by using one additional pin on both the SSC master and slave devices for the SSC communication. SSC Slave Device SSC Master Device SSC Master Module To ut TBUF Tin RBUF Tin Frame Control BRG SSG MTSR Tp ro p MRST Tprop Shift Clock Tp ro p (for Master Receive ) Shift Clock Tprop Slave Select Tprop Tin SSC Slave Module RBUF Tou t TBUF Tou t Frame Control Tin Tin Figure 14-49 SSC Complete Closed-loop Delay Compensation The principle behind this delay compensation method is to have the slave feedback the shift clock back to the master, which uses it as the receive shift clock. By going through a complete closed-loop signal path, the receive shift clock is thus fully compensated. The slave has to setup the SCLKOUT pin function to output the shift clock by setting the bit BRG.SCLKOSEL to 1, while the master has to setup the DX1 pin function to receive the shift clock from the slave and enable the delay compensation with DX1CR.DCEN = 1 and DX1CR.INSW = 0. Reference Manual USIC, V2.14 14-108 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5 Inter-IC Bus Protocol (IIC) The IIC protocol of the USIC refers to the IIC bus specification [7]. Contrary to that specification, the USIC device assumes rise/fall times of the bus signals of max. 300 ns in all modes. Please refer to the pad characteristics in the AC/DC chapter for the driver capability. CBUS mode and HS mode are not supported. The IIC mode is selected by CCR.MODE = 0100B with CCFG.IIC = 1 (IIC mode available). 14.5.1 Introduction USIC IIC Features: • • • • • • • • • Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA) Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s) Support of 7-bit addressing, as well as 10-bit addressing Master mode operation, where the IIC controls the bus transactions and provides the clock signal. Slave mode operation, where an external master controls the bus transactions and provides the clock signal. Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave. The master/slave operation of an IIC bus participant can change from frame to frame. Efficient frame handling (low software effort) Powerful interrupt handling due to multitude of indication flags Compensation support for input delays 14.5.1.1 Signal Description An IIC connection is characterized by two wires (SDA and SCL). The output drivers for these signals must have open-drain characteristics to allow the wired-AND connection of all SDA lines together and all SCL lines together to form the IIC bus system. Due to this structure, a high level driven by an output stage does not necessarily lead immediately to a high level at the corresponding input. Therefore, each SDA or SCL connection has to be input and output at the same time, because the input function always monitors the level of the signal, also while sending. • • Shift data SDA: input handled by DX0 stage, output signal DOUT0 Shift clock SCL: input handled by DX1 stage, output signal SCLKOUT Figure 14-29 shows a connection of two IIC bus participants (modules IIC A and IIC B) using the USIC. In this example, the pin assignment of module IIC A shows separate pins for the input and output signals for SDA and SCL. This assignment can be used if the application does not provide pins having DOUT0 and a DX0 stage input for the same pin Reference Manual USIC, V2.14 14-109 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) (similar for SCLKOUT and DX1). The pin assignment of module IIC B shows the connection of DOUT0 and a DX0 input at the same pin, also for SCLKOUT and a DX1 input. IIC Module A IIC Module B TBUF RBUF TBUF SCLKOUT + 3.3 V RBUF SCLKOUT Transfer Protocol SCLKIN DX1 SCLKIN DX1 SCL DOUT0 PPP IIC + 3.3 V DOUT0 DIN0 Transfer Protocol PPP IIC DIN0 DX0 DX0 SDA Baud Rate Generator fPER IPH (IIC A) fPER fSYS IPH (IIC (IIC A) B) Baud Rate Generator Figure 14-50 IIC Signal Connections 14.5.1.2 Symbols A symbol is a sequence of edges on the lines SDA and SCL. Symbols contain 10 or 25 time quanta tq, depending on the selected baud rate. The baud rate generator determines the length of the time quanta tq, the sequence of edges in a symbol is handled by the IIC protocol pre-processor, and the sequence of symbols can be programmed by the user according to the application needs. The following symbols are defined: • • Bus idle: SDA and SCL are high. No data transfer takes place currently. Data bit symbol: SDA stable during the high phase of SCL. SDA then represents the transferred bit value. There is one clock pulse on SCL for each transferred bit of data. During data transfers SDA may only change while SCL is low. Reference Manual USIC, V2.14 14-110 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • Start symbol: Signal SDA being high followed by a falling edge of SDA while SCL is high indicates a start condition. This start condition initiates a data transfer over the IIC bus after the bus has been idle. Repeated start symbol: This start condition initiates a data transfer over the bus after a data symbol when the bus has not been idle. Therefore, SDA is set high and SCL low, followed by a start symbol. Stop symbol: A rising edge on SDA while SCL is high indicates a stop condition. This stop condition terminates a data transfer to release the bus to idle state. Between a start condition and a stop condition an arbitrary number of bytes may be transferred. 14.5.1.3 Frame Format Data is transferred by the 2-line IIC bus (SDA, SCL) using a protocol that ensures reliable and efficient transfers. The sender of a (data) byte receives and checks the value of the following acknowledge field. The IIC being a wired-AND bus system, a 0 of at least one device leads to a 0 on the bus, which is received by all devices. A data word consists of 8 data bit symbols for the data value, followed by another data bit symbol for the acknowledge bit. The data word can be interpreted as address information (after a start symbol) or as transferred data (after the address). In order to be able to receive an acknowledge signal, the sender of the data bits has to release the SDA line by sending a 1 as acknowledge value. Depending on the internal state of the receiver, the acknowledge bit is either sent active or passive. 1 SDA Master D7 SCL Master 1 D6 Dx D0 P 0 1 2 8 9 0 SDA Slave 1 SCL Slave 1 0 0 Start Data Word Ack Stop Figure 14-51 IIC Frame Example (simplified) Reference Manual USIC, V2.14 14-111 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.2 Operating the IIC In order to operate the IIC protocol, the following issues have to be considered: • • • • • Select IIC mode: It is recommended to configure all parameters of the IIC that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 11B should be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIC mode can be enabled by CCR.MODE = 0100B afterwards. Pin connections: Establish a connection of input stage DX0 (with DX0CR.DPOL = 0) to the selected shift data pin SDA (signal DIN0) with DX0CR.INSW = 0 and configure the transmit data output signal DOUT0 (with SCTR.DOCFG = 00B) to the same pin. If available, this can be the same pin for input and output, or connect the selected input pin and the output pin to form the SDA line. The same mechanism applies for the shift clock line SCL. Here, signal SCLKOUT (with BRG.SCLKCFG = 00B) and an input of the DX1 stage have to be connected (with DX1CR.DPOL = 0). The input stage DX2 is not used for the IIC protocol. If the digital input filters are enabled in the DX0/1 stages, their delays have to be taken into account for correct calculation of the signal timings. The pins used for SDA and SCL have to be set to open-drain mode to support the wired-AND structure of the IIC bus lines. Note that the step to enable the alternate output port functions should only be done after the IIC mode is enabled, to avoided unintended spikes on the output. Bit timing configuration: In standard mode (100 kBit/s) a minimum module frequency of 2 MHz is necessary, whereas in fast mode (400 kBit/s) a minimum of 10 MHz is required. Additionally, if the digital filter stage should be used to eliminate spikes up to 50 ns, a filter frequency of 20 MHz is necessary. There could be an uncertainty in the SCL high phase timing of maximum 1/fPPP if another IIC participant lengthens the SCL low phase on the bus. More details are given in Section 14.5.3. Data format configuration: The data format has to be configured for 8 data bits (SCTR.WLE = 7), unlimited data flow (SCTR.FLE = 3FH), and MSB shifted first (SCTR.SDIR = 1). The parity generation has to be disabled (CCR.PM = 00B). General hints: The IIC slave module becomes active (for reception or transmission) if it is selected by the address sent by the master. In the case that the slave sends data to the master, it uses the transmit path. So a master must not request to read data from the slave address defined for its own channel in order to avoid collisions. The built-in error detection mechanisms are only activated while the IIC module is Reference Manual USIC, V2.14 14-112 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) taking part in IIC bus traffic. If the slave can not deal with too high frequencies, it can lengthen the low phase of the SCL signal. For data transfers according to the IIC specification, the shift data line SDA shall only change while SCL = 0 (defined by IIC bus specification). 14.5.2.1 Transmission Chain The IIC bus protocol requiring a kind of in-bit-response during the arbitration phase and while a slave is transmitting, the resulting loop delay of the transmission chain can limit the reachable maximal baud rate, strongly depending on the bus characteristics (bus load, module frequency, etc.). Figure 14-50 shows the general signal path and the delays in the case of a slave transmission. The shift clock SCL is generated by the master device, output on the wire, then it passes through the input stage and the input filter. Now, the edges can be detected and the SDA data signal can be generated accordingly. The SDA signal passes through the output stage and the wire to the master receiver part. There, it passes through the input stage and the input filter before it is sampled. This complete loop has to be finished (including all settling times to obtain stable signal levels) before the SCL signal changes again. The delays in this path have to be taken into account for the calculation of the baud rate as a function of fPERIPH and fPPP. 14.5.2.2 Byte Stretching If a device is selected as transceiver and should transmit a data byte but the transmit buffer TBUF does not contain valid data to be transmitted, the device ties down SCL = 0 at the end of the previous acknowledge bit. The waiting period is finished if new valid data has been detected in TBUF. 14.5.2.3 Master Arbitration During the address and data transmission, the master transmitter checks at the rising edge of SCL for each data bit if the value it is sending is equal to the value read on the SDA line. If yes, the next data bit values can be 0. If this is not the case (transmitted value = 1, value read = 0), the master has lost the transmit arbitration. This is indicated by status flag PSR.ARL and can generate a protocol interrupt if enabled by PCR.ARLIEN. When the transmit arbitration has been lost, the software has to initialize the complete frame again, starting with the first address byte together with the start condition for a new master transmit attempt. Arbitration also takes place for the ACK bit. Reference Manual USIC, V2.14 14-113 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.2.4 Non-Acknowledge and Error Conditions In case of a non-acknowledge or an error, the TCSR.TDV flag remains set, but no further transmission will take place. User software must invalidate the transmit buffer and disable transmissions (by writing FMRL.MTDV = 10B), before configuring the transmission (by writing TBUF) again with appropriate values to react on the previous event. In the case the FIFO data buffer is used, additionally the FIFO buffer needs to be flushed and filled again. 14.5.2.5 Mode Control Behavior In multi-master mode, only run mode 0 and stop mode 0 are supported, the other modes must not be programmed. • • • • Run Mode 0: Behavior as programmed. If TCSR.TDV = 0 (no new valid TBUF entry found) when a new TBUF entry needs to be processed, the IIC module waits for TDV becoming set to continue operation. Run Mode 1: Behavior as programmed. If in master mode, TCSR.TDV = 0 (no new valid TBUF entry found) when a new TBUF entry needs to be processed, the IIC module sends a stop condition to finish the frame. In slave mode, no difference to run mode 0. Stop Mode 0: Bit TCSR.TDV is internally considered as 0 (the bit itself is not modified by the stop mode). A currently running word is finished normally, but no new word is started in case of master mode (wait for TDV active). Bit TDV being considered as 0 for master and slave, the slave will force a wait state on the bus if read by an external master, too. Additionally, it is not possible to force the generation of a STOP condition out of the wait state. The reason is, that a master read transfer must be finished with a notacknowledged followed by a STOP condition to allow the slave to release his SDA line. Otherwise the slave may force the SDA line to 0 (first data bit of next byte) making it impossible to generate the STOP condition (rising edge on SDA). To continue operation, the mode must be switched to run mode 0 Stop Mode 1: Same as stop mode 0, but additionally, a master sends a STOP condition to finish the frame. If stop mode 1 is requested for a master device after the first byte of a 10 bit address, a stop condition will be sent out. In this case, a slave device will issue an error interrupt. 14.5.2.6 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to IIC frame handling. As the data input and output pins are the same in IIC protocol, a IIC transmitter also receives the Reference Manual USIC, V2.14 14-114 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) output data at its input pin. However, no receive related interrupts will be generated in this case. • • • • • Transmit buffer event: The transmit buffer event indication flag PSR.TBIF is set when the content of the transmit buffer TBUF has been loaded to the transmit shift register, indicating that the action requested by the TBUF entry has started. With this event, bit TCSR.TDV is cleared. This interrupt can be used to write the next TBUF entry while the last one is in progress (handled by the transmitter part). Receive event: This receive event indication flag PSR.RIF indicates that a new data byte has been written to the receive buffer RBUF0/1 (except for the first data byte of a new frame, that is indicated by an alternative receive interrupt). The flag becomes set when the data byte is received (after the falling edge of SCL). This interrupt can be used to read out the received data while a new data byte can be in progress (handled by the receiver part). Alternate receive event: The alternative receive event indication flag AIF is based on bit RBUFSR[9] (same as RBUF[9]), indicating that the received data word has been the first data word of a new data frame. Transmit shift event: The transmit shift event indication flag TSIF is set after the start of the last data bit of a data byte. Receive start event: The receive start event indication flag RSIF is set after the sample point of the first data bit of a data byte. Note: The transmit shift and receive start events can be ignored if the application does not require them during the IIC data transfer. 14.5.2.7 IIC Protocol Interrupt Events The following protocol-related events are generated in IIC mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • • • • • • • start condition received at a correct position in a frame (PSR.SCR) repeated start condition received at a correct position in a frame (PSR.RSCR) stop condition transferred at a correct position in a frame (PSR.PCR) master arbitration lost (PSR.ARL) slave read requested (PSR.SRR) acknowledge received (PSR.ACK) non-acknowledge received (PSR.NACK) start condition not at the expected position in a frame (PSR.ERR) Reference Manual USIC, V2.14 14-115 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • • • • stop condition not at the expected position in a frame (PSR.ERR) as slave, 10-bit address interrupted by a stop condition after the first address byte (PSR.ERR) TDF slave code in master mode (PSR.WTDF) TDF master code in slave mode (PSR.WTDF) Reserved TDF code found (PSR.WDTF) Start condition code during a running frame in master mode (PSR.WTDF) Data byte transmission code after transfer direction has been changed to reception (master read) in master mode (PSR.WTDF) If a wrong TDF code is found in TBUF, the error event is active until the TDF value is either corrected or invalidated. If the related interrupt is enabled, the interrupt handler should check PSR.WDTF first and correct or invalidate TBUF, before dealing with the other possible interrupt events. 14.5.2.8 Baud Rate Generator Interrupt Handling The baud rate generator interrupt indicate that the capture mode timer has reached its maximum value. With this event, the bit PSR.BRGIF is set. 14.5.2.9 Receiver Address Acknowledge After a (repeated) start condition, the master sends a slave address to identify the target device of the communication. The start address can comprise one or two address bytes (for 7 bit or for 10 bit addressing schemes). After an address byte, a slave sensitive to the transmitted address has to acknowledge the reception. Therefore, the slave’s address can be programmed in the device, where it is compared to the received address. In case of a match, the slave answers with an acknowledge (SDA = 0). Slaves that are not targeted answer with an non-acknowledge (SDA = 1). In addition to the match of the programmed address, another address byte value has to be answered with an acknowledge if the slave is capable to handle the corresponding requests. The address byte 00H indicates a general call address, that can be acknowledged. The value 01H stands for a start byte generation, that is not acknowledged In order to allow selective acknowledges for the different values of the address byte(s), the following control mechanism is implemented: • • • The address byte 00H is acknowledged if bit PCR.ACK00 is set. The address byte 01H is not acknowledged. The first 7 bits of a received first address byte are compared to the programmed slave address (PCR.SLAD[15:9]). If these bits match, the slave sends an acknowledge. In addition to this, if the slave address is programmed to 1111 0XXB, the slave device waits for a second address byte and compares it also to PCR.SLAD[7:0] and sends an acknowledge accordingly to cover the 10 bit addressing mode. The user has to Reference Manual USIC, V2.14 14-116 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) take care about reserved addresses (refer to IIC specification for more detailed description). Only the address 1111 0XXB is supported. Under each of these conditions, bit PSR.SLSEL will be set when the addressing delivered a match. This bit is cleared automatically by a (repeated) start condition. 14.5.2.10 Receiver Handling A selected slave receiver always acknowledges a received data byte. If the receive buffers RBUF0/1 are already full and can not accept more data, the respective register is overwritten (PSR.DLI becomes set in this case and a protocol interrupt can be generated). An address reception also uses the registers RBUF0/1 to store the address before checking if the device is selected. The received addresses do not set RDV0/1, so the addresses are not handled like received data. 14.5.2.11 Receiver Status Information In addition to the received data byte, some IIC protocol related information is stored in the 16-bit data word of the receive buffer. The received data byte is available at the bit positions RBUF[7:0], whereas the additional information is monitored at the bit positions RBUF[12:8]. This structure allows to identify the meaning of each received data byte without reading additional registers, also when using a FIFO data buffer. • • • • • RBUF[8]: Value of the received acknowledge bit. This information is also available in RBUFSR[8] as protocol argument. RBUF[9]: A 1 at this bit position indicates that after a (repeated) start condition followed by the address reception the first data byte of a new frame has been received. A 0 at this bit position indicates further data bytes. This information is also available in RBUFSR[9], allowing different interrupt routines for the address and data handling. RBUF[10]: A 0 at this bit position indicates that the data byte has been received when the device has been in slave mode, whereas a 1 indicates a reception in master mode. RBUF[11]: A 1 at this bit position indicates an incomplete/erroneous data byte in the receive buffer caused by a wrong position of a START or STOP condition in the frame. The bit is not identical to the frame error status bit in PSR, because the bit in the PSR has to be cleared by software (“sticky” bit), whereas RBUF[11] is evaluated data byte by data byte. If RBUF[11] = 0, the received data byte has been correct, independent of former errors. RBUF[12]: A 0 at this bit position indicates that the programmed address has been received. A 1 indicates a general call address. Reference Manual USIC, V2.14 14-117 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.3 Symbol Timing The symbol timing of the IIC is determined by the master stimulating the shift clock line SCL. It is different in each of the modes. • • 100 kBaud standard mode (PCR.STIM = 0): The symbol timing is based on 10 time quanta tq per symbol. A minimum module clock frequency fPERIPH = 2 MHz is required. 400 kBaud fast mode (PCR.STIM = 1): The symbol timing is based on 25 time quanta tq per symbol. A minimum module clock frequency fPERIPH = 10 MHz is required. The baud rate setting should only be changed while the transmitter and the receiver are idle or CCR.MODE = 0. The bits in register BRG define the length of a time quantum tq that is given by one period of fPCTQ. • • • BRG.CTQSEL to define the input frequency fCTQIN for the time quanta generation BRG.PCTQ to define the length of a time quantum (division of fCTQIN by 1, 2, 3, or 4) BRG.DCTQ to define the number of time quanta per symbol (number of tq = DCTQ + 1) The standard setting is given by CTQSEL = 00B (fCTQIN = fPDIV) and PPPEN = 0 (fPPP = fIN). Under these conditions, the frequency fPCTQ is given by: fPCTQ = fPIN × 1 1 × PCTQ + 1 PDIV + 1 (14.10) To respect the specified SDA hold time of 300 ns for standard mode and fast mode after a falling edge of signal SCL, a hold delay tHDEL has been introduced. It also prevents an erroneous detection of a start or a stop condition. The length of this delay can be programmed by bit field PCR.HDEL. Taking into account the input sampling and output update, bit field HDEL can be programmed according to: (14.11) f PPP HDEL ≥ 300 ns × f PPP – ⎛ 3 × --------------------⎞ + 1 ⎝ f PERIPH⎠ with digital filter and HDELmin = 2 f PPP HDEL ≥ 300 ns × f PPP – ⎛⎝ 3 × --------------------⎞⎠ + 2 f PERIPH without digital filter and HDELmin = 1 If the digital input filter is used, HDEL compensates the filter delay of 2 filter periods (fPPP should be used) in case of a spike on the input signal. This ensures that a data bit on the SDA line changing just before the rising edge or behind the falling edge of SCL will not be treated as a start or stop condition. Reference Manual USIC, V2.14 14-118 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.3.1 Start Symbol Figure 14-52 shows the general start symbol timing. Start Symbol Bus Idle SDA SCL Standard Mode X 0 .... 0 .... 4 .... 5 9 X tq Fast Mode X .... 15 16 24 X Figure 14-52 Start Symbol Timing 14.5.3.2 Repeated Start Symbol During the first part of a repeated start symbol, an SCL low value is driven for the specified number of time quanta. Then a high value is output. After the detection of a rising edge at the SCL input, a normal start symbol is generated, as shown in Figure 14-53. Repeated Start Symbol Start Symbol SDA tH D EL SCL Standard Mode X 0 .... 4 0 .... 4 5 .... 9 X tq Fast Mode X 0 15 0 .... 15 16 .... 24 X Figure 14-53 Repeated Start Symbol Timing Reference Manual USIC, V2.14 14-119 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.3.3 Stop Symbol Figure 14-54 shows the stop symbol timing. Stop Symbol Bus Idle SDA tH D EL SCL Standard Mode X 0 .... 0 .... 5 .... 15 16 .... 24 .... 9 X .... 24 X 4 9 X tq Fast Mode X X Figure 14-54 Stop Symbol Timing 14.5.3.4 Data Bit Symbol Figure 14-55 shows the general data bit symbol timing. Data Bit Symbol SDA tH D EL SCL Standard Mode X 0 .... Fast Mode X 0 .... 4 5 tq 15 16 Figure 14-55 Data Bit Symbol Output SDA changes after the time tHDEL defined by PCR.HDEL has elapsed if a falling edge is detected at the SCL input to respect the SDA hold time. The value of PCR.HDEL allows compensation of the delay of the SCL input path (sampling, filtering). Reference Manual USIC, V2.14 14-120 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) In the case of an acknowledge transmission, the USIC IIC waits for the receiver indicating that a complete byte has been received. This adds an additional delay of 3 periods of fPERIPH to the path. The minimum module input frequency has to be selected properly to ensure the SDA setup time to SCL rising edge. 14.5.4 Data Flow Handling The handling of the data flow and the sequence of the symbols in an IIC frame is controlled by the IIC transmitter part of the USIC communication channel. The IIC bus protocol is byte-oriented, whereas a USIC data buffer word can contain up to 16 data bits. In addition to the data byte to be transmitted (located at TBUF[7:0]), bit field TDF (transmit data format) to control the IIC sequence is located at the bit positions TBUF[10:8]. The TDF code defines for each data byte how it should be transmitted (IIC master or IIC slave), and controls the transmission of (repeated) start and stop symbols. This structure allows the definition of a complete IIC frame for an IIC master device only by writing to TBUFx or by using a FIFO data buffer mechanism, because no other control registers have to be accessed. Alternatively, polling of the ACK and NACK bits in PSR register can be performed, and the next data byte is transmitted only after an ACK is received. If a wrong or unexpected TDF code is encountered (e.g. due to a software error during setup of the transmit buffer), a stop condition will be sent out by the master. This leads to an abort of the currently running frame. A slave module waits for a valid TDF code and sets SCL = 0. The software then has to invalidate the unexpected TDF code and write a valid one. Please note that during an arbitration phase in multi-master bus systems an unpredictable bus behavior may occur due to an unexpected stop condition. 14.5.4.1 Transmit Data Formats The following transmit data formats are available in master mode: Table 14-13 Master Transmit Data Formats TDF Code Description 000B Send data byte as master This format is used to transmit a data byte from the master to a slave. The transmitter sends its data byte (TBUF[7:0]), receives and checks the acknowledge bit sent by the slave. 010B Receive data byte and send acknowledge This format is used by the master to read a data byte from a slave. The master acknowledges the transfer with a 0-level to continue the transfer. The content of TBUF[7:0] is ignored. Reference Manual USIC, V2.14 14-121 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-13 Master Transmit Data Formats (cont’d) TDF Code Description 011B Receive data byte and send not-acknowledge This format is used by the master to read a data byte from a slave. The master does not acknowledge the transfer with a 1-level to finish the transfer. The content of TBUF[7:0] is ignored. 100B Send start condition If TBUF contains this entry while the bus is idle, a start condition will be generated. The content of TBUF[7:0] is taken as first address byte for the transmission (bits TBUF[7:1] are the address, the LSB is the read/write control). 101B Send repeated start condition If TBUF contains this entry and SCL = 0 and a byte transfer is not in progress, a repeated start condition will be sent out if the device is the current master. The current master is defined as the device that has set the start condition (and also won the master arbitration) for the current message. The content of TBUF[7:0] is taken as first address byte for the transmission (bits TBUF[7:1] are the address, the LSB is the read/write control). 110B Send stop condition If the current master has finished its last byte transfer (including acknowledge), it sends a stop condition if this format is in TBUF. The content of TBUF[7:0] is ignored. 111B Reserved This code must not be programmed. No additional action except releasing the TBUF entry and setting the error bit in PSR (that can lead to a protocol interrupt). The following transmit data format is available in slave mode (the symbols in a frame are controlled by the master and the slave only has to send data if it has been “asked” by the master): Table 14-14 Slave Transmit Data Format TDF Code Description 001B Send data byte as slave This format is used to transmit a data byte from a slave to the master. The transmitter sends its data byte (TBUF[7:0]) plus the acknowledge bit as a 1. Reference Manual USIC, V2.14 14-122 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.4.2 Valid Master Transmit Data Formats Due to the IIC frame format definitions, only some specific sequences of TDF codes are possible and valid. If the USIC IIC module detects a wrong TDF code in a running frame, the transfer is aborted and flag PCR.WTDF is set. Additionally, an interrupt can be generated if enabled by the user. In case of a wrong TDF code, the frame will be aborted immediately with a STOP condition if the USIC IIC master still owns the SDA line. But if the accessed slave owns the SDA line (read transfer), the master must perform a dummy read with a non-acknowledge so that the slave releases the SDA line before a STOP condition can be sent. The received data byte of the dummy read will be stored in RBUF0/1, but RDV0/1 will not be set. Therefore the dummy read will not generate a receive interrupt and the data byte will not be stored into the receive FIFO. If the transfer direction has changed in the current frame (master read access), the transmit data request (TDF = 000B) is not possible and won't be accepted (leading to a wrong TDF Code indication). Table 14-15 Valid TDF Codes Overview Frame Position Valid TDF Codes First TDF code (master idle) Start (100B) Read transfer: second TDF code (after start or repeated start) Receive with acknowledge (010B) or receive with not-acknowledge (011B) Write transfer: second TDF code (after start Transmit (000B), repeated start (101B), or or repeated start) stop (110B) Read transfer: third and subsequent TDF code after acknowledge Receive with acknowledge (010B) or receive with not-acknowledge (011B) Read transfer: third and subsequent TDF code after not-acknowledge Repeated start (101B) or stop (110B) Write transfer: third and subsequent TDF code Transmit (000B), repeated start (101B), or stop (110B) • • First TDF code: A master transfer starts with the TDF start code (100B). All other codes are ignored, but no WTDF error will be indicated. TDF code after a start (100B) or repeated start code (101B) in case of a read access: If a master-read transfer is started (determined by the LSB of the address byte = 1), the transfer direction of SDA changes and the slave will actively drive the data line. In this case, only the codes 010B and 011B are valid. To abort the transfer in case of a wrong code, a dummy read must be performed by the master before the STOP condition can be generated. Reference Manual USIC, V2.14 14-123 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • • TDF code after a start (100B) or repeated start code (101B) in case of a write access: If a master-write transfer is started (determined by the LSB of the address byte = 0), the master still owns the SDA line. In this case, the transmit (000B), repeated start (101B) and stop (110B) codes are valid. The other codes are considered as wrong. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. TDF code of the third and subsequent command in case of a read access with acknowledged previous data byte: If a master-read transfer is started (determined by the LSB of the address byte), the transfer direction of SDA changes and the slave will actively drive the data line. To force the slave to release the SDA line, the master has to not-acknowledge a byte transfer. In this case, only the receive codes 010B and 011B are valid. To abort the transfer in case of a wrong code, a dummy read must be performed by the master before the STOP condition can be generated. TDF code of the third and subsequent command in case of a read access with a notacknowledged previous data byte: If a master-read transfer is started (determined by the LSB of the address byte), the transfer direction of SDA changes and the slave will actively drive the data line. To force the slave to release the SDA line, the master has to not-acknowledge a byte transfer. In this case, only the restart (101B) and stop code (110B) are valid. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. TDF code of the third and subsequent command in case of a write access: If a master-write transfer is started (determined by the LSB of the address byte), the master still owns the SDA line. In this case, the transmit (000B), repeated start (101B) and stop (110B) codes are valid. The other codes are considered as wrong. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. After a master device has received a non-acknowledge from a slave device, a stop condition will be sent out automatically, except if the following TDF code requests a repeated start condition. In this case, the TDF code is taken into account, whereas all other TDF codes are ignored. Reference Manual USIC, V2.14 14-124 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) no Bus idle? yes no TDF = 100 B ? yes Indicate arbitration loss and release bus Send start condition Send repeated start condition Send TBUF[7:0] with ACK = 1 yes Arbitration lost ? Send all 1s with ACK = 1 no Get new valid TBUF value Send all 1s with ACK = 0 Receive Transmit or receive ? Transmit yes no TDF = 000 B ? yes TDF = 010 B? no Send stop condition yes yes Indicate error Ignore TBUF no TDF = 101 B? no TDF = 011 B? yes TDF = 110 B? no Figure 14-56 IIC Master Transmission Reference Manual USIC, V2.14 14-125 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.4.3 Master Transmit/Receive Modes In master transmit mode, the IIC sends a number of data bytes to a slave receiver. The TDF code sequence for the master transmit mode is shown in Table 14-16. Table 14-16 TDF Code Sequence for Master Transmit TDF Code Sequence TBUF[10:8] TBUF[7:0] (TDF Code) IIC Response 1st code 100B Slave address + write bit Send START SCR: Indicates a condition, slave START condition is address and write bit detected TBIF: Next word can be written to TBUF 2nd code 000B Data or 2nd Send data or 2nd slave slave address byte address byte TBIF: Next word can be written to TBUF Subsequent 000B codes for data transmit Data Send data TBIF: Next word can be written to TBUF Last code Don’t care Send STOP condition PCR: Indicates a STOP condition is detected 110B Interrupt Events In master receive mode, the IIC receives a number of data bytes from a slave transmitter. The TDF code sequence for the master receive 7-bit and 10-bit addressing modes are shown in Table 14-17 and Table 14-18. Table 14-17 TDF Code Sequence for Master Receive (7-bit Addressing Mode) TDF Code Sequence TBUF[10:8] TBUF[7:0] (TDF Code) IIC Response 1st code 100B Slave address + read bit Send START SCR: Indicates a condition, slave START condition is address and read bit detected TBIF: Next word can be written to TBUF 2nd code 010B Don’t care Receive data and send ACK bit Reference Manual USIC, V2.14 14-126 Interrupt Events TBIF: Next word can be written to TBUF AIF: First data received can be read V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-17 TDF Code Sequence for Master Receive (7-bit Addressing Mode) TDF Code Sequence TBUF[10:8] TBUF[7:0] (TDF Code) IIC Response Interrupt Events Subsequent 010B codes for data receive Don’t care Receive data and send ACK bit TBIF: Next word can be written to TBUF RIF: Subsequent data received can be read Code for 011B last data to be received Don’t care Receive data and send NACK bit TBIF: Next word can be written to TBUF RIF: Last data received can be read Last code Don’t care Send STOP condition PCR: Indicates a STOP condition is detected 110B Table 14-18 TDF Code Sequence for Master Receive (10-bit Addressing Mode) TDF Code Sequence TBUF[10:8] TBUF[7:0] (TDF Code) IIC Response Interrupt Events 1st code 100B Slave address (1st byte) + write bit Send START condition, slave address (1st byte) and write bit SCR: Indicates a START condition is detected TBIF: Next word can be written to TBUF 2nd code 000B Slave address (2nd byte) Send address (2nd byte) TBIF: Next word can be written to TBUF 3rd code 101B 1st slave address + read bit Send repeated START condition, slave address (1st byte) and read bit RSCR: Indicates a repeated START condition is detected TBIF: Next word can be written to TBUF 4th code 010B Don’t care Receive data and send ACK bit TBIF: Next word can be written to TBUF AIF: First data received can be read Subsequent 010B codes for data receive Don’t care Receive data and send ACK bit TBIF: Next word can be written to TBUF RIF: Subsequent data received can be read Reference Manual USIC, V2.14 14-127 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-18 TDF Code Sequence for Master Receive (10-bit Addressing Mode) TDF Code Sequence TBUF[10:8] TBUF[7:0] (TDF Code) IIC Response Interrupt Events Code for 011B last data to be received Don’t care Receive data and send NACK bit TBIF: Next word can be written to TBUF RIF: Last data received from slave can be read Last code Don’t care Send STOP condition PCR: Indicates a STOP condition is detected 110B Figure 14-57 shows the interrupt events during the master transmit-slave receive and master receive/slave transmit sequences. Master Transmit – Slave Receive TBIF SCR TBIF TBIF PCR Master Transmit S Slave Address W A Data A Data A P Slave Receive SCR AIF RIF PCR RIF PCR Master Receive – Slave Transmit TBIF SCR TBIF AIF TBIF Master Receive S Slave Address R A Data A Data NA P Slave Transmit SCR SRR From master to slave TBIF TBIF From slave to master Interrupt events on the master PCR Interrupt events on the slave Figure 14-57 Interrupt Events on Data Transfers 14.5.4.4 Slave Transmit/Receive Modes In slave receive mode, no TDF code needs to be written and data reception is indicated by the alternate receive (AIF) or receive (RIF) events. In slave transmit mode, upon receiving its own slave address or general call address if this option is enabled, a slave read request event (SRR) will be triggered. The slave IIC then writes the TDF code 001B and the requested data to TBUF to transmit the data to Reference Manual USIC, V2.14 14-128 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) the master. The slave does not check if the master reply with an ACK or NACK to the transmitted data. In both cases, the data transfer is terminated by the master sending a STOP condition, which is indicated by a PCR event. See also Figure 14-57. 14.5.5 IIC Protocol Registers In IIC mode, the registers PCR and PSR handle IIC related information. 14.5.5.1 IIC Protocol Control Registers In IIC mode, the PCR register bits or bit fields are defined as described in this section. PCR Protocol Control Register [IIC Mode] (3CH) 31 30 29 28 MCL ACKI K EN rw rw 15 14 27 26 rw 12 11 24 23 22 21 20 19 18 17 16 SAC ERRI SRRI ARLI NAC PCRI RSC SCRI ACK STIM KDIS EN EN EN KIEN EN RIEN EN 00 HDEL 13 25 Reset Value: 0000 0000H 10 rw rw rw rw rw rw rw rw rw rw 9 8 7 6 5 4 3 2 1 0 SLAD rw Field Bits Type Description SLAD [15:0] rw Slave Address This bit field contains the programmed slave address. The corresponding bits in the first received address byte are compared to the bits SLAD[15:9] to check for address match. If SLAD[15:11] = 11110B, then the second address byte is also compared to SLAD[7:0]. ACK00 16 rw Acknowledge 00H This bit defines if a slave device should be sensitive to the slave address 00H. 0B The slave device is not sensitive to this address. The slave device is sensitive to this address. 1B Reference Manual USIC, V2.14 14-129 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description STIM 17 rw Symbol Timing This bit defines how many time quanta are used in a symbol. A symbol contains 10 time quanta. The timing is 0B adapted for standard mode (100 kBaud). A symbol contains 25 time quanta. The timing is 1B adapted for fast mode (400 kBaud). SCRIEN 18 rw Start Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a start condition is detected. The start condition interrupt is disabled. 0B 1B The start condition interrupt is enabled. RSCRIEN 19 rw Repeated Start Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a repeated start condition is detected. The repeated start condition interrupt is disabled. 0B 1B The repeated start condition interrupt is enabled. PCRIEN 20 rw Stop Condition Received Interrupt Enable This bit enables the generation of a protocol interrupt if a stop condition is detected. The stop condition interrupt is disabled. 0B 1B The stop condition interrupt is enabled. NACKIEN 21 rw Non-Acknowledge Interrupt Enable This bit enables the generation of a protocol interrupt if a non-acknowledge is detected by a master. The non-acknowledge interrupt is disabled. 0B 1B The non-acknowledge interrupt is enabled. ARLIEN 22 rw Arbitration Lost Interrupt Enable This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. The arbitration lost interrupt is disabled. 0B 1B The arbitration lost interrupt is enabled. SRRIEN 23 rw Slave Read Request Interrupt Enable This bit enables the generation of a protocol interrupt if a slave read request is detected. The slave read request interrupt is disabled. 0B 1B The slave read request interrupt is enabled. Reference Manual USIC, V2.14 14-130 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description ERRIEN 24 rw Error Interrupt Enable This bit enables the generation of a protocol interrupt if an IIC error condition is detected (indicated by PSR.ERR or PSR.WTDF). The error interrupt is disabled. 0B The error interrupt is enabled. 1B SACKDIS 25 rw Slave Acknowledge Disable This bit disables the generation of an active acknowledge signal for a slave device (active acknowledge = 0 level). Once set by software, it is automatically cleared with each (repeated) start condition. If this bit is set after a byte has been received (indicated by an interrupt) but before the next acknowledge bit has started, the next acknowledge bit will be sent with passive level. This would indicate that the receiver does not accept more bytes. As a result, a minimum of 2 bytes will be received if the first receive interrupt is used to set this bit. The generation of an active slave acknowledge is 0B enabled (slave acknowledge with 0 level = more bytes can be received). The generation of an active slave acknowledge is 1B disabled (slave acknowledge with 1 level = reception stopped). HDEL [29:26] rw Hardware Delay This bit field defines the delay used to compensate the internal treatment of the SCL signal (see Page 14-118) in order to respect the SDA hold time specified for the IIC protocol. ACKIEN 30 rw Acknowledge Interrupt Enable This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 0B The acknowledge interrupt is disabled. The acknowledge interrupt is enabled. 1B MCLK 31 rw Master Clock Enable This bit enables generation of the master clock MCLK (not directly used for IIC protocol, can be used as general frequency output). The MCLK generation is disabled and MCLK is 0. 0B 1B The MCLK generation is enabled. Reference Manual USIC, V2.14 14-131 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.5.5.2 IIC Protocol Status Register The following PSR status bits or bit fields are available in IIC mode. Please note that the bits in register PSR are not cleared by hardware. The flags in the PSR register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but does not lead to further actions (no interrupt generation). Writing a 0 has no effect. These flags should be cleared by software before enabling a new protocol. PSR Protocol Status Register [IIC Mode] 31 30 29 13 28 23 22 21 20 19 18 17 16 0 BRG IF r rwh AIF rwh rwh rwh 9 24 NAC RSC WTD SLS RIF TBIF TSIF DLIF RSIF ACK ERR SRR ARL PCR SCR K R F EL rwh 10 25 14 rwh 11 26 Reset Value: 0000 0000H 15 rwh 12 27 (48H) rwh 8 rwh 7 rwh 6 rwh 5 rwh 4 rwh 3 rwh 2 1 rwh rwh 0 rwh Field Bits Type Description SLSEL 0 rwh Slave Select This bit indicates that this device has been selected as slave. The device is not selected as slave. 0B 1B The device is selected as slave. WTDF 1 rwh Wrong TDF Code Found1) This bit indicates that an unexpected/wrong TDF code has been found. A protocol interrupt can be generated if PCR.ERRIEN = 1. A wrong TDF code has not been found. 0B 1B A wrong TDF code has been found. SCR 2 rwh Start Condition Received1) This bit indicates that a start condition has been detected on the IIC bus lines.A protocol interrupt can be generated if PCR.SCRIEN = 1. A start condition has not yet been detected. 0B A start condition has been detected. 1B Reference Manual USIC, V2.14 14-132 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RSCR 3 rwh Repeated Start Condition Received1) This bit indicates that a repeated start condition has been detected on the IIC bus lines. A protocol interrupt can be generated if PCR.RSCRIEN = 1. A repeated start condition has not yet been 0B detected. A repeated start condition has been detected. 1B PCR 4 rwh Stop Condition Received1) This bit indicates that a stop condition has been detected on the IIC bus lines. A protocol interrupt can be generated if PCR.PCRIEN = 1. A stop condition has not yet been detected. 0B 1B A stop condition has been detected. NACK 5 rwh Non-Acknowledge Received1) This bit indicates that a non-acknowledge has been received in master mode. This bit is not set in slave mode. A protocol interrupt can be generated if PCR.NACKIEN = 1. A non-acknowledge has not been received. 0B 1B A non-acknowledge has been received. ARL 6 rwh Arbitration Lost1) This bit indicates that an arbitration has been lost. A protocol interrupt can be generated if PCR.ARLIEN = 1. An arbitration has not been lost. 0B 1B An arbitration has been lost. SRR 7 rwh Slave Read Request1) This bit indicates that a slave read request has been detected. It becomes active to request the first data byte to be made available in the transmit buffer. For further consecutive data bytes, the transmit buffer issues more interrupts. For the end of the transfer, the master transmitter sends a stop condition. A protocol interrupt can be generated if PCR.SRRIEN = 1. A slave read request has not been detected. 0B A slave read request has been detected. 1B Reference Manual USIC, V2.14 14-133 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description ERR 8 rwh Error1) This bit indicates that an IIC error (frame format or TDF code) has been detected. A protocol interrupt can be generated if PCR.ERRIEN = 1. An IIC error has not been detected. 0B An IIC error has been detected. 1B ACK 9 rwh Acknowledge Received1) This bit indicates that an acknowledge has been received in master mode. This bit is not set in slave mode. A protocol interrupt can be generated if PCR.ACKIEN = 1. An acknowledge has not been received. 0B 1B An acknowledge has been received. RSIF 10 rwh Receiver Start Indication Flag 0B A receiver start event has not occurred. 1B A receiver start event has occurred. DLIF 11 rwh Data Lost Indication Flag 0B A data lost event has not occurred. A data lost event has occurred. 1B TSIF 12 rwh Transmit Shift Indication Flag 0B A transmit shift event has not occurred. 1B A transmit shift event has occurred. TBIF 13 rwh Transmit Buffer Indication Flag 0B A transmit buffer event has not occurred. 1B A transmit buffer event has occurred. RIF 14 rwh Receive Indication Flag 0B A receive event has not occurred. A receive event has occurred. 1B AIF 15 rwh Alternative Receive Indication Flag 0B An alternative receive event has not occurred. 1B An alternative receive event has occurred. BRGIF 16 rwh Baud Rate Generator Indication Flag 0B A baud rate generator event has not occurred. 1B A baud rate generator event has occurred. 0 [31:17] r Reserved Returns 0 if read; not modified in IIC mode. 1) This status bit can generate a protocol interrupt (see Page 14-22). The general interrupt status flags are described in the general interrupt chapter. Reference Manual USIC, V2.14 14-134 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.6 Inter-IC Sound Bus Protocol (IIS) This chapter describes how the USIC module handles the IIS protocol. This serial protocol can handle reception and transmission of synchronous data frames between a device operating in master mode and a device in slave mode. An IIS connection based on a USIC communication channel supports half-duplex and full-duplex data transfers. The IIS mode is selected by CCR.MODE = 0011B with CCFG.IIS = 1 (IIS mode is available). 14.6.1 Introduction The IIS protocol is a synchronous serial communication protocol mainly for audio and infotainment applications [8]. 14.6.1.1 Signal Description A connection between an IIS master and an IIS slave is based on the following signals: • • • • A shift clock signal SCK, generated by the transfer master. It is permanently generated while an IIS connection is established, also while no valid data bits are transferred. A word address signal WA (also named WS), generated by the transfer master. It indicates the beginning of a new data word and the targeted audio channel (e.g. left/right). The word address output signal WA is available on all SELOx outputs if the WA generation is enabled (by PCR.WAGEN = 1 for the transfer master). The WA signal changes synchronously to the falling edges of the shift clock. If the transmitter is the IIS master device, it generates a master transmit slave receive data signal. The data changes synchronously to the falling edges of the shift clock. If the transmitter is the IIS slave device, it generates a master receive slave transmit data signal. The data changes synchronously to the falling edges of the shift clock. The transmitter part and the receiver part of the USIC communication channel can be used together to establish a full-duplex data connection between an IIS master and a slave device. Table 14-19 IIS IO Signals IIS Mode Receive Data Shift Clock Word Address Master Input DIN0, Output DOUT0 handled by DX0 Output SCLKOUT Output(s) SELOx Slave Input DIN0, Output DOUT0 handled by DX0 Input SCLKIN, Input SELIN, handled by DX1 handled by DX2 Reference Manual USIC, V2.14 Transmit Data 14-135 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) IIS Communication Master DOUT0 TBUF DIN0 RBUF DX0 SELOx WA Generator SCLKOUT IIS Communication Slave Master Transmit / Slave Receive DIN0 Master Receive / Slave Transmit DOUT0 Word Address (Word Select ) SELIN Shift Clock Baud Rate Generator DX0 RBUF TBUF DX2 SCLKIN DX1 MCLKOUT Master Clock Output SCLKIN DX1 fPER IPH (Slave) Synchronization Clock Input fPER IPH (Master) Figure 14-58 IIS Signals Two additional signals are available for the USIC IIS communication master: • • A master clock output signal MCLKOUT with a fixed phase relation to the shift clock to support oversampling for audio components. It can also be used as master clock output of a communication network with synchronized IIS connections. A synchronization clock input SCLKIN for synchronization of the shift clock generation to an external frequency to support audio frequencies that can not be directly derived from the system clock fPERIPH of the communication master. It can be used as master clock input of a communication network with synchronized IIS connections. 14.6.1.2 Protocol Overview An IIS connection supports transfers for two different data frames via the same data line, e.g. a data frames for the left audio channel and a data frame for the right audio channel. The word address signal WA is used to distinguish between the different data frames. Each data frame can consist of several data words. Reference Manual USIC, V2.14 14-136 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) In a USIC communication channel, data words are tagged for being transmitted for the left or for the right channel. Also the received data words contain a tag identifying the WA state when the data has been received. WA (WS) Left Channel Right Channel SCK MSB DOUT0 0 DIN0 X LSB MSB Right Data Frame MSB 0 LSB LSB Left Data Frame MSB Right Data Frame X 0 LSB Left Data Frame X Figure 14-59 Protocol Overview 14.6.1.3 Transfer Delay The transfer delay feature allows the transfer of data (transmission and reception) with a programmable delay (counted in shift clock periods). SCK SCK WA WA DATA DATA Without Delay With Delay 1 Figure 14-60 Transfer Delay for IIS 14.6.1.4 Connection of External Audio Components The IIS signals can be used to communicate with external audio devices (such as Codecs) or other audio data sources/destinations. Reference Manual USIC, V2.14 14-137 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) USIC IIS Audio-ADC MCLKOUT MCLK_IN SCLKOUT SCK_IN WA WA_IN DIN0 R L Analog Inputs SD_OUT DOUT0 Audio-DAC MCLK_IN SCK_IN R L Analog Outputs WA_IN SD_IN Figure 14-61 Connection of External Audio Devices In some applications, especially for Audio-ADCs or Audio-DACs, a master clock signal is required with a fixed phase relation to the shift clock signal. The frequency of MCLKOUT is a multiple of the shift frequency SCLKOUT. This factor defines the oversampling factor of the external device (commonly used values: 256 or 384). 14.6.2 Operating the IIS This chapter contains IIS issues, that are of general interest and not directly linked to master mode or slave mode. 14.6.2.1 Frame Length and Word Length Configuration After each change of the WA signal, a complete data frame is intended to be transferred (frame length ≤ system word length). The number of data bits transferred after a change of signal WA is defined by SCTR.FLE. A data frame can consist of several data words with a data word length defined by SCTR.WLE. The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA (number of bits available for the right channel and same number available for the left channel). If the system word length is longer than the frame length defined by SCTR.FLE, the additional bits are transmitted with passive data level (SCTR.PDL). If the system word Reference Manual USIC, V2.14 14-138 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) length is smaller than the device frame length, not all LSBs of the transmit data can be transferred. It is recommended to program bits WLEMD, FLEMD and SELMD in register TCSR to 0. 14.6.2.2 Automatic Shadow Mechanism The baud rate and shift control setting are internally kept constant while a data frame is transferred by an automatic shadow mechanism. The registers can be programmed all the time with new settings that are taken into account for the next data frame. During a data frame, the applied (shadowed) setting is not changed, although new values have been written after the start of the data frame. The setting is internally “frozen” with the start of each data frame. Although this shadow mechanism being implemented, it is recommended to change the baud rate and shift control setting only while the IIS protocol is switched off. 14.6.2.3 Mode Control Behavior In IIS mode, the following kernel modes are supported: • • Run Mode 0/1: Behavior as programmed, no impact on data transfers. Stop Mode 0/1: Bit PCR.WAGEN is internally considered as 0 (the bit itself is not changed). If WAGEN = 1, the WA generation is stopped, but PSR.END is not set. The complete data frame is finished before entering stop mode, including a possible delay due to PCR.TDEL. When leaving a stop mode with WAGEN = 1, the WA generation starts from the beginning. 14.6.2.4 Transfer Delay The transfer delay can be used to synchronize a data transfer to an event (e.g. a change of the WA signal). This event has to be synchronously generated to the falling edge of the shift clock SCK (like the change of the transmit data), because the input signal for the event is directly sampled in the receiver (as a result, the transmitter can use the detection information with its next edge). Event signals that are asynchronous to the shift clock while the shift clock is running must not be used. In the example in Figure 14-60, the event (change of signal WA) is generated by the transfer master and as a result, is synchronous to the shift clock SCK. With the rising edge of SCK, signal WA is sampled and checked for a change. If a change is detected, a transfer delay counter TDC is automatically loaded with its programmable reload value (PCR.TDEL), otherwise it is decremented with each rising edge of SCK until it reaches 0, where it stops. The transfer itself is started if the value of TDC has become 0. This can happen under two conditions: Reference Manual USIC, V2.14 14-139 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • TDC is reloaded with a PCR.TDEL = 0 when the event is detected TDC has reached 0 while counting down The transfer delay counter is internal to the IIS protocol pre-processor and can not be observed by software. The transfer delay in SCK cycles is given by PCR.TDEL+1. In the example in Figure 14-62, the reload value PCR.TDEL for TDC is 0. When the samples taken on receiver side show the change of the WA signal, the counter TDC is reloaded. If the reload value is 0, the data transfer starts with 1 shift clock cycle delay compared to the change of WA. SCK s s s s s s s WA TDC 0 DOUT0 X 0 0 D0 DIN0 sampled D1 D0 s X D1 D0 D0 = sampling of WA Figure 14-62 Transfer Delay with Delay 1 The ideal case without any transfer delay is shown in Figure 14-63. The WA signal changes and the data output value become valid at the same time. This implies that the transmitter “knows” in advance that the event signal will change with the next rising edge of TCLK. This is achieved by delaying the data transmission after the previously detected WA change the system word length minus 1. Reference Manual USIC, V2.14 14-140 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) SCK s s s s s s s WA TDC DOUT0 1 n 0 D0 X DIN0 sampled n-1 D1 D0 s n-2 D2 1 0 X D1 n D0 D1 D0 D1 = sampling of WA Figure 14-63 No Transfer Delay If the end of the transfer delay is detected simultaneously to change of WA, the transfer is started and the delay counter is reloaded with PCR.TDEL. This allows to run the USIC as IIS device without any delay. In this case, internally the delay from the previous event elapses just at the moment when a new event occurs. If PCR.TDEL is set to a value bigger than the system word length, no transfer takes place. 14.6.2.5 Parity Mode Parity generation is not supported in IIS mode and bit field CCR.PM = 00B has to be programmed. 14.6.2.6 Transfer Mode In IIS mode, bit field SCTR.TRM = 11B has to be programmed to allow data transfers. Setting SCTR.TRM = 00B disables and stops the data transfer immediately. 14.6.2.7 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to IIS frame handling. • • Transmit buffer interrupt TBI: Bit PSR.TBIF is set after the start of first data bit of a data word. Transmit shift interrupt TSI: Bit PSR.TSIF is set after the start of the last data bit of a data word. Reference Manual USIC, V2.14 14-141 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • Receiver start interrupt RSI: Bit PSR.RSIF is set after the reception of the first data bit of a data word. With this event, bit TCSR.TDV is cleared and new data can be loaded to the transmit buffer. Receiver interrupt RI and alternative interrupt AI: Bit PSR.RIF is set at after the reception of the last data bit of a data word with WA = 0. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a new data frame. Bit PSR.AIF is set at after the reception of the last data bit of a data word with WA = 1. Bit RBUFSR.SOF indicates whether the received data word has been the first data word of a new data frame. 14.6.2.8 Baud Rate Generator Interrupt Handling The baud rate generator interrupt indicate that the capture mode timer has reached its maximum value. With this event, the bit PSR.BRGIF is set. 14.6.2.9 Protocol-Related Argument and Error In order to distinguish between data words received for the left or the right channel, the IIS protocol pre-processor samples the level of the WA input (just after the WA transition) and propagates it as protocol-related error (although it is not an error, but an indication) to the receive buffer status register at the bit position RBUFSR[9]. This bit position defines if either a standard receive interrupt (if RBUFSR[9] = 0) or an alternative receive interrupt (if RBUFSR[9] = 1) becomes activated when a new data word has been received. Incoming data can be handled by different interrupts for the left and the right channel if the corresponding events are directed to different interrupt nodes. Flag PAR is always 0. 14.6.2.10 Transmit Data Handling The IIS protocol pre-processor allows to distinguish between the left and the right channel for data transmission. Therefore, bit TCSR.WA indicates on which channel the data in the buffer will be transmitted. If TCSR.WA = 0, the data will be transmitted after a falling edge of WA. If TCSR.WA = 1, the data will be transmitted after a rising edge of WA. The WA value sampled after the WA transition is considered to distinguish between both channels (referring to PSR.WA). Bit TCSR.WA can be automatically updated by the transmit control information TCI[4] for each data word if TCSR.WAMD = 1. In this case, data written to TBUF[15:0] (or IN[15:0] if a FIFO data buffer is used) is considered as left channel data, whereas data written to TBUF[31:16] (or IN[31:16] if a FIFO data buffer is used) is considered as right channel data. Reference Manual USIC, V2.14 14-142 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.6.2.11 Receive Buffer Handling If a receive FIFO buffer is available (CCFG.RB = 1) and enabled for data handling (RBCTR.SIZE > 0), it is recommended to set RBCTR.RCIM = 11B in IIS mode. This leads to an indication that the data word has been the first data word of a new data frame if bit OUTR.RCI[0] = 1, and the channel indication by the sampled WA value is given by OUTR.RCI[4]. The standard receive buffer event and the alternative receive buffer event can be used for the following operation in RCI mode (RBCTR.RNM = 1): • • A standard receive buffer event indicates that a data word can be read from OUTR that belongs to a data frame started when WA = 0. An alternative receive buffer event indicates that a data word can be read from OUTR that belongs to a data frame started when WA = 1. 14.6.2.12 Loop-Delay Compensation The synchronous signaling mechanism of the IIS protocol being similar to the one of the SSC protocol, the closed-loop delay has to be taken into account for the application setup. In IIS mode, loop-delay compensation in master mode is also possible to achieve higher baud rates. Please refer to the more detailed description in the SSC chapter. 14.6.3 Operating the IIS in Master Mode In order to operate the IIS in master mode, the following issues have to be considered: • • • Select IIS mode: It is recommended to configure all parameters of the IIS that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 11B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIS mode can be enabled by CCR.MODE = 0011B afterwards. Pin connection for data transfer: Establish a connection of input stage DX0 with the selected receive data input pin (DIN0) with DX0CR.INSW = 1. Configure a transmit data output pin (DOUT0) for a transmitter. The data shift unit allowing full-duplex data transfers based on the same WA signal, the values delivered by the DX0 stage are considered as data bits (receive function can not be disabled independently from the transmitter). To receive IIS data, the transmitter does not necessarily need to be configured (no assignment of DOUT0 signal to a pin). Baud rate generation: The desired baud rate setting has to be selected, comprising the fractional divider Reference Manual USIC, V2.14 14-143 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • and the baud rate generator. Bit DX1CR.INSW = 0 has to be programmed to use the baud rate generator output SCLK directly as input for the data shift unit. Word address WA generation: The WA generation has to be enabled by setting PCR.WAGEN = 1 and the programming of the number of shift clock cycles between the changes of WA. Bit DX2CR.INSW = 0 has to be programmed to use the WA generator as input for the data shift unit. Configure WA output pin for signal SELOx if needed. Data format configuration: The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the register SCTR. Generally, the MSB is shifted first (SCTR.SDIR = 1). Bit TCSR.WAMD can be set to use the transmit control information TCI[4] to distinguish the data words for transmission while WA = 0 or while WA = 1. Note: The step to enable the alternate output port functions should only be done after the IIS mode is enabled, to avoided unintended spikes on the output. 14.6.3.1 Baud Rate Generation The baud rate is defined by the frequency of the SCLK signal (one period of fSCLK represents one data bit). If the fractional divider mode is used to generate fPIN, there can be an uncertainty of one period of fPERIPH for fPIN. This uncertainty does not accumulate over several SCLK cycles. As a consequence, the average frequency is reached, whereas the duty cycle of 50% of the SCLK and MCLK signals can vary by one period of fPERIPH. In IIS applications, where the phase relation between the optional MCLK output signal and SCLK is not relevant, SCLK can be based on the frequency fPIN (BRG.PPPEN = 0). In the case that a fixed phase relation between the MCLK signal and SCLK is required (e.g. when using MCLK as clock reference for external devices), the additional divider by 2 stage has to be taken into account (BRG.PPPEN = 1). This division is due to the fact that signal MCLK toggles with each cycle of fPIN. Signal SCLK is then based on signal MCLK, see Figure 14-64. The adjustable integer divider factor is defined by bit field BRG.PDIV. fPIN 1 PDIV + 1 fPIN 1 × fSCLK = 2×2 PDIV + 1 fSCLK = 2 × if PPPEN = 0 (14.12) if PPPEN = 1 Note: In the IIS protocol, the master (unit generating the shift clock and the WA signal) changes the status of its data and WA output line with the falling edge of SCK. The slave transmitter also has to transmit on falling edges. The sampling of the received data is done with the rising edges of SCLK. The input stage DX1 and the Reference Manual USIC, V2.14 14-144 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) SCLKOUT have to be programmed to invert the shift clock signal to fit to the internal signals. 14.6.3.2 WA Generation The word address (or word select) line WA regularly toggles after N cycles of signal SCLK. The time between the changes of WA is called system word length and can be programmed by using the following bit fields. In IIS master mode, the system word length is defined by: • • • BRG.CTQSEL = 10B to base the WA toggling on SCLK BRG.PCTQ to define the number N of SCLK cycles per system word length BRG.DCTQ to define the number N of SCLK cycles per system word length N = (PCTQ + 1) × (DCTQ + 1) (14.13) 14.6.3.3 Master Clock Output The master clock signal MCLK can be generated by the master of the IIS transfer (BRG.PPPEN = 1). It is used especially to connect external Codec devices. It can be configured by bit BRG.MCLKCFG in its polarity to become the output signal MCLKOUT. ½ x SCLK = (PDIV+1) x MCLK fPIN ½ x SCLK = (PDIV+1) x MCLK MCLK MCLK SCLK SCLK zoom in Transmitter DOUT0 D(n) Receiver sampled DIN0 D(n) D(n+1) D(n+1) 1 Period of SCLK = 1 Data Bit Length Figure 14-64 MCLK and SCLK for IIS Reference Manual USIC, V2.14 14-145 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.6.3.4 Protocol Interrupt Events The following protocol-related events are generated in IIS mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • • WA rising/falling edge events: The WA generation block indicates two events that are monitored in register PSR. Flag PSR.WAFE is set with the falling edge, flag PSR.WARE with the rising edge of the WA signal. A protocol interrupt can be generated if PCR.WAFEIEN = 1 for the falling edge, similar for PCR.WAREIEN = 1 for a rising edge. WA end event: The WA generation block also indicates when it has stopped the WA generation after it has been disabled by writing PCR.WAGEN = 0. A protocol interrupt can be generated if PCR.ENDIEN = 1. DX2T event: An activation of the trigger signal DX2T is indicated by PSR.DX2TEV = 1 and can generate a protocol interrupt if PCR.DX2TIEN = 1. This event can be evaluated instead of the WA rising/falling events if a delay compensation like in SSC mode (for details, refer to corresponding SSC section) is used. 14.6.4 Operating the IIS in Slave Mode In order to operate the IIS in slave mode, the following issues have to be considered: • • Select IIS mode: It is recommended to configure all parameters of the IIS that do not change during run time while CCR.MODE = 0000B. Bit field SCTR.TRM = 11B has to be programmed. The configuration of the input stages has to be done while CCR.MODE = 0000B to avoid unintended edges of the input signals and the IIS mode can be enabled by CCR.MODE = 0011B afterwards. Pin connection for data transfer: Establish a connection of input stage DX0 with the selected receive data input pin (DIN0) with DX0CR.INSW = 1. Configure a transmit data output pin (DOUT0) for a transmitter. The data shift unit allowing full-duplex data transfers based on the same WA signal, the values delivered by the DX0 stage are considered as data bits (receive function can not be disabled independently from the transmitter). To receive IIS data, the transmitter does not necessarily need to be configured (no assignment of DOUT0 signal to a pin). Note that the step to enable the alternate output port functions should only be done after the IIS mode is enabled, to avoided unintended spikes on the output. Reference Manual USIC, V2.14 14-146 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • • Pin connection for shift clock: Establish a connection of input stage DX1 with the selected shift clock input pin (SCLKIN) with DX1CR.INSW = 1 and with inverted polarity (DX1CR.DPOL = 1). Pin connection for WA input: Establish a connection of input stage DX2 with the WA input pin (SELIN) with DX2CR.INSW = 1. Baud rate generation: The baud rate generator is not needed and can be switched off by the fractional divider. WA generation: The WA generation is not needed and can be switched off (PCR.WAGEN = 0). 14.6.4.1 Protocol Events and Interrupts The following protocol-related event is generated in IIS mode and can lead to a protocol interrupt. Please note that the bits in register PSR are not all automatically cleared by hardware and have to be cleared by software in order to monitor new incoming events. • • WA rising/falling/end events: The WA generation being switched off, these events are not available. DX2T event: An activation of the trigger signal DX2T is indicated by PSR.DX2TEV = 1 and can generate a protocol interrupt if PCR.DX2TIEN = 1. 14.6.5 IIS Protocol Registers In IIS mode, the registers PCR and PSR handle IIS related information. 14.6.5.1 IIS Protocol Control Registers In IIS mode, the PCR register bits or bit fields are defined as described in this section. Reference Manual USIC, V2.14 14-147 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) PCR Protocol Control Register [IIS Mode] (3CH) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 MCL K 0 TDEL rw rw rw 15 14 13 12 11 10 DX2 TIEN 0 rw rw 9 8 7 6 5 4 ENDI WAR WAF EN EIEN EIEN rw rw rw 3 0 rw 2 17 16 1 0 SELI DTE WAG NV N EN rw rw rw Field Bits Type Description WAGEN 0 rw WA Generation Enable This bit enables/disables the generation of word address control output signal WA. The IIS can be used as slave. The generation of the 0B word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK. The IIS can be used as master. The generation of 1B the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods. DTEN 1 rw Data Transfers Enable This bit enables/disables the transfer of IIS frames as a reaction to changes of the input word address control line WA. The changes of the WA input signal are ignored and 0B no transfers take place. Transfers are enabled. 1B Reference Manual USIC, V2.14 14-148 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SELINV 2 rw Select Inversion This bit defines if the polarity of the SELOx outputs in relation to the internally generated word address signal WA. The SELOx outputs have the same polarity as the 0B WA signal. The SELOx outputs have the inverted polarity to the 1B WA signal. WAFEIEN 4 rw WA Falling Edge Interrupt Enable This bit enables/disables the activation of a protocol interrupt when a falling edge of WA has been generated. A protocol interrupt is not activated if a falling edge 0B of WA is generated. A protocol interrupt is activated if a falling edge of 1B WA is generated. WAREIEN 5 rw WA Rising Edge Interrupt Enable This bit enables/disables the activation of a protocol interrupt when a rising edge of WA has been generated. A protocol interrupt is not activated if a rising edge 0B of WA is generated. 1B A protocol interrupt is activated if a rising edge of WA is generated. ENDIEN 6 rw END Interrupt Enable This bit enables/disables the activation of a protocol interrupt when the WA generation stops after clearing PCR.WAGEN (complete system word length is processed before stopping). A protocol interrupt is not activated. 0B 1B A protocol interrupt is activated. DX2TIEN 15 rw DX2T Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the DX2T signal becomes activated (indicated by PSR.DX2TEV = 1). A protocol interrupt is not generated if DX2T is 0B active. A protocol interrupt is generated if DX2T is active. 1B Reference Manual USIC, V2.14 14-149 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TDEL [21:16] rw Transfer Delay This bit field defines the transfer delay when an event is detected. If bit field TDEL = 0, the additional delay functionality is switched off and a delay of one shift clock cycle is introduced. MCLK 31 rw Master Clock Enable This bit enables generation of the master clock MCLK (not directly used for IIC protocol, can be used as general frequency output). The MCLK generation is disabled and MCLK is 0. 0B The MCLK generation is enabled. 1B 0 3, [14:7], [30:22] rw Reserved Returns 0 if read; should be written with 0; 14.6.5.2 IIS Protocol Status Register The following PSR status bits or bit fields are available in IIS mode. Please note that the bits in register PSR are not cleared by hardware. The flags in the PSR register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but does not lead to further actions (no interrupt generation). Writing a 0 has no effect. These flags should be cleared by software before enabling a new protocol. PSR Protocol Status Register [IIS Mode] 31 15 30 14 29 13 28 12 27 11 26 10 25 9 (48H) 24 Reset Value: 0000 0000H 23 22 21 20 19 r rwh 8 7 6 5 4 3 RIF TBIF TSIF DLIF RSIF 0 rwh rwh r rwh Reference Manual USIC, V2.14 rwh rwh 16 BRG IF AIF rwh 17 0 WAR WAF DX2 END E E TEV rwh 18 14-150 rwh rwh rwh 2 1 0 0 DX2 WA S r rwh rwh V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description WA 0 rwh Word Address This bit indicates the status of the WA input signal, sampled after a transition of WA has been detected. This information is forwarded to the corresponding bit position RBUFSR[9] to distinguish between data received for the right and the left channel. WA has been sampled 0. 0B WA has been sampled 1. 1B DX2S 1 rwh DX2S Status This bit indicates the current status of the DX2S signal, which is used as word address signal WA. 0B DX2S is 0. DX2S is 1. 1B DX2TEV 3 rwh DX2T Event Detected1) This bit indicates that the DX2T signal has been activated. In IIS slave mode, an activation of DX2T generates a protocol interrupt if PCR.DX2TIEN = 1. The DX2T signal has not been activated. 0B 1B The DX2T signal has been activated. WAFE 4 rwh WA Falling Edge Event1) This bit indicates that a falling edge of the WA output signal has been generated. This event generates a protocol interrupt if PCR.WAFEIEN = 1. A WA falling edge has not been generated. 0B 1B A WA falling edge has been generated. WARE 5 rwh WA Rising Edge Event1) This bit indicates that a rising edge of the WA output signal has been generated. This event generates a protocol interrupt if PCR.WAREIEN = 1. A WA rising edge has not been generated. 0B A WA rising edge has been generated. 1B Reference Manual USIC, V2.14 14-151 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description END 6 rwh WA Generation End1) This bit indicates that the WA generation has ended after clearing PCR.WAGEN. This bit should be cleared by software before clearing WAGEN. The WA generation has not yet ended (if it is 0B running and WAGEN has been cleared). The WA generation has ended (if it has been 1B running). RSIF 10 rwh Receiver Start Indication Flag 0B A receiver start event has not occurred. A receiver start event has occurred. 1B DLIF 11 rwh Data Lost Indication Flag 0B A data lost event has not occurred. 1B A data lost event has occurred. TSIF 12 rwh Transmit Shift Indication Flag 0B A transmit shift event has not occurred. 1B A transmit shift event has occurred. TBIF 13 rwh Transmit Buffer Indication Flag 0B A transmit buffer event has not occurred. A transmit buffer event has occurred. 1B RIF 14 rwh Receive Indication Flag 0B A receive event has not occurred. 1B A receive event has occurred. AIF 15 rwh Alternative Receive Indication Flag 0B An alternative receive event has not occurred. 1B An alternative receive event has occurred. BRGIF 16 rwh Baud Rate Generator Indication Flag 0B A baud rate generator event has not occurred. A baud rate generator event has occurred. 1B 0 2, [9:7], r [31:17] Reserved Returns 0 if read; not modified in IIS mode. 1) This status bit can generate a protocol interrupt (see Page 14-22). The general interrupt status flags are described in the general interrupt chapter. Reference Manual USIC, V2.14 14-152 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.7 Service Request Generation The USIC module provides 6 service request outputs SR[5:0] to be shared between two channels. The service request outputs SR[5:0] are connected to interrupt nodes in the Nested Vectored Interrupt Controller (NVIC). Each USIC communication channel can be connected to up to 6 service request handlers (connected to USICx.SR[5:0], though 3 or 4 are normally used, e.g. one for transmission, one for reception, one or two for protocol or error handling, or for the alternative receive events). 14.8 Debug Behaviour Each USIC communication channel can be pre-configured to enter one of four kernel modes, when the program execution of the CPU is halted by the debugger. Refer to Section 14.2.2.2 for details. 14.9 Power, Reset and Clock The USIC module is located in the core power domain. The module can be reset to its default state by a system reset. The USIC module is clocked by the main clock, MCLK, from SCU. MCLK is disabled by default and can be enabled via the SCU_CGATCLR0 register. Enabling and disabling the module clock could cause a load change and clock blanking could occur as described in the CCU (Clock Gating Control) section of the SCU chapter. It is strongly recommended to set up the module clock in the user initialization code to avoid clock blanking during runtime. Note: To differentiate from the USIC baud rate generator output, master clock (MCLK), the SCU MCLK is referenced throughout the USIC chapter as fPERIPH. 14.10 Initialization and System Dependencies The application has to apply the following initialization sequence before operating the USIC module: • Enable the module by writing 1s to the MODEN and BPMODEN bits in KSCFG register. 14.11 Registers Table 14-20 shows all registers which are required for programming a USIC channel, as well as the FIFO buffer. It summarizes the USIC communication channel registers and defines the relative addresses and the reset values. Please note that all registers can be accessed with any access width (8-bit, 16-bit, 32bit), independent of the described width. Reference Manual USIC, V2.14 14-153 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) All USIC registers (except bit field KSCFG.SUMCFG) are always reset by a system reset. Bit field KSCFG.SUMCFG is reset by a debug reset. Note: The register bits marked “w” always deliver 0 when read. They are used to modify flip-flops in other registers or to trigger internal actions. Figure 14-65 shows the register types of the USIC module registers and channel registers. In a specific microcontroller, module registers of USIC module “x” are marked by the module prefix “USICx_”. Channel registers of USIC module “x” are marked by the channel prefix “USICx_CH0_” and “USICx_CH1_”. USICx Module Channel 0 Registers Channel 1 Registers FIFO Buffer Registers FIFO Buffer Registers Channel Registers Channel Registers Module Registers Figure 14-65 USIC Module and Channel Registers Table 14-20 USIC Kernel-Related and Kernel Registers Register Register Long Name Short Name Offset Addr. Access Mode Description Read Write see 008H U, PV U, PV Page 14-158 reserved 000H BE Module Registers1) ID Module Identification Register Channel Registers – BE – CCFG Channel Configuration Register 004H U, PV U, PV Page 14-163 KSCFG Kernel State Configuration Register 00CH U, PV U, PV Page 14-164 FDR Fractional Divider Register 010H U, PV PV Reference Manual USIC, V2.14 14-154 Page 14-177 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-20 USIC Kernel-Related and Kernel Registers (cont’d) Register Register Long Name Short Name Offset Addr. Access Mode Description Read Write see Page 14-178 BRG Baud Rate Generator Register 014H U, PV PV INPR Interrupt Node Pointer Register 018H U, PV U, PV Page 14-167 DX0CR Input Control Register 0 01CH U, PV U, PV Page 14-172 DX1CR Input Control Register 1 020H U, PV U, PV Page 14-174 DX2CR Input Control Register 2 024H U, PV U, PV Page 14-172 DX3CR Input Control Register 3 028H U, PV U, PV DX4CR Input Control Register 4 02CH U, PV U, PV DX5CR Input Control Register 5 030H U, PV U, PV SCTR Shift Control Register 034H U, PV U, PV Page 14-182 TCSR Transmit Control/Status Register 038H U, PV U, PV Page 14-185 PCR Protocol Control Register 03CH U, PV U, PV Page 14-168 2) U, PV U, PV Page 14-663) U, PV U, PV Page 14-984) U, PV U, PV Page 14-129 5) U, PV U, PV Page 14-148 6) CCR Page 14-159 Channel Control Register 040H U, PV PV CMTR Capture Mode Timer Register 044H U, PV U, PV Page 14-181 PSR Protocol Status Register 048H U, PV U, PV Page 14-169 2) U, PV U, PV Page 14-703) U, PV U, PV Page 14-102 4) U, PV U, PV Page 14-132 5) U, PV U, PV Page 14-150 6) PSCR Protocol Status Clear Register Reference Manual USIC, V2.14 04CH 14-155 U, PV U, PV Page 14-170 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-20 USIC Kernel-Related and Kernel Registers (cont’d) Register Register Long Name Short Name Offset Addr. Access Mode Description Read Write see RBUFSR Receiver Buffer Status Register 050H U, PV U, PV Page 14-203 RBUF Receiver Buffer Register 054H U, PV U, PV Page 14-201 RBUFD Receiver Buffer Register for Debugger 058H U, PV U, PV Page 14-202 RBUF0 Receiver Buffer Register 0 05CH U, PV U, PV Page 14-194 RBUF1 Receiver Buffer Register 1 060H U, PV U, PV Page 14-195 RBUF01SR Receiver Buffer 01 Status Register 064H U, PV U, PV Page 14-196 FMR Flag Modification Register 068H U, PV U, PV Page 14-192 – reserved; do not access this location 06CH U, PV BE – – reserved 070H 07CH BE – TBUFx Transmit Buffer Input Location x 080H + U, PV U, PV Page 14-194 (x = 00-31) x*4 BE FIFO Buffer Registers BYP Bypass Data Register 100H U, PV U, PV Page 14-204 BYPCR Bypass Control Register 104H U, PV U, PV Page 14-205 TBCTR Transmit Buffer Control Register 108H U, PV U, PV Page 14-213 RBCTR Receive Buffer Control Register 10CH U, PV U, PV Page 14-217 TRBPTR Transmit/Receive Buffer Pointer 110H Register U, PV U, PV Page 14-225 TRBSR Transmit/Receive Buffer Status Register 114H U, PV U, PV Page 14-208 TRBSCR Transmit/Receive Buffer Status Clear Register 118H U, PV U, PV Page 14-212 OUTR Receive Buffer Output Register 11CH U, PV U, PV Page 14-223 OUTDR Receive Buffer Output Register for Debugger 120H U, PV U, PV Page 14-224 Reference Manual USIC, V2.14 14-156 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-20 USIC Kernel-Related and Kernel Registers (cont’d) Register Register Long Name Short Name Offset Addr. Access Mode Description Read Write see – reserved 124H 17CH BE INx Transmit FIFO Buffer Input Location x (x = 00-31) 180H + U, PV U, PV Page 14-222 x*4 BE – 1) Details of the module identification registers are described in the implementation section (see Page 14-158). 2) This page shows the general register layout. 3) This page shows the register layout in ASC mode. 4) This page shows the register layout in SSC mode. 5) This page shows the register layout in IIC mode. 6) This page shows the register layout in IIS mode. 14.11.1 Address Map The registers of the USIC communication channel are available at the following base addresses. The exact register address is given by the relative address of the register (given in Table 14-20) plus the channel base address (given in Table 14-21). Table 14-21 Registers Address Space Module Base Address End Address Note USIC0_CH0 48000000H 480001FFH – USIC0_CH1 48000200H 480003FFH – Table 14-22 FIFO and Reserved Address Space Module USIC0 Base Address End Address Access Mode Read Write 48000400H 480007FFH nBE reserved 48000800H 4800FFFFH BE 14.11.2 Note nBE if in direct RAM test mode; otherwise BE USIC0 RAM area, shared between USIC0_CH0 and USIC0_CH1 BE – Module Identification Registers The module identification registers indicate the function and the design step of the USIC modules. Reference Manual USIC, V2.14 14-157 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) USIC0_ID Module Identification Register (4800 0008H) 31 30 29 28 27 26 25 24 23 Reset Value: 00AA C0XXH 22 21 20 19 18 17 16 5 4 3 2 1 0 MOD_NUMBER r 15 14 13 12 11 10 9 8 7 6 MOD_TYPE MOD_REV r r Field Bits Type Description MOD_REV [7:0] r Module Revision Number MOD_REV defines the revision number. The value of a module revision starts with 01H (first revision). MOD_TYPE [15:8] r Module Type This bit field is C0H. It defines the module as a 32-bit module. MOD_NUMBE R [31:16] r Module Number Value This bit field defines the USIC module identification number (00AAH = USIC). 14.11.3 Channel Control and Configuration Registers 14.11.3.1 Channel Control Register The channel control register contains the enable/disable bits for hardware port control and interrupt generation on channel events, the control of the parity generation and the protocol selection of a USIC channel. FDR can be written only with a privilege mode access. Reference Manual USIC, V2.14 14-158 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) CCR Channel Control Register 31 15 30 14 AIEN RIEN rw rw 29 13 28 12 27 (40H) 26 11 10 TBIE TSIE DLIE RSIE N N N N rw rw rw rw 25 24 9 23 22 21 20 19 18 17 16 0 BRG IEN r rw 8 7 6 5 4 3 2 1 PM HPCEN 0 MODE rw rw r rw Field Bits Type Description MODE [3:0] rw Reference Manual USIC, V2.14 Reset Value: 0000 0000H 0 Operating Mode This bit field selects the protocol for this USIC channel. Selecting a protocol that is not available (see register CCFG) or a reserved combination disables the USIC channel. When switching between two protocols, the USIC channel has to be disabled before selecting a new protocol. In this case, registers PCR and PSR have to be cleared or updated by software. The USIC channel is disabled. All protocol0H related state machines are set to an idle state. The SSC (SPI) protocol is selected. 1H 2H The ASC (SCI, UART) protocol is selected. The IIS protocol is selected. 3H 4H The IIC protocol is selected. Other bit combinations are reserved. 14-159 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description HPCEN [7:6] rw Hardware Port Control Enable This bit enables the hardware port control for the specified set of DX[3:0] and DOUT[3:0] pins. 00B The hardware port control is disabled. 01B The hardware port control is enabled for DX0 and DOUT0. 10B The hardware port control is enabled for DX3, DX0 and DOUT[1:0]. 11B The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0]. Note: The hardware port control feature is useful only for SSC protocols in half-duplex configurations, such as dual- and quad-SSC. For all other protocols HPCEN must always be written with 00B. PM [9:8] rw Parity Mode This bit field defines the parity generation of the sampled input values. 00B The parity generation is disabled. 01B Reserved 10B Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data). 11B Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data). RSIEN 10 rw Receiver Start Interrupt Enable This bit enables the interrupt generation in case of a receiver start event. 0B The receiver start interrupt is disabled. The receiver start interrupt is enabled. 1B In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated. Reference Manual USIC, V2.14 14-160 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DLIEN 11 rw Data Lost Interrupt Enable This bit enables the interrupt generation in case of a data lost event (data received in RBUFx while RDVx = 1). The data lost interrupt is disabled. 0B The data lost interrupt is enabled. In case of a 1B data lost event, the service request output SRx indicated by INPR.PINP is activated. TSIEN 12 rw Transmit Shift Interrupt Enable This bit enables the interrupt generation in case of a transmit shift event. The transmit shift interrupt is disabled. 0B 1B The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated. TBIEN 13 rw Transmit Buffer Interrupt Enable This bit enables the interrupt generation in case of a transmit buffer event. The transmit buffer interrupt is disabled. 0B 1B The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated. RIEN 14 rw Receive Interrupt Enable This bit enables the interrupt generation in case of a receive event. The receive interrupt is disabled. 0B 1B The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated. AIEN 15 rw Alternative Receive Interrupt Enable This bit enables the interrupt generation in case of a alternative receive event. The alternative receive interrupt is disabled. 0B The alternative receive interrupt is enabled. In 1B case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated. Reference Manual USIC, V2.14 14-161 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description BRGIEN 16 rw Baud Rate Generator Interrupt Enable This bit enables the interrupt generation in case of a baud rate generator event. The baud rate generator interrupt is disabled. 0B 1B The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated. 0 [5:4], [31:17] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-162 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.3.2 Channel Configuration Register The channel configuration register contains indicates the functionality that is available in the USIC channel. CCFG Channel Configuration Register 31 30 29 28 27 26 (04H) 25 24 Reset Value: 0000 80CFH 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 1 0 TB RB 0 IIS IIC r r r r r r r ASC SSC r r Field Bits Type Description SSC 0 r SSC Protocol Available This bit indicates if the SSC protocol is available. 0B The SSC protocol is not available. 1B The SSC protocol is available. ASC 1 r ASC Protocol Available This bit indicates if the ASC protocol is available. The ASC protocol is not available. 0B 1B The ASC protocol is available. IIC 2 r IIC Protocol Available This bit indicates if the IIC functionality is available. 0B The IIC protocol is not available. The IIC protocol is available. 1B IIS 3 r IIS Protocol Available This bit indicates if the IIS protocol is available. 0B The IIS protocol is not available. 1B The IIS protocol is available. RB 6 r Receive FIFO Buffer Available This bit indicates if an additional receive FIFO buffer is available. A receive FIFO buffer is not available. 0B A receive FIFO buffer is available. 1B Reference Manual USIC, V2.14 14-163 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TB 7 r Transmit FIFO Buffer Available This bit indicates if an additional transmit FIFO buffer is available. A transmit FIFO buffer is not available. 0B 1B A transmit FIFO buffer is available. 1 15 r Reserved Read as 1; should be written with 1. 0 [5:4], [14:8], [31:16] r Reserved Read as 0; should be written with 0. 14.11.3.3 Kernel State Configuration Register The kernel state configuration register KSCFG allows the selection of the desired kernel modes for the different device operating modes. KSCFG Kernel State Configuration Register 31 30 29 28 27 26 25 (0CH) 24 Reset Value: 0000 0000H 23 22 21 20 19 18 7 6 5 4 3 2 17 16 1 0 0 r 15 14 13 12 11 10 9 8 0 BPS UM 0 SUMCFG BPN OM 0 NOMCFG 0 r w r rw w r rw r Reference Manual USIC, V2.14 14-164 BPM MOD ODE EN N w rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description MODEN 0 rw Module Enable This bit enables the module kernel clock and the module functionality. 0B The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG). The module is switched on and can operate. 1B After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other USIC registers. BPMODEN 1 w Bit Protection for MODEN This bit enables the write access to the bit MODEN. It always reads 0. 0B MODEN is not changed. MODEN is updated with the written value. 1B NOMCFG [5:4] rw Normal Operation Mode Configuration This bit field defines the kernel mode applied in normal operation mode. 00B Run mode 0 is selected. 01B Run mode 1 is selected. 10B Stop mode 0 is selected. 11B Stop mode 1 is selected. BPNOM 7 w Bit Protection for NOMCFG This bit enables the write access to the bit field NOMCFG. It always reads 0. NOMCFG is not changed. 0B 1B NOMCFG is updated with the written value. SUMCFG [9:8] rw Suspend Mode Configuration This bit field defines the kernel mode applied in suspend mode. Coding like NOMCFG. Reference Manual USIC, V2.14 14-165 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description BPSUM 11 w 0 [3:2], 6, r 10, [31:12] Reference Manual USIC, V2.14 Bit Protection for SUMCFG This bit enables the write access to the bit field SUMCFG. It always reads 0. SUMCFG is not changed. 0B 1B SUMCFG is updated with the written value. Reserved Read as 0; should be written with 0. Bit 2 can read as 1 after BootROM exit (but can be ignored). 14-166 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.3.4 Interrupt Node Pointer Register The interrupt node pointer register defines the service request output SRx that is activated if the corresponding event occurs and interrupt generation is enabled. INPR Interrupt Node Pointer Register 31 15 30 14 29 13 28 12 27 26 11 10 (18H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 0 PINP r rw 9 8 7 6 5 4 3 2 1 0 AINP 0 RINP 0 TBINP 0 TSINP r rw r rw r rw r rw Field Bits Type Description TSINP [2:0] rw 16 0 Transmit Shift Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a transmit shift interrupt. 000B Output SR0 becomes activated. 001B Output SR1 becomes activated. 010B Output SR2 becomes activated. 011B Output SR3 becomes activated. 100B Output SR4 becomes activated. 101B Output SR5 becomes activated. Note: All other settings of the bit field are reserved. TBINP [6:4] rw Transmit Buffer Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a transmit buffer interrupt or a receive start interrupt. Coding like TSINP. RINP [10:8] rw Receive Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a receive interrupt. Coding like TSINP. Reference Manual USIC, V2.14 14-167 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description AINP [14:12] rw Alternative Receive Interrupt Node Pointer This bit field defines which service request output SRx will be activated in case of a alternative receive interrupt. Coding like TSINP. PINP [18:16] rw Protocol Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a protocol interrupt. Coding like TSINP. 0 3, 7, 11, r 15, [31:19] 14.11.4 Reserved Read as 0; should be written with 0. Protocol Related Registers 14.11.4.1 Protocol Control Registers The bits in the protocol control register define protocol-specific functions. They have to be configured by software before enabling a new protocol. Only the bits used for the selected protocol are taken into account, whereas the other bit positions always read as 0. The protocol-specific meaning is described in the related protocol section. PCR Protocol Control Register 31 30 29 28 27 (3CH) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR CTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw Field Bits Type Description CTRx (x = 0-31) x rw Reference Manual USIC, V2.14 rw rw rw rw rw rw rw Protocol Control Bit x This bit is a protocol control bit. 14-168 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.4.2 Protocol Status Register The flags in the protocol status register can be cleared by writing a 1 to the corresponding bit position in register PSCR. Writing a 1 to a bit position in PSR sets the corresponding flag, but does not lead to further actions (no interrupt generation). Writing a 0 has no effect. These flags should be cleared by software before enabling a new protocol. The protocol-specific meaning is described in the related protocol section. PSR Protocol Status Register 31 30 29 28 13 23 22 21 20 19 18 17 16 0 BRG IF r rwh RIF TBIF TSIF DLIF RSIF ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 rwh rwh rwh 9 24 AIF rwh 10 25 14 rwh 11 26 Reset Value: 0000 0000H 15 rwh 12 27 (48H) rwh 8 rwh 7 rwh 6 rwh 5 rwh 4 rwh 3 rwh 2 1 rwh rwh Field Bits Type Description STx (x = 0-9) x rwh Protocol Status Flag x See protocol specific description. RSIF 10 rwh Receiver Start Indication Flag 0B A receiver start event has not occurred. 1B A receiver start event has occurred. DLIF 11 rwh Data Lost Indication Flag 0B A data lost event has not occurred. 1B A data lost event has occurred. TSIF 12 rwh Transmit Shift Indication Flag 0B A transmit shift event has not occurred. A transmit shift event has occurred. 1B TBIF 13 rwh Transmit Buffer Indication Flag 0B A transmit buffer event has not occurred. 1B A transmit buffer event has occurred. RIF 14 rwh Receive Indication Flag 0B A receive event has not occurred. A receive event has occurred. 1B Reference Manual USIC, V2.14 14-169 0 rwh V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description AIF 15 rwh Alternative Receive Indication Flag 0B An alternative receive event has not occurred. An alternative receive event has occurred. 1B BRGIF 16 rwh Baud Rate Generator Indication Flag 0B A baud rate generator event has not occurred. 1B A baud rate generator event has occurred. 0 [31:17] r Reserved; read as 0; should be written with 0; 14.11.4.3 Protocol Status Clear Register Read accesses to this register always deliver 0 at all bit positions. PSCR Protocol Status Clear Register 31 15 30 14 29 28 13 12 27 26 11 10 (4CH) 25 9 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 0 CBR GIF r w 8 7 6 5 4 3 2 1 0 CTBI CTSI CDLI CRSI CST CST CST CST CST CST CST CST CST CST CAIF CRIF F F F F 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w Field Bits Type Description CSTx (x = 0-9) x w Clear Status Flag x in PSR 0B No action Flag PSR.STx is cleared. 1B CRSIF 10 w Clear Receiver Start Indication Flag 0B No action 1B Flag PSR.RSIF is cleared. CDLIF 11 w Clear Data Lost Indication Flag 0B No action 1B Flag PSR.DLIF is cleared. Reference Manual USIC, V2.14 14-170 w w w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description CTSIF 12 w Clear Transmit Shift Indication Flag 0B No action Flag PSR.TSIF is cleared. 1B CTBIF 13 w Clear Transmit Buffer Indication Flag 0B No action 1B Flag PSR.TBIF is cleared. CRIF 14 w Clear Receive Indication Flag 0B No action 1B Flag PSR.RIF is cleared. CAIF 15 w Clear Alternative Receive Indication Flag 0B No action Flag PSR.AIF is cleared. 1B CBRGIF 16 w Clear Baud Rate Generator Indication Flag 0B No action 1B Flag PSR.BRGIF is cleared. 0 [31:17] r Reserved; read as 0; should be written with 0; 14.11.5 Input Stage Register 14.11.5.1 Input Control Registers The input control registers contain the bits to define the characteristics of the input stages (input stage DX0 is controlled by register DX0CR, etc.). Reference Manual USIC, V2.14 14-171 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) DX0CR Input Control Register 0 DX2CR Input Control Register 2 DX3CR Input Control Register 3 DX4CR Input Control Register 4 DX5CR Input Control Register 5 31 30 29 28 27 26 25 (1CH) Reset Value: 0000 0000H (24H) Reset Value: 0000 0000H (28H) Reset Value: 0000 0000H (2CH) Reset Value: 0000 0000H (30H) Reset Value: 0000 0000H 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 DXS 0 CM rh r rw 9 8 SFS DPO EL L rw rw Field Bits Type Description DSEL [2:0] rw Reference Manual USIC, V2.14 0 r DSE DFE INS N N W rw rw rw 0 DSEL r rw Data Selection for Input Signal This bit field defines the input data signal for the corresponding input line for protocol pre-processor. The selection can be made from the input vector DXn[G:A]. 000B The data input DXnA is selected. 001B The data input DXnB is selected. 010B The data input DXnC is selected. 011B The data input DXnD is selected. 100B The data input DXnE is selected. 101B The data input DXnF is selected. 110B The data input DXnG is selected. 111B The data input is always 1. 14-172 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description INSW 4 rw Input Switch This bit defines if the data shift unit input is derived from the input data path DXn or from the selected protocol pre-processors. The input of the data shift unit is controlled by the 0B protocol pre-processor. The input of the data shift unit is connected to 1B the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol preprocessor. DFEN 5 rw Digital Filter Enable This bit enables/disables the digital filter for signal DXnS. The input signal is not digitally filtered. 0B 1B The input signal is digitally filtered. DSEN 6 rw Data Synchronization Enable This bit selects if the asynchronous input signal or the synchronized (and optionally filtered) signal DXnS can be used as input for the data shift unit. The un-synchronized signal can be taken as 0B input for the data shift unit. The synchronized signal can be taken as input 1B for the data shift unit. DPOL 8 rw Data Polarity for DXn This bit defines the signal polarity of the input signal. The input signal is not inverted. 0B 1B The input signal is inverted. SFSEL 9 rw Sampling Frequency Selection This bit defines the sampling frequency of the digital filter for the synchronized signal DXnS. The sampling frequency is fPERIPH. 0B The sampling frequency is fFD. 1B Reference Manual USIC, V2.14 14-173 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits CM [11:10] rw Type Description Combination Mode This bit field selects which edge of the synchronized (and optionally filtered) signal DXnS actives the trigger output DXnT of the input stage. 00B The trigger activation is disabled. 01B A rising edge activates DXnT. 10B A falling edge activates DXnT. 11B Both edges activate DXnT. DXS 15 Synchronized Data Value This bit indicates the value of the synchronized (and optionally filtered) input signal. The current value of DXnS is 0. 0B 1B The current value of DXnS is 1. 0 3, 7, r [14:12] , [31:16] rh Reserved Read as 0; should be written with 0. DX1CR Input Control Register 1 31 30 29 28 (20H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 DXS 0 CM rh r rw Reference Manual USIC, V2.14 9 8 SFS DPO EL L rw rw 0 r 14-174 DSE DFE INS DCE N N W N rw rw rw rw DSEL rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DSEL [2:0] rw Data Selection for Input Signal This bit field defines the input data signal for the corresponding input line for protocol pre-processor. The selection can be made from the input vector DX1[G:A]. 000B The data input DX1A is selected. 001B The data input DX1B is selected. 010B The data input DX1C is selected. 011B The data input DX1D is selected. 100B The data input DX1E is selected. 101B The data input DX1F is selected. 110B The data input DX1G is selected. 111B The data input is always 1. DCEN 3 rw Delay Compensation Enable This bit selects if the receive shift clock is controlled by INSW or derived from the input data path DX1. The receive shift clock is dependent on INSW 0B selection. The receive shift clock is connected to the 1B selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. INSW 4 rw Input Switch This bit defines if the data shift unit input is derived from the input data path DX1 or from the selected protocol pre-processors. The input of the data shift unit is controlled by the 0B protocol pre-processor. 1B The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol preprocessor. DFEN 5 rw Digital Filter Enable This bit enables/disables the digital filter for signal DX1S. The input signal is not digitally filtered. 0B The input signal is digitally filtered. 1B Reference Manual USIC, V2.14 14-175 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DSEN 6 rw Data Synchronization Enable This bit selects if the asynchronous input signal or the synchronized (and optionally filtered) signal DX1S can be used as input for the data shift unit. The un-synchronized signal can be taken as 0B input for the data shift unit. The synchronized signal can be taken as input 1B for the data shift unit. DPOL 8 rw Data Polarity for DXn This bit defines the signal polarity of the input signal. The input signal is not inverted. 0B 1B The input signal is inverted. SFSEL 9 rw Sampling Frequency Selection This bit defines the sampling frequency of the digital filter for the synchronized signal DX1S. The sampling frequency is fPERIPH. 0B 1B The sampling frequency is fFD. CM [11:10] rw Combination Mode This bit field selects which edge of the synchronized (and optionally filtered) signal DX1S actives the trigger output DX1T of the input stage. 00B The trigger activation is disabled. 01B A rising edge activates DX1T. 10B A falling edge activates DX1T. 11B Both edges activate DX1T. DXS 15 Synchronized Data Value This bit indicates the value of the synchronized (and optionally filtered) input signal. The current value of DX1S is 0. 0B 1B The current value of DX1S is 1. 0 7, r [14:12] , [31:16] Reference Manual USIC, V2.14 rh Reserved Read as 0; should be written with 0. 14-176 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.6 Baud Rate Generator Registers 14.11.6.1 Fractional Divider Register The fractional divider register FDR allows the generation of the internal frequency fFD, that is derived from the system clock fPERIPH. FDR can be written only with a privilege mode access. FDR Fractional Divider Register 31 30 29 28 27 (10H) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 0 0 RESULT rw r rh 15 14 13 12 11 10 9 8 7 6 5 4 DM 0 STEP rw r rw 19 18 17 16 3 2 1 0 Field Bits Type Description STEP [9:0] rw Step Value In normal divider mode STEP contains the reload value for RESULT after RESULT has reached 3FFH. In fractional divider mode STEP defines the value added to RESULT with each input clock cycle. DM [15:14] rw Divider Mode This bit fields defines the functionality of the fractional divider block. 00B The divider is switched off, fFD = 0. 01B Normal divider mode selected. 10B Fractional divider mode selected. 11B The divider is switched off, fFD = 0. Reference Manual USIC, V2.14 14-177 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RESULT [25:16] rh Result Value In normal divider mode this bit field is updated with fPERIPH according to: RESULT = RESULT + 1 In fractional divider mode this bit field is updated with fPERIPH according to: RESULT = RESULT + STEP If bit field DM is written with 01B or 10B, RESULT is loaded with a start value of 3FFH. 0 [31:30] rw Reserved for Future Use Must be written with 0 to allow correct fractional divider operation. 0 [13:10], r [29:26] Reserved Read as 0; should be written with 0. 14.11.6.2 Baud Rate Generator Register The protocol-related counters for baud rate generation and timing measurement are controlled by the register BRG. FDR can be written only with a privilege mode access. BRG Baud Rate Generator Register 31 30 29 28 27 MCL SCL SCLKCFG KCF KOS G EL rw rw rw 15 14 13 12 11 26 (14H) 25 24 Reset Value: 0000 0000H 23 22 21 0 PDIV r rw 10 9 8 7 6 5 0 DCTQ PCTQ CTQSEL 0 r rw rw rw r Reference Manual USIC, V2.14 20 14-178 4 19 18 17 16 3 2 1 0 PPP TME EN N rw rw 0 CLKSEL r rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description CLKSEL [1:0] rw Clock Selection This bit field defines the input frequency fPIN 00B The fractional divider frequency fFD is selected. 01B Reserved, no action 10B The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. 11B Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. TMEN 3 rw Timing Measurement Enable This bit enables the timing measurement of the capture mode timer. Timing measurement is disabled: 0B The trigger signals DX0T and DX1T are ignored. Timing measurement is enabled: 1B The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. PPPEN 4 rw Enable 2:1 Divider for fPPP This bit defines the input frequency fPPP. 0B The 2:1 divider for fPPP is disabled. fPPP = fPIN 1B The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. CTQSEL [7:6] rw Input Selection for CTQ This bit defines the length of a time quantum for the protocol pre-processor. 00B fCTQIN = fPDIV 01B fCTQIN = fPPP 10B fCTQIN = fSCLK 11B fCTQIN = fMCLK Reference Manual USIC, V2.14 14-179 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description PCTQ [9:8] rw Pre-Divider for Time Quanta Counter This bit field defines length of a time quantum tq for the time quanta counter in the protocol pre-processor. tQ = (PCTQ + 1) / fCTQIN DCTQ [14:10] rw Denominator for Time Quanta Counter This bit field defines the number of time quanta tq taken into account by the time quanta counter in the protocol pre-processor. PDIV [25:16] rw Divider Mode: Divider Factor to Generate fPDIV This bit field defines the ratio between the input frequency fPPP and the divider frequency fPDIV. SCLKOSEL 28 rw Shift Clock Output Select This bit field selects the input source for the SCLKOUT signal. SCLK from the baud rate generator is selected 0B as the SCLKOUT input source. 1B The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. Note: The setting SCLKOSEL = 1 is used only when complete closed loop delay compensation is required for a slave SSC/IIS. The default setting of SCLKOSEL = 0 should be always used for all other cases. MCLKCFG 29 rw Master Clock Configuration This bit field defines the level of the passive phase of the MCLKOUT signal. The passive level is 0. 0B 1B The passive level is 1. SCLKCFG [31:30] rw Shift Clock Output Configuration This bit field defines the level of the passive phase of the SCLKOUT signal and enables/disables a delay of half of a SCLK period. 00B The passive level is 0 and the delay is disabled. 01B The passive level is 1 and the delay is disabled. 10B The passive level is 0 and the delay is enabled. 11B The passive level is 1 and the delay is enabled. 0 2, 5, 15, r [27:26] Reference Manual USIC, V2.14 Reserved Read as 0; should be written with 0. 14-180 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.6.3 Capture Mode Timer Register The captured timer value is provided by the register CMTR. CMTR Capture Mode Timer Register 31 30 29 28 27 26 (44H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 CTV r rwh Field Bits Type Description CTV [9:0] rwh Captured Timer Value The value of the counter is captured into this bit field if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage. 0 [31:10] r Reserved Read as 0; should be written with 0. 14.11.7 Transfer Control and Status Registers 14.11.7.1 Shift Control Register The data shift unit is controlled by the register SCTR. The values in this register are applied for data transmission and reception. Please note that the shift control settings SDIR, WLE, FLE, DSM and HPCDIR are shared between transmitter and receiver. They are internally “frozen” for a each data word transfer in the transmitter with the first transmit shift clock edge and with the first receive shift clock edge in the receiver. The software has to take care that updates of these bit fields by software are done coherently (e.g. refer to the receiver start event indication PSR.RSIF). Reference Manual USIC, V2.14 14-181 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) SCTR Shift Control Register 31 15 30 14 29 28 (34H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 0 WLE 0 FLE r rwh r rwh 13 12 11 10 9 8 7 6 5 4 3 2 0 TRM DOCFG 0 HPC DIR DSM r rw rw r rw rw 17 16 1 0 PDL SDIR rw rw Field Bits Type Description SDIR 0 rw Shift Direction This bit defines the shift direction of the data words for transmission and reception. 0B Shift LSB first. The first data bit of a data word is located at bit position 0. Shift MSB first. The first data bit of a data word 1B is located at the bit position given by bit field SCTR.WLE. PDL 1 rw Passive Data Level This bit defines the output level at the shift data output signal when no data is available for transmission. The PDL level is output with the first relevant transmit shift clock edge of a data word. The passive data level is 0. 0B 1B The passive data level is 1. Reference Manual USIC, V2.14 14-182 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DSM [3:2] rw Data Shift Mode This bit field describes how the receive and transmit data is shifted in and out. 00B Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0. 01B Reserved. 10B Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively. 11B Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively. Note: Dual- and Quad-output modes are used only by the SSC protocol. For all other protocols DSM must always be written with 00B. HPCDIR 4 rw Port Control Direction This bit defines the direction of the port pin(s) which allows hardware pin control (CCR.PCEN = 1). 0B The pin(s) with hardware pin control enabled are selected to be in input mode. The pin(s) with hardware pin control enabled 1B are selected to be in output mode. DOCFG [7:6] rw Data Output Configuration This bit defines the relation between the internal shift data value and the data output signal DOUTx. X0B DOUTx = shift data value X1B DOUTx = inverted shift data value Reference Manual USIC, V2.14 14-183 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TRM [9:8] rw Transmission Mode This bit field describes how the shift control signal is interpreted by the DSU. Data transfers are only possible while the shift control signal is active. 00B The shift control signal is considered as inactive and data frame transfers are not possible. 01B The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers. 10B The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal. 11B The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal. FLE [21:16] rwh Frame Length This bit field defines how many bits are transferred within a data frame. A data frame can consist of several concatenated data words. If TCSR.FLEMD = 1, the value can be updated automatically by the data handler. WLE [27:24] rwh Word Length This bit field defines the data word length (amount of bits that are transferred in each data word) for reception and transmission. The data word is always right-aligned in the data buffer at the bit positions [WLE down to 0]. If TCSR.WLEMD = 1, the value can be updated automatically by the data handler. The data word contains 1 data bit located at bit 0H position 0. The data word contains 2 data bits located at bit 1H positions [1:0]. ... The data word contains 15 data bits located at EH bit positions [14:0]. The data word contains 16 data bits located at FH bit positions [15:0]. Reference Manual USIC, V2.14 14-184 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description 0 5, [15:10], [23:22], [31:28] r Reserved Read as 0; should be written with 0. 14.11.7.2 Transmission Control and Status Register The data transmission is controlled and monitored by register TCSR. TCSR Transmit Control/Status Register 31 30 15 Reset Value: 0000 0000H 28 27 26 25 24 0 TE TVC TV 0 TSO F 0 r rh rh rh r rh r 12 11 10 9 14 29 (38H) 13 0 TDV WA TR r rwh rw TDEN 0 rw r 8 23 7 6 21 5 20 4 19 18 17 16 3 2 1 0 TDS HPC WA FLE SEL WLE TDV EOF SOF SM MD MD MD MD MD rw rh Field Bits Type Description WLEMD 0 rw Reference Manual USIC, V2.14 22 rwh rwh rw rw rw rw rw WLE Mode This bit enables the data handler to automatically update the bit field SCTR.WLE by the transmit control information TCI[3:0] and bit TCSR.EOF by TCI[4] (see Page 14-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of SCTR.WLE and 0B TCSR.EOF is disabled. 1B The automatic update of SCTR.WLE and TCSR.EOF is enabled. 14-185 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SELMD 1 rw Select Mode This bit can be used mainly for the SSC protocol. It enables the data handler to automatically update bit field PCR.CTR[20:16] by the transmit control information TCI[4:0] and clear bit field PCR.CTR[23:21] (see Page 14-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of PCR.CTR[23:16] is 0B disabled. The automatic update of PCR.CTR[23:16] is 1B disabled. FLEMD 2 rw FLE Mode This bit enables the data handler to automatically update bits SCTR.FLE[4:0] by the transmit control information TCI[4:0] and to clear bit SCTR.FLE[5] (see Page 14-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of FLE is disabled. 0B 1B The automatic update of FLE is enabled. WAMD 3 rw WA Mode This bit can be used mainly for the IIS protocol. It enables the data handler to automatically update bit TCSR.WA by the transmit control information TCI[4] (see Page 14-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of bit WA is disabled. 0B The automatic update of bit WA is enabled. 1B Reference Manual USIC, V2.14 14-186 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description HPCMD 4 rw Hardware Port Control Mode This bit can be used mainly for the dual and quad SSC protocol. It enables the data handler to automatically update bit SCTR.DSM by the transmit control information TCI[1:0] and bit SCTR.HPCDIR by TCI[2] (see Page 14-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer input locations TBUFx or by an optional data buffer. The automatic update of bits SCTR.DSM and 0B SCTR.HPCDIR is disabled. The automatic update of bits SCTR.DSM and 1B SCTR.HPCDIR is enabled. SOF 5 rwh Start Of Frame This bit is only taken into account for the SSC protocol, otherwise it is ignored. It indicates that the data word in TBUF is considered as the first word of a new SSC frame if it is valid for transmission (TCSR.TDV = 1). This bit becomes cleared when the TBUF data word is transferred to the transmit shift register. The data word in TBUF is not considered as 0B first word of a frame. 1B The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays). Reference Manual USIC, V2.14 14-187 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description EOF 6 rwh End Of Frame This bit is only taken into account for the SSC protocol, otherwise it is ignored. It can be modified automatically by the data handler if bit WLEMD = 1. It indicates that the data word in TBUF is considered as the last word of an SSC frame. If it is the last word, the MSLS signal becomes inactive after the transfer, respecting the programmed delays. This bit becomes cleared when the TBUF data word is transferred to the transmit shift register. The data word in TBUF is not considered as 0B last word of an SSC frame. The data word in TBUF is considered as last 1B word of an SSC frame. TDV 7 rh Transmit Data Valid This bit indicates that the data word in the transmit buffer TBUF can be considered as valid for transmission. The TBUF data word can only be sent out if TDV = 1. It is automatically set when data is moved to TBUF (by writing to one of the transmit buffer input locations TBUFx, or optionally, by the bypass or FIFO mechanism). The data word in TBUF is not valid for 0B transmission. 1B The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1. Reference Manual USIC, V2.14 14-188 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TDSSM 8 rw TBUF Data Single Shot Mode This bit defines if the data word TBUF data is considered as permanently valid or if the data should only be transferred once. The data word in TBUF is not considered as 0B invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV. The data word in TBUF is considered as invalid 1B after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used. TDEN [11:10] rw TBUF Data Enable This bit field controls the gating of the transmission start of the data word in the transmit buffer TBUF. 00B A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out. 01B A transmission of the data word in TBUF can be started if TDV = 1. 10B A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0. 11B A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1. TDVTR 12 rw TBUF Data Valid Trigger This bit enables the transfer trigger unit to set bit TCSR.TE if the trigger signal DX2T becomes active for event driven transfer starts, e.g. timer-based or depending on an event at an input pin. Bit TDVTR has to be 0 for protocols where the input stage DX2 is used for data shifting. Bit TCSR.TE is permanently set. 0B Bit TCSR.TE is set if DX2T becomes active 1B while TDV = 1. Reference Manual USIC, V2.14 14-189 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description WA 13 rwh Word Address This bit is only taken into account for the IIS protocol, otherwise it is ignored. It can be modified automatically by the data handler if bit WAMD = 1. Bit WA defines for which channel the data stored in TBUF will be transmitted. The data word in TBUF will be transmitted after 0B a falling edge of WA has been detected (referring to PSR.WA). The data word in TBUF will be transmitted after 1B a rising edge of WA has been detected (referring to PSR.WA). TSOF 24 rh Transmitted Start Of Frame This bit indicates if the latest start of a data word transmission has taken place for the first data word of a new data frame. This bit is updated with the transmission start of each data word. The latest data word transmission has not been 0B started for the first word of a data frame. The latest data word transmission has been 1B started for the first word of a data frame. TV 26 rh Transmission Valid This bit represents the transmit buffer underflow and indicates if the latest start of a data word transmission has taken place with a valid data word from the transmit buffer TBUF. This bit is updated with the transmission start of each data word. The latest start of a data word transmission has 0B taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started. The latest start of a data word transmission has 1B taken place with valid data from TBUF. Reference Manual USIC, V2.14 14-190 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TVC 27 rh Transmission Valid Cumulated This bit cumulates the transmit buffer underflow indication TV. It is cleared automatically together with bit TV and has to be set by writing FMR.ATVC = 1. Since TVC has been set, at least one data 0B buffer underflow condition has occurred. Since TVC has been set, no data buffer 1B underflow condition has occurred. TE 28 rh Trigger Event If the transfer trigger mechanism is enabled, this bit indicates that a trigger event has been detected (DX2T = 1) while TCSR.TDV = 1. If the event trigger mechanism is disabled, the bit TE is permanently set. It is cleared by writing FMR.MTDV = 10B or when the data word located in TBUF is loaded into the shift register. The trigger event has not yet been detected. A 0B transmission of the data word in TBUF can not be started. The trigger event has been detected (or the 1B trigger mechanism is switched off) and a transmission of the data word in TBUF can be started. 0 9, [23:14], 25, [31:29] r Reserved Read as 0; should be written with 0. 14.11.7.3 Flag Modification Registers The flag modification register FMR allows the modification of control and status flags related to data handling by using only write accesses. Read accesses to FMR always deliver 0 at all bit positions. Additionally, the service request outputs of this USIC channel can be activated by software (the activation is triggered by the write access and is deactivated automatically). Reference Manual USIC, V2.14 14-191 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) FMR Flag Modification Register 31 30 29 28 27 (68H) 26 25 24 Reset Value: 0000 0000H 23 22 0 14 13 12 11 10 CRD CRD V1 V0 w w 20 19 18 17 16 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 r 15 21 9 8 7 6 w w w w w w 5 4 3 2 1 0 0 ATV C 0 MTDV r w r w Field Bits Type Description MTDV [1:0] w Modify Transmit Data Valid Writing to this bit field can modify bits TCSR.TDV and TCSR.TE to control the start of a data word transmission by software. 00B No action. 01B Bit TDV is set, TE is unchanged. 10B Bits TDV and TE are cleared. 11B Reserved ATVC 4 w Activate Bit TVC Writing to this bit can set bit TCSR.TVC to start a new cumulation of the transmit buffer underflow condition. 0B No action. Bit TCSR.TVC is set. 1B CRDV0 14 w Clear Bits RDV for RBUF0 Writing 1 to this bit clears bits RBUF01SR.RDV00 and RBUF01SR.RDV10 to declare the received data in RBUF0 as no longer valid (to emulate a read action). No action. 0B 1B Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared. Reference Manual USIC, V2.14 14-192 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description CRDV1 15 w Clear Bit RDV for RBUF1 Writing 1 to this bit clears bits RBUF01SR.RDV01 and RBUF01SR.RDV11 to declare the received data in RBUF1 as no longer valid (to emulate a read action). No action. 0B 1B Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared. SIO0, SIO1, SIO2, SIO3, SIO4, SIO5 16, 17, 18, 19, 20, 21 w Set Interrupt Output SRx Writing a 1 to this bit field activates the service request output SRx of this USIC channel. It has no impact on service request outputs of other USIC channels. No action. 0B 1B The service request output SRx is activated. 0 [3:2], [13:5], [31:22] r Reserved Read as 0; should be written with 0. 14.11.8 Data Buffer Registers 14.11.8.1 Transmit Buffer Locations The 32 independent data input locations TBUF00 to TBUF31 are address locations that can be used as data entry locations for the transmit buffer. Data written to one of these locations will appear in a common register TBUF. Additionally, the 5 bit coding of the number [31:0] of the addressed data input location represents the transmit control information TCI (please refer to the protocol sections for more details). The internal transmit buffer register TBUF contains the data that will be loaded to the transmit shift register for the next transmission of a data word. It can be read out at all TBUF00 to TBUF31 addresses. Reference Manual USIC, V2.14 14-193 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) TBUFx (x = 00-31) Transmit Buffer Input Location x 31 30 29 28 27 26 25 (80H + x*4) 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 TDATA rwh Field Bits Type Description TDATA [15:0] rwh Transmit Data This bit field contains the data to be transmitted (read view). A data write action to at least the low byte of TDATA sets TCSR.TDV. 0 [31:16] r Reserved Read as 0; should be written with 0. 14.11.8.2 Receive Buffer Registers RBUF0, RBUF1 The receive buffer register RBUF0 contains the data received from RSR0[3:0]. A read action does not change the status of the receive data from “not yet read = valid” to “already read = not valid”. RBUF0 Receiver Buffer Register 0 31 30 29 28 27 (5CH) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 DSR0 rh Reference Manual USIC, V2.14 14-194 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DSR0 [15:0] rh Data of Shift Registers 0[3:0] 0 [31:16] r Reserved Read as 0; should be written with 0. The receive buffer register RBUF1 contains the data received from RSR1[3:0]. A read action does not change the status of the receive data from “not yet read = valid” to “already read = not valid”. RBUF1 Receiver Buffer Register 1 31 30 29 28 27 (60H) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 DSR1 rh Field Bits Type Description DSR1 [15:0] rh Data of Shift Registers 1[3:0] 0 [31:16] r Reserved Read as 0; should be written with 0. The receive buffer status register RBUF01SR provides the status of the data in receive buffers RBUF0 and RBUF1. Reference Manual USIC, V2.14 14-195 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) RBUF01SR Receiver Buffer 01 Status Register 31 DS1 30 29 RDV RDV 11 10 rh rh rh 15 14 13 DS0 rh 28 26 r 12 11 10 24 r Reset Value: 0000 0000H 23 22 21 20 19 18 17 0 SOF 1 0 WLEN1 r rh rh rh r rh 9 8 7 6 0 SOF 0 0 WLEN0 r rh r rh PER PAR R0 0 0 rh 25 PER PAR R1 1 0 RDV RDV 01 00 rh 27 (64H) rh rh 5 4 3 2 1 16 0 Field Bits Type Description WLEN0 [3:0] rh Received Data Word Length in RBUF0 This bit field indicates how many bits have been received within the last data word stored in RBUF0. This number indicates how many data bits have to be considered as receive data, whereas the other bits in RBUF0 have been cleared automatically. The received bits are always right-aligned. For all protocol modes besides dual and quad SSC, Received data word length = WLEN0 + 1 For dual SSC mode, Received data word length = WLEN0 + 2 For quad SSC mode, Received data word length = WLEN0 + 4 SOF0 6 rh Start of Frame in RBUF0 This bit indicates whether the data word in RBUF0 has been the first data word of a data frame. The data in RBUF0 has not been the first data 0B word of a data frame. The data in RBUF0 has been the first data word 1B of a data frame. Reference Manual USIC, V2.14 14-196 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description PAR0 8 rh Protocol-Related Argument in RBUF0 This bit indicates the value of the protocol-related argument. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF0. The meaning of this bit is described in the corresponding protocol chapter. PERR0 9 rh Protocol-related Error in RBUF0 This bit indicates if the value of the protocol-related argument meets an expected value. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF0. The meaning of this bit is described in the corresponding protocol chapter. The received protocol-related argument PAR 0B matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. The received protocol-related argument PAR 1B does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. RDV00 13 rh Receive Data Valid in RBUF0 This bit indicates the status of the data content of register RBUF0. This bit is identical to bit RBUF01SR.RDV10 and allows consisting reading of information for the receive buffer registers. It is set when a new data word is stored in RBUF0 and automatically cleared if it is read out via RBUF. Register RBUF0 does not contain data that has 0B not yet been read out. 1B Register RBUF0 contains data that has not yet been read out. Reference Manual USIC, V2.14 14-197 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RDV01 14 rh Receive Data Valid in RBUF1 This bit indicates the status of the data content of register RBUF1. This bit is identical to bit RBUF01SR.RDV11 and allows consisting reading of information for the receive buffer registers. It is set when a new data word is stored in RBUF1 and automatically cleared if it is read out via RBUF. Register RBUF1 does not contain data that has 0B not yet been read out. Register RBUF1 contains data that has not yet 1B been read out. DS0 15 rh Data Source This bit indicates which receive buffer register (RBUF0 or RBUF1) is currently visible in registers RBUF(D) and in RBUFSR for the associated status information. It indicates which buffer contains the oldest data (the data that has been received first). This bit is identical to bit RBUF01SR.DS1 and allows consisting reading of information for the receive buffer registers. The register RBUF contains the data of RBUF0 0B (same for associated status information). The register RBUF contains the data of RBUF1 1B (same for associated status information). WLEN1 [19:16] rh Received Data Word Length in RBUF1 This bit field indicates how many bits have been received within the last data word stored in RBUF1. This number indicates how many data bits have to be considered as receive data, whereas the other bits in RBUF1 have been cleared automatically. The received bits are always right-aligned. For all protocol modes besides dual and quad SSC, Received data word length = WLEN1 + 1 For dual SSC mode, Received data word length = WLEN1 + 2 For quad SSC mode, Received data word length = WLEN1 + 4 Reference Manual USIC, V2.14 14-198 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SOF1 22 rh Start of Frame in RBUF1 This bit indicates whether the data word in RBUF1 has been the first data word of a data frame. The data in RBUF1 has not been the first data 0B word of a data frame. The data in RBUF1 has been the first data word 1B of a data frame. PAR1 24 rh Protocol-Related Argument in RBUF1 This bit indicates the value of the protocol-related argument. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF1. The meaning of this bit is described in the corresponding protocol chapter. PERR1 25 rh Protocol-related Error in RBUF1 This bit indicates if the value of the protocol-related argument meets an expected value. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF1. The meaning of this bit is described in the corresponding protocol chapter. The received protocol-related argument PAR 0B matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt. The received protocol-related argument PAR 1B does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt. RDV10 29 rh Receive Data Valid in RBUF0 This bit indicates the status of the data content of register RBUF0. This bit is identical to bit RBUF01SR.RDV00 and allows consisting reading of information for the receive buffer registers. Register RBUF0 does not contain data that has 0B not yet been read out. Register RBUF0 contains data that has not yet 1B been read out. Reference Manual USIC, V2.14 14-199 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RDV11 30 rh Receive Data Valid in RBUF1 This bit indicates the status of the data content of register RBUF1. This bit is identical to bit RBUF01SR.RDV01 and allows consisting reading of information for the receive buffer registers. Register RBUF1 does not contain data that has 0B not yet been read out. 1B Register RBUF1 contains data that has not yet been read out. DS1 31 rh Data Source This bit indicates which receive buffer register (RBUF0 or RBUF1) is currently visible in registers RBUF(D) and in RBUFSR for the associated status information. It indicates which buffer contains the oldest data (the data that has been received first). This bit is identical to bit RBUF01SR.DS0 and allows consisting reading of information for the receive buffer registers. The register RBUF contains the data of RBUF0 0B (same for associated status information). The register RBUF contains the data of RBUF1 1B (same for associated status information). 0 [5:4], 7, r [12:10], [21:20], 23, [28:26] Reserved Read as 0; should be written with 0. 14.11.8.3 Receive Buffer Registers RBUF, RBUFD, RBUFSR The receiver buffer register RBUF shows the content of the either RBUF0 or RBUF1, depending on the order of reception. Always the oldest data (the data word that has been received first) from both receive buffers can be read from RBUF. It is recommended to read out the received data from RBUF instead of RBUF0/1. With a read access of at least the low byte of RBUF, the status of the receive data is automatically changed from “not yet read = valid” to “already read = not valid”, the content of RBUF becomes updated, and the next received data word becomes visible in RBUF. Reference Manual USIC, V2.14 14-200 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) RBUF Receiver Buffer Register 31 30 29 28 27 (54H) 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 DSR rh Field Bits Type Description DSR [15:0] rh Received Data This bit field monitors the content of either RBUF0 or RBUF1, depending on the reception sequence. 0 [31:16] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-201 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) If a debugger should be used to monitor the received data, the automatic update mechanism has to be de-activated to guaranty data consistency. Therefore, the receiver buffer register for debugging RBUFD is available. It is similar to RBUF, but without the automatic update mechanism by a read action. So a debugger (or other monitoring function) can read RBUFD without disturbing the receive sequence. RBUFD Receiver Buffer Register for Debugger(58H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 DSR rh Field Bits Type Description DSR [15:0] rh Data from Shift Register Same as RBUF.DSR, but without releasing the buffer after a read action. 0 [31:16] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-202 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The receive buffer status register RBUFSR provides the status of the data in receive buffers RBUF and RBUFD. If bits RBUF01SR.DS0 (or RBUF01SR.DS1) are 0, the lower 16-bit content of RBUF01SR is monitored in RBUFSR, otherwise the upper 16-bit content of RBUF01SR is shown. RBUFSR Receiver Buffer Status Register 31 30 29 28 27 26 (50H) 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 SOF 0 WLEN r rh r rh 0 r 15 DS 14 13 12 RDV RDV 1 0 rh rh 11 10 8 PER PAR R 0 rh 9 r rh rh Field Bits Type Description WLEN [3:0] rh Received Data Word Length in RBUF or RBUFD Description see RBUF01SR.WLEN0 or RBUF01SR.WLEN1. SOF 6 rh Start of Frame in RBUF or RBUFD Description see RBUF01SR.SOF0 or RBUF01SR.SOF1. PAR 8 rh Protocol-Related Argument in RBUF or RBUFD Description see RBUF01SR.PAR0 or RBUF01SR.PAR1. PERR 9 rh Protocol-related Error in RBUF or RBUFD Description see RBUF01SR.PERR0 or RBUF01SR.PERR1. RDV0 13 rh Receive Data Valid in RBUF or RBUFD Description see RBUF01SR.RDV00 or RBUF01SR.RDV10. RDV1 14 rh Receive Data Valid in RBUF or RBUFD Description see RBUF01SR.RDV01 or RBUF01SR.RDV11. Reference Manual USIC, V2.14 14-203 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DS 15 rh 0 [5:4], 7, r [12:10], [31:16] 14.11.9 Data Source of RBUF or RBUFD Description see RBUF01SR.DS0 or RBUF01SR.DS1. Reserved Read as 0; should be written with 0. FIFO Buffer and Bypass Registers 14.11.9.1 Bypass Registers A write action to at least the low byte of the bypass data register sets BYPCR.BDV = 1 (bypass data tagged valid). BYP Bypass Data Register 31 30 29 28 (100H) 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 BDATA rw Bit (Field) Width Type Description BDATA [15:0] rw Bypass Data This bit field contains the bypass data. 0 [31:16] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-204 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) BYPCR Bypass Control Register 31 30 15 14 BDV 0 rh r 29 28 13 12 BPRI BDV O TR rw rw 27 (104H) 26 25 24 23 Reset Value: 0000 0000H 22 21 20 19 18 0 BHPC BSELO r rw rw 11 10 7 6 5 4 3 2 17 16 1 0 9 8 BDEN 0 BDS SM 0 BWLE rw r rw r rw Field Bits Type Description BWLE [3:0] rw Bypass Word Length This bit field defines the word length of the bypass data. The word length is given by BWLE + 1 with the data word being right-aligned in the data buffer at the bit positions [BWLE down to 0]. The bypass data word is always considered as an own frame with the length of BWLE. Same coding as SCTR.WLE. BDSSM 8 rw Bypass Data Single Shot Mode This bit defines if the bypass data is considered as permanently valid or if the bypass data is only transferred once (single shot mode). The bypass data is still considered as valid after 0B it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV. The bypass data is considered as invalid after it 1B has been loaded into TBUF. The loading of the data into TBUF clears BDV. Reference Manual USIC, V2.14 14-205 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description BDEN [11:10] rw Bypass Data Enable This bit field defines if and how the transfer of bypass data to TBUF is enabled. 00B The transfer of bypass data is disabled. 01B The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1. 10B Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0. 11B Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1. BDVTR 12 rw Bypass Data Valid Trigger This bit enables the bypass data for being tagged valid when DX2T is active (for time framing or timeout purposes). Bit BDV is not influenced by DX2T. 0B 1B Bit BDV is set if DX2T is active. BPRIO 13 rw Bypass Priority This bit defines the priority between the bypass data and the transmit FIFO data. The transmit FIFO data has a higher priority 0B than the bypass data. The bypass data has a higher priority than the 1B transmit FIFO data. BDV 15 rh Bypass Data Valid This bit defines if the bypass data is valid for a transfer to TBUF. This bit is set automatically by a write access to at least the low-byte of register BYP. It can be cleared by software by writing TRBSCR.CBDV. The bypass data is not valid. 0B The bypass data is valid. 1B BSELO [20:16] rw Bypass Select Outputs This bit field contains the value that is written to PCR.CTR[20:16] if bypass data is transferred to TBUF while TCSR.SELMD = 1. In the SSC protocol, this bit field can be used to define which SELOx output line will be activated when bypass data is transmitted. Reference Manual USIC, V2.14 14-206 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description BHPC [23:21] rw 0 [7:4], 9, r 14, [31:24] Bypass Hardware Port Control This bit field contains the value that is written to SCTR[4:2] if bypass data is transferred to TBUF while TCSR.HPCMD = 1. In the SSC protocol, this bit field can be used to define the data shift mode and if hardware port control is enabled through CCR.HPCEN = 1, the pin direction when bypass data is transmitted. Reserved Read as 0; should be written with 0. 14.11.9.2 General FIFO Buffer Control Registers The transmit and receive FIFO status information of USICx_CHy is given in registers USICx_CHy.TRBSR. The bits related to the transmitter buffer in this register can only by written if the transmit buffer functionality is enabled by CCFG.TB = 1, otherwise write accesses are ignored. A similar behavior applies for the bits related to the receive buffer referring to CCFG.RB = 1. The interrupt flags (event flags) in the transmit and receive FIFO status register TRBSR can be cleared by writing a 1 to the corresponding bit position in register TRBSCR, whereas writing a 0 has to effect on these bits. Writing a 1 by software to SRBI, RBERI, ARBI, STBI, or TBERI sets the corresponding bit to simulate the detection of a transmit/receive buffer event, but without activating any service request output (therefore, see FMR.SIOx). Bits TBUS and RBUS have been implemented for testing purposes. They can be ignored by data handling software. Please note that a read action can deliver either a 0 or a 1 for these bits. It is recommended to treat them as “don’t care”. Reference Manual USIC, V2.14 14-207 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) TRBSR Transmit/Receive Buffer Status Register (114H) 31 30 29 28 27 26 25 24 23 Reset Value: 0000 0808H 22 21 20 19 0 TBFLVL 0 RBFLVL r rh r rh 15 0 14 13 12 11 STB TBU TFU TEM T S LL PTY r rh rh rh rh 10 9 8 7 0 TBE STBI RI 0 r rwh r rwh 6 5 4 3 18 17 16 2 1 0 SRB RBU RFU REM RBE ARBI SRBI T S LL PTY RI rh rh rh rh rwh rwh rwh Field Bits Type Description SRBI 0 rwh Standard Receive Buffer Event This bit indicates that a standard receive buffer event has been detected. It is cleared by writing TRBSCR.CSRBI = 1. If enabled by RBCTR.SRBIEN, the service request output SRx selected by RBCTR.SRBINP becomes activated if a standard receive buffer event is detected. A standard receive buffer event has not been 0B detected. A standard receive buffer event has been 1B detected. RBERI 1 rwh Receive Buffer Error Event This bit indicates that a receive buffer error event has been detected. It is cleared by writing TRBSCR.CRBERI = 1. If enabled by RBCTR.RBERIEN, the service request output SRx selected by RBCTR.ARBINP becomes activated if a receive buffer error event is detected. A receive buffer error event has not been 0B detected. A receive buffer error event has been 1B detected. Reference Manual USIC, V2.14 14-208 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description ARBI 2 rwh Alternative Receive Buffer Event This bit indicates that an alternative receive buffer event has been detected. It is cleared by writing TRBSCR.CARBI = 1. If enabled by RBCTR.ARBIEN, the service request output SRx selected by RBCTR.ARBINP becomes activated if an alternative receive buffer event is detected. An alternative receive buffer event has not 0B been detected. 1B An alternative receive buffer event has been detected. REMPTY 3 rh Receive Buffer Empty This bit indicates whether the receive buffer is empty. 0B The receive buffer is not empty. The receive buffer is empty. 1B RFULL 4 rh Receive Buffer Full This bit indicates whether the receive buffer is full. 0B The receive buffer is not full. 1B The receive buffer is full. RBUS 5 rh Receive Buffer Busy This bit indicates whether the receive buffer is currently updated by the FIFO handler. The receive buffer information has been 0B completely updated. The OUTR update from the FIFO memory is 1B ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. SRBT 6 rh Standard Receive Buffer Event Trigger This bit triggers a standard receive buffer event when set. If enabled by RBCTR.SRBIEN, the service request output SRx selected by RBCTR.SRBINP becomes activated until the bit is cleared. A standard receive buffer event is not triggered 0B using this bit. 1B A standard receive buffer event is triggered using this bit. Reference Manual USIC, V2.14 14-209 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description STBI 8 rwh Standard Transmit Buffer Event This bit indicates that a standard transmit buffer event has been detected. It is cleared by writing TRBSCR.CSTBI = 1. If enabled by TBCTR.STBIEN, the service request output SRx selected by TBCTR.STBINP becomes activated if a standard transmit buffer event is detected. A standard transmit buffer event has not been 0B detected. 1B A standard transmit buffer event has been detected. TBERI 9 rwh Transmit Buffer Error Event This bit indicates that a transmit buffer error event has been detected. It is cleared by writing TRBSCR.CTBERI = 1. If enabled by TBCTR.TBERIEN, the service request output SRx selected by TBCTR.ATBINP becomes activated if a transmit buffer error event is detected. A transmit buffer error event has not been 0B detected. 1B A transmit buffer error event has been detected. TEMPTY 11 rh Transmit Buffer Empty This bit indicates whether the transmit buffer is empty. 0B The transmit buffer is not empty. The transmit buffer is empty. 1B TFULL 12 rh Transmit Buffer Full This bit indicates whether the transmit buffer is full. 0B The transmit buffer is not full. 1B The transmit buffer is full. Reference Manual USIC, V2.14 14-210 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description TBUS 13 rh Transmit Buffer Busy This bit indicates whether the transmit buffer is currently updated by the FIFO handler. The transmit buffer information has been 0B completely updated. The FIFO memory update after write to INx is 1B ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. STBT 14 rh Standard Transmit Buffer Event Trigger This bit triggers a standard transmit buffer event when set. If enabled by TBCTR.STBIEN, the service request output SRx selected by TBCTR.STBINP becomes activated until the bit is cleared. A standard transmit buffer event is not 0B triggered using this bit. A standard transmit buffer event is triggered 1B using this bit. RBFLVL [22:16] rh Receive Buffer Filling Level This bit field indicates the filling level of the receive buffer, starting with 0 for an empty buffer. TBFLVL [30:24] rh Transmit Buffer Filling Level This bit field indicates the filling level of the transmit buffer, starting with 0 for an empty buffer. Note: The first data word written to Transmit FIFO will be loaded immediately to TBUF and removed from FIFO. 0 Reference Manual USIC, V2.14 7, 10, 15, 23, 31 r Reserved Read as 0; should be written with 0. 14-211 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The bits in register TRBSCR are used to clear the notification bits in register TRBSR or to clear the FIFO mechanism for the transmit or receive buffer. A read action always delivers 0. TRBSCR Transmit/Receive Buffer Status Clear Register (118H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 FLU FLU SHT SHR B B w w 12 0 11 10 9 8 CBD CTB CST V ERI BI r w w 0 w r CAR CRB CSR BI ERI BI w w Field Bits Type Description CSRBI 0 w Clear Standard Receive Buffer Event 0B No effect. 1B Clear TRBSR.SRBI. CRBERI 1 w Clear Receive Buffer Error Event 0B No effect. 1B Clear TRBSR.RBERI. CARBI 2 w Clear Alternative Receive Buffer Event 0B No effect. Clear TRBSR.ARBI. 1B CSTBI 8 w Clear Standard Transmit Buffer Event 0B No effect. 1B Clear TRBSR.STBI. CTBERI 9 w Clear Transmit Buffer Error Event 0B No effect. 1B Clear TRBSR.TBERI. CBDV 10 w Clear Bypass Data Valid 0B No effect. Clear BYPCR.BDV. 1B Reference Manual USIC, V2.14 14-212 w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description FLUSHRB 14 w Flush Receive Buffer 0B No effect. The receive FIFO buffer is cleared (filling level 1B is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. FLUSHTB 15 w Flush Transmit Buffer 0B No effect. 1B The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic. 0 [7:3], r [13:11], [31:16] Reserved Read as 0; should be written with 0. 14.11.9.3 Transmit FIFO Buffer Control Registers The transmit FIFO buffer is controlled by register TBCTR. TBCTR can only by written if the transmit buffer functionality is enabled by CCFG.TB = 1, otherwise write accesses are ignored. TBCTR Transmitter Buffer Control Register (108H) 31 30 TBE STBI RIEN EN 29 28 27 0 LOF 0 SIZE 0 ATBINP STBINP rw r rw rw rw rw r rw r 15 14 13 12 11 STB STB TEN TM rw rw Reference Manual USIC, V2.14 26 10 25 9 24 Reset Value: 0000 0000H 8 23 22 7 6 21 5 20 4 19 18 3 2 LIMIT 0 DPTR rw r w 14-213 17 1 16 0 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description DPTR [5:0] w Data Pointer This bit field defines the start value for the transmit buffer pointers when assigning the FIFO entries to the transmit FIFO buffer. A read always delivers 0. When writing DPTR while SIZE = 0, both transmitter pointers TDIPTR and RTDOPTR in register TRBPTR are updated with the written value and the buffer is considered as empty. A write access to DPTR while SIZE > 0 is ignored and does not modify the pointers. LIMIT [13:8] rw Limit For Interrupt Generation This bit field defines the target filling level of the transmit FIFO buffer that is used for the standard transmit buffer event detection. STBTM 14 rw Standard Transmit Buffer Trigger Mode This bit selects the standard transmit buffer event trigger mode. Trigger mode 0: 0B While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT. Trigger mode 1: 1B While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE. STBTEN 15 rw Standard Transmit Buffer Trigger Enable This bit enables/disables triggering of the standard transmit buffer event through bit TRBSR.STBT. The standard transmit buffer event trigger 0B through bit TRBSR.STBT is disabled. 1B The standard transmit buffer event trigger through bit TRBSR.STBT is enabled. Reference Manual USIC, V2.14 14-214 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description STBINP [18:16] rw Standard Transmit Buffer Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a standard transmit buffer event. 000B Output SR0 becomes activated. 001B Output SR1 becomes activated. 010B Output SR2 becomes activated. 011B Output SR3 becomes activated. 100B Output SR4 becomes activated. 101B Output SR5 becomes activated. ATBINP [21:19] rw Alternative Transmit Buffer Interrupt Node Pointer This bit field define which service request output SRx will be activated in case of a transmit buffer error event. 000B Output SR0 becomes activated. 001B Output SR1 becomes activated. 010B Output SR2 becomes activated. 011B Output SR3 becomes activated. 100B Output SR4 becomes activated. 101B Output SR5 becomes activated. Note: All other settings of the bit field are reserved. Note: All other settings of the bit field are reserved. SIZE Reference Manual USIC, V2.14 [26:24] rw Buffer Size This bit field defines the number of FIFO entries assigned to the transmit FIFO buffer. 000B The FIFO mechanism is disabled. The buffer does not accept any request for data. 001B The FIFO buffer contains 2 entries. 010B The FIFO buffer contains 4 entries. 011B The FIFO buffer contains 8 entries. 100B The FIFO buffer contains 16 entries. 101B The FIFO buffer contains 32 entries. 110B The FIFO buffer contains 64 entries. 111B Reserved 14-215 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description LOF 28 rw Buffer Event on Limit Overflow This bit defines which relation between filling level and programmed limit leads to a standard transmit buffer event. A standard transmit buffer event occurs when 0B the filling level equals the limit value and gets lower due to transmission of a data word. A standard transmit buffer interrupt event 1B occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx. STBIEN 30 rw Standard Transmit Buffer Interrupt Enable This bit enables/disables the generation of a standard transmit buffer interrupt in case of a standard transmit buffer event. The standard transmit buffer interrupt 0B generation is disabled. The standard transmit buffer interrupt 1B generation is enabled. TBERIEN 31 rw Transmit Buffer Error Interrupt Enable This bit enables/disables the generation of a transmit buffer error interrupt in case of a transmit buffer error event (software writes to a full transmit buffer). The transmit buffer error interrupt generation 0B is disabled. The transmit buffer error interrupt generation 1B is enabled. 0 [7:6], r [23:22], 27, 29 Reference Manual USIC, V2.14 Reserved Read as 0; should be written with 0. 14-216 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.9.4 Receive FIFO Buffer Control Registers The receive FIFO buffer is controlled by register RBCTR. This register can only be written if the receive buffer functionality is enabled by CCFG.RB = 1, otherwise write accesses are ignored. RBCTR Receiver Buffer Control Register 31 30 29 28 27 26 RBE SRBI ARBI LOF RNM RIEN EN EN rw rw rw rw rw 15 14 13 12 11 SRB SRB TEN TM rw rw 10 25 (10CH) 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 SIZE RCIM ARBINP SRBINP rw rw rw rw 9 8 7 6 5 4 3 2 LIMIT 0 DPTR rw r w 1 16 0 Field Bits Type Description DPTR [5:0] w Data Pointer This bit field defines the start value for the receive buffer pointers when assigning the FIFO entries to the receive FIFO buffer. A read always delivers 0. When writing DPTR while SIZE = 0, both receiver pointers RDIPTR and RDOPTR in register TRBPTR are updated with the written value and the buffer is considered as empty. A write access to DPTR while SIZE > 0 is ignored and does not modify the pointers. LIMIT [13:8] rw Limit For Interrupt Generation This bit field defines the target filling level of the receive FIFO buffer that is used for the standard receive buffer event detection. Reference Manual USIC, V2.14 14-217 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SRBTM 14 rw Standard Receive Buffer Trigger Mode This bit selects the standard receive buffer event trigger mode. Trigger mode 0: 0B While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. Trigger mode 1: 1B While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. SRBTEN 15 rw Standard Receive Buffer Trigger Enable This bit enables/disables triggering of the standard receive buffer event through bit TRBSR.SRBT. The standard receive buffer event trigger 0B through bit TRBSR.SRBT is disabled. 1B The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. SRBINP [18:16] rw Standard Receive Buffer Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a standard receive buffer event. 000B Output SR0 becomes activated. 001B Output SR1 becomes activated. 010B Output SR2 becomes activated. 011B Output SR3 becomes activated. 100B Output SR4 becomes activated. 101B Output SR5 becomes activated. Note: All other settings of the bit field are reserved. Reference Manual USIC, V2.14 14-218 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description ARBINP [21:19] rw Alternative Receive Buffer Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of an alternative receive buffer event or a receive buffer error event. 000B Output SR0 becomes activated. 001B Output SR1 becomes activated. 010B Output SR2 becomes activated. 011B Output SR3 becomes activated. 100B Output SR4 becomes activated. 101B Output SR5 becomes activated. Note: All other settings of the bit field are reserved. RCIM [23:22] rw Receiver Control Information Mode This bit field defines which information from the receiver status register RBUFSR is propagated as 5 bit receiver control information RCI[4:0] to the receive FIFO buffer and can be read out in registers OUT(D)R. 00B RCI[4] = PERR, RCI[3:0] = WLEN 01B RCI[4] = SOF, RCI[3:0] = WLEN 10B RCI[4] = 0, RCI[3:0] = WLEN 11B RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF SIZE [26:24] rw Buffer Size This bit field defines the number of FIFO entries assigned to the receive FIFO buffer. 000B The FIFO mechanism is disabled. The buffer does not accept any request for data. 001B The FIFO buffer contains 2 entries. 010B The FIFO buffer contains 4 entries. 011B The FIFO buffer contains 8 entries. 100B The FIFO buffer contains 16 entries. 101B The FIFO buffer contains 32 entries. 110B The FIFO buffer contains 64 entries. 111B Reserved Reference Manual USIC, V2.14 14-219 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description RNM 27 rw Receiver Notification Mode This bit defines the receive buffer event mode. The receive buffer error event is not affected by RNM. Filling level mode: 0B A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). RCI mode: 1B A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. LOF 28 rw Buffer Event on Limit Overflow This bit defines which relation between filling level and programmed limit leads to a standard receive buffer event in filling level mode (RNM = 0). In RCI mode (RNM = 1), bit fields LIMIT and LOF are ignored. A standard receive buffer event occurs when 0B the filling level equals the limit value and gets lower due to a read access from OUTR. A standard receive buffer event occurs when 1B the filling level equals the limit value and gets bigger due to the reception of a new data word. ARBIEN 29 rw Alternative Receive Buffer Interrupt Enable This bit enables/disables the generation of an alternative receive buffer interrupt in case of an alternative receive buffer event. The alternative receive buffer interrupt 0B generation is disabled. The alternative receive buffer interrupt 1B generation is enabled. Reference Manual USIC, V2.14 14-220 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Field Bits Type Description SRBIEN 30 rw Standard Receive Buffer Interrupt Enable This bit enables/disables the generation of a standard receive buffer interrupt in case of a standard receive buffer event. The standard receive buffer interrupt 0B generation is disabled. The standard receive buffer interrupt 1B generation is enabled. RBERIEN 31 rw Receive Buffer Error Interrupt Enable This bit enables/disables the generation of a receive buffer error interrupt in case of a receive buffer error event (the software reads from an empty receive buffer). The receive buffer error interrupt generation is 0B disabled. 1B The receive buffer error interrupt generation is enabled. 0 [7:6] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-221 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.9.5 FIFO Buffer Data Registers The 32 independent data input locations IN00 to IN31 are addresses that can be used as data entry locations for the transmit FIFO buffer. Data written to one of these locations will be stored in the transmit buffer FIFO. Additionally, the 5-bit coding of the number [31:0] of the addressed data input location represents the transmit control information TCI. If the FIFO is already full and new data is written to it, the write access is ignored and a transmit buffer error event is signaled. INx (x = 00-31) Transmit FIFO Buffer Input Location x (180H + x *4) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 TDATA w Field Bits Type Description TDATA [15:0] w Transmit Data This bit field contains the data to be transmitted (write view), read actions deliver 0. A write action to at least the low byte of TDATA triggers the data storage in the FIFO. 0 [31:16] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-222 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) The receiver FIFO buffer output register OUTR shows the oldest received data word in the FIFO buffer and contains the receiver control information RCI containing the information selected by RBCTR.RCIM. A read action from this address location delivers the received data. With a read access of at least the low byte, the data is declared to be read and the next entry becomes visible. Write accesses to OUTR are ignored. OUTR Receiver Buffer Output Register 31 15 30 14 29 13 28 12 27 26 11 (11CH) 25 24 23 Reset Value: 0000 0000H 22 21 20 19 18 0 RCI r rh 10 9 8 7 6 5 4 3 2 17 16 1 0 DSR rh Field Bits Type Description DSR [15:0] rh Received Data This bit field monitors the content of the oldest data word in the receive FIFO. Reading at least the low byte releases the buffer entry currently shown in DSR. RCI [20:16] rh Receiver Control Information This bit field monitors the receiver control information associated to DSR. The bit structure of RCI depends on bit field RBCTR.RCIM. 0 [31:21] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-223 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) If a debugger should be used to monitor the received data in the FIFO buffer, the FIFO mechanism must not be activated in order to guaranty data consistency. Therefore, a second address set is available, named OUTDR (D like debugger), having the same bit fields like the original buffer output register OUTR, but without the FIFO mechanism. A debugger can read here (in order to monitor the receive data flow) without the risk of data corruption. Write accesses to OUTDR are ignored. OUTDR Receiver Buffer Output Register L for Debugger (120H) 31 15 30 14 29 13 28 12 27 26 11 25 24 23 22 Reset Value: 0000 0000H 21 20 19 18 0 RCI r rh 10 9 8 7 6 5 4 3 2 17 16 1 0 DSR rh Field Bits Type Description DSR [15:0] rh Data from Shift Register Same as OUTR.DSR, but without releasing the buffer after a read action. RCI [20:16] rh Receive Control Information from Shift Register Same as OUTR.RCI. 0 [31:21] r Reserved Read as 0; should be written with 0. Reference Manual USIC, V2.14 14-224 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.11.9.6 FIFO Buffer Pointer Registers The pointers for FIFO handling of the transmit and receive FIFO buffers are located in register TRBPTR. The pointers are automatically handled by the FIFO buffer mechanism and do not need to be modified by software. As a consequence, these registers can only be read by software (e.g. for verification purposes), whereas write accesses are ignored. TRBPTR Transmit/Receive Buffer Pointer Register (110H) 31 30 29 28 27 26 25 24 Reset Value: 0000 0000H 23 22 21 20 19 18 0 RDOPTR 0 RDIPTR r rh r rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 TDOPTR 0 TDIPTR r rh r rh 17 16 1 0 Field Bits Type Description TDIPTR [5:0] rh Transmitter Data Input Pointer This bit field indicates the buffer entry that will be used for the next transmit data coming from the INx addresses. TDOPTR [13:8] rh Transmitter Data Output Pointer This bit field indicates the buffer entry that will be used for the next transmit data to be output to TBUF. RDIPTR [21:16] rh Receiver Data Input Pointer This bit field indicates the buffer entry that will be used for the next receive data coming from RBUF. RDOPTR [29:24] rh Receiver Data Output Pointer This bit field indicates the buffer entry that will be used for the next receive data to be output at the OUT(D)R addresses. 0 [7:6], r [15:14], [23:22], [31:30] Reference Manual USIC, V2.14 Reserved Read as 0; should be written with 0. 14-225 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) 14.12 Interconnects The XMC1100 device contains one USIC module (USIC0) with 2 communication channels. Port Lines Channel 1 Channel 0 USIC0 Bus Interface AHB-Lite Bus Figure 14-66 USIC Module Structure in XMC1100 Figure 14-67 shows the I/O lines of one USIC channel. The tables in this section define the pin assignments and internal connections of the USIC channels I/O lines in the XMC1100 device. Naming convention: USICx_CHy refers to USIC module x channel y. The meaning of these pins with respect to each protocol is described in the protocols’ respective chapters and summarized in Table 14-2 and Table 14-3. Reference Manual USIC, V2.14 14-226 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) USIC Channel DX0A : : DX0G HWIN0 : : Input Stage DX0 DX0INS DX1A : : DX1G : : Input Stage SR0 SR1 SR2 SR3 SR4 SR5 Interrupt Control DX1 DX1INS DX2A : : DX2G : : Input Stage DX2 Slave Select Generator : : SELO0 SELO1 : : SELO6 SELO7 DX2INS DX3A : : DX3G HWIN1 : : Input Stage DX3 Output Stage DOUT DOUT0 DOUT1 DOUT2 DOUT3 DX3INS DX4A : : DX4G HWIN2 : : Input Stage DX4 Baud Rate Generator SCLKOUT MCLKOUT DX4INS DX5A : : DX5G HWIN3 : : Input Stage DX5 DX5INS Figure 14-67 USIC Channel I/O Lines The service request outputs SR[5:0] of one USIC channel is combined with those of the other channel with the module. Therefore, only 6 service request outputs are available per module. 14.12.1 USIC Module 0 Interconnects The interconnects of USIC module 0 is grouped into the following categories: Reference Manual USIC, V2.14 14-227 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) • • • USIC Module 0 Channel 0 Interconnects (Table 14-23) USIC Module 0 Channel 1 Interconnects (Table 14-24) USIC Module 0 Module Interconnects (Table 14-25) Table 14-23 USIC Module 0 Channel 0 Interconnects Input/Output I/O Connected To Description USIC0_CH0.DX0A I P0.14 USIC0_CH0.DX0B I P0.15 USIC0_CH0.DX0C I P1.0 USIC0_CH0.DX0D I P1.1 Shift data input; used for: • ASC RXD • SSC MTSR/MRST • IIC SDA • IIS DIN USIC0_CH0.DX0E I P2.0 USIC0_CH0.DX0F I P2.1 USIC0_CH0.DX0G I USIC0_CH0.DX3INS USIC0_CH0.HWIN0 I P1.0 HW controlled shift data input Shift clock input; used for: • SSC Slave SCLKIN • IIC SCL • IIS Slave SCLKIN • Optional for ASC, SSC Master and IIS Master Data Inputs (DX0) Clock Inputs USIC0_CH0.DX1A I P0.14 USIC0_CH0.DX1B I P0.8 USIC0_CH0.DX1C I P0.7 USIC0_CH0.DX1D I P1.1 USIC0_CH0.DX1E I P2.0 USIC0_CH0.DX1F I USIC0_CH0.DX0INS USIC0_CH0.DX1G I USIC0_CH0.DX4INS Control Inputs USIC0_CH0.DX2A I P0.0 USIC0_CH0.DX2B I P0.9 USIC0_CH0.DX2C I P0.10 USIC0_CH0.DX2D I P0.11 USIC0_CH0.DX2E I P0.12 USIC0_CH0.DX2F I P0.13 USIC0_CH0.DX2G I USIC0_CH0.DX5INS Reference Manual USIC, V2.14 Shift control input; used for: • SSC Slave SELIN • IIS Slave WAIN • Optional for ASC, SSC Master, IIC and IIS Master 14-228 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-23 USIC Module 0 Channel 0 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH0.DX3A I P2.2 USIC0_CH0.DX3B I P2.4 USIC0_CH0.DX3C I P2.10 USIC0_CH0.DX3D I P2.8 USIC0_CH0.DX3E I P2.6 USIC0_CH0.DX3F I USIC0_CH0.DX5INS Shift data input; used for: • Dual and Quad SSC MTSR1/MRST1 • Can be ignored for all other protocols It can also be used as a DX0 function if DX0G input is selected. USIC0_CH0.DX3G I USIC0_CH0.DOUT0 USIC0_CH0.HWIN1 I P1.1 HW controlled shift data input USIC0_CH0.DX4A I P2.2 USIC0_CH0.DX4B I P2.4 USIC0_CH0.DX4C I P2.10 USIC0_CH0.DX4D I P2.8 USIC0_CH0.DX4E I P2.6 USIC0_CH0.DX4F I USIC0_CH0.DX5INS Shift data input; used for: • Quad SSC MTSR2/MRST2 • Can be ignored for all other protocols It can also be used as a DX1 function if DX1G input is selected. USIC0_CH0.DX4G I USIC0_CH0.SCLKOU T USIC0_CH0.HWIN2 I P1.2 HW controlled shift data input USIC0_CH0.DX5A I P2.9 USIC0_CH0.DX5B I P2.3 USIC0_CH0.DX5C I P2.7 USIC0_CH0.DX5D I P2.5 USIC0_CH0.DX5E I P1.4 USIC0_CH0.DX5F I P1.6 Shift data input; used for: • Quad SSC MTSR3/MRST3 • Can be ignored for all other protocols It can also be used as a DX2/DX3/DX4 function if DX2G/DX3F/DX4F input is selected. Data Inputs (DX3) Data Inputs (DX4) Data Inputs (DX5) USIC0_CH0.DX5G I USIC0_CH0.SELO0 USIC0_CH0.HWIN3 I P1.3 Reference Manual USIC, V2.14 HW controlled shift data input 14-229 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-23 USIC Module 0 Channel 0 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH0.DOUT0 O P0.14 P0.15 P1.0 P1.0 (HW1_OUT) P1.1 P1.5 P2.0 P2.1 USIC0_CH0.DX3G Shift data output; used for: • ASC TXD • SSC MTSR/MRST • IIC SDA • IIS DOUT USIC0_CH0.DOUT1 O P1.1 (HW1_OUT) Shift data output; used for: • Dual and Quad SSC MTSR1/MRST1 • Can be ignored for all other protocols USIC0_CH0.DOUT2 O P1.2 (HW1_OUT) Shift data output; used for: • Quad SSC MTSR2/MRST2 • Can be ignored for all other protocols USIC0_CH0.DOUT3 O P1.3 (HW1_OUT) Shift data output; used for: • Quad SSC MTSR3/MRST3 • Can be ignored for all other protocols O P0.11 Master clock output (optional for all protocols) P0.7 P0.8 P0.14 P1.6 P2.0 USIC0_CH0.DX4G Shift clock output; used for: • Master SCLKOUT in SSC and IIS • IIC SCL • Can be ignored in ASC Data Outputs Clock Outputs USIC0_CH0.MCLKO UT USIC0_CH0.SCLKOU O T Reference Manual USIC, V2.14 14-230 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-23 USIC Module 0 Channel 0 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH0.SELO0 O P0.0 P0.9 P1.4 USIC0_CH0.DX5G USIC0_CH0.SELO1 O P0.10 P1.5 Shift control output; used for: • SSC Master SELO • IIS WA • Can be ignored for all other protocols USIC0_CH0.SELO2 O P0.11 P1.6 USIC0_CH0.SELO3 O P0.12 USIC0_CH0.SELO4 O P0.13 USIC0_CH0.SELO5 O not connected USIC0_CH0.SELO6 O not connected USIC0_CH0.SELO7 O not connected Control Outputs System Related Outputs USIC0_CH0.DX0INS O USIC0_CH0.DX1F Selected DX0 input signal USIC0_CH0.DX1INS O not connected Selected DX1 input signal USIC0_CH0.DX2INS O CCU40.IN0L Selected DX2 input signal USIC0_CH0.DX3INS O USIC0_CH0.DX0G Selected DX3 input signal USIC0_CH0.DX4INS O USIC0_CH0.DX1G Selected DX4 input signal USIC0_CH0.DX5INS O USIC0_CH0.DX2G USIC0_CH0.DX3F USIC0_CH0.DX4F Selected DX5 input signal Reference Manual USIC, V2.14 14-231 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-24 USIC Module 0 Channel 1 Interconnects Input/Output I/O Connected To Description USIC0_CH1.DX0A I P1.3 USIC0_CH1.DX0B I P1.2 USIC0_CH1.DX0C I P0.6 Shift data input; used for: • ASC RXD • SSC MTSR/MRST • IIC SDA • IIS DIN Data Inputs (DX0) USIC0_CH1.DX0D I P0.7 USIC0_CH1.DX0E I P2.11 USIC0_CH1.DX0F I P2.10 USIC0_CH1.DX0G I USIC0_CH1.DX3INS USIC0_CH1.HWIN0 I ERU0.PDOUT0 HW controlled shift data input USIC0_CH1.DX1A I P1.3 USIC0_CH1.DX1B I P0.8 Shift clock input; used for: • SSC Slave SCLKIN • IIC SCL • IIS Slave SCLKIN • Optional for ASC, SSC Master and IIS Master Clock Inputs USIC0_CH1.DX1C I P0.7 USIC0_CH1.DX1D I 0 USIC0_CH1.DX1E I P2.11 USIC0_CH1.DX1F I USIC0_CH1.DX0INS USIC0_CH1.DX1G I USIC0_CH1.DX4INS USIC0_CH1.DX2A I P0.0 USIC0_CH1.DX2B I P0.9 USIC0_CH1.DX2C I P0.10 USIC0_CH1.DX2D I P0.11 USIC0_CH1.DX2E I P1.1 Control Inputs Shift control input; used for: • SSC Slave SELIN • IIS Slave WAIN • Optional for ASC, SSC Master, IIC and IIS Master USIC0_CH1.DX2F I P2.0 USIC0_CH1.DX2G I USIC0_CH1.DX5INS Reference Manual USIC, V2.14 14-232 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-24 USIC Module 0 Channel 1 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH1.DX3A I P2.1 USIC0_CH1.DX3B I P2.9 USIC0_CH1.DX3C I P2.3 USIC0_CH1.DX3D I P2.7 USIC0_CH1.DX3E I P2.5 USIC0_CH1.DX3F I USIC0_CH1.DX5INS Shift data input; used for: • Dual and Quad SSC MTSR1/MRST1 • Can be ignored for all other protocols It can also be used as a DX0 function if DX0G input is selected. Data Inputs (DX3) USIC0_CH1.DX3G I USIC0_CH1.DOUT0 USIC0_CH1.HWIN1 I 0 HW controlled shift data input USIC0_CH1.DX4A I P2.1 USIC0_CH1.DX4B I P2.9 USIC0_CH1.DX4C I P2.3 USIC0_CH1.DX4D I P2.7 USIC0_CH1.DX4E I P2.5 USIC0_CH1.DX4F I USIC0_CH1.DX5INS Shift data input; used for: • Quad SSC MTSR2/MRST2 • Can be ignored for all other protocols It can also be used as a DX1 function if DX1G input is selected. USIC0_CH1.DX4G I USIC0_CH1.SCLKOU T USIC0_CH1.HWIN2 I ERU0.PDOUT1 HW controlled shift data input USIC0_CH1.DX5A I P2.2 USIC0_CH1.DX5B I P2.4 USIC0_CH1.DX5C I P2.8 USIC0_CH1.DX5D I P2.6 USIC0_CH1.DX5E I P1.4 USIC0_CH1.DX5F I P1.5 Shift data input; used for: • Quad SSC MTSR3/MRST3 • Can be ignored for all other protocols It can also be used as a DX2/DX3/DX4 function if DX2G/DX3F/DX4F input is selected. Data Inputs (DX4) Data Inputs (DX5) USIC0_CH1.DX5G I USIC0.SR0 USIC0_CH1.HWIN3 I USIC0_CH1.DOUT0 Reference Manual USIC, V2.14 14-233 HW controlled shift data input V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-24 USIC Module 0 Channel 1 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH1.DOUT0 O P0.6 P0.7 P1.2 P1.3 P1.6 P2.10 P2.11 USIC0_CH1.DX3G USIC0_CH1.HWIN3 Shift data output; used for: • ASC TXD • SSC MTSR/MRST • IIC SDA • IIS DOUT USIC0_CH1.DOUT1 O not connected Shift data output; used for: • Dual and Quad SSC MTSR1/MRST1 • Can be ignored for all other protocols USIC0_CH1.DOUT2 O not connected Shift data output; used for: • Quad SSC MTSR2/MRST2 • Can be ignored for all other protocols USIC0_CH1.DOUT3 O not connected Shift data output; used for: • Quad SSC MTSR3/MRST3 • Can be ignored for all other protocols O P0.6 P0.15 Master clock output (optional for all protocols) P0.8 P1.3 P1.4 P2.1 P2.11 USIC0_CH1.DX4G Shift clock output; used for: • Master SCLKOUT in SSC and IIS • IIC SCL • Can be ignored in ASC Data Outputs Clock Outputs USIC0_CH1.MCLKO UT USIC0_CH1.SCLKOU O T Reference Manual USIC, V2.14 14-234 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Table 14-24 USIC Module 0 Channel 1 Interconnects (cont’d) Input/Output I/O Connected To Description USIC0_CH1.SELO0 O P0.0 P0.9 P1.1 USIC0_CH1.SELO1 O P0.10 P1.4 Shift control output; used for: • SSC Master SELO • IIS WA • Can be ignored for all other protocols USIC0_CH1.SELO2 O P0.11 P1.5 USIC0_CH1.SELO3 O P1.6 USIC0_CH1.SELO4 O not connected USIC0_CH1.SELO5 O not connected USIC0_CH1.SELO6 O not connected USIC0_CH1.SELO7 O not connected Control Outputs System Related Outputs USIC0_CH1.DX0INS O USIC0_CH1.DX1F Selected DX0 input signal USIC0_CH1.DX1INS O not connected Selected DX1 input signal USIC0_CH1.DX2INS O CCU40.IN1L Selected DX2 input signal USIC0_CH1.DX3INS O USIC0_CH1.DX0G Selected DX3 input signal USIC0_CH1.DX4INS O USIC0_CH1.DX1G Selected DX4 input signal USIC0_CH1.DX5INS O USIC0_CH1.DX2G USIC0_CH1.DX3F USIC0_CH1.DX4F Selected DX5 input signal Table 14-25 USIC Module 0 Module Interconnects Input/Output I/O Connected To Description USIC0_SR0 O NVIC USIC0_CH1.DX5G interrupt output lines (service requests SRx) USIC0_SR[5:1] O NVIC interrupt output lines (service requests SRx) Reference Manual USIC, V2.14 14-235 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Universal Serial Interface Channel (USIC) Reference Manual USIC, V2.14 14-236 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15 Analog-to-Digital Converter (VADC) The analog-to-digital converter (ADC) in XMC1100 series provides a subset of functions compared to the feature-rich VADC (versatile analog-to-digital converter) which is implemented in XMC1200 and XMC1300 series. The XMC1100 provides a series of analog input channels combined into two groups. The ADC is based on a high-speed 12-Bit converter clocked at 32 MHz using the successive approximation register (SAR) principle to convert analog input values (voltages) to discrete digital values. Each analog input channel can be configured to be amplified by an adjustable gain factor. Conversion mode and sampling time can be configured for each group in order to meet the requirements of the application. P2.6 ch0 P2.8 ch1 P2.9 ch2 P2.10 ch3 P2.11 ch4 P2.0 ch5 P2.1 ch6 P2.2 ch7 G0 Conversion Request Control Conversion Result Handling ch1 ch2 Service Request Generation ch3 ch4 P2.3 ch5 P2.4 ch6 P2.5 ERU Analog to Digital Converter ch0 P2.7 CCU4 G1 NVIC ERU ADC Configuration ch7 VDD analog reference voltage VSS analog reference gnd Internal VAR EF Reference Voltage V Calibration AGN D XMC1100_Overview.emf Figure 15-1 Block Diagram The reference voltage of the ADC is internally generated and can be automatically calibrated to the supply voltage of the device. If required, additional calibration steps can be automatically perfomed after each conversion. The ADC offers two first-order sigma-delta loops which can be assigned to any of the input channels (Section 15.1.3). They hold the quantization error of the previous conversion in order to automatically consider this tiny amount of charge in the next Reference Manual VADC, V1.0ED4 15-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) conversion. This will increase the Effective Number Of Bits (ENOB) while implementing oversampling algorithms. The Conversion Request Control Unit (Section 15.2) controls the sampling and conversion of the analog input signal. Conversions of single channels as well as a scan of selected channels can be configured. The start of the conversion sequence is either a software command or a hardware trigger from an interconnected peripheral or a signal at a port pin. The conversion result is provided in a result register with a wait-for-read option. The waitfor-read mode avoids data loss due to premature result overwrite, by blocking a conversion until the previous result has been read. Automatic accumulation of consecutive measurements can be performed by the data reduction filter which is described in Section 15.4.4. Flexible service request generation is based on selectable events which can be routed to two interrupts. • • Source events indicate the completion of a conversion sequence in the corresponding request source. This event can be used to trigger the setup of a new sequence. Result events indicate the availability of new result data in the corresponding result register. If data reduction mode is active, events are generated only after a complete accumulation sequence. Each event can be assigned to one of four service request nodes. This allows grouping the requests according to the requirements of the application. Reference Manual VADC, V1.0ED4 15-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.1 Analog Module Activation and Control The analog converter of the ADC is the functional block that generates the digital result values from the selected input voltage. It draws a permanent current during its operation and can be deactivated between conversions to reduce the consumed overall energy. Note: After reset, the analog converters are off. They must be enabled before triggering any action involving the converter. 15.1.1 Analog Converter Control Bit ANOFF in register SHS0_SHSCFG forces the analog part into power-down mode, without changing the configuration of the associated groups. While ANOFF = 0, the analog part is enabled. Wakeup Time from Analog Powerdown When the converter is activated (ANOFF = 0), it needs a certain wakeup time to settle before a conversion can be properly executed. This wakeup time can be established by waiting the required period before starting a conversion. 15.1.2 Calibration Calibration compensates deviations caused by process, temperature, and voltage variations. This ensures accurate results throughout the operation time. Several different calibration cycles are executed for offset and gain calibration. These calibration cycles are executed alternating after a conversion. An initial startup calibration is required once after a reset. First, the converter must be enabled (ANOFF = 0B), then the startup calibration can be initiated by setting bit SUCAL in register GLOBCFG. Conversions may be started after the initial calibration sequence. This is indicated by parameter SHS0_SHSCFG.STATE which can be polled by software. The start-up calibration phase takes 1920 cycles (1920 × 31.25 ns = 60 µs). Note: Since the ADC error depends on the temperature, the calibration can be repeated periodically. 15.1.3 Sigma-Delta-Loop Function Each standard analog-to-digital conversion incurs a quantization error due to the limited number of steps i.e. discrete result values. By activating the sigma-delta-loop function this residual quantization error can be forwarded to the next conversion. The residual charge is stored and added to the next sampled charge. Averaging successive conversion results (with the loop enabled) can, therefore, reduce the quantization error. Note: The data accumulation function (see Section 15.4.4) supports this averaging. The loop control bitfields are available in pairs in register SHS0_LOOP. Reference Manual VADC, V1.0ED4 15-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.2 Conversion Request Generation The conversion request unit of a group autonomously handles the generation of conversion requests. • • • Software triggers directly activate the request source and requests a conversion. External triggers an external signal can act as conversion trigger request. As a result it synchronizes the request source activation with external events, such as a trigger pulse from a timer generating a PWM signal, or from a port pin. External gating an external signal can block a conversion request. Application software selects the trigger type and source (BRSCTRL), the gating mechanism (BRSMR) and the channel(s) to be converted (BRSSELx (x = 0 - 1)). The request source can also be activated directly by software (BRSMR.LDEV = 1) without requiring an external trigger. The conversion request is then forwarded to the converter to start the sampling and conversion of the requested channel. Figure 15-2 gives an overview to the conversion request source. BRSSEL1 -|-|0|0|0|-|0|- BRSSEL0 1|0|0|0|1|1|0|0 A Generate Load Event by software CCU40.SR 3 B CCU40.SR 2 (LDM, LDEV) G ERU0.IOUT2 H ERU0.IOUT3 M ERU0.IOUT0 N ERU0.IOUT1 Copy SEL to PND BRSPND1 -|-|0|0|0|-|0|- BRSPND0 1|0|0|0|1|1|0|0 Sequence Control scan pending channels Enable Gating Trigger Mode (ENGT, ENTR) (XTMODE) never, always, gated no, rising , falling , any XT SEL P SEV Request Conversion Channel Number Group Number GT SEL to ADC to Service Request Generation A CCU40.ST 3 B CCU40.ST 2 C CCU40.ST 1 D CCU40.ST 0 K ERU0.PDOUT2 L ERU0.PDOUT3 O ERU0.PDOUT0 P ERU0.PDOUT1 Figure 15-2 Conversion Request Source The request source can operate in single-shot (scan mode) or in continuous mode (autoscan mode): • • In single-shot mode, the programmed conversion (sequence) is requested once after being triggered. A subsequent conversion (sequence) must be triggered again. In continuous mode, the programmed conversion (sequence) is automatically requested repeatedly after being triggered once. Reference Manual VADC, V1.0ED4 15-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) External triggers are generated from one of 15 selectable trigger inputs (REQTRx[P:A]) and from one of 16 selectable gating inputs (REQGTx[P:A]). The available trigger signals for the XMC1100 are listed in Section 15.7.3. 15.2.1 Channel Scan Request Source Handling Each analog input channel can be included in or excluded from the scan sequence by setting or clearing the corresponding channel select bit in register BRSSELx (x = 0 - 1). The programmed register value remains unchanged by an ongoing scan sequence. The scan sequence starts with the highest enabled channel number and continues towards lower channel numbers. Upon a load event which is triggered by hardware signals or software, the request pattern is transferred to the pending bits in register BRSPNDx (x = 0 - 1). The pending conversion requests indicate which input channels are to be converted in an ongoing scan sequence. Each conversion start that was triggered by the scan request source, automatically clears the corresponding pending bit. If the last conversion triggered by the scan source is finished and all pending bits are cleared, the current scan sequence is considered finished and a request source event (REV) is generated. The trigger and gating unit generates load events from the selected external (outside the ADC) trigger and gating signals. For example, a timer unit can issue a request signal to synchronize conversions to PWM events. Load events start a scan sequence and can be generated either via software or via the selected hardware triggers. The request source event can also generate an automatic load event, so the programmed sequence is automatically repeated. Scan Source Operation Configure the scan request source by executing the following actions: • • • Select the input channels for the sequence by programming BRSSELx (x = 0 - 1) If hardware trigger or gating is desired, select the appropriate trigger and gating inputs and the proper signal transitions by programming BRSCTRL. Enable the trigger and select the gating mode by programming BRSMR.1) Define the load event operation (handling of pending bits, autoscan mode) by programming BRSMR. A load event with bit LDM = 0 copies the content of BRSSELx (x = 0 - 1) to BRSPNDx (x = 0 - 1) (overwrite mode). This starts a new scan sequence and aborts any pending conversions from a previous scan sequence. A load event with bit LDM = 1 OR-combines the content of BRSSELx (x = 0 - 1) to 1) If PDOUT signals from the ERU are used, initialize the ERU accordingly before enabling the gate inputs to avoid unexpected signal transitions. Reference Manual VADC, V1.0ED4 15-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) BRSPNDx (x = 0 - 1) (combine mode). This starts a scan sequence that includes pending conversions from a previous scan sequence. Start a channel scan sequence by generating a load event: • • • If a hardware trigger is selected and enabled, generate the configured transition at the selected input signal, e.g. from a timer or an input pin. or: Generate a software load event by setting LDEV = 1 ( BRSMR) or: Generate a load event by writing the scan pattern directly to the pending bits in BRSPNDx (x = 0 - 1). The pattern is copied to BRSSELx (x = 0 - 1) and a load event is generated automatically. In this case, a scan sequence can be defined and started with a single data write action (provided that the pattern fits into one register). Note: If autoscan is enabled, a load event is generated automatically each time a request source event occurs when the scan sequence has finished. This permanently repeats the defined scan sequence (autoscan). Stop or abort an ongoing scan sequence by executing one of the following actions: • • If external gating is enabled, switch the gating signal to the defined inactive level. This does not modify the conversion pending bits, but only prevents issuing conversion requests to the ADC. Disable the channel scan source by clearing bitfield ENGT = 00B. Clear the pending request bits by setting bit CLRPND = 1 ( BRSMR). Scan Request Source Events and Interrupt Service Requests A request source event of a scan source occurs when the last conversion of a scan sequence is finished (all pending bits = 0). A request source event interrupt can be generated based on a request source event. If a request source event is detected, it sets the corresponding indication flag in register GLOBEFLAG. This flag can also be set by writing 1 to the corresponding bit position, whereas writing 0 has no effect. The service request output SRx that is selected by the request source event interrupt node pointer bitfields in register GLOBEVNP becomes activated each time the related request source event is detected (and enabled by ENSI) or the related bit position in register GLOBEFLAG is written with 1 (this write action simulates a request source event). The indication flags can be cleared by SW by writing 1 to the corresponding bit position in register GLOBEFLAG.1) 1) Please refer to “Service Request Generation” on Page 15-13. Reference Manual VADC, V1.0ED4 15-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.3 Analog Input Channel Configuration The analog input channels are assigned to one of two groups. For each group a number of parameters can be configured in register GLOBICLASSy (y = 0 - 1) that control the conversion of the channels. 15.3.1 Conversion Modes A conversion can be executed in several ways. The conversion mode is selected according to the requested resolution of the digital result and according to the acceptable conversion time (Section 15.3.2). Use bitfield CMS in register GLOBICLASSy (y = 0 - 1) to select a mode. Standard Conversions A standard conversion returns a result value with a predefined resolution. 8-bit, 10-bit, and 12-bit resolution can be selected. These result values can be accumulated. Fast Compare Mode In Fast Compare Mode, the selected input voltage is directly compared with a digital value that is stored in the result register. This compare operation returns a binary result indicating the compared input voltage is above or below the given reference value. This result is generated quickly and thus supports monitoring of boundary values. Fast Compare Mode uses a 10-bit compare value stored left-aligned at bit position 11. Reference Manual VADC, V1.0ED4 15-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.3.2 Conversion Timing The total time required for a conversion comprises the time from the start of the sample phase1) until the availability of the result. The timing basis are the module clock fADC (derived from MCLK) and the converter clock fSH (typically 32 MHz). The sample rate at which consecutive conversions are triggered also depends on several configurable factors: • • The conversion time, according to the selected conversion mode. The frequency of external trigger signals, if enabled. The sample time can be adjusted according to the application requirements. Use bitfield STC in register GLOBICLASSy (y = 0 - 1) to adjust the sample time. The conversion time is the sum of sample time and conversion time. It can be computed with the following formula: tCN = (2 + STC) × 2 × tADC + 4 × tSH + (N + 8) × tSH + 5 × tADC A conversion round comprises a conversion and a calibration step. Calibration steps are executed after each conversion (up to 12 × tSH)2), so the maximum complete conversion round will take: tCR = (2 + STC) × 2 × tADC + 4 × tSH + (N + 8) × tSH + 5 × tADC + 12 × tSH2) Timing Examples System assumptions: fADC = fSH = 32 MHz i.e. tADC = tSH = 31.25 ns According to the given formula the following minimum conversion times can be achieved: 12-bit conversion: tCN12C = 2 × 2 × tADC + 4 × tSH + (12 + 8) × tSH + 5 × tADC = 33 × 31.25 ns = 1 032 ns 10-bit conversion: tCN10C = 2 × 2 × tADC + 4 × tSH + (10 + 8) × tSH + 5 × tADC = 31 × 31.25 ns = 969 ns The maximum time for an isolated conversion will take up to: tC1 = 1 032 ns + 12 × 31.25 ns = 1 407 ns (12-bit conversion)3) 1) The time from the trigger event that requests the corresponding conversion until the start of the sample phase depends on propagation delays of the selected trigger signal. 2) Offset and gain calibration steps are executed alternating, where gain calibration takes more time than offset calibration (9 cycles). 3) 12 calibration clock cycles are the maximum resulting from a gain calibration step. Reference Manual VADC, V1.0ED4 15-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.4 Conversion Result Handling The A/D converters can preprocess the conversion result data to a certain extent before storing them for retrieval by the CPU. This supports the subsequent handling of result data by the application software. Conversion result handling comprises the following functions: • • • • Storage of Conversion Results and Data Alignment Wait-for-Read Mode to avoid loss of data Result Event Generation Data Modification 15.4.1 Storage of Conversion Results The conversion result values are stored in the result register (GLOBRES). The result register has an individual data valid flag (VF) associated with it. This flag indicates when “new” valid data has been stored in the result register and can be read out. For standard conversions, result values are available in bitfield RESULT. Conversions in Fast Compare Mode use bitfield RESULT for the reference value, so the result of the operation is stored in bit FCR. The result register can be read via two different views. These views use different addresses but access the same register data: • • When the result register is read via the application view (GLOBRES), the corresponding valid flag is automatically cleared when the result is read. This provides an easy handshake between result generation and retrieval. This also supports wait-for-read mode. When the result register is read via the debug view (GLOBRESD), the corresponding valid flag remains unchanged when the result is read. This supports debugging by delivering the result value without disturbing the handshake with the application. Reference Manual VADC, V1.0ED4 15-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.4.1.1 Data Alignment The position of a conversion result value within the selected result register depends on two configurations: • • The selected result width (12/10/8 bits, see Section 15.3.1) The selected data accumulation mode (data reduction, see Section 15.4.4) These options provide the conversion results in a way that minimizes data handling for the application software. Standard Conversion Bit in Result Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 12-Bit 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 10-Bit 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 8-Bit 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 12-Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10-Bit 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 6 5 4 3 2 1 0 0 0 0 0 Accumulated Conversion 10-Bit fast compare 8-Bit 11 10 9 8 7 0 Figure 15-3 Result Register Data Alignment Bitfield RESULT of register GLOBRES must be written by SW with the wanted reference comparison value for Fast Compare Mode. In this mode, bits 11-2 are evaluated, the other bits are ignored. 15.4.2 Wait-for-Read Mode The wait-for-read mode (GLOBRCR.WFR = 1) prevents data loss due to overwriting the result register with a new conversion result before the CPU has read the previous data. Since the results come from different input channels, an overwrite may destroy the result from the previous conversion. Wait-for-read mode automatically suspends the start of a conversion until the current result has been read. As a result, a conversion or a conversion sequence can be requested by a hardware or software trigger, while each conversion is only started after the result of the previous one has been read. This automatically aligns the conversion sequence with the CPU capability to read the formerly converted result (latency). Reference Manual VADC, V1.0ED4 15-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.4.3 Result Event Generation A result event can be generated when a new value is stored in the result register. Result events can be restricted due to data accumulation and can be generated only if the accumulation is complete. Result events can also be suppressed completely. 15.4.4 Data Modification The data resulting from conversions can be automatically modified before being used by an application. The data reduction mode can be used as a digital filter for anti-aliasing or decimation purposes. It accumulates a maximum of 4 conversion values to generate a final result. The result register can be configured for data reduction, controlled by bitfield GLOBRCR.DRCTR. r1 r2 r3 r4 r5 r6 r7 r8 Conversion Results 0 3 2 1 0 3 2 1 0 DRC 0 r0 r0 + r1 r0 + r1 + r2 r0 + r1 + r2 + r3 r4 r4 + r5 r4 + r5 + r6 r4 + r5 + r6 + r7 r0 Contents of Result Reg. VF t1 t2 t3 t4 t5 t6 t7 t8 t9 MC_VADC_DRC Figure 15-4 Standard Data Reduction Filter This example shows a data reduction sequence of 4 accumulated conversion results. Eight conversion results (r0 … r7) are accumulated and produce 2 final results. When a conversion is complete, data is stored in the result register with data reduction mode enabled, and the data handling is controlled by the data reduction counter DRC: • If DRC = 0 (t1, t5, t9 in the example), the conversion result is stored to the result register. DRC is loaded with the contents of bitfield DRCTR (i.e. the accumulation begins). Reference Manual VADC, V1.0ED4 15-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) • • If DRC > 0 (t2, t3, t4 and t6, t7, t8 in the example), the conversion result is added to the value in the result register. DRC is decremented by 1. If DRC becomes 0, either decremented from 1 (t4 and t8 in the example) or loaded from DRCTR, the valid bit for the respective result register is set and a result register event occurs. The final result must be read before the next data reduction sequence starts (before t5 or t9 in the example). This automatically clears the valid flag. Note: The data reduction filter may be used with a single channel only unless averaging of several channels is intended. Reference Manual VADC, V1.0ED4 15-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.5 Service Request Generation Each A/D Converter group can activate up to 4 shared service request output signals. 2 shared request signals can issue an interrupt, see Table 15-5 “Digital Connections in the XMC1100” on Page 15-40. Several events can be assigned to each service request output. Service requests can be generated by three types of events: • • Request source events (SEV): indicate that the request source completed the requested conversion sequence and the application software can initiate further actions. The event is generated when the complete defined set of channels (pending bits) has been converted. Result events (REV): indicate a new valid result in the result register. Usually, this triggers a read action by the CPU. Optionally, result events can be generated only at a reduced rate if data reduction is active. Each ADC event is indicated by a dedicated flag that can be cleared by software. If a service request is enabled for a certain event, the service request is generated for each event, independent of the status of the corresponding event indication flag. This ensures that the ADC event can generate a service request without the need to clear the indication flag. Event flag registers indicate all types of events that occur during the ADC’s operation. Software can set/clear each flag by writing a 1 to the respective position in register GLOBEFLAG to trigger/clear an event. If enabled, service requests are generated for each occurrance of an event, even if the associated flag remains set. Node Pointer Registers Requests from each event source can be directed to a set of service request nodes via associated node pointers. Requests from several sources can be directed to the same node; in this case, they are ORed to the service request output signal. Reference Manual VADC, V1.0ED4 15-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6 Registers The register map of the ADC is built from two blocks, the VADC0 and the SHS0. The corresponding registers, therefore, have an individual offset assigned (see Table 15-2). The exact register location is obtained by adding the respective register offset to the base address (see Table 15-1) of the corresponding block. Table 15-1 Registers Address Space Module Base Address End Address VADC0 4803 0000H 4803 03FFH SHS0 4803 4000H 4803 41FFH Table 15-2 Note Registers Overview Register Short Register Long Name Name Offset Addr. Access Mode Page Read Write Num. VADC0 Register ID Module Identification Register 0008H U, PV BE 15-16 CLC Clock Control Register 0000H U, PV PV 15-17 15-18 OCS OCDS Control and Status Register 0028H U, PV PV GLOBCFG Global Configuration Register 0080H U, PV U, PV 15-20 BRSCTRL Request Source Control Register 0200H U, PV U, PV 15-23 BRSMR Request Source Mode Register 0204H U, PV U, PV 15-25 BRSSEL0 Request Source Channel Select Register, Group 0 0180H U, PV U, PV 15-27 BRSSEL1 Request Source Channel Select Register, Group 1 0184H U, PV U, PV 15-27 BRSPND0 Request Source Channel Pending Register, Group 0 01C0H U, PV U, PV 15-28 BRSPND1 Request Source Channel Pending Register, Group 1 01C4H U, PV U, PV 15-28 GLOBICLASS0 Input Class Register 0 00A0H U, PV U, PV 15-29 GLOBICLASS1 Input Class Register 1 00A4H U, PV U, PV 15-29 GLOBRCR Result Control Register 0280H U, PV U, PV 15-31 GLOBRES Result Register 0300H U, PV U, PV 15-32 GLOBRESD Result Register (debug view) 0380H U, PV U, PV 15-32 Reference Manual VADC, V1.0ED4 15-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Table 15-2 Registers Overview (cont’d) Register Short Register Long Name Name Offset Addr. Access Mode Page Read Write Num. GLOBEFLAG Event Flag Register 00E0H U, PV U, PV 15-36 GLOBEVNP Event Node Pointer Register 0140H U, PV U, PV 15-37 SHS0 Register SHS0_ID SHS Module Identification Register 0008H U, SV U, SV 15-16 SHSCFG SHS Configuration Register 0040H U, SV U, SV 15-21 GNCTR00 Gain Control Register 0, Group 0 0180H U, SV U, SV 15-33 GNCTR10 Gain Control Register 0, Group 1 0190H U, SV U, SV 15-33 LOOP SD Loop Control Register 0050H U, SV U, SV 15-35 Reference Manual VADC, V1.0ED4 15-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.1 Module Identification The module identification register indicates the version of the ADC module that is used in the XMC1100. ID Module Identification Register SHS0_ID Module Identification Register (0008H) Reset Value: 00C5 C0XXH (4803 4008H) Reset Value: 0099 C0XXH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD_NUMBER MOD_TYPE MOD_REV r r r Field Bits Type Description MOD_REV [7:0] r Module Revision Indicates the revision number of the implementation. This information depends on the design step. MOD_TYPE [15:8] r Module Type This internal marker is fixed to C0H. MOD_NUMBER [31:16] r Reference Manual VADC, V1.0ED4 Module Number Indicates the module identification number (00C5H = SARADC, 0099H = SHS). 15-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.2 System Registers A set of standardized registers provides general access to the module and controls basic system functions. The Clock Control Register CLC allows the programmer to adapt the functionality and power consumption of the module to the requirements of the application. Register CLC controls the module clock signal and the reactivity to the sleep mode signal. CLC Clock Control Register (0000H) Reset Value: 0000 0003H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DIS S DIS R r r rw 0 0 0 0 0 0 0 0 0 0 0 0 E DIS r r r r r r r r r r r r rw Field Bits Type Description DISR 0 rw Module Disable Request Bit Used for enable/disable control of the module. Also the analog section is disabled by clearing ANONS. 0B On request: enable the module clock Off request: stop the module clock 1B DISS 1 r Module Disable Status Bit 0B Module clock is enabled 1B Off: module is not clocked 0 2 r Reserved, write 0, read as 0 EDIS 3 rw Sleep Mode Enable Control Used to control module’s reaction to sleep mode. 0B Sleep mode request is enabled and functional 1B Module disregards the sleep mode control signal 0 [31:4] r Reserved, write 0, read as 0 Reference Manual VADC, V1.0ED4 15-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) The OCDS control and status register OCS controls the module’s behavior in suspend mode (used for debugging). The OCDS Control and Status (OCS) register is cleared by Debug Reset. The OCS register can only be written when the OCDS is enabled. If OCDS is being disabled, the OCS register value will not change. When OCDS is disabled the OCS suspend control is ineffective. Write access is 32 bit wide only and requires Supervisor Mode. OCS OCDS Control and Status Register 31 30 29 28 27 26 0 0 r r rh w 15 14 13 12 11 10 9 0 0 0 0 0 0 r r r r r r SUS SUS STA _P 25 (0028H) 24 Reset Value: 0000 0000H 23 22 21 20 19 18 17 16 SUS 0 0 0 0 0 0 0 0 rw r r r r r r r r 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r Field Bits Type Description 0 [23:0] r Reserved, write 0, read as 0 SUS [27:24] rw OCDS Suspend Control Controls the sensitivity to the suspend signal coming from the OCDS Trigger Switch (OTGS) 0000BWill not suspend 0001BHard suspend: Clock is switched off immediately. 0010BSoft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter. 0011BSoft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round. others: Reserved SUS_P 28 w SUS Write Protection SUS is only written when SUS_P is 1, otherwise unchanged. Read as 0. Reference Manual VADC, V1.0ED4 15-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits Type Description SUSSTA 29 rh Suspend State 0B Module is not (yet) suspended Module is suspended 1B 0 [31:30] r Reserved, write 0, read as 0 Reference Manual VADC, V1.0ED4 15-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.3 General Registers The global configuration register provides global control and configuration options that are valid for all converters of the cluster. GLOBCFG Global Configuration Register (0080H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SU CAL 0 0 0 0 0 0 0 0 0 0 0 0 0 w r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r DP DP CAL CAL 1 0 rw rw Field Bits Type Description 0 [15:0] r Reserved, write 0, read as 0 DPCALx (x = 0 - 1) x+16 rw Disable Post-Calibration 0B Automatic post-calibration after each conversion of group x No post-calibration 1B Note: This bit is only valid for the calibrated converter. 0 [30:18] r Reserved, write 0, read as 0 SUCAL 31 Start-Up Calibration The 0-1 transition of bit SUCAL initiates the start-up calibration phase of all calibrated analog converters. No action 0B 1B Initiate the start-up calibration phase (indication in SHS0_SHSCFG.STATE) Reference Manual VADC, V1.0ED4 w 15-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) SHS0_SHSCFG SHS Configuration Register 31 15 30 29 26 25 24 23 22 21 20 19 18 STATE 0 0 0 0 0 0 0 0 0 0 rh r r r r r r r r r r rh rh 11 10 9 8 7 6 5 4 3 2 1 0 SC AN WC RDY w Reset Value: 0000 1000H 27 14 rh 28 (4803 4040H) 17 16 SP1 SP0 13 12 0 AN OFF AREF 0 0 0 0 0 0 0 0 0 0 r rw rw r r r r r r r r r r Field Bits Type Description 0 [9:0] r AREF [11:10] rw Analog Reference Voltage Selection 00B External reference, upper supply range 01B Reserved 10B Internal reference, upper supply range 11B Internal reference, lower supply range ANOFF 12 rw Analog Converter Power Down Force1) 0B Converter controlled by bitfields ANONS (digital control block) Converter is permanently off 1B Reserved, write 0, read as 0 0 13 r Reserved, write 0, read as 0 ANRDY 14 rh Analog Converter Ready 0B Converter is in power-down mode 1B Converter is operable SCWC 15 w Write Control for SHS Configuration 0B No write access to SHS configuration 1B Bitfields ANOFF, AREF can be written SP0, SP1 16, 17 rh Sample Pending on Group x 0B No sample pending Group x has finished the sample phase 1B 0 [27:18] r Reference Manual VADC, V1.0ED4 Reserved, write 0, read as 0 15-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits STATE [31:28] rh Type Description Current State of Sequencer 0000B Idle 0001B Offset calibration active 0010B Gain calibration active 0011B Startup calibration active Others: Normal operation 1) See also “Analog Converter Control” on Page 15-3. Reference Manual VADC, V1.0ED4 15-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.4 Conversion Request Source Registers The control register of the request source selects the external gate and/or trigger signals. Write control bits allow separate control of each function with a simple write access. BRSCTRL Request Source Control Register (0200H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 0 0 0 GT WC 0 0 GT LVL GT SEL r r r r r r r r w r r rh rw 15 14 13 12 11 10 9 8 16 7 6 5 4 3 2 1 0 XT WC XT MODE XT LVL XT SEL 0 0 0 0 0 0 0 0 w rw rh rw r r r r r r r r Field Bits Type Description 0 [7:0] r Reserved, write 0, read as 0 XTSEL [11:8] rw External Trigger Input Selection The connected trigger input signals are listed in Table 15-5 “Digital Connections in the XMC1100” on Page 15-40 Note: XTSEL = 1111B uses the selected gate input as trigger source (ENGT must be 0XB). XTLVL 12 XTMODE [14:13] rw Trigger Operating Mode 00B No external trigger 01B Trigger event upon a falling edge 10B Trigger event upon a rising edge 11B Trigger event upon any edge XTWC 15 Write Control for Trigger Configuration 0B No write access to trigger configuration 1B Bitfields XTMODE and XTSEL can be written Reference Manual VADC, V1.0ED4 rh w External Trigger Level Current level of the selected trigger input 15-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits GTSEL [19:16] rw Type Description Gate Input Selection The connected gate input signals are listed in Table 15-5 “Digital Connections in the XMC1100” on Page 15-40 GTLVL 20 Gate Input Level Current level of the selected gate input rh 0 [22:21] r Reserved, write 0, read as 0 GTWC 23 Write Control for Gate Configuration 0B No write access to gate configuration 1B Bitfield GTSEL can be written 0 [31:24] r Reference Manual VADC, V1.0ED4 w Reserved, write 0, read as 0 15-24 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) The Conversion Request Mode Register configures the operating mode of the background request source. BRSMR Request Source Mode Register (0204H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 r r r r r r LD CLR REQ EV PND GT w w rh Field Bits Type Description ENGT [1:0] rw 0 r SCA EN LDM N SI rw rw rw EN TR ENGT rw rw Enable Gate Selects the gating functionality for source 1. 00B No conversion requests are issued 01B Conversion requests are issued if at least one pending bit is set 10B Conversion requests are issued if at least one pending bit is set and REQGTx = 1. 11B Conversion requests are issued if at least one pending bit is set and REQGTx = 0. Note: REQGTx is the selected gating signal. ENTR 2 rw Enable External Trigger 0B External trigger disabled 1B The selected edge at the selected trigger input signal REQTR generates the load event ENSI 3 rw Enable Source Interrupt 0B No request source interrupt 1B A request source interrupt is generated upon a request source event (last pending conversion is finished) Reference Manual VADC, V1.0ED4 15-25 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits Type Description SCAN 4 rw Autoscan Enable 0B No autoscan Autoscan functionality enabled: 1B a request source event automatically generates a load event LDM 5 rw Autoscan Source Load Event Mode 0B Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event Combine mode: 1B Set all pending bits that are set in the select registers upon a load event (logic OR) 0 6 r Reserved, write 0, read as 0 REQGT 7 rh Request Gate Level Monitors the level at the selected REQGT input. 0B The gate input is low 1B The gate input is high CLRPND 8 w Clear Pending Bits 0B No action The bits in registers BRSPNDx are cleared 1B LDEV 9 w Generate Load Event 0B No action 1B A load event is generated 0 [31:10] r Reference Manual VADC, V1.0ED4 Reserved, write 0, read as 0 15-26 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) The Channel Select Registers select the channels to be converted by the request source. Its bits are used to update the pending registers, when a load event occurs. The number of valid channel bits depends on the channels available in the respective product type (please refer to “Product-Specific Configuration” on Page 15-39). BRSSELx (x = 0 - 1) Request Source Channel Select Register, Group x (0180H + x * 0004H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r r r r r r r r CH CH CH CH CH CH CH CH SEL SEL SEL SEL SEL SEL SEL SEL G7 G6 G5 G4 G3 G2 G1 G0 rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description CHSELGy (y = 0 - 7) y rwh Channel Selection Group x Each bit (when set) enables the corresponding input channel of the respective group to take part in the background scan sequence. Ignore this channel 0B 1B This channel is part of the scan sequence 0 [31:8] r Reserved, write 0, read as 0 Reference Manual VADC, V1.0ED4 15-27 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) The Channel Pending Registers indicate the channels to be converted in the current conversion sequence. They are updated from the select registers, when a load event occurs. BRSPNDx (x = 0 - 1) Request Source Pending Register, Group x (01C0H + x * 0004H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 r r r r r r r r 7 6 5 4 3 2 1 0 CH PND G7 rwh CH PND G6 rwh CH PND G5 rwh CH PND G4 rwh CH PND G3 rwh CH PND G2 rwh CH PND G1 rwh CH PND G0 rwh Field Bits Type Description CHPNDGy (y = 0 - 7) y rwh Channels Pending Group x Each bit (when set) request the conversion of the corresponding input channel of the respective group. 0B Ignore this channel Request conversion of this channel 1B 0 [31:8] r Reserved, write 0, read as 0 Note: Writing to any of registers BRSPNDx automatically updates the corresponding register BRSSELx and generates a load event that copies all bits from all registers BRSSELx to BRSPNDx. Use this shortcut only when writing the last word of the request pattern. Reference Manual VADC, V1.0ED4 15-28 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.5 Channel Control Registers GLOBICLASSy (y = 0 - 1) Input Class Register y (00A0H + y * 0004H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 CMS 0 0 0 STCS r r r r r rw r r r rw Field Bits Type Description STCS [4:0] rw Sample Time Control for Standard Conversions Number of additional clock cycles to be added to the minimum sample phase of 2 analog clock cycles: Coding and resulting sample time see Table 15-3. 0 [7:5] r Reserved, write 0, read as 0 CMS [10:8] rw Conversion Mode for Standard Conversions 000B 12-bit conversion 001B 10-bit conversion 010B 8-bit conversion 011B Reserved 100B Reserved 101B 10-bit fast compare mode 110B Reserved 111B Reserved 0 [31:11] r Table 15-3 Reserved, write 0, read as 0 Sample Time Coding STCS Additional Clock Cycles Sample Time 0 0000B 0 2 / fADCI 0 0001B 1 3 / fADCI … … … Reference Manual VADC, V1.0ED4 15-29 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Table 15-3 Sample Time Coding (cont’d) STCS Additional Clock Cycles Sample Time 0 1111B 15 17 / fADCI 1 0000B 16 18 / fADCI 1 0001B 32 34 / fADCI … … … 1 1110B 240 242 / fADCI 1 1111B 256 258 / fADCI Reference Manual VADC, V1.0ED4 15-30 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.6 Result Register The result control register selects the behavior of the result register. GLOBRCR Result Control Register (0280H) Reset Value: 0100 0000H 31 30 29 28 27 26 25 24 23 22 21 20 SRG EN 19 18 17 16 0 0 0 0 0 0 WFR 0 0 0 0 DRCTR rw r r r r r r rw r r r r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r Field Bits Type Description 0 [15:0] r DRCTR [19:16] rw Data Reduction Control Defines how result values are stored/accumulated in this register for the final result. The data reduction counter DRC can be loaded from this bitfield. 0000BData reduction disabled 0001BAccumulate 2 result values 0010BAccumulate 3 result values 0011BAccumulate 4 result values others: Reserved 0 [23:20] r Reserved, write 0, read as 0 WFR 24 Wait-for-Read Mode Enable 0B Overwrite mode 1B Wait-for-read mode enabled for this register 0 [30:25] r Reserved, write 0, read as 0 SRGEN 31 Service Request Generation Enable 0B No service request 1B Service request after a result event Reference Manual VADC, V1.0ED4 rw rw Reserved, write 0, read as 0 15-31 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) The result register provides a common storage location for all channels of all groups. GLOBRES Result Register, Application view GLOBRESD Result Register, Debug view (0300H) Reset Value: 0000 0000H (0380H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 VF FCR 1 0 0 0 0 CHNR GNR rwh rh r r r r r rh rh 15 14 13 12 11 10 9 8 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 RESULT rwh Field Bits Type Description RESULT [15:0] rwh GNR [19:16] rh Group Number Indicates the group to which the channel number in bitfield CHNR refers. CHNR [24:20] rh Channel Number Indicates the channel number corresponding to the value in bitfield RESULT. Result of most recent conversion The position of the result bits within this bitfield depends on the configured operating mode.1) Please, refer to Section 15.4.1.1. 0 [28:25] r Reserved, read as 0 1 29 r Reserved, read as 1 FCR 30 rh Fast Compare Result Indicates the result of an operation in Fast Compare Mode. Signal level was below compare value 0B 1B Signal level was above compare value Reference Manual VADC, V1.0ED4 15-32 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits Type Description VF 31 rwh Valid Flag Indicates a new result in bitfield RESULT or bit FCR. Read access: No new valid data available 0B Write access: No effect 1B Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action)1) 1) Only writable in register GLOBRES, not in register GLOBRESD. 15.6.7 Gain Control Register The gain control registers GNCTRx0 selects the gain level for each input. SHS0_GNCTR00 Gain Control Register 00 SHS0_GNCTR10 Gain Control Register 10 31 15 30 29 28 27 26 25 (4803 4180H) Reset Value: 0000 0000H (4803 4190H) Reset Value: 0000 0000H 24 23 22 21 20 19 18 17 GAIN7 GAIN6 GAIN5 GAIN4 rw rw rw rw 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GAIN3 GAIN2 GAIN1 GAIN0 rw rw rw rw Field Bits GAINz (z = 0 - 7) [z*4+3: rw z*4] Reference Manual VADC, V1.0ED4 16 0 Type Description Gain Control z 0000BGain factor = 1 0001BGain factor = 3 0010BGain factor = 6 0011BGain factor = 12 Others: Reserved 15-33 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Note: The first index (x0) indicates the associated group. The channel number is z. Reference Manual VADC, V1.0ED4 15-34 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.8 Miscellaneous Registers The sigma-delta-loop control register LOOP configures the functionality of the sigmadelta-loop(s). SHS0_LOOP Loop Control Register (4803 4050H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 LP EN1 0 0 0 0 0 0 LP SH1 0 0 0 LPCH1 rw r r r r r r rw r r r rw 15 14 13 12 11 10 9 8 7 6 5 0 0 0 LPCH0 r r r rw LP EN0 0 0 0 0 0 0 LP SH0 rw r r r r r r rw 20 4 19 18 3 2 17 16 1 0 Field Bits Type Description LPCH0, LPCH1 [4:0], rw [20:16] Loop y Channel Selects the input channel, for which the sigma-deltaloop function shall be enabled. 0 [7:5] r Reserved, write 0, read as 0 LPSH0, LPSH1 8, 24 rw Loop y Group Select Selects the group, to which the indicated channel is assigned. 0 [14:9] r Reserved, write 0, read as 0 LPEN0, LPEN1 15, 31 rw Loop y Enable 0H Off: standard operation 1H ON: sigma-delta-loop is active 0 [23:21] r Reserved, write 0, read as 0 0 [30:25] r Reserved, write 0, read as 0 Note: Bitfields LPSHy and LPCHy together select one individual input channel that is associated with the corresponding sigma-delta loop. Reference Manual VADC, V1.0ED4 15-35 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.6.9 Service Request Registers GLOBEFLAG Event Flag Register 31 30 29 28 (00E0H) 27 26 25 24 REV GLB CLR w 23 Reset Value: 0000 0000H 22 21 20 19 0 0 0 0 0 0 0 r r r r r r r 15 14 13 12 11 10 9 8 0 0 0 0 0 r r r r r 0 0 0 0 0 0 0 REV GLB r r r r r r r rwh 18 17 16 SEV GLB CLR w 0 0 0 0 0 0 0 r r r r r r r 7 6 5 4 3 2 1 0 0 0 SEV GLB r r rwh Field Bits Type Description SEVGLB 0 rwh Source Event 0B No source event A source event has occurred 1B 0 [7:1] r Reserved, write 0, read as 0 REVGLB 8 rwh Result Event 0B No result event New result was stored in register GLOBRES 1B 0 [15:9] r Reserved, write 0, read as 0 SEVGLBCLR 16 w Clear Source Event 0B No action Clear the source event flag SEVGLB 1B 0 [23:17] r Reserved, write 0, read as 0 REVGLBCLR 24 Clear Result Event 0B No action Clear the result event flag REVGLB 1B 0 [31:25] r w Reserved, write 0, read as 0 Note: Software can set flags REVGLB and SEVGLB and trigger the corresponding event by writing 1 to the respective bit. Writing 0 has no effect. Software can clear these flags by writing 1 to bit REVGLBCLR and SECGLBCLR, respectively. Reference Manual VADC, V1.0ED4 15-36 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Setting both bits (e.g. SEVGLB and SEVGLBCLR) simultaneously clears the corresponding flag (e.g. SEVGLB). GLOBEVNP Event Node Pointer Register (0140H) Reset Value: 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 0 0 0 0 0 0 0 REV0NP r r r r r r r r r r r r rw 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SEV0NP r r r r r r r r r r r r rw Field Bits Type Description SEV0NP [3:0] rw Reference Manual VADC, V1.0ED4 [15:4] r 3 18 17 2 1 16 0 Service Request Node Pointer Source Event Routes the corresponding event trigger to one of the service request lines (nodes). 0000BSelect shared service request line 0 of common service request group 0 … 0011BSelect shared service request line 3 of common service request group 0 others: Reserved Note: For shared Table 15-5. 0 19 service request lines see Reserved, write 0, read as 0 15-37 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Field Bits REV0NP [19:16] rw Type Description Service Request Node Pointer Result Event Routes the corresponding event trigger to one of the service request lines (nodes). 0000BSelect shared service request line 0 of common service request group 0 … 0011BSelect shared service request line 3 of common service request group 0 others: Reserved Note: For shared Table 15-5. 0 Reference Manual VADC, V1.0ED4 [31:20] r service request lines see Reserved, write 0, read as 0 15-38 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.7 Interconnects This section describes the actual implementation of the VADC module into the XMC1100, i.e. the incorporation into the microcontroller system. 15.7.1 Product-Specific Configuration The functional description describes the features and operating modes of the A/D Converters in a general way. This section summarizes the configuration that is available in this product (XMC1100). 15.7.2 Analog Module Connections in the XMC1100 The VADC module accepts a number of analog input signals. The analog input multiplexers select the input channels from the signals available in this product. The exact number of analog input channels and the available connection to port pins depend on the employed product type. A summary of channels enclosing all versions of the XMC1100 can be found in Table 15-4. Table 15-4 Analog Connections in the XMC1100 Signal Dir. Source/Destin. Description Reference Voltage Pins VAREF VAGND I VDD positive analog reference I VSS negative analog reference Group 0 Analog Inputs, controlled by input class 0 G0CH0 I P2.6 analog input channel 0 of group 0 G0CH1 I P2.8 analog input channel 1 of group 0 G0CH2 I P2.9 analog input channel 2 of group 0 G0CH3 I P2.10 analog input channel 3 of group 0 G0CH4 I P2.11 analog input channel 4 of group 0 G0CH5 I P2.0 analog input channel 5 of group 0 G0CH6 I P2.1 analog input channel 6 of group 0 G0CH7 I P2.2 analog input channel 7 of group 0 Group 1 Analog Inputs, controlled by input class 1 G1CH1 I P2.7 analog input channel 1 of group 1 G1CH5 I P2.3 analog input channel 5 of group 1 G1CH6 I P2.4 analog input channel 6 of group 1 G1CH7 I P2.5 analog input channel 7 of group 1 Reference Manual VADC, V1.0ED4 15-39 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) 15.7.3 Digital Module Connections in the XMC1100 The VADC module accepts a number of digital input signals and generates a number of output signals. This section summarizes the connection of these signals to other on-chip modules or to external resources via port pins. Note: The control bitfields for triggers and gates select the corresponding multiplexer input. Values 0000B … 1111B select inputs with suffix -A … -P. Table 15-5 Digital Connections in the XMC1100 Signal Dir. Source/Destin. Description Gate Inputs BGREQGTA I CCU40.ST3 Gating input A (GTSEL = 0000B) BGREQGTB I CCU40.ST2 Gating input B (GTSEL = 0001B) BGREQGTC I CCU40.ST1 Gating input C (GTSEL = 0010B) BGREQGTD I CCU40.ST0 Gating input D (GTSEL = 0011B) BGREQGTE I 0 Gating input E (GTSEL = 0100B) BGREQGTF I 0 Gating input F (GTSEL = 0101B) BGREQGTG I 0 Gating input G (GTSEL = 0110B) BGREQGTH I 0 Gating input H (GTSEL = 0111B) BGREQGTI I 0 Gating input I (GTSEL = 1000B) BGREQGTJ I 0 Gating input J (GTSEL = 1001B) BGREQGTK I ERU0.PDOUT2 Gating input K (GTSEL = 1010B) BGREQGTL I ERU0.PDOUT3 Gating input L (GTSEL = 1011B) BGREQGTM I 0 Gating input M (GTSEL = 1100B) BGREQGTN I 0 Gating input N (GTSEL = 1101B) BGREQGTO I ERU0.PDOUT0 Gating input O (GTSEL = 1110B) BGREQGTP I ERU0.PDOUT1 Gating input P (GTSEL = 1111B) BGREQGTSEL 1) O BGREQTRP Selected gating signal BGREQTRA I CCU40.SR2 Trigger input A (XTSEL = 0000B) BGREQTRB I CCU40.SR3 Trigger input B (XTSEL = 0001B) BGREQTRC I 0 Trigger input C (XTSEL = 0010B) BGREQTRD I 0 Trigger input D (XTSEL = 0011B) BGREQTRE I 0 Trigger input E (XTSEL = 0100B) Trigger Inputs Reference Manual VADC, V1.0ED4 15-40 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Table 15-5 Digital Connections in the XMC1100 (cont’d) Signal Dir. Source/Destin. Description BGREQTRF I 0 Trigger input F (XTSEL = 0101B) BGREQTRG I ERU0.IOUT2 Trigger input G (XTSEL = 0110B) BGREQTRH I ERU0.IOUT3 Trigger input H (XTSEL = 0111B) BGREQTRI I 0 Trigger input I (XTSEL = 1000B) BGREQTRJ I 0 Trigger input J (XTSEL = 1001B) BGREQTRK I 0 Trigger input K (XTSEL = 1010B) BGREQTRL I 0 Trigger input L (XTSEL = 1011B) BGREQTRM I ERU0.IOUT0 Trigger input M (XTSEL = 1100B) BGREQTRN I ERU0.IOUT1 Trigger input N (XTSEL = 1101B) BGREQTRO I 0 Trigger input O (XTSEL = 1110B) BGREQTRP I BGREQGTSEL1) Extend triggers to selected gating input (XTSEL = 1111B) System-Internal Connections C0SR0 O NVIC (15) Service request 0 of common block 0 C0SR1 O NVIC (16) Service request 1 of common block 0 C0SR2 O ERU0.OGU02 ERU0.OGU12 Service request 2 of common block 0 C0SR3 O ERU0.OGU22 ERU0.OGU32 Service request 3 of common block 0 1) Internal signal connection. Reference Manual VADC, V1.0ED4 15-41 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Analog-to-Digital Converter (VADC) Reference Manual VADC, V1.0ED4 15-42 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Temperature Sensor (TSE) 16 Temperature Sensor (TSE) This chapter describes the controls for Temperature Sensor (TSE). 16.1 General Description The Temperature Sensor (TSE) generates a measurement result that indicates directly the current temperature. The result of the measurement is displayed via bit field ANATSEMON.TSE_MON. The user routines (_CalcTemperature) inside ROM takes this value and calulate the actual silicon temperature. This routine can be called by the application software and more details are described in Chapter “Bootstrap Loaders and User Routines”. Library functions are also available and described in the Temperature Sensor device guide. The TSE has to be enabled before it can be used via bit ANATSECTRL.TSE_EN. The measurement result is ready when the SRRAW.TSE_DONE flag is set. An interrupt can be triggered when it is enabled via SRMSK.TSE_DONE bit. After the measurement is completed and result is stored in TSE_MON, TSE continue with next measurement. Measurement are disabled when TSE_EN is cleared to 0. Hence, reading the TSE_MON value will provide you the latest temperature. The TSE is capable of generating interrupt requests when TSE temperature measurement in result crosses upper and/or lower threshold value configured in bit ANATSEIH.TSE_IH and ANATSEIL.TSE_IL respectively. Digital comparators are implemented to compare the actual measurement result against configured limits and triggers interrupt if the value fall outside of valid range. Result of comparison is shown as the SRRAW.TSE_HIGH and TSE_LOW flag. The user routines (_CalcTSEVAR) can be used to obtain the upper and lower temperature limits needed to program the bit TSE_IH and TSE_IL and more details are described in Chapter “Bootstrap Loaders and User Routines”. Library functions are also available and described in the Temperature Sensor device guide. 16.2 Service Request Generation The TSE has a service request output for TSE Done, TSE HIGH and TSE Low event. They are combined with events from other modules into a single output and connected to one of the interrupt node in the Nested Vectored Interrupt Controller (NVIC) via SCU.SR1. The service request handling is part of the GCU block in SCU module. Refer to the “Service Request” description in the GCU section which is part of the SCU chapter for more details. Reference Manual TSE, V1.1 16-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Temperature Sensor (TSE) 16.3 Registers TSE registers are accessible via the APB bus. The absolute register address is calculated by adding: Module Base Address + Offset Address Following access to TSE SFRs result in an AHB/APB error response: • • Read or write access to undefined address Write access to read-only registers Table 16-1 Registers Address Space Module Base Address End Address Note TSE 4001 0000H 4001 FFFFH System Control Unit Registers Table 16-2 Registers Overview Short Name Description Offset Access Mode Description Addr.1) Read Write See ANATSECTRL Temperature Sensor Control Register 0024H U, PV U, PV Page 16-3 ANATSEIH Temperature Sensor High 0030H Interrupt Register U, PV U, PV Page 16-3 ANATSEIL Temperature Sensor Low 0034H Interrupt Register U, PV U, PV Page 16-4 ANATSEMON Temperature Sensor Counter2 Monitor Register U, PV U, PV Page 16-4 0040H 1) The absolute register address is calculated as follows: Module Base Address + Offset Address (shown in this column) 16.3.1 Registers ANATSECTRL Temperature Sensor Control Register Reference Manual TSE, V1.1 16-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Temperature Sensor (TSE) ANATSECTRL Temperature Sensor Control Register (1024H) 15 14 13 12 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 2 1 0 0 TSE _EN r rw Field Bits Type Description TSE_EN 0 rw Temperature sensor enable 0B Temperature sensor is disabled 1B Temperature sensor is switched on 0 15:1 r Reserved Read as 0; should be written with 0. ANATSEIH Temperature Sensor High Temperature Interrupt Register ANATSEIH Temperature Sensor High Temperature Interrupt Register (1030H) 15 14 13 12 11 10 9 8 7 6 5 Reset Value: 0000H 4 3 2 1 0 TSE_IH rw Field Bits Type Description TSE_IH 15:0 rw Counter value for high temperature interrupt ANATSEIH value is compared with ANATSEMON (with the counter value) An high temperature interrupt is triggered if: ANATSE_MON < ANATSEIH The comparison result can be observed from SCU_SRRAW.TSE_HIGH Reference Manual TSE, V1.1 16-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Temperature Sensor (TSE) ANATSEIL Temperature Sensor Low Temperature Interrupt Register ANATSEIL Temperature Sensor Low Temperature Interrupt Register (1034H) 15 14 13 12 11 10 9 8 7 6 5 Reset Value: FFFFH 4 3 2 1 0 TSE_IL rw Field Bits Type Description TSE_IL 15:0 rw Counter value for low temperature interrupt ANATSEIL value is compared with ANATSEMON An low interrupt is triggered if: ANATSEMON > ANATSEIL The comparison result can be observed from SCU_SRRAW.TSE_LOW ANATSEMON Temperature Sensor Counter2 Monitor Register ANATSEMON Temperature Sensor Counter2 Monitor Register (1040H) 15 14 13 12 11 10 9 8 7 6 Reset Value: 0000H 5 4 3 2 1 0 TSE_MON rh Reference Manual TSE, V1.1 16-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Temperature Sensor (TSE) Field Bits Type Description TSE_MON 15:0 rh Reference Manual TSE, V1.1 Monitor Counter2 value; loaded by TSE_DONE After each measurement done event (indicated by a set in SCU_SRRAW.TSE_DONE bit), the result is stored in this register. 16-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17 Capture/Compare Unit 4 (CCU4) The CCU4 peripheral is a major component for systems that need general purpose timers for signal monitoring/conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like switched mode power supplies or uninterruptible power supplies, can easily be implemented with the functions inside the CCU4 peripheral. The internal modularity of CCU4, translates into a software friendly system for fast code development and portability between applications. Table 17-1 Abbreviations table PWM Pulse Width Modulation CCU4x Capture/Compare Unit 4 module instance x CC4y Capture/Compare Unit 4 Timer Slice instance y ADC Analog to Digital Converter POSIF Position Interface peripheral SCU System Control Unit fccu4 CCU4 module clock frequency ftclk CC4y timer clock frequency Note: A small “y” or “x” letter in a register indicates an index 17.1 Overview Each CCU4 module is comprised of four identical 16 bit Capture/Compare Timer slices, CC4y. Each timer slice can work in compare mode or in capture mode. In compare mode one compare channel is available while in capture mode, up to four capture registers can be used in parallel. Each CCU4 module has four service request lines and each timer slice contains a dedicated output signal, enabling the generation of up to four independent PWM signals. Straightforward timer slice concatenation is also possible, enabling up to 64 bit timing operations. This offers a flexible frequency measurement, frequency multiplication and pulse width modulation scheme. A programmable function input selector for each timer slice, that offers up to nine functions, discards the need of complete resource mapping due to input ports availability. A built-in link between the CCU4 and several other modules enable flexible digital motor control loops implementation, e.g. with Hall Sensor monitoring or direct coupling with Encoders. Reference Manual CCU4, V1.15 17-1 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.1.1 Features CCU4 module features Each CCU4 represents a combination of four timer slices, that can work independently in compare or capture mode. Each timer slice has a dedicated output for PWM signal generation. All four CCU4 timer slices, CC4y, are identical in terms of available functions and operating modes. Avoiding this way the need of implementing different software routines, depending on which resource of CCU4 is used. A built-in link between the four timer slices is also available, enabling this way a simplified timer concatenation and sequential operations. General Features • • • • • • • • • • • • • • 16 bit timer cells capture and compare mode for each timer slice – four capture registers in capture mode – one compare channel in compare mode programmable low pass filter for the inputs built-in timer concatenation – 32, 48 or 64 bit width shadow transfer for the period and compare values programmable clock prescaler normal timer mode gated timer mode three counting schemes – center aligned – edge aligned – single shot PWM generation TRAP function start/stop can be controlled by external events counting external events four dedicated service request lines per CCU4 Additional features • • • • • • external modulation function load controlled by external events dithering PWM floating point pre scaler output state override by an external event suitable and flexible connectivity to several modules: – motor and power conversion applications – high number of signal conditioning possibilities Reference Manual CCU4, V1.15 17-2 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCU4 features vs. applications On Table 17-2 a summary of the major features of the CCU4 unit mapped with the most common applications. Table 17-2 Applications summary Feature Applications Four independent timer cells Independent PWM generation: • Multiple buck/boost converter control (with independent frequencies) • Different modes of operation for each timer, increasing the resource optimization • Up to 2 Half-Bridges control • multiple Zero Voltage Switch (ZVS) converter control with easy link to the ADC channels. Concatenated timer cells Easy to configure timer extension up to 64 bit: • High dynamic trigger capturing • High dynamic signal measurement Dithering PWM Generating a fractional PWM frequency or duty cycle: • To avoid big steps on frequency or duty cycle adjustment in slow control loop applications • Increase the PWM signal resolution over time Floating prescaler Automated control signal measurement: • decrease SW activity for monitoring signals with high or unknown dynamics • emulating more than a 16 bit timer for system control Up to 9 functions via external signals for each timer Flexible resource optimization: • The complete set of external functions is always available • Several arrangements can be done inside a CCU4, e.g., one timer working in capture mode and one working in compare Reference Manual CCU4, V1.15 17-3 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-2 Applications summary (cont’d) Feature Applications 4 dedicated service request lines Specially developed for: • generating interrupts for the microprocessor • flexible connectivity between peripherals, e.g. ADC triggering. Linking with other modules 17.1.2 Flexible profiles for: • Hall Sensor feedback/monitoring • Motor Encoders feedback/monitoring • PWM parallel modulation • Flexible signal conditioning Block Diagram Each CCU4 timer slice can operate independently from the other slices for all the available modes. Each timer slice contains a dedicated input selector for functions linked with external events and has a dedicated compare output signal, for PWM signal generation. The built-in timer concatenation is only possible with adjacent slices, e.g. CC40/CC41. Combinations for slice concatenations like, CC40/CC42 or CC40/CC43 are not possible. The individual service requests for each timer slice (four per slice) are multiplexed into four module service requests lines, Figure 17-1. Reference Manual CCU4, V1.15 17-4 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCU4x Module CCU4x.MCLK Prescaler CCU4x.CLK[C:A] CC40 CCU4x.MCSS Capture Register 3 Capture Register 2 (CC40C0V) Capture Register 1 (CC40C0V) Capture Register 0 (CC40C0V) (CC40C0V) Address decode System clock control Output Functions PWM Input Functions CCU4x.OUT0 CCU4x.ST0 CCU4x.PS0 Period Register (CC40PR) CCU4x.IN0[P:A] Timer (CC40TIMER) Interrupt control CCU4x.MCI0 Compare Register (CC40CR) 4 Timer link CC41 Capture Register 3 Capture Register 2 (CC40C0V) Capture Register 1 (CC40C0V) Capture Register 0 (CC40C0V) (CC41C0V) Output Functions PWM Input Functions CCU4x.OUT1 CCU4x.ST1 CCU4x.PS1 Period Register (CC41PR) CCU4x.IN1[P:A] Timer (CC41TIMER) CCU4x.MCI1 Compare Register (CC41CR) Timer link Device Connections ... CC42 Capture Register 3 Capture Register 2 (CC40C0V) Capture Register 1 (CC40C0V) Capture Register 0 (CC40C0V) (CC42C0V) Output Functions PWM Input Functions CCU4x.OUT2 CCU4x.ST2 CCU4x.PS2 Period Register (CC42PR) CCU4x.IN2[P:A] Timer (CC42TIMER) CCU4x.MCI2 Compare Register (CC42CR) Timer link CC43 Capture Register 3 Capture Register 2 (CC40C0V) Capture Register 1 (CC40C0V) Capture Register 0 (CC40C0V) (CC43C0V) Output Functions Input Functions Period Register (CC43PR) PWM CCU4x.OUT3 CCU4x.ST3 CCU4x.PS3 CCU4x.IN3[P:A] Timer (CC43TIMER) CCU4x.MCI3 Compare Register (CC43CR) Figure 17-1 CCU4 block diagram Reference Manual CCU4, V1.15 17-5 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2 Functional Description 17.2.1 CC4y Overview The input path of a CCU4 slice is comprised of a selector (Section 17.2.2) and a connection matrix unit (Section 17.2.3). The output path contains a service request control unit, a timer concatenation unit and two units that control directly the state of the output signal for each specific slice (for TRAP and modulation handling), see Figure 17-2. The timer core is built of a 16 bit counter one period and one compare register in compare mode, or up to four capture registers in capture mode. In compare mode the period register sets the maximum counting value while the compare channel is controlling the ACTIVE/PASSIVE state of the dedicated comparison slice output. CC4y CCU4x.MCLK Clock Selection + Floating Prescaler CC4y.TCLK[15:0] CC4y.SR[3...0] Interrupt Generation Compare or Capture Mode CC4yC3V Input Selector + Filtering CCU4x.INy[P:A] Timer concatenation Link 7 / CC4yC2V CC4yPR To the next slice Comp Active/ Passive Control Compare or Capture Mode CC4yCR Comp CCU4x.STy CCU4x.PSy Connection matrix CC4yC0V Timer concat Additional functions CC4yC1V Load Capture Output Modulation Control Timer control CC4yTIMER CCU4x.OUTy Comp Dither CCU4x.MCSS 0 Output Functions From previous slice Timer concatenation Link 7 / CCU4x.MCIy Figure 17-2 CCU4 slice block diagram Reference Manual CCU4, V1.15 17-6 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Each CCU4 slice, with the exception of the first, contains six dedicated inputs outputs that are used for the built-in timer concatenation functionality. Inputs and outputs that are not seen at the CCU4 boundaries have a nomenclature of CC4y.<name>, whilst CCU4 module inputs and outputs are described as CCU4x.<signal_name>y (indicating the variable y the object slice). Table 17-3 CCU4 slice pin description Pin I/O Description CCU4x.MCLK I Module clock CC4y.TCLK[15:0] I Clocks from the pre scaler CCU4x.INy[P:A] I Slice functional inputs (used to control the functionality throughout slice external events) CCU4x.MCIy I Multi Channel mode input CCU4x.MCSS I Multi Channel shadow transfer trigger CC4y.SR[3...0] O Slice service request lines CC4x.STy O Slice comparison status value CCU4x.PSy O Multi channel pattern update trigger CCU4x.OUTy O Slice dedicated output pin Note: 4. The status bit outputs of the Kernel, CCU4x.STy, are extended for one more kernel clock cycle. 5. The Service Request signals at the output of the kernel are extended for one more kernel clock cycle. 6. The maximum output signal frequency of the CCU4x.STy outputs is module clock divided by 4. The slice timer, can count up or down depending on the selected operating mode. A direction flag holds the actual counting direction. The timer is connected to two stand alone comparators, one for the period match and one for a compare match. The registers used for period match and comparison match can be programmed to serve as capture registers enabling sequential capture capabilities on external events. In normal edge aligned counting scheme, the counter is cleared to 0000H each time that matches the period value defined in the period register. In center aligned mode, the counter direction changes from ‘up counting’ to ‘down counting’ after reaching the period Reference Manual CCU4, V1.15 17-7 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) value. Both period and compare registers have an aggregated shadow register, which enables the update of the PWM period and duty cycle on the fly. A single shot mode is also available, where the counter stops after it reaches the value set in the period register. The start and stop of the counter can be controlled via software access or by a programmable input pin. Functions like, load, counting direction (up/down), TRAP and output modulation can also be controlled with external events, see Section 17.2.3. 17.2.2 Input Selector The first unit of the slice input path, is used to select which inputs are used to control the available external functions. Inside this block the user also has the possibility to perform a low pass filtering of the signals and selecting the active edge(s) or level of the external event, see Figure 17-3. Reference Manual CCU4, V1.15 17-8 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCU4x.INy[P:A] 16 Configures the edge or level Selects the input for Event 0 Low pass filter value CC4yINS.EV0IS CC4yINS.EV0LM CC4yINS.EV0EM CC4yINS.LPF0M LPF synchronizer CCyINEV0_E Event 0 LD CCyINEV0_L CC4yINS.EV1LM CC4yINS.EV1IS CC4yINS.LPF1M CC4yINS.EV1EM LPF synchronizer CCyINEV1_E Event 1 LD CCyINEV1_L CC4yINS.EV2LM CC4yINS.EV2IS CC4yINS.LPF2M CC4yINS.EV2EM LPF synchronizer CCyINEV2_E Event 2 LD CCyINEV2_L Figure 17-3 Slice input selector diagram The user has the possibility of selecting any of the CCU4x.INy[P:A] inputs as the source of an event. At the output of this unit we have a user selection of three events, that were configured to be active at rising, falling or both edges, or level active. These selected events can then be mapped to several functions. Notice that each decoded event contains two outputs, one edge active and one level active, due to the fact that some functions like counting, capture or load are edge sensitive events while, timer gating or up down counting selection are level active. Reference Manual CCU4, V1.15 17-9 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.3 Connection Matrix The connection matrix maps the events coming from the input selector to several user configured functions, Figure 17-4.The following functions can be enabled on the connection matrix: Table 17-4 Connection matrix available functions Function Brief description Map to figure Figure 17-4 Start Edge signal to start the timer CCystrt Stop Edge signal to stop the timer CCystp Count Edge signal used for counting events CCycnt Up/down Level signal used to select up or down counting direction CCyupd Capture 0 Edge signal that triggers a capture into the capture registers 0 and 1 CCycapt0 Capture 1 Edge signal that triggers a capture into the capture register 2 and 3 CCycapt1 Gate Level signal used to gate the timer clock CCygate Load Edge signal that loads the timer with the CCyload value present at the compare register TRAP Level signal used for fail-safe operation CCytrap Modulation Level signal used to modulate/clear the output CCymod Status bit override Status bit is going to be overridden with an input value CCyoval for the value CCyoset for the trigger Inside the connection matrix we also have a unit that performs the built-in timer concatenation. This concatenation enables a completely synchronized operation between the concatenated slices for timing operations and also for capture and load actions. The timer slice concatenation is done via the CC4yCMC.TCE bitfield. For a complete description of the concatenation function, please address Section 17.2.9. Reference Manual CCU4, V1.15 17-10 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCyINEV0 Timer Link with the previous Timer Slice CCyINEV1 CCyINEV2 Selects which event is mapped to which function CC4yCMC.TCE CC4yCMC[19:0] (level con) Enables a concatenation of input functions capt0 CCycapt0 capt1 CCycapt1 gate (level con) load Slice concatenation CCygate CCyload CCyupd CCystp CCycnt CCystrt CCytrap (level con) (level con) CCymod CCyoval (level con) CCyoset Figure 17-4 Slice connection matrix diagram Reference Manual CCU4, V1.15 17-11 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.4 Starting/Stopping the Timer Each timer slice contains a run bit register that indicates the actual status of the timer, CC4yTCST.TRB. The start and stop of the timer can be done via software access or can be controlled directly by external events, see Figure 17-5. Selecting an external signal that acts as a start trigger does not force the user to use an external stop trigger and vice versa. Selecting the single shot mode, imposes that after the counter reaches the period value the run bit, CC4yTCST.TRB, is going to be cleared and therefore the timer is stopped. Configures how the external start is used CC4yTC.STRM Writing a 1b to this bit will set the CC4yTCST.TRB Stop/Run CC4yTCSET.TRBS External start trigger CC4yTIMER Run bit Set Control CCystrt CC4yTCST.TRB Writing a 1b to this bit will clear the CC4yTCST.TRB S Q R Q CC4yTCCLR.TRBC External stop trigger Run bit Clear Control CCystp CC4yTC.ENDM[1:0] Configures how the external stop is used Figure 17-5 Timer start/stop control diagram One can use the external stop signal to perform the following functions (configuration via CC4yTC.ENDM): • • • Clear the run bit (stops the timer) - default Clear the timer (to 0000H) but it does not clear the run bit (timer still running) Clear the timer and the run bit One can use the external start to perform the following functions (configuration via CC4yTC.STRM): • • Start the timer (resume operation) Clear and start the timer The set (start the timer) of the timer run bit, always has priority over a clear (stop the timer). Reference Manual CCU4, V1.15 17-12 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) To start multiple CCU4 timers at the same time/synchronously one should use a dedicated input as external start (see Section 17.2.7.1 for a description how to configure an input as start function). This input should be connected to all the Timers that need to started synchronously (see Section 17.8 for a complete list of module connections), Figure 17-6. For starting the timers synchronously via software there is a dedicated input signal, controlled by the SCU (System Control Unit), that is connected to all the CCU4 timers. This signal should then be configured as an external start signal (see Section 17.2.7.1) and then the software must write a 1B/0B (depending on the external start signal configuration) to the specific bitfield of the CCUCON register (this register is described on the SCU chapter). CC4x CC40 CCystrt Common Signal CC41 CCystrt CC42 SCU Other Modules CC43 Figure 17-6 Starting multiple timers synchronously 17.2.5 Counting Modes Each CC4y timer slice can be programmed into three different counting schemes: • • • Edge aligned (default) Center aligned Single shot (can be edge or center aligned) These three counting schemes can be used as stand alone without the need of selecting any inputs as external event sources. Nevertheless it is also possible to control the Reference Manual CCU4, V1.15 17-13 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) counting operation via external events like, timer gating, counting trigger, external stop, external start, etc. For all the counting modes, it is possible to update on the fly the values for the timer period and compare channel. This enables a cycle by cycle update of the PWM frequency and duty cycle. The compare channel of each CC4y Timer Slice, has an associated Status Bit (GCST.CC4yST), that indicates the active or passive state of the channel, Figure 17-7. The set and clear of the status bit and the respective PWM signal generation is dictated by the timer period, compare value and the current counting mode. See the different counting mode descriptions, Section 17.2.5.3 to Section 17.2.5.5 to understand how this bit is set and cleared. CC4yPR Comp CC4yTIMER Comp CC4yCR Set/Clear Control GCST.CC4yST D SET CLR 0x0000 For PWM generation Q Q Comp Figure 17-7 CC4y Status Bit 17.2.5.1 Calculating the PWM Period and Duty Cycle The period of the timer is determined by the value in the period register, CC4yPR and by the timer mode. The base for the PWM signal frequency and duty cycle, is always related to the clock frequency of the timer itself and not to the frequency of the module clock (due to the fact that the timer clock can be a scaled version of the module clock). In Edge Aligned Mode, the timer period is: Tper= <Period-Value> + 1; in ftclk (17.1) In Center Aligned Mode, the timer period is: Tper= (<Period-Value> + 1) x 2; in ftclk (17.2) For each of these counting schemes, the duty cycle of generated PWM signal is dictated by the value programmed into the CC4yCR register. Reference Manual CCU4, V1.15 17-14 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) In Edge Aligned and Center Aligned Mode, the PWM duty cycle is: DC= 1 - <Compare-Value>/(<Period-Value> + 1) (17.3) Both CC4yPR and CC4yCR can be updated on the fly via software, enabling a glitch free transition between different period and duty cycle values for the generated PWM signal, Section 17.2.5.2 17.2.5.2 Updating the Period and Duty Cycle Each CCU4 timer slice provides an associated shadow register for the period and compare values. This facilitates a concurrent update by software for these two parameters, with the objective of modifying during run time the PWM signal period and duty cycle. In addition to the shadow registers for the period and compare values, one also has available shadow registers for the floating prescaler and dither functions, CC4yFPCS and CC4yDITS respectively (please address Section 17.2.11 and Section 17.2.10 for a complete description of these functions). The structure of the shadow registers can be seen in Figure 17-8. Reference Manual CCU4, V1.15 17-15 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Shadow transfer trigger SW read CC4yPR.PR CC4yFPC.PCMP Load new value SW read Load new value SW write CC4yPRS.PRS (shadow) CC4yFPCS.PCMPS (shadow) SW write SW read CC4yCR.CR CC4yDIT.DCV SW read Load new value SW write Load new value CC4yCRS.CRS (shadow) CC4yDITS.DCVS SW write CC4yPSL.PSL SW read Load new value CC4yPSL.PSL (shadow) SW write Figure 17-8 Shadow registers overview The update of these registers can only be done by writing a new value into the associated shadow register and wait for a shadow transfer to occur. Each group of shadow registers have an individual shadow transfer enable bit, Figure 17-9. The software must set this enable bit to 1B, whenever an update of the values is needed. These bits are automatically cleared by the hardware, whenever an update of the values if finished. Therefore every time that an update of the registers is needed the software must set again the specific bit(s). Nevertheless it is also possible to clear the enable bit via software. This can be used in the case that an update of the values needs to be cancelled (after the enable bit has already been set). Reference Manual CCU4, V1.15 17-16 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Shadow transfer trigger Shadow transfer done Enables the shadow transfer trigger for period/compare SW writes 1b to this field to set the SySS GCST.SySS GCSS.SySE SW writes 1b to this field to clear the SySS Control Logic GCSC.SySC Control Logic GCSC.SyDSC Q & S Q R Q & Load new values into the CC4yDIT Enables the shadow transfer trigger for floating prescaler SW writes 1b to this field to set the SyPSS GCST.SyPSS GCSS.SyPSE GCSC.SyPSC R GCST.SyDSS GCSS.SyDSE SW writes 1b to this field to clear the SyPSS Q Enables the shadow transfer trigger for dither SW writes 1b to this field to set the SyDSS SW writes 1b to this field to clear the SyDSS S Load new values into the CC4yCR, CC4yPR and CC4yPSL Control Logic S Q R Q & Load new values into the CC4yFPC Figure 17-9 Shadow transfer enable logic The shadow transfer operation is going to be done in the immediately next occurrence of a shadow transfer trigger, after the shadow transfer enable is set (GCST.SySS, GCST.SyDSS, GCST.SyPSS set to 1B). The occurrence of the shadow transfer trigger is imposed by the timer counting scheme (edge aligned or center aligned). Therefore the slots when the values are updated can be: • • • in the next clock cycle after a Period Match while counting up in the next clock cycle after an One Match while counting down immediately, if the timer is stopped and the shadow transfer enable bit(s) is set Figure 17-10 shows an example of the shadow transfer control when the timer slice has been configured into center aligned mode. For a complete description of all the timer slice counting modes, please address Section 17.2.5.3, Section 17.2.5.4 and Section 17.2.5.5. Reference Manual CCU4, V1.15 17-17 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) SW writes new values into CC4yPRS SW writes new values into CC4yPRS SW writes new values into CC4yCRS SW writes new values into CC4yCRS CC4yTIMER CC4yCRS CC4yPRS Valuen Valuen+2 Valuen+1 Valuen Valuen+2 Valuen+1 Shadow transfer trigger SySS Trigger is enabled New values are loaded Trigger is enabled New values are loaded CC4yCR Valuesn Valuen+1 Valuen+2 CC4yPR Values n Valuen+1 Valuen+2 SW enables the shadow transfer by writing 1b into the GCSS.SySE PWM generation with valuen Nothing happens because SySS has not been set SW enables the shadow transfer by writing 1b into the GCSS.SySE PWM generation with valuen+1 PWM generation with valuen+2 Figure 17-10 Shadow transfer timing example - center aligned mode In some application cases it may be necessary to request shadow transfers not by software but by hardware. To perform this action each CCU4 contains a dedicated input that can be used to request a shadow transfer by hardware, the CCU4x.MCSS. This input, when enabled, is used to set the shadow transfer enable bitfields (GCST.SySS, GCST.SyDSS and GCST.SyPSS) of the specific slice. It is possible to select which slice is using this input to perform the synchronization via the GCTRL.MSEy bit field. It is also possible to enable the usage of this signal for the three different shadow transfer signals: compare and period values, dither compare value and prescaler compare value. This can be configured on the GCTRL.MSDE field. The structure for using the CCU4x.MCSS input signal can be seen in Figure 17-9. The usage of this signal is just an add on to the shadow transfer control and therefore all the previous described functions are still available. Reference Manual CCU4, V1.15 17-18 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) SW writes 1b to this field to set the SySS Enables the input to set the shadow transfer enable fields GCSS.SySE GCTRL.MSEy ≥1 Sets the GCST.SySS to 1b CCU4x.MCSS SW writes 1b to this field to set the SyDSS GCSS.SyDSE ≥1 Sets the GCST.SyDSS to 1b GCTRL.MSDE Enables the usage of the input to set the SyDSS SW writes 1b to this field to set the SyPSS GCSS.SyPSE ≥1 Sets the GCST.SyPSS to 1b GCTRL.MSDE Enables the usage of the input to set the SyPSS Figure 17-11 Usage of the CCU4x.MCSS input 17.2.5.3 Edge Aligned Mode Edge aligned mode is the default counting scheme. In this mode, the timer is incremented until it matches the value programmed in the period register, CC4yPR. When period match is detected the timer is cleared to 0000H and continues to be incremented. In this mode, the value of the period register and compare register are updated with the value written by software into the correspondent shadow register, every time that an overflow occurs (period match), see Figure 17-12. In edge aligned mode, the status bit of the comparison (CC4yST) is set one clock cycle after the timer hits the value programmed into the compare register. The clear of the status bit is done one clock cycle after the timer reaches 0000H. Reference Manual CCU4, V1.15 17-19 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCTclk Period match Period value n+1 Period match Period value n CCTimer Compare value n+1 Compare value n Zero CDIR PR/CR(shadow) PR/CR valuen+1 valuen valuen+2 valuen+1 CC4yST Figure 17-12 Edge aligned mode, CC4yTC.TCM = 0B 17.2.5.4 Center Aligned Mode In center aligned mode, the timer is counting up or down with respect to the following rules: • • • The counter counts up while CC4yTCST.CDIR = 0B and it counts down while CC4yTCST.CDIR = 1B. Within the next clock cycle, the count direction is set to counting up (CC4yTCST.CDIR = 0B) when the counter reaches 0001H while counting down. Within the next clock cycle, the count direction is set to counting down (CC4yTCST.CDIR = 1B), when the period match is detected while counting up. The status bit (CC4yST) is always 1B when the counter value is equal or greater than the compare value and 0B otherwise. While in edge aligned mode, the shadow transfer for compare and period registers is executed once per period. It is executed twice in center aligned mode as follows • • Within the next clock cycle after the counter reaches the period value, while counting up (CC4yTCST.CDIR = 0B). Within the next clock cycle after the counter reaches 0001H, while counting down (CC4yTCST.CDIR = 1B). Note: Bit CC4yTCST.CDIR changes within the next timer clock after the one-match or the period-match, which means that the timer continues counting in the previous direction for one more cycle before changing the direction. Reference Manual CCU4, V1.15 17-20 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCTclk Period match Period valuen Compare valuen+1 CCTimer One match Compare value n Compare valuen+2 Zero CDIR PR/CR(shadow) PR/CR valuen+1 valuen+2 valuen valuen+1 valuen+2 CC4yST Figure 17-13 Center aligned mode, CC4yTC.TCM = 1B 17.2.5.5 Single Shot Mode In single shot mode, the timer is stopped after the current timer period is finished. This mode can be used with center or edge aligned scheme. In edge aligned mode, Figure 17-14, the timer is stopped when it is cleared to 0000H after having reached the period value. In center aligned mode, Figure 17-15, the period is finished when the timer has counted down to 0000H. CCTclk Period match Period value CCTimer Compare value Zero CDIR TRB CC4yST TSSM Figure 17-14 Single shot edge aligned - CC4yTC.TSSM = 1B, CC4yTC.TCM = 0B Reference Manual CCU4, V1.15 17-21 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCTclk Period match Period value CCTimer Compare value One match Zero CDIR TRB CC4yST TSSM Figure 17-15 Single shot center aligned - CC4yTC.TSSM = 1B, CC4yTC.TCM = 1B 17.2.6 Active/Passive Rules The general rules that set or clear the associated timer slice status bit (CC4yST), can be generalized independently of the timer counting mode. The following events set the Status bit (CC4yST) to Active: • • in the next ftclk cycle after a compare match while counting up in the next ftclk cycle after a zero match while counting down The following events set the Status bit (CC4yST) to Inactive: • • in the next ftclk cycle after a zero match (and not compare match) while counting up in the next ftclk cycle after a compare match while counting down If external events are being used to control the timer operation, these rules are still applicable. The status bit state can only be ‘override’ via software or by the external status bit override function, Section 17.2.7.10. The software can at any time write a 1B into the GCSS.SySTS bitfield, which will set the status bit GCST.CC4yST of the specific timer slice. Writing a 1B into the GCSC.SySTC bitfield will clear the specific status bit. 17.2.7 External Events Control Each CCU4 timer slice has the possibility of using up to three different input events, see Section 17.2.2. These three events can then be mapped to Timer Slice functions (the full set of available functions is described at Section 17.2.3) These events can be mapped to any of the CCU4x.INy[P...A] inputs and there isn’t any imposition that an event cannot be used to perform several functions, or that an input Reference Manual CCU4, V1.15 17-22 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) cannot be mapped to several events (e.g. input X triggers event 0 with rising edge and triggers event 1 with the falling edge). 17.2.7.1 External Start/Stop To select an external start function, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS field and indicating the active edge of the signal on the CC4yINS.EVxEM field. This event should be then mapped to the start or stop functionality by setting the CC4yCMC.STRTS (for the start) or the CC4yTC.ENDM (for the stop) with the proper value. Notice that both start and stop functions are edge and not level active and therefore the active/passive configuration is set only by the CC4yINS.EVxEM. The external stop by default just clears the run bit (CC4yTCST.TRB), while the start functions does the opposite. Nevertheless one can select an extended subset of functions for the external start and stop. This subset is controlled by the registers CC4yTC.ENDM (for the stop) and CC4yTC.STRM (for the start). For the start subset (CC4yTC.STRM): • • sets the run bit/starts the timer (resume operation) clears the timer, sets the run bit/starts the timer (flush and start) For the stop subset (CC4yTC.ENDM): • • • clears the run/stops the timer (stop) clears the timer (flush) clears the timer, clears the run bit/stops the timer (flush and stop) If in conjunction with an external start/stop (configured also/only as flush) and external up/down signal is used, during the flush operation the timer is going to be set to 0000H if the actual counting direction is up or set with the value of the period register if the counting direction is down. Figure 17-16 to Figure 17-19 shows the usage of two signals to perform the start/stop functions in all the previously mentioned subsets. External Signal(1) acts as an active HIGH start signal, while External Signal(2) is used as an active HIGH stop function. Reference Manual CCU4, V1.15 17-23 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External Signal(1) External Signal(2) CCTclk Period match Period match Period valuen CCTimer Compare value Zero TRB CC4yST Figure 17-16 Start (as start)/ stop (as stop) - CC4yTC.STRM = 0B, CC4yTC.ENDM = 00B External Signal(1) External signal(2) CCTclk Period match Period match Period value CCTimer Compare value Zero TRB CC4yST Figure 17-17 Start (as start)/ stop (as flush) - CC4yTC.STRM = 0B, CC4yTC.ENDM = 01B Reference Manual CCU4, V1.15 17-24 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCStrt CCStp CCTclk Period match Period value CCTimer Compare value Zero TRB CC4yST Figure 17-18 Start (as flush and start)/ stop (as stop) - CC4yTC.STRM = 1B, CC4yTC.ENDM = 00B External Signal(1) External Signal(2) CCTclk Period match Period value CCTimer Compare value Zero TRB CC4yST Figure 17-19 Start (as start)/ stop (as flush and stop) - CC4yTC.STRM = 0B, CC4yTC.ENDM = 10B 17.2.7.2 External Counting Direction There is the possibility of selecting an input signal to act as increment/decrement control. To select an external up/down control, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS field and indicating the active level of the signal on the CC4yINS.EVxLM. This event should be then mapped to the up/down functionality by setting CC4yCMC.UDS with the proper value. Reference Manual CCU4, V1.15 17-25 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Notice that the up/down function is level active and therefore the active/passive configuration is set only by the CC4yINS.EVxLM. The status bit of the slice (CC4yST) is always set when the timer value is equal or greater than the value stored in the compare register, see Section 17.2.6. The update of the period and compare register values is done when: • • with the next clock after a period match, while counting up (CC4yTCST.CDIR = 0B) with the next clock after a one match, while counting down (CC4yTCST.CDIR = 1B) The value of the CC4yTCST.CDIR register is updated accordingly with the changes on the decoded event. The Up/Down direction is always understood as CC4yTCST.CDIR = 1B when counting down and CC4yTCST.CDIR = 0B when counting up. Using an external signal to perform the up/down counting function and configuring the event as active HIGH means that the timer is counting up when the signal is HIGH and counting down when LOW. Figure 17-20 shows an external signal being used to control the counting direction of the time. This signal was selected as active HIGH, which means that the timer is counting down while the signal is HIGH and counting up when the signal is LOW. Note: For a signal that should impose an increment when LOW and a decrement when HIGH, the user needs to set the CC4yINS.EVxLM = 0B. When the operation is switched, then the user should set CC4yINS.EVxLM = 1B. Note: Using an external counting direction control, sets the slice in edge aligned mode. External Signal CCTclk Period value n+2 Period value n Comparen+2 CCTimer Reload Comparen= Comparen+1 Zero CDIR PR/CRx(shadow) PR/CRx value n+1 valuen valuen+2 valuen+1 valuen+2 CC4yST Figure 17-20 External counting direction Reference Manual CCU4, V1.15 17-26 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.7.3 External Gating Signal For pulse measurement, the user has the possibility of selecting an input signal that operates as counting gating. To select an external gating control, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS register and indicating the active level of the signal on the CC4yINS.EVxLM register. This event should be then mapped to the gating functionality by setting the CC4yCMC.GATES with the proper value. Notice that the gating function is level active and therefore the active/passive configuration is set only by the CC4yINS.EVxLM. The status bit during an external gating signal continues to be asserted when the compare value is reached and deasserted when the counter reaches 0000H. One should note that the counter continues to use the period register to identify the wrap around condition. Figure 17-21 shows the usage of an external signal for gating the slice counter. The signal was set as active LOW, which means the counter gating functionality is active when the external value is zero. External signal Period value CCTimer Compare value Zero CDIR CC4yST Figure 17-21 External gating For any type of usage of the external gating function, the specific run bit of the Timer Slice, CC4yTCST.TRB, needs to be set. This can be done via an additional external signal or directly via software. 17.2.7.4 External Count Signal There is also the possibility of selecting an external signal to act as the counting event. To select an external counting, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS register and indicating the active edge of the signal on the CC4yINS.EVxEM register. Reference Manual CCU4, V1.15 17-27 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) This event should be then mapped to the counting functionality by setting the CC4yCMC.CNTS with the proper value. Notice that the counting function is edge active and therefore the active/passive configuration is set only by the CC4yINS.EVxEM. One can select just a the rising, falling or both edges to perform a count. On Figure 17-22, the external signal was selected as a counter event for both falling and rising edges. Wrap around condition is still applied with a comparison with the period register. External signal CCcnt Period value CCTimer Compare value Zero CDIR CC4yST Figure 17-22 External count For any type of usage of the external gating function, the specific run bit of the Timer Slice, CC4yTCST.TRB, needs to be set. This can be done via an additional external signal or directly via software. 17.2.7.5 External Load Each slice of the CCU4 also has a functionality that enables the user to select an external signal as trigger for reloading the value of the timer with the current value of the compare register (if CC4yTCST.CDIR = 0B) or with the value of the period register (if CC4yTCST.CDIR = 1B). To select an external load signal, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS register and indicating the active edge of the signal on the CC4yINS.EVxEM register. This event should be then mapped to the load functionality by setting the CC4yCMC.LDS with the proper value. Notice that the load function is edge active and therefore the active/passive configuration is set only by the CC4yINS.EVxEM. On figure Figure 17-23, the external signal (1) was used to act as a load trigger, active on the rising edge. Every time that a rising edge on external signal (1) is detected, the Reference Manual CCU4, V1.15 17-28 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) timer value is loaded with the value present on the compare register. If an external signal is being used to control the counting direction, up or down, the timer value can be loaded also with the value set in the period register. The External signal (2) represents the counting direction control (active HIGH). If at the moment that a load trigger is detected, the signal controlling the counting direction is imposing a decrement, then the value set in the timer is the period value. External signal(1) External signal(2) Period valuen+1 Period match Period valuen CCTimer Load valuen Load valuen+1 Zero PR/CR (shadow) PR/CR valuen+1 valuen+2 valuen+1 valuen CC4yST Figure 17-23 External load 17.2.7.6 External Capture When selecting an external signal to be used as a capture trigger (if CC4yCMC.CAP0S or CC4yCMC.CAP1S are different from 0H), the user is automatically setting the specific slice into capture mode. In capture mode the user can have up to four capture registers, see Figure 17-26: capture register 0 (CC4yC0V), capture register 1 (CC4yC1V), capture register 2 (CC4yC2V) and capture register 3 (CC4yC3V). These registers are shared between compare and capture modes which imposes: • • if CC4yC0V and CC4yC1V are used for capturing, the compare registers CC4yCR and CC4yCRS are not available (no compare channel) if CC4yC2V and CC4yC3V are used for capturing, the period registers CC4yPR and CC4yPRS are not available (no period control) To select an external capture signal, one should map one of the events (output of the input selector) to a specific input signal, by setting the required value in the CC4yINS.EVxIS register and indicating the active edge of the signal on the Reference Manual CCU4, V1.15 17-29 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC4yINS.EVxEM register. This event should be then mapped to the capture functionality by setting the CC4yCMC.CAP0S/CC4yCMC.CAP1S with the proper value. Notice that the capture function is edge active and therefore the active/passive configuration is set only by the CC4yINS.EVxEM. The user has the possibility of selecting the following capture schemes: • • Different capture events for CC4yC0V/CC4yC1V and CC4yC2V/CC4yC3V The same capture event for CC4yC0V/CC4yC1V and CC4yC2V/CC4yC3V with the same capture edge. For this capture scheme, only the CCcapt1 functionality needs to be programmed. To enable this scheme, the field CC4yTC.SCE needs to be set to 1. Different Capture Events (SCE = 0B) Every time that a capture trigger 1 occurs, CCcapt1, the actual value of the timer is captured into the capture register 3 and the previous value stored in this register is transferred into capture register 2. Every time that a capture trigger 0 occurs, CCcapt0, the actual value of the timer is captured into the capture register 1 and the previous value stored in this register is transferred into capture register 0. Every time that a capture procedure into one of the registers occurs, the respective full flag is set. This flag is cleared automatically by HW when the SW reads back the value of the capture register (by reading the specific capture register or by reading the extended capture read value, see Section 17.2.7.7). The capture of a new value into a specific capture registers is dictated by the status of the full flag as follows: CC4yC1Vcapt= NOT(CC4yC1Vfull_flag AND CC4yC0Vfull_flag) (17.4) CC4yC0Vcapt= CC4yC1Vfull_flag AND NOT(CC4yC0Vfull_flag) (17.5) It is also possible to disable the effect of the full flags reset by setting the CC4yTC.CCS = 1B. This enables a continuous capturing independent if the values captured have been read or not. Note: When using the period registers for capturing, CC4yCMC.CAP1S different from 00B, the counter always uses its full 16 bit width as period value. On Figure 17-24, an external signal was selected as an event for capturing the timer value into the CC4yC0V/CC4yC1V registers. The status bit, CC4yST, during capture mode is asserted whenever a capture trigger is detected and deasserted when the counter matches 0000H. Reference Manual CCU4, V1.15 17-30 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External signal Capture into CC4C1V Capture into CC4C1V Capture into CC4C1V CCcapt0 Period value (0xA) Period value n+1 (0x7) 0x8 CCTimer 0x5 0x4 Zero CC4C1V valuen 0x4 0x8 0x5 CC4C0V value n-1 value n 0x4 0x8 PR (shadow) PR valuen+2 valuen+1 valuen+1 valuen CC4yST Figure 17-24 External capture - CC4yCMC.CAP0S != 00B, CC4yCMC.CAP1S = 00B On Figure 17-25, two different signals were used as source for capturing the timer value into the CC4yC0V/CC4yC1V and CC4yC2V/CC4yC3V registers. External signal(1) was selected as rising edge active capture source for CC4yC0V/CC4yC1V. External signal(2) was selected has the capture source for CC4yC2V/CC4yC3V, but as opposite to the external signal(1), the active edge was selected has falling. See Section 17.2.12.4, for the complete capture mode usage description. Reference Manual CCU4, V1.15 17-31 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External signal(1) External signal(2) Capture into CC4C1V Capture into CC4C1V Capture into CC4C1V CCcapt0 Capture into CC4C3V Capture into CC4C3V CCcapt1 Full scale as Period CCTimer Zero CC4C1V CValuen CValue n+1 CValue n+2 CC4C0V CValuen-1 CValue n CValuen+1 CC4C3V PValuen PValuen+1 PValuen+2 CC4C2V PValuen-1 PValuen PValuen+1 CC4yST Figure 17-25 External capture - CC4yCMC.CAP0S != 00B, CC4yCMC.CAP1S != 00B Reference Manual CCU4, V1.15 17-32 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) SW read/clear & SW read/clear & Full/ empty Capture reg1 CCcapt0 Full/ empty & Capture reg0 & CC4yTIMER CCcapt1 & & Capture reg2 Capture reg3 Full/ empty & & Full/ empty SW read/clear SW read/clear Figure 17-26 Slice capture logic Same Capture Event (SCE = 1B) Setting the field CC4yTC.SCE = 1B, enables the possibility of having 4 capture registers linked with the same capture event, Figure 17-28. The function that controls the capture is the CCcapt1. The capture logic follows the same structure shown in Figure 17-26 but extended to a four register chain, see Figure 17-27. The same full flag lock rules are applied to the four register chain (it also can be disabled by setting the CC4yTC.CCS = 1B): CC4yC3Vcapt= NOT(CC4yC3Vfull_flag AND CC4yC2Vfull_flag AND CC4yC2Vfull_flag AND CC4yC1Vfull_flag) (17.6) CC4yC2Vcapt= CC4yC3Vfull_flag AND NOT(CC4yC2Vfull_flag AND CC4yC1Vfull_flag AND CC4yC0Vfull_flag) (17.7) CC4yC1Vcapt= CC4yC2Vfull_flag AND NOT(CC4yC1Vfull_flag AND CC4yC0Vfull_flag) (17.8) CC4yC0Vcapt= CC4yC1Vfull_flag AND NOT(CC4yC0Vfull_flag) Reference Manual CCU4, V1.15 17-33 (17.9) V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External signal CCcapt1 FS CCTimer Zero CC4C3V CValuen CValuen+1 CValuen+2 CValuen+3 CC4C2V CValuen-1 CValuen CValuen+1 CValuen+2 CC4C1V CValuen-2 CValuen-1 CValuen Cvaluen+1 CC4C0V CValuen-3 CValuen-2 CValuen-1 CValuen CC4yST Figure 17-27 External Capture - CC4yTC.SCE = 1B Full/ empty Full/ empty Full/ empty Full/ empty Capture reg3 Capture reg2 Capture reg1 Capture reg0 CCcapt1 Capture enable CC4yTIMER Figure 17-28 Slice Capture Logic - CC4yTC.SCE = 1B Reference Manual CCU4, V1.15 17-34 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.7.7 Capture Extended Read Back Mode Each Timer Slice capture logic can operate in a FIFO read back mode. This mode can be enabled by setting the CC4yTC.ECM = 1B. This Extended Read back mode allows the software to read back the capture data always from the same address (CC4yECRD0 for the structure linked with the cpature trigger 0 or CC4yECRD1 for the one linked with capture trigger 1). This read back will always return the oldest captured value, enabling an easy software routine implementation for reconstructing the capture data. This function allows the usage of a FIFO structure for each capturing trigger. This relaxes the software read back routine when multiple capture triggers are present, and the software is not fast enough to perform a read operation in each capture event. This FIFO read back function is present for a depth-4 and depth-2 FIFO structure. The read back data contains also a lost value bitfield, that indicates if a capture trigger was lost due to the fact that the FIFO structure was full. This bitfield is set whenever a capture event was sensed and the FIFO was full (regardless if the continuos capture mode was enabled or not). This bitfield is cleared automatically by HW whenever the next read of the CC4yECRD0/CC4yECRD1 register occurs. This bitfield does not indicate how many capture events were lost, it just indicates that between two ECRD reads at least a capture event was lost (this can help the SW evaluate which part of the data read, can be used for calculation). Note: When the ECM bitfield is set, reading the individual capture registers is still possible. Nevertheless the full flags can only be cleared by the HW when a read back is done via the CC4yECRD0/CC4yECRD1 address. Depth 4 Structure The FIFO depth-4 structure is present in the hardware when the capture trigger 1 is enabled and the CC4yTC.SCE = 1B (same capture event), Figure 17-29. Reference Manual CCU4, V1.15 17-35 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 23.05.2012 - 30.05.2012 Depth-4 FIFO capture CC4yTIMER shift Capture register 3 CC4yC3V Full Flag shift Capture register 2 CC4yC2V Full Flag shift Capture register 1 CC4yC1V Full Flag Capture register 0 CC4yC0V Full Flag Capture trigger 1 FIFO State Machine Oldest Captured Value CC4yECRD1 SW reads back always the oldest captured value Figure 17-29 Capture Extended Read Back - Depth 4 Reference Manual CCU4, V1.15 17-36 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 1st Capture Event 2nd Capture Event After Read Back CC4yC0V Empty CC4yC0V Empty CC4yC0V Empty CC4yC1V Empty CC4yC1V Empty CC4yC1V Empty CC4yC2V Empty CC4yC2V 5790H Full CC4yC2V Full CC4yC3V 8845H Full CC4yC3V 8845H CC4yTIMER 8845H CC4yTIMER 2567H CC4yC3V 5790H CC4yTIMER 5790H Empty Full SW read back via CC4yECRD1 3rd Capture Event 4th Capture Event After Read Back CC4yC0V Empty CC4yC0V Empty CC4yC0V CC4yC1V Empty CC4yC1V 8845H Full CC4yC1V Empty Empty CC4yC2V 8845H Full CC4yC2V 4799H Full CC4yC2V 4799H Full CC4yC3V 4799H Full CC4yC3V 6555H Full CC4yC3V 6555H Full CC4yTIMER 4799H CC4yTIMER 6555H CC4yTIMER 0045H SW read back via CC4yECRD1 Figure 17-30 Depth 4 software access example Depth 2 Structure Each Timer Slice can have two capture structures of depth-2: one used with capture trigger 0 and another with capture trigger 1. The one linked with capture trigger 0, is accessed via the CC4yECRD0 while the one linked with the capture trigger 1 is accessed via the CC4yECRD1, Figure 17-31. Reference Manual CCU4, V1.15 17-37 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 23.05.2012 - 30.05.2012 Depth-2 FIFO x 2 Capture trigger 1 shift capture Capture register 3 CC4yC3V Full Flag Oldest Captured Value from CC4yC3v, CC4yC2V CC4yECRD1 FIFO State Machine CC4yTIMER capture Capture register 2 CC4yC2V Full Flag Full Flag Capture register 1 CC4yC1V CC4yECRD0 Oldest Captured Value from CC4yC1V, CC4yC0V Full Flag Capture register 0 CC4yC0V Capture trigger 0 shift Figure 17-31 Capture Extended Read Back - Depth 2 SW read back via CC4yECRD1 1st Capture Event to CC4yC2V/CC4yC3V CC4yC2V CC4yC3V 5790H CC4yTIMER 5790H 2nd Capture Event to CC4yC2V/CC4yC3V After Read Back Empty CC4yC2V 5790H Full CC4yC2V Full CC4yC3V 8845H Full CC4yC3V 8845H CC4yTIMER 8845H CC4yTIMER 2567H CC4yTIMER 6777H CC4yC1V 6777H CC4yC0V Empty Full CC4yTIMER 3345H Full CC4yC1V Empty CC4yC1V 3345H Full Empty CC4yC0V Empty CC4yC0V 8845H Empty 1st Capture Event to CC4yC0V/CC4yC1V After Read Back 2nd Capture Event to CC4yC0V/CC4yC1V SW read back via CC4yECRD0 Figure 17-32 Depth 2 software access example 17.2.7.8 External Modulation An external signal can be used to perform a modulation at the output of each timer slice. To select an external modulation signal, one should map one of the input signals to one of the events, by setting the required value in the CC4yINS.EVxIS register and indicating the active level of the signal on the CC4yINS.EVxLM register. This event should be then Reference Manual CCU4, V1.15 17-38 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) mapped to the modulation functionality by setting the CC4yCMC.MOS = 01B if event 0 is being used, CC4yCMC.MOS = 10B if event 1 or CC4yCMC.MOS = 11B if event 2. Notice that the modulation function is level active and therefore the active/passive configuration is set only by the CC4yINS.EVxLM. The modulation has two modes of operation: • • modulation event is used to clear the CC4yST bit - CC4yTC.EMT = 0B modulation event is used to gate the outputs - CC4yTC.EMT = 1B On Figure 17-33, we have a external signal configured to act as modulation source that clears the CC4yST bit, CC4yTC.EMT = 0B. It was programmed to be an active LOW event and therefore, when this signal is LOW the output value follows the normal ACTIVE/PASSIVE rules. When the signal is HIGH (inactive state), then the CC4yST bit is cleared and the output is forced into the PASSIVE state. Notice that the values of the status bit, CC4yST and the specific output CCU4x.OUTy are not linked together. One can choose for the output to be active LOW or HIGH through the PSL bit. The exit of the external modulation inactive state is synchronized with the PWM signal due to the fact that the CC4yST bit is cleared and cannot be set while the modulation signal is inactive. The entering into inactive state also can be synchronized with the PWM signal, by setting CC4yTC.EMS = 1B. With this all possible glitches at the output are avoided, see Figure 17-34. External signal Period value CCTimer Compare value Zero CC4yST/ CCU4x.OUTy Figure 17-33 External modulation clearing the ST bit - CC4yTC.EMT = 0B Reference Manual CCU4, V1.15 17-39 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External signal Period value CCTimer Compare value Zero Waiting for the CC4yST to go LOW CC4yST/ CCU4x.OUTy Figure 17-34 External modulation clearing the ST bit - CC4yTC.EMT = 0B, CC4yTC.EMS = 1B On Figure 17-35, the external modulation event was used as gating signal of the outputs, CC4yTC.EMT = 1B. The external signal was configured to be active HIGH, CC4yINS.EVxLM = 0B, which means that when the external signal is HIGH the outputs are set to the PASSIVE state.In this mode, the gating event can also be synchronized with the PWM signal by setting the CC4yTC.EMS = 1B. External signal Period value CCTimer Compare value Zero CC4yST CC4yST is still HIGH CCU4x.OUTy Figure 17-35 External modulation gating the output - CC4yTC.EMT = 1B Reference Manual CCU4, V1.15 17-40 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.7.9 TRAP Function The TRAP functionality allows the PWM outputs to react on the state of an input pin. This functionality can be used to switch off the power devices if the TRAP input becomes active. To select the TRAP functionality, one should map one of the input signals to event number 2, by setting the required value in the CC4yINS.EV2IS register and indicating the active level of the signal on the CC4yINS.EV2LM register. This event should be then mapped to the trap functionality by setting the CC4yCMC.TS = 1B. Notice that the trap function is level active and therefore the active/passive configuration is set only by the CC4yINTS.EV2LM. There are two bitfields that can be monitored via software to crosscheck the TRAP function, Figure 17-36: • • The TRAP state bit, CC4yINTS.E2AS. This bitfield if the TRAP is currently active or not. This bitfield is therefore setting the specific Timer Slice output, into ACTIVE or PASSIVE state. The TRAP Flag, CC4yINTS.TRPF. This bitfield is used as a remainder in the case that the TRAP condition is cleared automatically via hardware. This field needs to be cleared by the software. TRAP State Enter Decoded TRAP function from connection matrix TRAP State Entry control CCtrap Sets the TRPF and E2AS CC4yTC.TRAPE TRAP State Info Second level TRAP enable Remainder flag CC4yINTS.TRPF Sets the CCU4x.OUTy in PASSIVE state TRAP State Exit Configuration for exiting the TRAP State CC4yINTS.E2AS CC4yTC.TRPSW CC4yTC.TRPSE Sync signal for exiting the TRAP state Timer = 0000h TRAP State Exit control SW writes a 1b to this bitfield to clear the TRAP state bit Clears the E2AS CC4ySWR.RTRPF SW writes a 1b to this bitfield to clear the TRPF bit CC4ySWR.RE2A Figure 17-36 Trap control diagram When a TRAP condition is detected at the selected input pin, both the Trap Flag and the Trap State bit are set to 1B. The Trap State is entered immediately, by setting the CCU4xOUTy into the programmed PASSIVE state, Figure 17-37. Reference Manual CCU4, V1.15 17-41 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Exiting the Trap State can be done in two ways (CC4yTC.TRPSW register): • • automatically via HW, when the TRAP signal becomes inactive - CC4yTC.TRPSW = 0B by SW only, by clearing the CC4yINTS.E2AS.The clearing is only possible if the input TRAP signal is in inactive state - CC4yTC.TRPSW = 1B Timer Compare Value CCtrap TRPS/ E2AS If TRPSW = 0 TRPS/ E2AS If TRPSW = 1 TRPF CCU4x.OUTy TRAP state is automatically exit via HW if TRPSW = 0 SW writes 1b to RE2A clear the TRAP state SW write 1b to RTPRF to clear the TRAP flag Figure 17-37 Trap timing diagram, CC4yPSL.PSL = 0B (output passive level is 0B) It is also possible to synchronize the exiting of the TRAP state with the PWM signal, Figure 17-38. This function is enabled when the bitfield CC4yTC.TRPSE = 1B. Reference Manual CCU4, V1.15 17-42 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Timer Compare Value CCtrap TRPS\ E2AS ”Zero Match” TRPSE = 1 CCU4x.OUTy Figure 17-38 Trap synchronization with the PWM signal, CC4yTC.TRPSE = 1B 17.2.7.10 Status Bit Override For complex timed output control, each Timer Slice has a functionality that enables the override of the status bit (CC4yST) with a value passed trough an external signal. The override of the status bit, can then lead to a change on the output pin, CCU4xOUTy (from inactive to active or vice versa). To enable this functionality, two signals are needed: • • One signal that acts as a trigger to override the status bit (edge active) One signal that contains the value to be set in the status bit (level active) To use the status bit override functionality, one should map the signal that acts as trigger to the event number 1, by setting the required value in the CC4yINS.EV1IS register and indicating the active edge of the signal on the CC4yINS.EV1EM register. The signal that carries the value to be set on the status bit, needs to be mapped to the event number 2, by setting the required value in the CC4yINS.EV2IS register. The CC4yINS.EV2LM register should be set to 0B if no inversion on the signal is needed and to 1B otherwise. The events should be then mapped to the status bit functionality by setting the CC4yCMC.OFS = 1B. Figure 17-39 shows the functionality of the status bit override, when the external signal(1) was selected as trigger source (rising edge active) and the external signal(2) was selected as override value. Reference Manual CCU4, V1.15 17-43 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) External signal 1 External signal 2 Timer Compare Value CC4yST Copies the value of external signal 2 to CC4yST Copies the value of external signal 2 to CC4yST Figure 17-39 Status bit override 17.2.8 Multi-Channel Control The multi channel control mode is selected individually in each slice by setting the CC4yTC.MCME = 1B. Within this mode, the output state of the Timer Slices (the ones set in multi channel mode) can be controlled in parallel by a single pattern. The pattern is controlled via the CCU4 inputs, CCU4x.MCI0, CCU4x.MCI1, CCU4x.MCI2 and CCU4x.MCI3. Each of these inputs is connected directly to the associated slice input, e.g. CCU4x.MCI0 to CC40MCI, CCU4x.MCI1 to CC41MCI. This pattern can be controlled directly by other module. The connectivity of each device may allow different control possibilities therefore one should address Section 17.8 to check what modules are connected to these inputs. When using the Multi Channel support of the CCU4, one can achieve a complete synchronicity between the output state update, CCU4x.OUTy, and the update of a new pattern, Figure 17-40. This synchronocity feature can be enabled by using some specific modules and therefore one should address Section 17.8 to check which module is controlling the CCU4x.MCIy inputs. Reference Manual CCU4, V1.15 17-44 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Period value TIMER Compare value Zero CC4yMCI ”Zero Match” used as sync CCU4x.OUTy (Passive level is LOW) Pattern is synchronized with falling edge of the output CCU4x.OUTy (Passive level is HIGH) Pattern is synchronized with rising edge of the output Figure 17-40 Multi channel pattern synchronization Figure 17-41 shows the usage of the multi channel mode in conjunction with all four Timer Slices inside the CCU4. CCU4x.OUT0 CCU4x.OUT2 CCU4x.OUT3 CCU4x.OUT4 Multi channel pattern 1001b 1100b 0110b Figure 17-41 Multi Channel mode for multiple Timer Slices The synchronization between the CCU4 and the module controlling the multi-channel pattern is achieved, by adding a 3 cycle delay on the output path of each Timer Slice Reference Manual CCU4, V1.15 17-45 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) (between the status bit, CC4yST and the direct control of the output pin). This path is only selected when CC4yTC.MCME = 1B, see Figure 17-42. The multi pattern input synchronization can be seen on Figure 17-43. To achieve a synchronization between the update of the status bit, the sampling of a new multi channel pattern input is controlled by the period match or one match signal. In a straightforward utilization of this synchronization feature, the module controlling the multi channel pattern signals, receives a sync signal from the CCU4, the CCU4x.PSy. This signal is then used by this module to update the multi-channel pattern. Due to the structure of the synchronization scheme inside the CCU4, the module controlling the multi-channel pattern needs to update this pattern, within 4 clock cycles after the CCU4x.PSy signal is asserted, Figure 17-43. In a normal operation, where no external signal is used to control the counting direction, the signal used to enable the sampling of the pattern is always the period match when in edge aligned and the one match when in center aligned mode. When an external signal is used to control the counting direction, depending if the counter is counting up or counting down, the period match or the one match signal is used, respectively. CC4yCMC.UDS CC4yTC.CDIR CC4yTC.MCME CC4yTC.EMT CC4yTC.EMS CC4yMCMI Timer = 0000H Multi Channel Mode control Timer = Period Timer = 0001 H Multi Channel Mode pattern Set/Clear the Status bit External Modulation CCmod External modulation control Output Path CC4yINTS.E2AS (TRAP) D Q fccu4 & CC4yST Set Status bit Clear Status bit CCoset S Q 1 Z-3 CCU4x.OUTy 1 0 Set/Clear Control CCoval R 0 Q CC4yTC.MCME Enables the multi channel mode path PSL S Q R Q CCU4x.STy Figure 17-42 CC4y Status bit and Output Path Reference Manual CCU4, V1.15 17-46 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC4yTC.MCME CC4yMCMI Multi Channel Mode pattern 1 1 D Q 0 CC4yTC.CDIR Timer = Period 1 0 ftclk fccu4 0 (While counting up) 0 Timer = 0001H 1 Z -1 Z -2 For the Module controlling the multi channel pattern (this signal can be used to request an update of the pattern) 1 CCU4x.PSy Center aligned Figure 17-43 Multi Channel Mode Control Logic 17.2.9 Timer Concatenation The CCU4 offers a very easy mechanism to perform a synchronous timer concatenation. This functionality can be used by setting the CC4yCMC.TCE = 1B. By doing this the user is doing a concatenation of the actual CCU4 slice with the previous one, see Figure 17-44. Notice that is not possible to perform concatenation with non adjacent slices and that timer concatenation automatically sets the slice mode into Edge Aligned. It is not possible to perform timer concatenation in Center Aligned mode. To enable a 64 bit timer, one should set the CC4yCMC.TCE = 1B in all the slices (with the exception of the CC40 due to the fact that it doesn’t contain this control register). To enable a 48 bit timer, one should set the CC4yCMC.TCE = 1B in two adjacent slices and to enable a 32 bit timer, the CC4yCMC.TCE is set to 1B in the slice containing the MSBs. Notice that the timer slice containing the LSBs should always have the TCE bitfield set to 0B. Several combinations for timer concatenation can be made inside a CCU4 module: • • • • one 64 bit timer one 48 bit timer plus a 16 timer two 32 bit timers one 32 bit timer plus two 16 bit timers Reference Manual CCU4, V1.15 17-47 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 04.10.2013 - 11.10.2013 32 bits CC40 Timer link CC41 (MSBs) CC41 CC40 (LSBs) CC41CMC.TCE = 1b CC40 04.10.2013 - 11.10.2013 48 bits Timer link CC41 CC41CMC.TCE = 1b CC42 (MSBs) CC41 CC40 (LSBs) Timer link CC42 CC42CMC.TCE = 1b CC40 04.10.2013 - 11.10.2013 Timer link CC41 64 bits CC41CMC.TCE = 1b Timer link CC42 CC43 (MSBs) CC42 CC41 CC40 (LSBs) CC42CMC.TCE = 1b Timer link CC43 CC43CMC.TCE = 1b Figure 17-44 Timer Concatenation Example Each Timer Slice is connected to the adjacent Timer Slices via a dedicated concatenation interface. This interface allows the concatenation of not only the Timer counting operation, but also a synchronous input trigger handling for capturing and loading operations, Figure 17-45. Note: For all cases CC40 and CC43 are not considered adjacent slices Reference Manual CCU4, V1.15 17-48 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC4(y-1) Connection matrix Timer concat Timer link CC4(y-1) Timer concat Timer logic Timer link CC4y Timer link Connection matrix CC4y Timer concat Timer concat Timer logic Timer link CC4(y+1) Timer link Timer link CC4(y+1) Connection matrix Timer concat Timer concat Timer logic Figure 17-45 Timer Concatenation Link Seven signals are present in the timer concatenation interface: • • • • • • • Timer Period match (CC4yPM) Timer Zero match (CC4yZM) Timer Compare match (CC4yCM) Timer counting direction function (CCupd) Timer load function (CCload) Timer capture function for CC4yC0V and CC4yC1V registers (CCcap0) Timer capture function for CC4yC2V and CC4yC3V registers (CCcap1) The first four signals are used to perform the synchronous timing concatenation at the output of the Timer Logic, like it is seen in Figure 17-45. With this link, the timer length can be easily adjusted to 32, 48 or 64 bits (counting up or counting down). The last three signals are used to perform a synchronous link between the capture and load functions, for the concatenated timer system. This means that the user can have a capture or load function programmed in the first Timer Slice, and propagate this capture or load trigger synchronously from the LSBs until the MSBs, Figure 17-46. The capture or load function only needs to be configured in the first Timer Slice (the one holding the LSBs). From the moment that CC4yCMC.TCE is set to 1B, in the following Timer Slices, the link between these functions is done automatically by the hardware. Reference Manual CCU4, V1.15 17-49 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC4(y-1) capture Connection matrix Timer concat Timer logic Timer concat load Timer link 28.10.2011 - 04.11.2011 48 bits CC4y Connection matrix Timer concat Timer logic Timer concat MSBs Timer link CC4(y+1) Connection matrix Timer concat Timer logic LSBs CC4(y+1) CC4y CC4(y-1) Capture/load register Capture/load register Capture/load register Timer concat Figure 17-46 Capture/Load Timer Concatenation The period match (CC4yPM) or zero match (CC4yZM) from the previous Timer Slice (with the immediately next lower index) are used in concatenated mode, as gating signal for the counter. This means that the counting operation of the MSBs only happens when a wrap around condition is detected, avoiding additional DSP operations to extract the counting value. With the same methodology, the compare match (CC4yCM), zero match and period match are gated with the specific signals from the previous slice. This means that the timing information is propagated throughout all the slices, enabling a completely synchronous match between the LSB and MSB count, see Figure 17-47. Reference Manual CCU4, V1.15 17-50 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) period Timer0 compare CC40PM CM40CM period Timer1 compare CC41PM CC41CM CC41PM (concat) CC41CM (concat) Output period match is AND gated Output compare is AND gated CC40.OUT CC41.OUT Figure 17-47 32 bit concatenation timing diagram Note: The counting direction of the concatenated timer needs to be fixed. The timer can count up or count down, but the direction cannot be updated on the fly. Figure 17-48 gives an overview of the timer concatenation logic. Notice that all the mechanism is controlled solely by the CC4yCMC.TCE bitfield. Reference Manual CCU4, V1.15 17-51 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC4(y-1) Connection matrix Timer concat Timer logic Timer concat CC4(y-1)ZM direction CCupd(y-1) capture CC4(y-1)CM CC4(y-1)PM CCcapt1(y-1) CCcapt0(y-1) CCload(y-1) load CC4y 0 1 1 CC4yPR 1 0 1 CCcapt1 Comp & CC4yPM & CC4yZM & CC4yCM 0 1 1 CCgate 1 CC4yTIMER 0 Conn. Matrix 0 Comp 0 1 Comp CCcapt0 0 1 1 CCload 0 Timer Concat CC4yCR 1 Timer Logic CC4yCMC.TCE = 1 0 Timer Concat CC4yCMC.TCE = 1 Additional functions Figure 17-48 Timer concatenation control logic 17.2.10 PWM Dithering The CCU4 has an automatic PWM dithering insertion function. This functionality can be used with very slow control loops that cannot update the period/compare values in a fast manner, and by that fact the loop can lose precision on long runs. By introducing dither on the PWM signal, the average frequency/duty cycle is then compensated against that error. Each slice contains a dither control unit, see Figure 17-49. Reference Manual CCU4, V1.15 17-52 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC40 Dither control Period match CC40 Dither enable Shadow transfer enable Dither counter Counting enable Dither compare Counting enable CC41 Dither enable Period match Dither counter Shadow transfer enable Counting enable CC42 Dither enable Period match Counting enable Dither enable Dither compare CC42 Dither control Dither counter Shadow transfer enable CC43 CC41 Dither control Period match Dither compare CC43 Dither control Dither counter Shadow transfer enable Dither compare Figure 17-49 Dither structure overview The dither control unit contains a 4 bit counter and a compare value. The four bit counter is incremented every time that a period match occurs. The counter works in a bit reverse mode so the distribution of increments stays uniform over 16 counter periods, see Table 17-5. Reference Manual CCU4, V1.15 17-53 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-5 Dither bit reverse counter counter[3] counter[2] counter[1] counter[0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 The counter is then compared against a programmed value, CC4yDIT.DCV. If the counter value is smaller than the programmed value, a gating signal is generated that can be used to extend the period, to delay the compare or both (controlled by the CC4yTC.DITHE field, see Table 17-6) for one clock cycle. Table 17-6 Dither modes DITHE[1] DITH[0] Mode 0 0 Dither is disabled 0 1 Period is increased by 1 cycle 1 0 Compare match is delayed by 1 cycle 1 1 Period is increased by 1 cycle and compare is delayed by 1 cycle The dither compare value also has an associated shadow register that enables concurrent update with the period/compare register of CC4y. The control logic for the dithering unit is represented on Figure 17-50. Reference Manual CCU4, V1.15 17-54 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Timer Logic Dither Logic CC4yTC.DITHE[0] & 0 Z-1 1 CC4yPR Comp CC4yDIT Output Path CC4yTIMER < & Comp Dither Counter CC4yTC.DITHE CC4yCR Z-1 1 0 & CC4yTC.DITHE[1] Timer clear Figure 17-50 Dither control logic Figure 17-51 to Figure 17-56 show the effect of the different configurations for the dithering function, CC4yTC.DITHE, for both counting schemes, Edge and Center Aligned mode. In each figure, the bit reverse scheme is represented for the dither counter and the compare value was programmed with the value 8H. In each figure, the variable T, represents the period of the counter, while the variable d indicates the duty cycle (status bit is set HIGH). T+1 T T+1 T T+1 T T+1 T Timer Compare CC4yST d+1 Dither counter 0H DCV d 8H d+1 4H d d+1 CH 2H d AH d+1 6H d EH 8H Figure 17-51 Dither timing diagram in edge aligned - CC4yTC.DITHE = 01B Reference Manual CCU4, V1.15 17-55 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) T T T T T T T T Timer Compare CC4yST d-1 Dither counter 0H d 8H d-1 d 4H d-1 CH d 2H AH d-1 d 6H EH 8H DCV Figure 17-52 Dither timing diagram in edge aligned - CC4yTC.DITHE = 10B T+1 T T+1 T T+1 T T+1 T Timer Compare CC4yST d Dither counter d 0H 8H d d 4H d CH d 2H AH d 6H d EH 8H DCV Figure 17-53 Dither timing diagram in edge aligned - CC4yTC.DITHE = 11B T+2 T T+2 T Timer Compare CC4yST d+2 Dither counter 0H DCV d d+2 8H 4H d CH 8H Figure 17-54 Dither timing diagram in center aligned - CC4yTC.DITHE = 01B Reference Manual CCU4, V1.15 17-56 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) T T T T Timer Compare CC4yST d-1 Dither counter 0H d d-1 8H 4H d CH 8H DCV Figure 17-55 Dither timing diagram in center aligned - CC4yTC.DITHE = 10B T+2 T T+2 T Timer CC4yST Dither counter Compare d+1 0H d d+1 8H 4H d CH 8H DCV Figure 17-56 Dither timing diagram in center aligned - CC4yTC.DITHE = 11B Note: When using the dither, is not possible to select a period value of FS when in edge aligned mode. In center aligned mode, the period value must be at least FS - 2. 17.2.11 Prescaler The CCU4 contains a 4 bit prescaler that can be used in two operating modes for each individual slice: • • normal prescaler mode floating prescaler mode The run bit of the prescaler can be set/cleared by SW by writing into the registers, GIDLC.SPRB and GIDLS.CPRB respectively, and it can also be cleared by the run bit of a specific slice. With the last mechanism, the run bit of the prescaler is cleared one clock cycle after the clear of the run bit of the selected slice. To select which slice can perform this action, one should program the GCTRL.PRBC register. Reference Manual CCU4, V1.15 17-57 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.2.11.1 Normal Prescaler Mode In Normal prescaler mode the clock fed to the CC4y counter is a normal fixed division by N, accordingly to the value set in the CC4yPSC.PSIV register. The values for the possible division values are listed in Table 17-7. The CC4yPSC.PSIV value is only modified by a SW access. Notice that each slice has a dedicated prescaler value selector (CC4yPSC.PSIV), which means that the user can select different counter clocks for each Timer Slice (CC4y). Table 17-7 Timer clock division options CC4yPSC.PSIV Resulting clock 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B fccu4 fccu4/2 fccu4/4 fccu4/8 fccu4/16 fccu4/32 fccu4/64 fccu4/128 fccu4/256 fccu4/512 fccu4/1024 fccu4/2048 fccu4/4096 fccu4/8192 fccu4/16384 fccu4/32768 17.2.11.2 Floating Prescaler Mode The floating prescaler mode can be used individually in each slice by setting the register CC4yTC.FPE = 1B. With this mode, the user can not only achieve a better precision on the counter clock for compare operations but also reduce the SW read access for the capture mode. The floating prescaler mode contains additionally to the initial configuration value register, CC4yPSC.PSIV, a compare register, CC4yFPC.PCMP with an associated shadow register mechanism. Reference Manual CCU4, V1.15 17-58 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Figure 17-57 shows the structure of the prescaler in floating mode when the specific slice is in compare mode (no external signal is used for capture). In this mode, the value of the clock division is increment by 1D every time that a timer overflow/underflow (overflow if in Edge Aligned Mode, underflow if in Center Aligned Mode) occurs. In this mode, the Compare Match from the timer is AND gated with the Compare Match of the prescaler and every time that this event occurs, the value of the clock division is updated with the CC4yPSC.PSIV value in the immediately next timer overflow/underflow event. The shadow transfer of the floating prescaler compare value, CC4yFPC.PCMP, is done following the same rules described on Section 17.2.5.2. fCCU4 input clock fTCLK prescaler NX prescaler mode next control first prescaler factor setting counter overflow/underflow compare event =? =? prescaler factor compare reg. counter compare reg. AND Figure 17-57 Floating prescaler in compare mode overview When the specific CC4y is operating in capture mode (when at least one external signal is decoded as capture functionality), the actual value of the clock division also needs to be stored every time that a capture event occurs. The floating prescaler can have up to 4 capture registers (the maximum number of capture registers is dictated by the number of capture registers used in the specific slice). The clock division value continues to be increment by 1D every time that a timer overflow (in capture mode, the slice is always operating in Edge Aligned Mode) occurs and it is loaded with the PSIV value every time that a capture triggers is detected. See the Section 17.2.12.2 for a full description of the usage of the floating prescaler mode in conjunction with compare and capture modes. Reference Manual CCU4, V1.15 17-59 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) fCCU4 input clock prescaler fTCLK NX prescaler mode next control first prescaler factor setting counter overflow capture event prescaler factor capture registers counter capture register Figure 17-58 Floating Prescaler in capture mode overview 17.2.12 CCU4 Usage 17.2.12.1 PWM Signal Generation The CCU4 offers a very flexible range in duty cycle configurations. This range is comprised between 0 to 100%. To generate a PWM signal with a 100% duty cycle in Edge Aligned Mode, one should program the compare value, CC4yCR.CR, to 0000H, see Figure 17-59. In the same manner a 100% duty cycle signal can be generated in Center Aligned Mode, see Figure 17-60. Reference Manual CCU4, V1.15 17-60 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCTclk Period match Period Value CCTimer Comparen Zero = Comparen+1 TRB CDIR PR(shadow) PR/CR value n+1 valuen+1 valuen CC4yST 100% duty cycle Figure 17-59 PWM with 100% duty cycle - Edge Aligned Mode CCTclk Period value Compare n Zero=Compare n+1 CCTimer CDIR PR(shadow) PR/CR valuen+1 valuen value n value n+1 CC4yST 100% duty cycle Figure 17-60 PWM with 100% duty cycle - Center Aligned Mode To generate a PWM signal with 0% duty cycle in Edge Aligned Mode, the compare register should be set with the value programmed into the period value plus 1. In the case that the timer is being used with the full 16 bit capability (counting from 0 to 65535), setting a value bigger than the period value into the compare register is not possible and therefore the smallest duty cycle that can be achieved is 1/FS, see Figure 17-61. In Center Aligned Mode, the counter is never running from 0 to 65535D, due to the fact that it has to overshoot for one clock cycle the value set in the period register. Therefore the user never has a FS counter, which means that generating a 0% duty cycle signal is Reference Manual CCU4, V1.15 17-61 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) always possible by setting a value in the compare register bigger than the one programmed into the period register, see Figure 17-62. CCTclk Period Value n+1 = Compare n+1 (FS) Compare n = Period+1 Period Value n CCTimer Zero TRB CDIR CC4yST 0% duty cycle Duty cycle = 1/Period Figure 17-61 PWM with 0% duty cycle - Edge Aligned Mode CCTclk Compare n+1 Period value CCTimer Comparen Zero CDIR valuen+1 PR(shadow) PR/CR valuen valuen+1 CC4yST 0% duty cycle Figure 17-62 PWM with 0% duty cycle - Center Aligned Mode 17.2.12.2 Prescaler Usage In Normal Prescaler Mode, the frequency of the ftclk fed to the specific CC4y is chosen from the Table 17-7, by setting the CC4yPSC.PSIV with the required value. In Floating Prescaler Mode, the frequency of the ftclk can be modified over a selected timeframe, within the values specified in Table 17-7. This mechanism is specially useful if, when in capture mode, the dynamic of the capture triggers is very slow or unknown. Reference Manual CCU4, V1.15 17-62 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) In Capture Mode, the Floating Prescaler value is incremented by 1 every time that a timer overflow happens and it is set with the initial programmed value when a capture event happens, see Figure 17-63. When using the Floating Prescaler Mode in Capture Mode, the timer should be cleared each time that a capture event happens, CC4yTC.CAPC = 11B. By operating the Capture mode in conjunction with the Floating Prescaler, even for capture signals that have a periodicity bigger that 16 bits, it is possible to use just a single CCU4 Timer Slice without monitoring the interrupt event of the timer overflow, cycle by cycle. For this the user just needs to know what is the timer captured value and the actual prescaler configuration at the time that the capture event occurred. These values are contained in each CC4yCxV register. ftclk Capture event Capture event CCTimer CCPM Increments PVAL PSIV PSIV + 1 T Tx2 Increments Increments PSIV PSIV + 2 PSIV + 1 Increments PSIV + 2 PSIV <Timer_value> x T x 4 Figure 17-63 Floating Prescaler capture mode usage When in Compare Mode, the Floating Prescaler function may be used to achieve a fractional PWM frequency or to perform some frequency modulation. The same incrementing by 1D mechanism is done every time that a overflow/underflow of the Timer occurs and the actual Prescaler value, doesn’t match the one programmed into the CC4yFPC.PCMP register. When a Compare Match from the Timer occurs and the actual Prescaler value is equal to the one programmed on the CC4yFPC.PCMP register, then the Prescaler value is set with the initial value, CC4yPSC.PSIV, when the next occurrence of a timer overflow/underflow. In Figure 17-64, the Compare value of the Floating Prescaler was set to PSIV + 2. Every time that a timer overflow occurs, the value of the Prescaler is incremented by 1, which means that if we give ftclk as the reference frequency for the CC4yPSC.PSIV value, we have ftclk/2 for CC4yPSC.PSIV + 1 and ftclk/4 for CC4yPSC.PSIV + 2. The period over time of the counter becomes: Period = (1/ftclk + 2/ftclk + 4/ftclk) / 3 Reference Manual CCU4, V1.15 (17.10) 17-63 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) The same mechanism is used in Center Aligned Mode, but to keep the rising arcade and falling arcade always symmetrical, instead of the overflow of the timer, the underflow is used, see Figure 17-65. ftclk Period CCTimer Compare Zero CCCM Compare match Correct Compare match CCPM Increments PVAL PSIV Sets the PSIV Increments PSIV + 1 PSIV + 2 PSIV PSIV + 1 T Tx2 PSIV + 2 PSIV + 2 PCMP T Tx2 Tx4 Figure 17-64 Floating Prescaler compare mode usage - Edge Aligned ftclk CCCMU Compare match Correct Compare match CCZM Increments PVAL PSIV Sets the PSIV PSIV + 1 PSIV Increments PSIV + 1 PSIV + 1 PCMP T Tx2 T Figure 17-65 Floating Prescaler compare mode usage - Center Aligned 17.2.12.3 PWM Dither The Dither functionality can be used to achieve a very fine precision on the periodicity of the output state in compare mode. The value set in the dither compare register, CC4yDIT.DCV is crosschecked against the actual value of the dither counter and every Reference Manual CCU4, V1.15 17-64 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) time that the dither counter is smaller than the comparison value one of the follows actions is taken: • • • • • The period is extended for 1 clock cycle - CC4yTC.DITHE = 01B; in edge aligned mode The period is extended for 2 clock cycles - CC4yTC.DITHE = 01B; in center aligned mode The comparison match while counting up (CC4yTCST.CDIR = 0B) is delayed (this means that the status bit is going to stay in the SET state 1 cycle less) for 1 clock cycle - CC4yTC.DITHE = 10B; The period is extended for 1 clock cycle and the comparison match while counting up is delayed for 1 clock cycle - CC4yTC.DITHE = 11B; in edge aligned mode The period is extended for 2 clock cycles and the comparison match while counting up is delayed for 1 clock cycle; center aligned mode The bit reverse counter distributes the number programmed in the CC4yDIT.DCV throughout a window of 16 timer periods. Table 17-8 describes the bit reverse distribution versus the programmed value on the CC4yDIT.DCV field. The fields marked as ’0’ indicate that in that counter period, one of the above described actions, is going to be performed. Table 17-8 Bit reverse distribution DCV Dither counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 C 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 2 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 6 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 5 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 Reference Manual CCU4, V1.15 17-65 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-8 Bit reverse distribution (cont’d) DCV Dither counter 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The bit reverse distribution versus the programmed CC4yDIT.DCV value results in the following values for the Period and duty cycle: DITHE = 01B Period = [(16 - DCV) x T + DCV x (T + 1)]/16; in Edge Aligned Mode (17.11) Duty cycle = [(16 - DCV) x d/T + DCV x (d+1)/(T + 1)]/16; in Edge Aligned Mode(17.12) Period = [(16 - DCV) x T + DCV x (T + 2)]/16; in Center Aligned Mode (17.13) Duty cycle = [(16 - DCV) x d/T + DCV x (d+2)/(T + 2)]/16; in Center Aligned Mode(17.14) DITHE = 10B Period = T ; in Edge Aligned Mode (17.15) Duty cycle = [(16 - DCV) x d/T + DCV x (d-1)/T ]/16; in Edge Aligned Mode (17.16) Period = T ; in Center Aligned Mode (17.17) Duty cycle = [(16 - DCV) x d/T + DCV x (d-1)/T]/16; in Center Aligned Mode (17.18) DITHE = 11B Period = [(16 - DCV) x T + DCV x (T + 1)]/16; in Edge Aligned Mode (17.19) Duty cycle = [(16 - DCV) x d/T + DCV x d/(T + 1)]/16; in Edge Aligned Mode (17.20) Period = [(16 - DCV) x T + DCV x (T + 2)]/16; in Center Aligned Mode (17.21) Duty cycle = [(16 - DCV) x d/T + DCV x (d+1)/(T + 2)]/16; in Center Aligned Mode(17.22) Reference Manual CCU4, V1.15 17-66 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) where: T - Original period of the signal, see Section 17.2.5.1 d - Original duty cycle of the signal, see Section 17.2.5.1 17.2.12.4 Capture Mode Usage Each Timer Slice can make use of 2 or 4 capture registers. Using only 2 capture registers means that only 1 Event was linked to a captured trigger. To use the four capture registers, both capture triggers need to be mapped into an Event (it can be the same signal with different edges selected or two different signals) or the CC4yTC.SCE field needs to be set to 1, which enables the linking of the 4 capture registers. The internal slice mechanism for capturing is the same for the capture trigger 1 or capture trigger 0. Different Capture Events - SCE = 0B Capture trigger 1 (CCcapt1) is appointed to the capture register 2, CC4yC2V and capture register 3, CC4yC3V, while trigger 0 (CCcapt0) is appointed to capture register 1, CC4yC1V and 0, CC4yC0V. In each CCcapt0 event, the timer value is stored into CC4yC1V and the value of the CC4yC1V is transferred into the CC4yC0V. In each CCcapt1 event, the timer value is stored into capture register CC4yC3V and the value of the capture register CC4yC3V is transferred into CC4yC2V. The capture/transfer mechanism only happens if the specific register is not full. A capture register becomes full when receives a new value and becomes empty after the SW has read back the value. The full flag is cleared every time that the SW reads back the CC4yC0V, CC4yC1V, CC4yC2V or CC4yC3V register. The SW can be informed of a new capture trigger by enabling the interrupt source linked to the specific Event. This means that every time that a capture is made an interrupt pulse is generated. In the case that the Floating Prescaler Mode is being used, the actual value of the clock division is also stored in the capture register (CC4yCxV). Figure 17-66 shows an example of how the capture/transfer may be used in a Timer Slice that is using a external signal as count function (to measure the velocity of a rotating device), and an equidistant capture trigger that is used to dictate the timestamp for the velocity calculation (two Timer waveforms are plotted, one that exemplifies the clearing of the timer in each capture event and another without the clearing function active). Reference Manual CCU4, V1.15 17-67 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CCcapt0/ CCcapt1 Period A Timer B cnt0 CC4yC1V/CC4yC3V CC4yC1V/CC4yC3V Full cnt1 cnt2 cnt3 cnt4 SW read SW read SW read cnt5 cnt6 All the registers are full SW read cnt0 CC4yC0V/CC4yC2V cnt2 cnt1 cnt3 CC4yC0V/CC4yC2V Full cnt5 All the registers are full SW read A CAPC = 0H SW read B SW read SW read CAPC = 3H Figure 17-66 Capture mode usage - single channel Same Capture Event - SCE = 1B If the CC4yTC.SCE is set to 1B, all the four capture registers are chained together, emulating a fifo with a depth of 4. In this case, only the capture trigger 1, CCcapt1, is used to perform a capture event. As an example for this mode, one can consider the case where one Timer Slice is being used in capture mode with SCE = 1B, with another external signal that controls the counting. This timer slice can be incremented at different speeds, depending on the frequency of the counting signal. An additional Timer Slice is used to control the capture trigger, dictating the time stamp for the capturing. A simple scheme for this can be seen in Figure 17-67. The CC40ST output of slice 0 was used as capture trigger in the CC41 slice (active on rising and falling edge). The CC40ST output is used as known timebase marker, while the slice timer used for capture is being controlled by external events, e.g. external count. Due to the fact that we have available 4 capture registers, every time that the SW reads back the complete set of values, 3 speed profiles can be measured. Reference Manual CCU4, V1.15 17-68 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Profile read window 1 ms 500 us 500 us CC40Timer CC40ST CC41Timer CC41C3V cnt0 cnt1 cnt2 cnt3 cnt4 cnt5 cnt6 cnt7 cnt8 cnt9 cnt10 cnt11 cnt7 cnt8 cnt9 cnt10 cnt6 cnt7 cnt8 cnt9 cnt5 cnt6 cnt7 cnt8 CC41C3V full SW read CC41C2V cnt0 cnt1 cnt2 SW read cnt3 cnt4 cnt5 cnt6 CC41C2V full SW read CC41C1V cnt0 cnt1 SW read cnt2 cnt3 cnt4 cnt5 CC41C1V full SW read SW read CC41C0V cnt0 cnt1 cnt2 cnt3 cnt4 CC41C0V full SW read SW read Figure 17-67 Three Capture profiles - CC4yTC.SCE = 1B To calculate the three different profiles in Figure 17-67, the 4 capture registers need to be read during the pointed read window. After that, the profile calculation is done: Profile 1 = CC41C1Vinfo - CC41C0Vinfo Profile 2 = CC41C2Vinfo - CC41C1Vinfo Reference Manual CCU4, V1.15 17-69 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Profile 3= CC41C3Vinfo - CC41C2Vinfo Note: This is an example and therefore several Timer Slice configurations and software loops can be implemented. High Dynamics Capturing In some cases the dynamics of the capture trigger(s) may vary greatly over time. This will impose that the software needs to be prepared for the worst case scenario, where the frequency of the capture triggers may be very high. In applications where cycle-bycycle calculation is needed (calculation in each capture trigger), then this constraints needs to be met by the software. Nevertheless for applications where a cycle-by-cycle calculation is not needed, the software can read back the FIFO data register in a periodic base and fetch all the data that has been captured so far, Figure 17-68. CCU4x SW + CMP 1 CC40 data Channel X - capture for CMP 1 ... Extended read register ECRD CC41 RAM Int CMP 1 buffer - timestamp read back for SW ... Figure 17-68 High dynamics capturing with software controlled timestamp In this scenario, the software/CPU will read back the complete set of capture registers (2 or 4 depending on the chosen configuration), every time that an interrupt is triggered from the timestamp timer (the periodicity of this timer can also be adjusted on-the-fly). Due to the fact that every capture register offers a full flag status bit, the software/CPU can always read back the complete set of registers. At the time of the data processing, this full flag is then checked, indicating if this value needs to be processed or not. This FIFO read back functionality can also be used for applications that impose a heavy load on the system, which may not guarantee fixed access times to read back the captured data. Reference Manual CCU4, V1.15 17-70 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) load* * this can be dictated by interrutps with higher priority Capture event Threshold that enables computation t SW reads back from the ECRD until it finds an empty register SW reads back from the ECRD until it finds an empty register SW reads back from the ECRD until it finds an empty register Figure 17-69 Extended read back during high load Capture Grouping In applications where multiple capture Timers are needed and the priority of the capture routines, does not imply that a cycle-by-cycle calculation needs to be done for every event, it may be suitable to group all the timers in the same CCU4x unit, Figure 17-70. CCU4x + CMP 1 CC40 - capture for CMP 1 RAM CMP 1 buffer ECRD1 CMP ... 2 buffer - OSC 1 buffer CC41 -capture for CMP 2 ECRD1 + CMP 2 CC42 -capture for OSC 1 SW ECRD1 - Channel X ... CC43 - timestamp read back for SW Int OSC 1 Figure 17-70 Capture grouping with extended read back Reference Manual CCU4, V1.15 17-71 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) By setting the ECM bitfield for the TImer Slices used for capturing, the extended read back mode enables the reading back of data always in the proper capture order (from oldest to newest data). A timestamp timer is then used to trigger the Software/CPU to read back all the capture data present in the Timer Slices. Every time that the interrupt is sensed, the Software/CPU (in this example) reads back the complete set of capture registers (via the ECRD address) for all Timer Slices. Due to the fact that each data read has a full flag indicator, the Software/CPU can read back the complete set of capture registers from all timers. This allows a fixed memory allocation that is as big as the number of captured registers, Figure 17-71 (in this example 4 capture registers for each Timer Slice are being used). The additional lost value bitfield (LCV) on the header of each ECRD data, will indicate if any capture trigger was lost between read operations (this can happen if the capture triggers are faster than the routine that is reading back the values). Reference Manual CCU4, V1.15 17-72 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) MEMORY 1st Read Back 2nd Read Back 2nd Read Back Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 2 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 1 previous data Previous Timer 0 previous data Previous Timer 0 previous data Previous Timer 0 previous data Previous Timer 0 previous data Previous Timer 0 previous data Empty Timer 0 xxxxH Empty Timer 0 previous data Previous Timer 0 5888 H Full Timer 0 5888 H Full Full Timer 0 5790 H Full Timer 0 5790 H Full Timer 0 5790 H ... 10th Read Back 11th Read Back Timer 2 previous data Previous Timer 2 previous data Timer 2 previous data 12th Read Back Previous Timer 2 xxxxH Empty Previous Timer 2 xxxxH Empty Timer 2 xxxxH Empty Timer 2 xxxx H Empty Timer 2 xxxxH Empty Timer 2 xxxxH Empty Timer 2 0009 H Full Timer 2 0009 H Full Timer 2 0009 H Full Timer 1 0FCCH Full Timer 1 0FCCH Full Timer 1 0FCCH Full Timer 1 0FC0H Full Timer 1 0FC0H Full Timer 1 0FC0H Full Timer 1 0F09H Full Timer 1 0F09H Full Timer 1 0F09H Full Timer 1 0EFFH Full Timer 1 0EFFH Full Timer 1 0EFFH Full Timer 0 xxxx H Empty Timer 0 xxxxH Empty Timer 0 xxxxH Empty Timer 0 xxxx H Empty Timer 0 xxxxH Empty Timer 0 xxxxH Empty Timer 0 5888 H Full Timer 0 5888 H Full Timer 0 5888 H Full Timer 0 5790 H Full Timer 0 5790 H Full Timer 0 5790 H Full Figure 17-71 Memory structure for extended read back 17.3 Service Request Generation Each CCU4 slice has an interrupt structure as the one in Figure 17-72. The register CC4yINTS is the status register for the interrupt sources. Each dedicated interrupt Reference Manual CCU4, V1.15 17-73 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) source can be set or cleared by SW, by writing into the specific bit in the CC4ySWS and CC4ySWR registers respectively. Each interrupt source can be enabled/disabled via the CC4yINTE register. An enabled interrupt source will always generate a pulse on the service request line even if the specific status bit was not cleared. Table 17-9 describes the interrupt sources of each CCU4 slice. The interrupt sources, Period Match while counting up and one Match while counting down are ORed together. The same mechanism is applied to the Compare Match while counting up and Compare Match while counting down. The interrupt sources for the external events are directly linked with the configuration set on the CC4yINS.EVxEM. If an event is programmed to be active on both edges, that means that service request pulse is going to be generated when any transition on the external signal is detected. If the event is linked with a level function, the CC4yINS.EVxEM still can be programmed to enable a service request pulse. The TRAP event doesn’t need any of extra configuration for generating the service request pulse when the slice enters the TRAP state. Table 17-9 Interrupt sources Signal Description CCINEV0_E Event 0 edge(s) information from event selector. Used when an external signal should trigger an interrupt. CCINEV1_E Event 1 edge(s) information from event selector. Used when an external signal should trigger an interrupt. CCINEV2_E Event 2 edge(s) information from event selector. Used when an external signal should trigger an interrupt. CCPM_U Period Match while counting up CCCM_U Compare Match while counting up CCCM_D Compare Match while counting down CCOM_D One Match while counting down Trap state set Entering Trap State. Will set the E2AS Reference Manual CCU4, V1.15 17-74 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) SW Set Enables/Disables the interrupts Selects the line for the interrupt CC4ySWS CC4yINTE CC4ySRS CC4yINTS CCINEV0_E E0AS CCINEV1_E E1AS CCINEV2_E E2AS CC4ySR0 Event selector Timer Logic CCCM_D CMDS CCCM_U CMUS CCPM_U PMUS CCOM_D OMDS CC4ySR1 ≥1 Node Pointer CC4ySR2 CC4ySR3 ≥1 Trap state set Trap Control Trap state clear Trap flag clear CC4ySWR SW Clear Figure 17-72 Slice interrupt structure overview Each of the interrupt events can then be forwarded to one of the slice’s four service request lines, Figure 17-73. The value set on the CC4ySRS controls which interrupt event is mapped into which service request line. Reference Manual CCU4, V1.15 17-75 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Service request source 1 Node pointer 1 Service request source 2 Service request source 3 ≥1 CC4ySR0 From other sources ≥1 CC4ySR1 From other sources ≥1 CC4ySR2 From other sources ≥1 CC4ySR3 ... Service request source 4 Service request source 5 From other sources Node pointer 5 Figure 17-73 Slice Interrupt Node Pointer overview The four service request lines of each slice are OR together inside the kernel of the CCU4, see Figure 17-74. This means that there are only four service request lines per CCU4, that can have in each line interrupt requests coming from different slices. Reference Manual CCU4, V1.15 17-76 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) CC40SR0 CC41SR0 CC42SR0 ≥1 CCU4x.SR0 ≥1 CCU4x.SR1 ≥1 CCU4x.SR2 ≥1 CCU4x.SR3 CC43SR0 CC40SR1 CC41SR1 CC42SR1 CC43SR1 CC40SR2 CC41SR2 CC42SR2 CC43SR2 CC40SR3 CC41SR3 CC42SR3 CC43SR3 Figure 17-74 CCU4 service request overview 17.4 Debug Behavior In suspend mode, the functional clocks for all slices as well the prescaler are stopped. The registers can still be accessed by the CPU (read only). This mode is useful for debugging purposes, e.g. where the current device status should be frozen in order to get a snapshot of the internal values. In suspend mode, all the slice timers are stopped. The suspend mode is non-intrusive concerning the register bits. This means register bits are not modified by hardware when entering or leaving the suspend mode. Entry into suspend mode can be configured at the kernel level by means of the field GCTRL.SUSCFG. The module is only functional after the suspend signal becomes inactive. 17.5 Power, Reset and Clock The following sections describe the operating conditions, characteristics and timing requirements for the CCU4. All the timing information is related to the module clock, fccu4. 17.5.1 Clocks Module Clock The module clock of the CCU4 module is described in the SCU chapter as fPCLK. The bus interface clock of the CCU4 module is described in the SCU chapter as fMCLK. Reference Manual CCU4, V1.15 17-77 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) It is possible to disable the module clock for the CCU4 via the GSTAT register, nevertheless, there may be a dependency of the fccu4 through the different CCU4 instances. One should address the SCU Chapter for a complete description of the product clock scheme. If module clock dependencies exist through different IP instances, then one can disable the module clock internally inside the specific CCU4, by disabling the prescaler (GSTAT.PRB = 0B). External Clock It is possible to use an external clock as source for the prescaler, and consequently for all the timer Slices, CC4y. This external source can be connected to one of the CCU4x.CLK[C...A] inputs. This external source is nevertheless synchronized against fccu4. Table 17-10 External clock operating conditions Parameter Symbol feclk toneclk toffeclk Frequency ON time OFF time Values Unit Note / Test Con dition Min. Typ. Max. – – fccu4/4 MHz 2Tccu41)2) 2Tccu41)2) – – ns – – ns Only the rising edge is used 1) Only valid if the signal was not previously synchronized/generated with the fccu4 clock (or a synchronous clock) 2) 50% duty cycle is not obligatory 17.5.2 Power The CCU4 is inside the power core domain, therefore no special considerations about power up or power down sequences need to be taken. For an explanation about the different power domains, please address the SCU (System Control Unit) chapter. An internal power down mode for the CCU4, can be achieved by disabling the clock inside the CCU4 itself. For this one should set the GSTAT register with the default reset value (via the idle mode set register, GIDLS). 17.6 Initialization and System Dependencies Reference Manual CCU4, V1.15 17-78 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.6.1 Initialization Sequence The initialization sequence for an application that is using the CCU4, should be the following: 1st Step: Enable the CCU4 clock via the specific SCU register, CGATCLR0. 2nd Step: Enable the prescaler block, by writing 1B to the GIDLC.SPRB field. 3rd Step: Configure the global CCU4 register GCTRL 4th Step: Configure all the registers related to the required Timer Slice(s) functions, including the interrupt/service request configuration. 5th Step: If needed, configure the startup value for a specific Compare Channel Status, of a Timer Slice, by writing 1B to the specific GCSS.SyTS. 6th Step: Enable the specific timer slice(s), CC4y, by writing 1B to the specific GIDLC.CSyI. 7th Step: For all the Timer Slices that should be started synchronously via SW, the specific system register localized in the SCU, CCUCON, that enables a synchronous timer start should be addressed. The SCU.GSC4x input signal needs to be configured previously as a start function, see Section 17.2.7.1. 17.6.2 System Dependencies Each CCU4 may have different dependencies regarding module and bus clock frequencies. This dependencies should be addressed in the SCU and System Architecture Chapters. Dependencies between several peripherals, regarding different clock operating frequencies may also exist. This should be addressed before configuring the connectivity between the CCU4 and some other peripheral. The following topics must be taken into consideration for good CCU4 and system operation: • • • • • CCU4 module clock must be at maximum two times faster than the module bus interface clock Module input triggers for the CCU4 must not exceed the module clock frequency (if the triggers are generated internally in the device) Module input triggers for the CCU4 must not exceed the frequency dictated in Section 17.5.1 Frequency of the CCU4 outputs used as triggers/functions on other modules, must be crosschecked on the end point Applying and removing CCU4 from reset, can cause unwanted operations in other modules. This can occur if the modules are using CCU4 outputs as triggers/functions. Reference Manual CCU4, V1.15 17-79 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) 17.7 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 17-11 Registers Address Space Module Base Address End Address CCU40 48040000H 4804FFFFH Note CCU4x Global registers CC43 GCTRL CC42 GSTAT CC41 GIDLS CC40 Control registers Data registers GIDLC Interrupt registers CC40INS CC40Timer CC40INTS CC40CMC CC40C0V CC40INTE CC40TCST CC40C1V CC40SWS CC40TCSET CC40C2V CC40SWR CC40TCCLR CC40C3V CC40SRS GCSS GCSC GCST ECRD CC40TC CC40PSL CC40DIT CC40PSC CC40FPC CC40FPCS CC40PR CC40PRS CC40CR CC40CRS Figure 17-75 CCU4 registers overview Reference Manual CCU4, V1.15 17-80 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 Short Name Description Offset Access Mode Description Addr.1) Read Write See CCU4 Global Registers U, PV Page 17-86 0000H U, PV GSTAT General Slice Status Register 0004H U, PV BE GIDLS General Idle Enable Register 0008H U, PV U, PV Page 17-90 GIDLC General Idle Disable Register 000CH U, PV U, PV Page 17-92 GCSS General Channel Set Register 0010H U, PV U, PV Page 17-93 GCSC General Channel Clear Register 0014H U, PV U, PV Page 17-95 GCST General Channel Status Register 0018H U, PV BE Page 17-98 MIDR Module Identification Register 0080H U, PV BE Page 17-101 GCTRL Module General Control Register Page 17-89 CC40 Registers CC40INS Input Selector Unit Configuration 0100H U, PV U, PV Page 17-101 CC40CMC Connection Matrix Configuration 0104H U, PV U, PV Page 17-103 CC40TST Timer Run Status 0108H U, PV BE Page 17-106 CC40TCSET Timer Run Set 010CH U, PV U,PV Page 17-107 CC40TCCLR Timer Run Clear 0110H U, PV U, PV Page 17-108 CC40TC General Timer Configuration 0114H U, PV U, PV Page 17-109 CC40PSL Output Passive Level Configuration 0118H U, PV U, PV Page 17-114 CC40DIT Dither Configuration 011CH U, PV BE Page 17-114 CC40DITS Dither Shadow Register 0120H U, PV U, PV Page 17-115 CC40PSC Prescaler Configuration 0124H U, PV U, PV Page 17-116 CC40FPC Prescaler Compare Value 0128H U, PV U, PV Page 17-117 Reference Manual CCU4, V1.15 17-81 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See CC40FPCS Prescaler Shadow Compare Value 012CH U, PV U, PV Page 17-118 CC40PR Timer Period Value 0130H U, PV BE Page 17-118 CC40PRS Timer Period Shadow Value 0134H U, PV U, PV Page 17-119 CC40CR Timer Compare Value 0138H U, PV BE CC40CRS Timer Compare Shadow Value 013CH U, PV U, PV Page 17-121 CC40TIMER Timer Current Value 0170H U, PV U, PV Page 17-122 CC40C0V Capture Register 0 Value 0174H U, PV BE Page 17-122 CC40C1V Capture Register 1Value 0178H U, PV BE Page 17-123 CC40C2V Capture Register 2 Value 017CH U, PV BE Page 17-124 CC40C3V Capture Register 3 Value 0180H U, PV BE Page 17-125 Page 17-126 Page 17-120 CC40INTS Interrupt Status 01A0H U, PV BE CC40INTE Interrupt Enable 01A4H U, PV U, PV Page 17-128 CC40SRS Interrupt Configuration 01A8H U, PV U, PV Page 17-130 CC40SWS Interrupt Status Set 01ACH U, PV U, PV Page 17-131 CC40SWR Interrupt Status Clear 01B0H U, PV U, PV Page 17-133 CC40ECRD0 Extended Read Back 0 01B8H U, PV BE Page 17-134 CC40ECRD1 Extended Read Back 1 01BCH U, PV BE Page 17-136 CC41 Registers CC41INS Input Selector Unit Configuration 0200H U, PV U, PV Page 17-101 CC41CMC Connection Matrix Configuration 0204H U, PV U, PV Page 17-103 CC41TST Timer Run Status 0208H U, PV BE Page 17-106 CC41TCSET Timer Run Set Page 17-107 020CH U, PV U,PV CC41TCCLR Timer Run Clear 0210H U, PV U, PV Page 17-108 CC41TC General Timer Configuration 0214H U, PV U, PV Page 17-109 CC41PSL Output Passive Level Configuration 0218H U, PV U, PV Page 17-114 Reference Manual CCU4, V1.15 17-82 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See Page 17-114 CC41DIT Dither Configuration 021CH U, PV BE CC41DITS Dither Shadow Register 0220H U, PV U, PV Page 17-115 CC41PSC Prescaler Configuration 0224H U, PV U, PV Page 17-116 CC41FPC Prescaler Compare Value 0228H U, PV U, PV Page 17-117 CC41FPCS Prescaler Shadow Compare Value 022CH U, PV U, PV Page 17-118 CC41PR Timer Period Value 0230H U, PV BE CC41PRS Timer Period Shadow Value 0234H U, PV U, PV Page 17-119 CC41CR Timer Compare Value 0238H U, PV BE CC41CRS Timer Compare Shadow Value 023CH U, PV U, PV Page 17-121 CC41TIMER Timer Current Value 0270H U, PV U, PV Page 17-122 Page 17-118 Page 17-120 CC41C0V Capture Register 0 Value 0274H U, PV BE Page 17-122 CC41C1V Capture Register 1Value 0278H U, PV BE Page 17-123 CC41C2V Capture Register 2 Value 027CH U, PV BE Page 17-124 CC41C3V Capture Register 3 Value 0280H U, PV BE Page 17-125 CC41INTS Interrupt Status 02A0H U, PV BE Page 17-126 CC41INTE Interrupt Enable 02A4H U, PV U, PV Page 17-128 CC41SRS Interrupt Configuration 02A8H U, PV U, PV Page 17-130 CC41SWS Interrupt Status Set 02ACH U, PV U, PV Page 17-131 CC41SWR Interrupt Status Clear 02B0H U, PV U, PV Page 17-133 CC41ECRD0 Extended Read Back 0 02B8H U, PV BE Page 17-134 CC41ECRD1 Extended Read Back 1 02BCH U, PV BE Page 17-136 CC42 Registers CC42INS Input Selector Unit Configuration 0300H U, PV U, PV Page 17-101 CC42CMC Connection Matrix Configuration 0304H U, PV U, PV Page 17-103 CC42TST Timer Run Status 0308H U, PV BE Page 17-106 CC42TCSET Timer Run Set 030CH U, PV U,PV Page 17-107 Reference Manual CCU4, V1.15 17-83 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See CC42TCCLR Timer Run Clear 0310H U, PV U, PV Page 17-108 CC42TC General Timer Configuration 0314H U, PV U, PV Page 17-109 CC42PSL Output Passive Level Configuration 0318H U, PV U, PV Page 17-114 CC42DIT Dither Configuration 031CH U, PV BE CC42DITS Dither Shadow Register 0320H U, PV U, PV Page 17-115 CC42PSC Prescaler Configuration 0324H U, PV U, PV Page 17-116 CC42FPC Prescaler Compare Value 0328H U, PV U, PV Page 17-117 CC42FPCS Prescaler Shadow Compare Value 032CH U, PV U, PV Page 17-118 CC42PR Timer Period Value 0330H U, PV BE CC42PRS Timer Period Shadow Value 0334H U, PV U, PV Page 17-119 CC42CR Timer Compare Value 0338H U, PV BE CC42CRS Timer Compare Shadow Value 033CH U, PV U, PV Page 17-121 CC42TIMER Timer Current Value 0370H U, PV U, PV Page 17-122 CC42C0V Capture Register 0 Value 0374H U, PV BE Page 17-122 CC42C1V Capture Register 1Value 0378H U, PV BE Page 17-123 CC42C2V Capture Register 2 Value 037CH U, PV BE Page 17-124 CC42C3V Capture Register 3 Value 0380H U, PV BE Page 17-125 Page 17-126 Page 17-114 Page 17-118 Page 17-120 CC42INTS Interrupt Status 03A0H U, PV BE CC42INTE Interrupt Enable 03A4H U, PV U, PV Page 17-128 CC42SRS Interrupt Configuration 03A8H U, PV U, PV Page 17-130 CC42SWS Interrupt Status Set 03ACH U, PV U, PV Page 17-131 CC42SWR Interrupt Status Clear 03B0H U, PV U, PV Page 17-133 CC42ECRD0 Extended Read Back 0 03B8H U, PV BE Page 17-134 CC42ECRD1 Extended Read Back 1 03BCH U, PV BE Page 17-136 CC43 Registers CC43INS Input Selector Unit Configuration Reference Manual CCU4, V1.15 0400H 17-84 U, PV U, PV Page 17-101 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See CC43CMC Connection Matrix Configuration 0404H U, PV U, PV Page 17-103 CC43TST Timer Run Status 0408H U, PV BE Page 17-106 CC43TCSET Timer Run Set Page 17-107 040CH U, PV U,PV CC43TCCLR Timer Run Clear 0410H U, PV U, PV Page 17-108 CC43TC General Timer Configuration 0414H U, PV U, PV Page 17-109 CC43PSL Output Passive Level Configuration 0418H U, PV U, PV Page 17-114 CC43DIT Dither Configuration 041CH U, PV BE Page 17-114 CC43DITS Dither Shadow Register 0420H U, PV U, PV Page 17-115 CC43PSC Prescaler Configuration 0424H U, PV U, PV Page 17-116 CC43FPC Prescaler Compare Value 0428H U, PV U, PV Page 17-117 CC43FPCS Prescaler Shadow Compare Value 042CH U, PV U, PV Page 17-118 CC43PR Timer Period Value 0430H U, PV BE Page 17-118 CC43PRS Timer Period Shadow Value 0434H U, PV U, PV Page 17-119 CC43CR Timer Compare Value 0438H U, PV BE CC43CRS Timer Compare Shadow Value 043CH U, PV U, PV Page 17-121 CC43TIMER Timer Current Value 0470H U, PV U, PV Page 17-122 Page 17-120 CC43C0V Capture Register 0 Value 0474H U, PV BE Page 17-122 CC43C1V Capture Register 1Value 0478H U, PV BE Page 17-123 CC43C2V Capture Register 2 Value 047CH U, PV BE Page 17-124 CC43C3V Capture Register 3 Value 0480H U, PV BE Page 17-125 CC43INTS Interrupt Status 04A0H U, PV BE Page 17-126 CC43INTE Interrupt Enable 04A4H U, PV U, PV Page 17-128 CC43SRS Interrupt Configuration 04A8H U, PV U, PV Page 17-130 CC43SWS Interrupt Status Set 04ACH U, PV U, PV Page 17-131 CC43SWR Interrupt Status Clear 04B0H U, PV Page 17-133 Reference Manual CCU4, V1.15 17-85 U, PV V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Table 17-12 Register Overview of CCU4 (cont’d) Short Name Description Offset Access Mode Description Addr.1) Read Write See CC43ECRD0 Extended Read Back 0 04B8H U, PV BE Page 17-134 CC43ECRD1 Extended Read Back 1 04BCH U, PV BE Page 17-136 1) The absolute register address is calculated as follows: Module Base Address + Offset Address (shown in this column) 17.7.1 Global Registers GCTRL The register contains the global configuration fields that affect all the timer slices inside CCU4. GCTRL Global Control Register 31 30 29 28 27 (0000H) 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 MSDE rw 13 12 11 10 9 8 MSE MSE MSE MSE SUSCFG 3 2 1 0 rw Reference Manual CCU4, V1.15 rw rw rw rw 17-86 0 PCIS 0 PRBC r rw r rw V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description PRBC [2:0] rw Prescaler Clear Configuration This register controls how the prescaler Run Bit and internal registers are cleared. 000B SW only 001B GSTAT.PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared. 010B GSTAT.PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared. 011B GSTAT.PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared. 100B GSTAT.PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared. PCIS [5:4] rw Prescaler Input Clock Selection 00B Module clock 01B CCU4x.ECLKA 10B CCU4x.ECLKB 11B CCU4x.ECLKC SUSCFG [9:8] rw Suspend Mode Configuration This field controls the entering in suspend mode for all the CAPCOM4 slices. 00B 01B 10B 11B MSE0 10 rw Slice 0 Multi Channel shadow transfer enable When this field is set, a shadow transfer of slice 0 can be requested not only by SW but also via the CCU4x.MCSS input. 0B 1B Reference Manual CCU4, V1.15 Suspend request ignored. The module never enters in suspend Stops all the running slices immediately. Safe stop is not applied. Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. Shadow transfer can only be requested by SW Shadow transfer can be requested via SW and via the CCU4x.MCSS input. 17-87 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description MSE1 11 rw Slice 1 Multi Channel shadow transfer enable When this field is set, a shadow transfer of slice 1 can be requested not only by SW but also via the CCU4x.MCSS input. 0B 1B MSE2 12 rw Slice 2 Multi Channel shadow transfer enable When this field is set, a shadow transfer of slice 2 can be requested not only by SW but also via the CCU4x.MCSS input. 0B 1B MSE3 13 rw [15:14] rw Shadow transfer can only be requested by SW Shadow transfer can be requested via SW and via the CCU4x.MCSS input. Multi Channel shadow transfer request configuration This field configures the type of shadow transfer requested via the CCU4x.MCSS input. The field CC4yTC.MSEy needs to be set in order for this configuration to have any effect. 00B 01B 10B 11B Reference Manual CCU4, V1.15 Shadow transfer can only be requested by SW Shadow transfer can be requested via SW and via the CCU4x.MCSS input. Slice 3 Multi Channel shadow transfer enable When this field is set, a shadow transfer of slice 3 can be requested not only by SW but also via the CCU4x.MCSS input. 0B 1B MSDE Shadow transfer can only be requested by SW Shadow transfer can be requested via SW and via the CCU4x.MCSS input. Only the shadow transfer for period and compare values is requested Shadow transfer for the compare, period and prescaler compare values is requested Reserved Shadow transfer for the compare, period, prescaler and dither compare values is requested 17-88 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits 0 3, [7:6], r [31:16] Type Description Reserved A read always returns 0. GSTAT The register contains the status of the prescaler and each timer slice (idle mode or running). GSTAT Global Status Register 31 30 29 28 (0004H) 27 26 25 24 Reset Value: 0000000FH 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 PRB 0 S3I S2I S1I S0I r rh r r r r r Field Bits Type Description S0I 0 r CC40 IDLE status This bit indicates if the CC40 slice is in IDLE mode or not. In IDLE mode the clocks for the CC40 slice are stopped. Running 0B 1B Idle S1I 1 r CC41 IDLE status This bit indicates if the CC41 slice is in IDLE mode or not. In IDLE mode the clocks for the CC41 slice are stopped. Running 0B 1B Idle Reference Manual CCU4, V1.15 17-89 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description S2I 2 r CC42 IDLE status This bit indicates if the CC42 slice is in IDLE mode or not. In IDLE mode the clocks for the CC42 slice are stopped. Running 0B Idle 1B S3I 3 r CC43 IDLE status This bit indicates if the CC43 slice is in IDLE mode or not. In IDLE mode the clocks for the CC43 slice are stopped. Running 0B 1B Idle PRB 8 rh Prescaler Run Bit 0B Prescaler is stopped 1B Prescaler is running 0 [7:4], [31:9] r Reserved Read always returns 0. GIDLS Through this register one can set the prescaler and the specific timer slices into idle mode. GIDLS Global Idle Set 31 30 (0008H) 29 28 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 9 8 0 PSIC CPR B 0 r w w r Reference Manual CCU4, V1.15 11 10 17-90 SS3I SS2I SS1I SS0I w w w w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description SS0I 0 w CC40 IDLE mode set Writing a 1B to this bit sets the CC40 slice in IDLE mode. The clocks for the slice are stopped when in IDLE mode. When entering IDLE, the internal slice registers are not cleared. A read access always returns 0. SS1I 1 w CC41 IDLE mode set Writing a 1B to this bit sets the CC41 slice in IDLE mode. The clocks for the slice are stopped when in IDLE mode. When entering IDLE, the internal slice registers are not cleared. A read access always returns 0. SS2I 2 w CC42 IDLE mode set Writing a 1B to this bit sets the CC42 slice in IDLE mode. The clocks for the slice are stopped when in IDLE mode. When entering IDLE, the internal slice registers are not cleared. A read access always returns 0. SS3I 3 w CC43 IDLE mode set Writing a 1B to this bit sets the CC43 slice in IDLE mode. The clocks for the slice are stopped when in IDLE mode. When entering IDLE, the internal slice registers are not cleared. A read access always returns 0. CPRB 8 w Prescaler Run Bit Clear Writing a 1B into this register clears the Run Bit of the prescaler. Prescaler internal registers are not cleared. A read always returns 0. PSIC 9 w Prescaler clear Writing a 1B to this register clears the prescaler counter. It also loads the PSIV into the PVAL field for all Timer Slices. This performs a re alignment of the timer clock for all Slices. The Run Bit of the prescaler is not cleared. A read always returns 0. 0 [7:4], r [31:10] Reference Manual CCU4, V1.15 Reserved Read always returns 0. 17-91 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) GIDLC Through this register one can remove the prescaler and the specific timer slices from idle mode. GIDLC Global Idle Clear 31 30 29 (000CH) 28 27 26 25 24 Reset Value: 00000000H 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 0 r 15 14 13 12 11 10 9 8 0 SPR B 0 r w r CS3I CS2I CS1I CS0I w w w w Field Bits Type Description CS0I 0 w CC40 IDLE mode clear Writing a 1B to this bit removes the CC40 from IDLE mode. A read access always returns 0. CS1I 1 w CC41 IDLE mode clear Writing a 1B to this bit removes the CC41 from IDLE mode. A read access always returns 0. CS2I 2 w CC42 IDLE mode clear Writing a 1B to this bit removes the CC42 from IDLE mode. A read access always returns 0. CS3I 3 w CC43 IDLE mode clear Writing a 1B to this bit removes the CC43 from IDLE mode. A read access always returns 0. SPRB 8 w Prescaler Run Bit Set Writing a 1B into this register sets the Run Bit of the prescaler. A read always returns 0. 0 [7:4], [31:9] r Reserved Read always returns 0. GCSS Through this register one can request a shadow transfer for the specific timer slice(s) and set the status bit for each of the compare channels. Reference Manual CCU4, V1.15 17-92 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) GCSS Global Channel Set 31 30 29 28 (0010H) 27 26 25 24 23 Reset Value: 00000000H 22 21 20 r 0 14 13 12 S3P S3D S3S SE SE E r w w w 11 0 10 9 8 S2P S2D S2S SE SE E r w 18 17 16 S3S S2S S1S S0S TS TS TS TS 0 15 19 w w 7 0 r 6 5 4 S1P S1D S1S SE SE E w w w w w w w 3 2 1 0 0 r S0P S0D S0S SE SE E w w w Field Bits Type Description S0SE 0 w Slice 0 shadow transfer set enable Writing a 1B to this bit will set the GCST.S0SS field, enabling then a shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S0DSE 1 w Slice 0 Dither shadow transfer set enable Writing a 1B to this bit will set the GCST.S0DSS field, enabling then a shadow transfer for the Dither compare value. A read always returns 0. S0PSE 2 w Slice 0 Prescaler shadow transfer set enable Writing a 1B to this bit will set the GCST.S0PSS field, enabling then a shadow transfer for the prescaler compare value. A read always returns 0. S1SE 4 w Slice 1 shadow transfer set enable Writing a 1B to this bit will set the GCST.S1SS field, enabling then a shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S1DSE 5 w Slice 1 Dither shadow transfer set enable Writing a 1B to this bit will set the GCST.S1DSS field, enabling then a shadow transfer for the Dither compare value. A read always returns 0. Reference Manual CCU4, V1.15 17-93 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description S1PSE 6 w Slice 1 Prescaler shadow transfer set enable Writing a 1B to this bit will set the GCST.S1PSS field, enabling then a shadow transfer for the prescaler compare value. A read always returns 0. S2SE 8 w Slice 2 shadow transfer set enable Writing a 1B to this bit will set the GCST.S2SS field, enabling then a shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S2DSE 9 w Slice 2 Dither shadow transfer set enable Writing a 1B to this bit will set the GCST.S2DSS field, enabling then a shadow transfer for the Dither compare value. A read always returns 0. S2PSE 10 w Slice 2 Prescaler shadow transfer set enable Writing a 1B to this bit will set the GCST.S2PSS field, enabling then a shadow transfer for the prescaler compare value. A read always returns 0. S3SE 12 w Slice 3 shadow transfer set enable Writing a 1B to this bit will set the GCST.S3SS field, enabling then a shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S3DSE 13 w Slice 3 Dither shadow transfer set enable Writing a 1B to this bit will set the GCST.S3DSS field, enabling then a shadow transfer for the Dither compare value. A read always returns 0. S3PSE 14 w Slice 3 Prescaler shadow transfer set enable Writing a 1B to this bit will set the GCST.S3PSS field, enabling then a shadow transfer for the prescaler compare value. A read always returns 0. S0STS 16 w Slice 0 status bit set Writing a 1B into this field sets the status bit of slice 0 (GCST.CC40ST) to 1B. A read always returns 0. Reference Manual CCU4, V1.15 17-94 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description S1STS 17 w Slice 1 status bit set Writing a 1B into this field sets the status bit of slice 1 (GCST.CC41ST) to 1B. A read always returns 0. S2STS 18 w Slice 2 status bit set Writing a 1B into this field sets the status bit of slice 2 (GCST.CC42ST) to 1B. A read always returns 0. S3STS 19 w Slice 3 status bit set Writing a 1B into this field sets the status bit of slice 3 (GCST.CC43ST) to 1B. A read always returns 0. 0 3, 7, r 11, 15, [31:20] Reserved Read always returns 0. GCSC Through this register one can reset a shadow transfer request for the specific timer slice and clear the status bit for each the compare channels. GCSC Global Channel Clear 31 30 29 28 (0014H) 27 26 25 24 23 Reset Value: 00000000H 22 21 20 r 0 r 14 13 12 S3P S3D S3S SC SC C w w Reference Manual CCU4, V1.15 w 11 0 r 10 9 8 S2P S2D S2S SC SC C w 18 17 16 S3S S2S S1S S0S TC TC TC TC 0 15 19 w w 7 0 r 17-95 6 5 4 S1P S1D S1S SC SC C w w w w w w w 3 2 1 0 0 r S0P S0D S0S SC SC C w w w V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description S0SC 0 w Slice 0 shadow transfer clear Writing a 1B to this bit will clear the GCST.S0SS field, canceling any pending shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S0DSC 1 w Slice 0 Dither shadow transfer clear Writing a 1B to this bit will clear the GCST.S0DSS field, canceling any pending shadow transfer for the Dither compare value. A read always returns 0. S0PSC 2 w Slice 0 Prescaler shadow transfer clear Writing a 1B to this bit will clear the GCST.S0PSS field, canceling any pending shadow transfer for the prescaler compare value. A read always returns 0. S1SC 4 w Slice 1 shadow transfer clear Writing a 1B to this bit will clear the GCST.S1SS field, canceling any pending shadow transfer for the Period, Compare and Passive level values. A read always returns 0. S1DSC 5 w Slice 1 Dither shadow transfer clear Writing a 1B to this bit will clear the GCST.S1DSS field, canceling any pending shadow transfer for the Dither compare value. A read always returns 0. S1PSC 6 w Slice 1 Prescaler shadow transfer clear Writing a 1B to this bit will clear the GCST.S1PSS field, canceling any pending shadow transfer for the prescaler compare value. A read always returns 0. S2SC 8 w Slice 2 shadow transfer clear Writing a 1B to this bit will clear the GCST.S2SS field, canceling any pending shadow transfer for the Period, Compare and Passive level values. A read always returns 0. Reference Manual CCU4, V1.15 17-96 V1.2, 2014-11 Subject to Agreement on the Use of Product Information XMC1100 AB-Step XMC1000 Family Capture/Compare Unit 4 (CCU4) Field Bits Type Description S2DSC