Platform Manager 2 In-System Programmable Hardware Management Controller May 2016 Data Sheet DS1043 Features Ten Rail Voltage Monitoring and Measurement FPGA Resources • 1280 LUT, 98 I/O Version (LPTM21) RAM and Flash Memories Scalable Hardware Management Architecture • UV/OV Fault Detection Accuracy – 0.2% Typ. • Fault Detection Speed < 100 µs • High Voltage, Single Ended and Differential Sensing • Glueless interface to Hardware Management Expander (L-ASC10) • Migrate between LPTM21 and larger density MachXO2 device to extend logic and I/O resources Two Channel Wide-Range Current Monitoring and Measurement • High-side current measurement up to 12 V • Programmable OC/UC Fault Detect • Detects Current faults in <1 µs System Level Support Three Temperature Monitoring and Measurement Channels • Operating voltage from 4.75 V to 13.2 V or 2.8 V to 3.46 V • 12 V DC-DC converter provides 3.3 V supply for ASC Hardware Management Expanders • Industrial and commercial temperature ranges • 237-ball ftBGA (LPTM21) • RoHS compliant and halogen-free • Programmable OT/UT Faults Threshold • Two channels of Temperature Monitoring using external diodes • On-Chip Temperature Monitor 4 High-Side MOSFET Drivers Applications • Programmable Charge Pump Four Precision Trim and Margin Channels • • • • • • Closed Loop Operation • Voltage Scaling and VID Support Ten General Purpose Input/Output • 5 V tolerant I/O Non-Volatile Fault Logging Programmed through JTAG or I2C Telecommunication and Networking Industrial, Test and Measurement Medical Systems Servers and Storage Systems High Reliability Systems • Background Update with Dual-Boot Backup Application Diagram Hardware Management Application Block Diagram Hot Swap Optional Input Rail Up to 12 V Current Monitor [1:2] HVOUT [1:4] NV Fault Log Board Temp Transistor Vin Vout EN Trim/FB Trim/Margin [1:4] GPIO [1..10] On-Die Temp Temp [1:2] On-Die Temp Diode ASIC 10 Rails 0.6 V to 5.7 V POL Rs Voltage, Current, Temp (VIT) High Speed Fault Detect/Alarms Voltage Monitor [1:10] ASC Section Voltage, Current, Temp (VIT) Measurement and Programming ADC I2C CPU Resets Fan(s) Platform Manager 2 FPGA Section VID JTAG Programming © 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 DS1043_1.4 Platform Manager 2 In-System Programmable Hardware Management Controller Description The Lattice Platform Manager 2 device is a fast-reacting, programmable logic based hardware management controller. Platform Manager 2 is an integrated solution combining analog sense and control elements with scalable programmable logic resources. This unique approach allows Platform Manager 2 to integrate Power Management (Power Sequencing, Voltage Monitoring, Trimming and Margining), Thermal Management (Temperature Monitoring, Fan Control, Power Control), and Control Plane functions (System Configuration, I/O Expansion, etc.) as a single device. Architecturally, the Platform Manager 2 device can be divided into two sections – Analog Sense and Control and FPGA. The Analog Sense and Control (ASC) section provides three types of analog sense channels: voltage (nine standard channels and one high voltage channel), current (one standard voltage and one high voltage) and temperature (two external and one internal). Each of the analog sense channels is monitored through two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. In addition, each of the current sense channels provides a fast fault detect (one µs response time) for detecting short circuit events. The temperature sense channels can be configured to work with different external transistor or diode configurations. The Analog Sense and Control section also provides ten general purpose 5 V tolerant open-drain digital input/output pins that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as well as for general purpose logic interface functions. In addition, four high-voltage charge pumped outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches. These HVOUT outputs can also be programmed as static output signals or as switched outputs (to support external charge pump implementation) operating at a dedicated duty cycle and frequency. The ASC section incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode of the trimming block. The internal 10-bit A/D converter can be used to measure the voltage and current through the I2C bus. The ADC is also used in the digital closed loop control mode of the trimming block. The ASC section also provides the capability of logging up to 16 status records into its nonvolatile EEPROM memory. Each record includes voltage, current and temperature monitor signals along with digital input and output levels. The ASC section includes an output control block (OCB) which allows certain inputs and control signals a direct connection to the digital outputs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to connect the fast current fault detect signal to an FPGA input directly. It also supports functions such as Hot Swap with a programmable hysteretic controller. The FPGA section contains non-volatile low cost programmable logic of 1280 Look-Up Tables (LUTs). In addition to the LUT-based logic, the FPGA section features Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), flexible I/Os, and hardened versions of commonly used functions such as SPI controller, I2C controller and Timer/counter. The FPGA I/Os offer enhanced features such as drive strength control, slew rate control, buskeeper latches, internal pull-up or pull-down resistors, and open-drain outputs. These features are controllable on a “per-pin” basis. The power management, thermal management and control plane logic functions are implemented in the FPGA section of Platform Manager 2. The FPGA receives the analog comparator values and inputs from the ASC section and sends output commands to the ASC section through the dedicated ASC-interface (ASC-I/F) high-speed, reliable serial channel. The FPGA hardware management functions are implemented using the Platform Designer tool inside Lattice Diamond software. The Platform Designer tool includes an easy to use sequence and monitor logic 2 Platform Manager 2 In-System Programmable Hardware Management Controller builder tool and a set of pre-engineered components for functions like time-stamped fault logging, voltage by identification (VID), and fan control. The Platform Manager 2 is designed to enable seamless scaling of the number of voltage, current and temperature sense channels in the system by adding external Analog Sense and Control (ASC) Hardware Management Expanders. The algorithm implemented within the FPGA can access and control these external ASCs through the dedicated ASC-I/F. Larger systems with up to eight ASC devices can be created by using a MachXO2 FPGA in place of the Platform Manager 2 device. The companion devices are connected in a scalable, star topology to Platform Manager 2 or MachXO2. The Platform Manager 2 has an I2C interface which is used by the FPGA section for ASC interface configuration. The I2C interface also provides the mechanism for parameter measurement or I/O control or status. For example, voltage trim targets can be set over the I2C bus and measured voltage, current, or temperature values can be read over the I2C bus. The Platform Manager 2 device can be programmed in-system through JTAG or I2C interfaces. The configuration is stored in on-chip non-volatile memory. Upon power-on, the FPGA section configuration is transferred to the on-chip SRAM and the device operates from SRAM. It is possible to update the non-volatile memory content in the background without interrupting the system operation. Block Diagram Figure 1. Platform Manager 2 Block Diagram FPGA Section Analog Sense and Control Section MOSFET & Digital I/O Drive (HVOUTs & GPIO) DC-DC Converter Output Control Block Current Sense ASC Interface (ASC-I/F) Temperature Sense Voltage Sense ADC NonVolatile Fault Log I2 C Interface ADC FPGA LUTs 1280 (Hardware Management Logic) FPGA I/O Ports SPI JTAG I2C Trim & Margin Control 3 Platform Manager 2 In-System Programmable Hardware Management Controller Table 1. Platform Manager 2 Device Features LPTM21 Analog Sense and Control Section Voltage Monitor Inputs 10 Current Monitor Inputs 2 Temperature Monitor Inputs 2 Trim Outputs 4 High Voltage Outputs 4 GPIO pins (5V tolerant) 10 FPGA section LUTs 1280 Distributed RAM (Kbits) 10 EBR SRAM (Kbits) 64 Number of EBR SRAM Blocks (9 Kbits/block) 7 UFM (Kbits) 64 Hardened Functions I2C SPI Timer/Counter 2 1 1 Digital I/Os1 Package 237 - ftBGA 95 1. Digital I/O count does not include SDA_M, SCL_M or JTAGENB pins. 4 Platform Manager 2 In-System Programmable Hardware Management Controller DC and Switching Characteristics Absolute Maximum Ratings1, 2, 3 Symbol Parameter Conditions Min Max. Units –0.5 3.75 V Supply Voltages VCCA ASC Supply 4 VCC FPGA Core Supply Voltage –0.5 3.75 V VCCIO FPGA Output Supply Voltage4 –0.5 3.75 V VVDC Power Supply Input to DC-DC Converter –0.5 13.3 V Monitor and I/O Pin Voltages VIN_VMON VMON input voltage –0.5 6 V VIN_VMONGS VMON input voltage ground sense –0.5 6 V VIN_HIMONP High voltage IMON input voltage –0.5 13.3 V VIN_HIMONN_HVMON High voltage IMON return / VMON input voltage –0.5 13.3 V VDIFF_HIMON High voltage IMON differential voltage –2.0 2.0 V VIN_IMONP Low voltage IMON1 input voltage –0.5 6.0 V VIN_IMONN Low voltage IMON1 return voltage –0.5 6.0 V VDIFF_IMON Low voltage IMON1 differential voltage –2.0 2.0 V VIN_TMONP TMON input voltage –0.5 VCCA V VIN_TMONN TMON return voltage –0.5 VCCA V VIN_GPIO Digital input voltage (ASC Section) –0.5 6 V VOUT Open-drain output voltage (ASC Section) HVOUT [1:4] –0.5 13.3 V GPIO[1:10] –0.5 6 V VTRIM TRIM output voltage –0.5 VCCA V VTRI_FPGA FPGA PIO Tri-State Voltage Applied5, 4 –0.5 3.75 V –0.5 3.75 V 23 mA VIN_FPGA FPGA PIO Dedicated Input Voltage Applied 4 Other ISINKMAX Maximum Sink Current on any ASC Section output TS Device Storage Temperature (Ambient) –55 +125 o TJ Junction Temperature –40 +125 o C C 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Overshoot and Undershoot of –2 V to (VIHMAX +2) volts is permitted for a duration of < 20 ns. 5. The dual function I2C pins SCL_M and SDA_M are limited to –0.25 to 3.75 V or to –0.3 V with a duration of < 20 ns. 5 Platform Manager 2 In-System Programmable Hardware Management Controller Recommended Operating Conditions1 Symbol Parameter Conditions Min Max. Units 2.8 3.465 V Supply Voltages VCCA ASC Supply VCC FPGA Core Supply Voltage 2.8 3.465 V VCCIO2, 3 FPGA Output Supply Voltage 1.14 3.465 V 4.75 13.2 V VVDC VDC Supply 5 Monitor and I/O Pin Voltages VIN_VMON VMON input voltage –0.3 5.9 V VIN_VMONGS VMON input voltage ground sense –0.2 0.3 V 4.5 13.2 V 4.5 13.2 V 4 VIN_HIMONP High voltage IMON input voltage VIN_HIMONN_HVMON High voltage IMON return /VMON voltage4 VDIFF_HIMON High voltage IMON differential voltage VIN_IMONP Low voltage IMON1 input voltage VIN_IMONN Low voltage IMON1 return voltage VDIFF_IMON Low voltage IMON1 differential voltage VIN_GPIO Digital input voltage (ASC Section) VOUT Open-drain output voltage (ASC Section) 0 500 mV Low Side Sense Disabled 0.6 5.9 V Low Side Sense Enabled –0.3 1.0 V Low Side Sense Disabled 0.6 5.9 V Low Side Sense Enabled –0.3 1.0 V 0 500 mV –0.3 5.5 V HVOUT [1:4] –0.3 13.2 V GPIO[1:10] –0.3 5.5 V 0 +85 o –40 +100 o Other TJCOM Junction Temperature (Commercial) TJIND Junction Temperature (Industrial) C C 1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same supply. VCCA, VCC, VCCIO0 and VCCIO1 should all be tied together. See the System Connections section for more details. 2. See recommended voltage by I/O standard in subsequent table. 3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards. 4. HIMON circuits are operational down to 3V. Accuracy is guaranteed within Recommended Operating Conditions 5. VDC supply voltage only required when on-chip DC-DC converter controller is used to generate VCCA/VCC. VDC should be left open when VCCA/VCC are supplied directly. Power Supply Ramp Rates1 Symbol tRAMP Parameter Power supply ramp rates for all VCC and VCCIO power supplies. 1. Assumes monotonic ramp rates. 6 Min. Typ. Max. Units 0.01 — 100 V/ms Platform Manager 2 In-System Programmable Hardware Management Controller DC/DC Converter1,2 Symbol Parameter VVDC Input Supply FDC PWM Frequency Conditions Min Typ. 4.75 Max. 13.2 215 VVDC_OUT Regulated Supply Voltage VVDC_DRVoh HDRV Isrc=4mA VVDC_DRVol HDRV Isrc=4mA 3.1 3.3 Units V kHz 3.45 3.17 V V 0.34 V 1. DC-DC converter performance is dependent on external component selection. See the For Further Information section for more details. 2. Valid for load currents up to 250 mA. Power-On-Reset and Flash Download Time Symbol Parameter Conditions Min Typ. Max. Units 100 us Analog Sense and Control Section TRST Delay from VTH to start-up state TSAFE Delay from RESETb release to ASC Safe State Exit and I/O Release2, 3 TSAFE2 Delay from WRCLK start to ASC Safe State Exit and I/O Release2, 3, 4 TGOOD Delay from I/O release to AGOOD asserted high in FPGA section5 TBRO Minimum duration brown out required to trigger RESETb 1.8 ms 56 us 16 1 us 5 us TPOR Delay from Brown out to reset state 13 us VTL Threshold below which RESETb is LOW 2.3 V VTH Threshold above which RESETb is Hi-Z 2.7 V VT Threshold above which RESETb is valid 0.8 V CL Capacitive load on RESETb 200 pF FPGA Section VCC_PORUPEXT1 Power-On-Reset ramp up trip point (external VCC power supply) 1.5 2.1 V VPORUPIO1 Power-On_Reset ramp up trip point (VCCIO0 power supply) 0.9 1.06 V Trefresh6 Flash Download Time (Power-On-Reset to Device I/O active) LPTM21 1.9 ms 1. These POR trip points are provided for guidance only. Device operation is only characterized for power supply voltages specified under recommended operating conditions. 2. Both TSAFE and TSAFE2 must complete before I/O are released from Safe State. 3. During the calibration period before TSAFE and TSAFE2, the ASC may ignore RESETb being driven low. After TSAFE and TSAFE2, the ASC can be reset by another device by driving RESETb low. 4. Safe State is released at ASC after a fixed number (64) of WRCLK cycles (typ.8 MHz frequency) and three ASC-I/F data packets are properly detected. 5. AGOOD asserted in the FPGA on the next ASC-I/F packet after I/O exits Safe State as ASC. 6. FPGA flash download time has a direct influence on WRCLK start time. See Figure 2. 7 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 2. Platform Manager 2 Power-On Reset VTH TBRO VTL VCCA / VCC / VCCIO0 / VCCIO1 VCC_POR VT TRST TPOR RESETb TSAFE2 I/O Release TSAFE TGOOD AGOOD Trefresh WRCLK FPGA I/O Release Brownout Behavior Power On Reset - Startup 8 Platform Manager 2 In-System Programmable Hardware Management Controller DC Electrical Characteristics Symbol Parameter Device ICCA Supply Current (Analog Section) ICC-HVOUT Supply Current Adder per HVOUT, VHVOUT = 12 V, Isrc = 100 uA ICC1, 2, 3, 4 Static Core Supply Current (FPGA Section) ICCIO1, 2, 3, 4, 6 Static Bank Power Supply, VCCIO = 2.5 V Min LPTM21 Typ.5 Max. 25 35 mA 2 mA Units 3.49 mA 500 µA 1. For further information on FPGA section supply current, please see details of additional technical documentation at the end of this data sheet. 2. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and held at VCCIO or GND, on-chip oscillator is off, on-chip PLL is off. 3. Frequency = 0 MHz. 4. To determine the FPGA peak start-up current data, use the Power Calculator tool. 5. Tj = 25C, power supplies at nominal voltage. 6. Does not include pull-up/pull-down. Programming and Erase Supply Current Symbol Parameter Device ICCA Supply Current (Analog Section) ICC1, 2, 3, 4 Core Supply Current (FPGA Section) ICCIO1, 2, 3, 4, 6 Bank Power Supply, VCCIO = 2.5 V Min Typ.5 Max. Units 40 LPTM21 mA 18.8 mA 500 µA 1. For further information on FPGA section supply current, please see details of additional technical documentation at the end of this data sheet. 2. Assumes all FPGA section inputs are held at VCCIO or GND and all outputs are tri-stated. 3. Typical user pattern. 4. JTAG programming is at 25 MHz. 5. Tj = 25C, power supplies at nominal voltage. 6. Per bank, does not include pull-up/pull-down. FPGA Configuration Memory Programming / Erase Specifications Min. Max.1 Flash Programming cycles per tRETENTION — 10,000 Flash functional programming cycles — 100,000 Data retention at 100 °C junction temperature 10 — Data retention at 85 °C junction temperature 20 — Symbol NPROGCYC tRETENTION Parameter Units Cycles Years 1. Maximum Flash memory reads are limited to 7.5E13 cycles over the lifetime of the product. FPGA I/O Hot Socketing Specifications1, 2, 3 Symbol IDK Parameter Input or I/O leakage Current Condition 0 < VIN < VIH (MAX) Max. Units +/–1000 µA 1. Insensitive to sequence of VCC and VCCIO. However, assumes monotonic rise/fall rates for VCC and VCCIO. 2. 0 < VCC < VCC (MAX), 0 < VCCIO < VCCIO (MAX). 3. IDK is additive to IPU, IPD or IBH. 9 Platform Manager 2 In-System Programmable Hardware Management Controller ESD Performance Please refer to the Platform Manager 2 Product Family Qualification Summary for complete qualification data, including ESD performance. Digital Specifications Symbol Parameter Conditions Min Typ. Max. Units +/ 10 µA Analog Sense and Control Section IIL,IIH Input leakage, no pull-up, pulldown7 IPD Active Pull-Down Current7 GPIO[1:10] configured as Inputs, Internal Pull-Down enabled 200 µA IPD-ASCIF Input Leakage (WDAT and WRCLK)8 Internal Pull-Down 175 µA IOH-HVOUT Output Leakage Current HVOUT[1:4] in open drain mode and pulled up to 12 V 35 IPU-RESETb Input Pull-Up Current (RESETb) VIL Voltage input, logic low –50 GPIO[1:10] Voltage input, logic high GPIO[1:10] VOL V 30% VCCA 2.0 SCL_S/SDA_S µA µA 0.8 SCL_S/SDA_S VIH 100 V 70% VCCA HVOUT[1:4] (open drain mode) ISINK = 10 mA 0.8 GPIO[1:10] ISINK = 20 mA 0.8 ISINKTOTAL6 All digital outputs V 130 mA +175 µA 10 µA FPGA Section – Programmable I/O IIL,IIH1,4 Input or I/O Leakage Clamp OFF and VCCIO < VIN < VIH (MAX) Clamp OFF and VIN = VCCIO –10 Clamp OFF and VCCIO –0.97V < VIN < VCCIO –175 µA Clamp OFF and 0V < VIN < VCCIO –0.97 V 10 µA Clamp OFF and VIN = GND 10 µA Clamp ON and 0V < VIN < VCCIO IPU I/O Active Pull-up Current IPD I/O Active Pull-down Current IBHLS Bus Hold Low Sustaining Current IBHHS 10 µA –30 –309 µA VIL (MAX) < VIN < VCCIO 30 305 VIN = VIL (MAX) 30 µA –30 µA 0< VIN < 0.7 VCCIO IBHLO Bus Hold High Sustaining Current VIN = 0.7 VCCIO Bus Hold Low Overdrive Current 0 ≤ VIN ≤ VCCIO IBHHO Bus Hold High Overdrive Current VBHT3 Bus Hold Trip Points C1 I/O Capacitance2 VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V VCC = Typ. VIO = 0 to VIH (MAX) 3 C2 Dedicated Input Capacitive VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = Typ. VIO = 0 to VIH (MAX) 3 305 µA –309 µA VIH (MIN) V 5 9 pF 5.5 7 pF 0 ≤ VIN ≤ VCCIO VIL (MAX) 10 µA Platform Manager 2 In-System Programmable Hardware Management Controller Digital Specifications (Cont.) Symbol VHYST Parameter Hysteresis for Schmitt Trigger Inputs5 Conditions Min Typ. Max. Units VCCIO = 3.3 V, Hysteresis = Large 450 mV VCCIO = 2.5 V, Hysteresis = Large 250 mV VCCIO = 1.8 V, Hysteresis = Large 125 mV VCCIO = 1.5 V, Hysteresis = Large 100 mV VCCIO = 3.3 V, Hysteresis = Small 250 mV VCCIO = 2.5 V, Hysteresis = Small 150 mV VCCIO = 1.8 V, Hysteresis = Small 60 mV VCCIO = 1.5 V, Hysteresis = Small 40 mV 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled. 2. TA 25 °C, f = 1.0 MHz. 3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document. 4. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-tolow transition. For true LVDS output pins in LPTM21, VIH must be less than or equal to VCCIO. 5. With bus keeper circuit turned on. For more details, refer to TN1202, MachXO2 sysIO Usage Guide. 6. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded. 7. During safe-state, all GPIO default to output, see the Safe State section for more details. GPIO[1:6] and GPIO[10] default to active low output. This will result in a leakage current dependent on the input voltage which can exceed the specified input leakage 8. WRCLK and WDAT pins may see transients above 1 mA in hot socket conditions. DC levels will remain below 1 mA. 11 Platform Manager 2 In-System Programmable Hardware Management Controller Voltage Monitors1 Symbol Parameter Conditions Min Typ Max Units 55 65 75 k RVMON_in Input Resistance CVMON_in Input Capacitance VMON Range Programmable trip-point Range 5.734 Volts VMON Accuracy Absolute accuracy of any trip-point – Differential VMON pins VMON voltage > 0.650 V 0.2 0.7 % Single-ended VMON pins VMON voltage > 0.650 V 0.3 0.9 % 8 0.075 pF VMON HYST Hysteresis of any trip-point (relative to setting) 1 % VMON CMR Differential VMON Common mode rejection ratio 60 dB VZ Sense Low Voltage Sense Trip Point Error – Differential VMON1-4 Low Voltage Sense Trip Point Error – Single-Ended VMON5-9 Trip Point = 0.075 V –5 +5 mV Trip Point = 0.150 V –5 +5 mV Trip Point = 0.300 V –10 +10 mV Trip Point = 0.545 V –15 +15 mV Trip Point = 0.080 V –10 +10 mV Trip Point = 0.155 V –15 +15 mV Trip Point = 0.310 V –25 +25 mV Trip Point = 0.565 V –55 +55 mV 0.3 13.2 Volts 1.0 % +20 mV High Voltage Monitor HVMON Range High Voltage VMON programmable trip-point range HVMON Accuracy HVMON Absolute accuracy of any trip-point VZ Sense Low Voltage Sense Trip Point Error HVMON pin HVMON voltage > 1.8 V 0.4 Trip Point = 0.220 V –20 Trip Point = 0.425 V –35 +35 mV Trip Point = 0.810 V –75 +75 mV Trip Point = 1.280 V –130 +130 mV 1. VMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details. 12 Platform Manager 2 In-System Programmable Hardware Management Controller Current Monitors Symbol Parameter IIMONPleak IMON1P input leakage IMON1N input leakage IIMONNleak IHIMONPleak HIMONP input leakage 2 IMONA/B Accuracy HIMON, IMON1A/B Comparator Trip Point accuracy IMONA/B Gain tIMONF Min Max Units –2 Typ 250 µA Low Side Sense Enabled Fast Trip Point Vsns = 500 mV –2 40 µA Low Side Sense Disabled Fast Trip Point Vsns = 500 mV –2 2 µA Low Side Sense Enabled Fast Trip Point Vsns = 500 mV –200 2 µA 550 µA 350 µA Fast Trip Point Vsns = 500 mV HIMONN_HVMON input leakage IHIMONNleak IMONF Accuracy Conditions Low Side Sense Disabled Fast Trip Point Vsns = 500 mV Programmable Gain Setting 2 Gain = 100x 8 % Gain = 50x 5 % Gain = 25x 3 % Gain = 10x 2 % Four settings in software 10 V/V 25 V/V 50 V/V 100 V/V 8 % Vsns = 200 mV, 250 mV, or 300 mV 5 % Vsns = 400 mV or 500 mV 3 % 1 Fast comparator trip-point accuracy Vsns = 50 mV, 100 mV, or 150 mV Fast comparator response time 1 µs 1. Vsns is the differential voltage between IMON1P and IMON1N (or HIMONP and HIMONN). 2. IMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details. 13 Platform Manager 2 In-System Programmable Hardware Management Controller ADC Characteristics Symbol Parameter Conditions Min Resolution tCONVERT Typ Max 10 2 Conversion Time from I C Request Units Bits 200 µs V Voltage Monitors VVMON-IN LSB EVMON-attenuator Input Range Full scale ADC Step Size Error due to attenuator Programmable Attenuator = 1 0 2.048 Programmable Attenuator = 3 0 5.91 Programmable Attenuator = 1 2 Programmable Attenuator = 3 6 Programmable Attenuator = 3 +/– 0.1 mV % High Voltage Monitor VHVMON-IN LSB EHVMON-attenuator Input Range Full scale ADC Step Size Error due to attenuator Programmable Attenuator = 4 0 8.192 Programmable Attenuator = 8 0 13.21 V Programmable Attenuator = 4 8 Programmable Attenuator = 8 16 Programmable Attenuator = 4 +/–0.2 % Programmable Attenuator = 8 +/–0.4 % 1 ms mV Current Monitors tIMON-sample Sample period of HVIMON and IMON1 conversions for averaged value 4 Settings via I2C command 2 4 8 VIMON-IN LSB 1 Input Range Full scale ADC Step Size Programmable Gain 10x 0 200 Programmable Gain 25x 0 80 Programmable Gain 50x 0 40 Programmable Gain 100x 0 20 Programmable Gain 10x 0.2 Programmable Gain 25x 0.08 Programmable Gain 50x 0.04 Programmable Gain 100x 0.02 1. Differential voltage applied across HIMONP/IMON1P and HIMONN/IMO1N before programmable gain amplification. 14 mV mV Platform Manager 2 In-System Programmable Hardware Management Controller ADC Error Budget Over Entire Operating Temperature Range Symbol TADC Error Parameter Conditions Total ADC Measurement Error Measurement Range 600mV - 2.048 V, at Any Voltage (Differential VMONxGS > -100 mV, Attenuator =1 Analog Inputs)1, 3 Measurement Range 600mV - 2.048 V, VMONxGS > –200 mV, Attenuator =1 Min Typ Max Units –8 +/– 4 8 mV Measurement Range 0 - 2.048 V, VMONxGS > –200 mV, Attenuator =1 Total Measurement Error at Any Voltage (Single-Ended Analog Inputs including IMON)1, 2, 3 Measurement Range 600 mV - 2.048 V, Attenuator =1 –8 +/– 6 mV +/– 10 mV +/– 4 8 mV 1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC. 2. Programmable gain error on IMON not included. 3. ADC accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details Temperature Monitors Symbol Parameter Conditions Min Typ Max Units TMON_REMOTE Accuracy1, 7 Temp Error – Remote Sensor Ta = –40 to +85 ºC Td = –64 to 127 ºC 1 ºC TMON_INT Accuracy7 Internal Sensor – Relative to ambient6 Ta=–40 to +85 ºC 1 ºC Resolution 0.25 TMON Range Programmable threshold range TMON Offset Temperature offset TMON Hysteresis tTMON_settle2 ºC –64 155 ºC Programmable in software –63.75 63.75 ºC Hysteresis of trip points Programmable in software 0 63 ºC Temperature measurement settling time3 Measurement Averaging Coefficient = 1 15 ms Measurement Averaging Coefficient = 8 120 ms Tn Ideality Factor n Programmable in software Tlimit Temperature measurement limit4 160 ºC CTMON Maximum Capacitance between TMONP and TMONN pins 200 pF RTMONSeries Equivalent external resistance to sensor5 200 ohms Measurement Averaging Coefficient = 16 240 0.9 ms 2 1. Accuracy number is valid for the use of a grounded collector PNP configuration, programmed with proper ideality factor, and 16x measurement filter enabled. Any other device or configuration can have additional errors, including beta, series resistance and ideality factor accuracy. See Temperature Monitor Inputs section for more details. 2. Settling time based on one TMON enabled. For multiple TMONs, settling time can be multiplied by the number of enabled TMON channels. 3. Settling time is defined as the time is takes a step change to settle to within 1% of the measured value. 4. All values above Tlimit read as 0x3FF over I2C. There is no cold temperature limiting reading, although performance is not specified below – 64 oC. 5. This is the maximum series resistance which the TMON circuit can compensate out. Equivalent series resistance includes all board trace wiring (TMONP and TMONN) as well as parasitic base and emitter resistances. Re=1/gm should not be included as part of series resistance. 6. Internal sensor is subject to self-heating, dependent on PCB design and device configuration. Self-heating not included in published accuracy. 7. TMON accuracy may degrade based on SSO conditions of FPGA section, especially bank 1. See the System Connections section for more details 15 Platform Manager 2 In-System Programmable Hardware Management Controller High Voltage FET Drivers Symbol VPP Parameter Gate driver output voltage Conditions Min Four settings in software Typ Max 12 Units Volts 10 8 6 IOUTSRC Gate driver source current (HIGH state) Four settings in software 12.5 µA 25 50 100 IOUTSINK Gate driver sink current (LOW state) Four settings in software 100 µA 250 500 3000 Frequency Switched Mode Frequency Two settings in software Duty Cycle Switched Mode Programmable Duty Cycle Range Programmable in software 15.625 kHz 31.25 6.25 Duty Cycle step size 93.75 6.25 % % Margin/Trim DAC Output Characteristics Symbol Parameter Conditions Min Resolution FSR Full scale range LSB LSB step size IOUT Output source/sink current ITRIM_Hi-Z Tri-state mode leakage BPZ Bipolar zero output voltage (code=80h) Typ. Max. 8 (7 + sign) Bits +/– 320 mV 2.5 mV –200 Four settings in software Units 200 µA 0.1 µA 0.6 V 0.8 1.0 1.25 tS TrimCell output voltage settling DAC code changed from 80H to FFH or time1 80H to 00H C_LOAD Maximum load capacitance TOSE Total open loop supply voltage Full scale DAC corresponds to +/– 5% supply voltage variation error2 Single DAC code change 2.5 ms 50 pF +1% V/V 260 –1% µs 1. To 1% of set value with 50 pF load connected to trim pins. 2. Total resultant error in the trimmed power supply output voltage referred to any DAC code due to DAC’s INL, DNL, gain, output impedance, offset error and bipolar offset error across the temperature, VCCA ranges of the device. 16 Platform Manager 2 In-System Programmable Hardware Management Controller Fault Log / User Tag EEPROM Symbol Parameter Conditions Records Number of available fault log records in EEPROM tfaultTrigger Minimum active time of trigger signal to start fault recording tfaultRecord Time to copy fault record to EEPROM Min Typ. Max. 16 Units Records 64 µs 5 ms Analog Sense and Control Oscillator Min Typ. Max. Units CLKASC Symbol Internal ASC0 Clock Parameter Conditions 7.6 8 8.4 MHz CLKext Externally Applied Clock 7.6 8 8.4 MHz FPGA sysIO Recommended Operating Conditions VCCIO (V) VREF (V) Standard Min. Typ. Max. Min. Typ. Max. LVCMOS 3.3 3.135 3.3 3.465 — — — LVCMOS 2.5 2.375 2.5 2.625 — — — LVCMOS 1.8 1.71 1.8 1.89 — — — LVCMOS 1.5 1.425 1.5 1.575 — — — LVCMOS 1.2 1.14 1.2 1.26 — — — LVTTL 3.135 3.3 3.465 — — — PCI3 3.135 3.3 3.465 — — — SSTL25 2.375 2.5 2.625 1.15 1.25 1.35 SSTL18 1.71 1.8 1.89 0.833 0.9 0.969 HSTL18 1.71 1.8 1.89 0.816 0.9 1.08 LVDS251, 2 2.375 2.5 2.625 — — — 1, 2 3.135 3.3 3.465 — — — 3.135 3.3 3.465 — — — 2.375 2.5 2.625 — — — 2.375 2.5 2.625 — — — SSTL18D 1.71 1.8 1.89 — — — SSTL25D 2.375 2.5 2.625 — — — HSTL18D 1.71 1.8 1.89 — — — LVDS33 LVPECL1 BLVDS 1 RSDS1 1. Inputs on-chip. Outputs are implemented with the addition of external resistors. 2. LPTM21 has dedicated LVDS buffers. 3. Input on the bottom bank of the LPTM21 only. 17 Platform Manager 2 In-System Programmable Hardware Management Controller FPGA sysIO Single-Ended DC Electrical Characteristics1, 2 Input/Output Standard LVCMOS 3.3 LVTTL VIL 3 Min. (V) VIH Max. (V) –0.3 0.8 Min. (V) Max. (V) 2.0 3.6 VOL Max. (V) 0.4 0.2 LVCMOS 2.5 LVCMOS 1.8 LVCMOS 1.5 LVCMOS 1.2 -0.3 0.7 –0.3 0.35VCCIO –0.3 0.35VCCIO –0.3 0.35VCCIO 1.7 3.6 0.65VCCIO 3.6 0.65VCCIO 3.6 0.65VCCIO 3.6 VOH Min. (V) IOL Max.4 (mA) IOH Max.4 (mA) 4 –4 VCCIO - 0.4 VCCIO - 0.2 8 –8 12 –12 16 –16 24 –24 0.1 –0.1 4 –4 8 –8 12 –12 0.4 VCCIO - 0.4 0.2 VCCIO - 0.2 0.4 VCCIO - 0.4 12 –12 0.2 VCCIO - 0.2 0.1 –0.1 0.4 VCCIO - 0.4 4 –4 8 –8 0.2 VCCIO - 0.2 0.1 –0.1 4 –2 16 –16 0.1 –0.1 4 –4 8 –8 0.4 VCCIO - 0.4 8 –6 0.2 VCCIO - 0.2 0.1 –0.1 PCI –0.3 0.3VCCIO 0.5VCCIO 3.6 0.1VCCIO 0.9VCCIO 1.5 –0.5 SSTL25 Class I –0.3 VREF - 0.18 VREF + 0.18 3.6 0.54 VCCIO - 0.62 8 8 SSTL25 Class II –0.3 VREF - 0.18 VREF +0.18 3.6 NA NA NA NA SSTL18 Class I –0.3 VREF - 0.125 VREF +0.125 VREF - 0.125 VREF +0.125 3.6 0.40 VCCIO - 0.40 8 8 SSTL18 Class II –0.3 3.6 NA NA NA NA HSTL18 Class I –0.3 VREF - 0.1 VREF +0.1 3.6 0.40 VCCIO - 0.40 8 8 HSTL18 Class II –0.3 VREF - 0.1 VREF +0.1 3.6 NA NA NA NA 1. Platform Manager 2 devices allow LVCMOS inputs to be placed in I/O banks where VCCIO is different from what is specified in the applicable JEDEC specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC specification. The cases where Platform Manager 2 devices do not meet the relevant JEDEC specification are documented in the table below. 2. Platform Manager 2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode operation please refer to please refer to TN1202, MachXO2 sysIO Usage Guide. 3. The I2C pins SCL_M and SDA_M are limited to a VIL min of –0.25V or to –0.3V with a duration of <10ns. 4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. Input Standard VCCIO (V) VIL Max. (V) LVCMOS 33 1.5 0.685 LVCMOS 25 1.5 0.687 LVCMOS 18 1.5 0.655 18 Platform Manager 2 In-System Programmable Hardware Management Controller FPGA sysIO Differential Electrical Characteristics The LVDS differential output buffers are available on the top side of the LPTM21 device. LVDS Over Recommended Operating Conditions Parameter Symbol VINP, VINM Parameter Description Test Conditions Input Voltage VCCIO = 3.3 VCCIO = 2.5 VTHD Differential Input Threshold VCM Input Common Mode Voltage Min. Typ. Max. Units 0 — 2.605 V 2.05 0 — ±100 — V VCCIO = 3.3V 0.05 — 2.6 V VCCIO = 2.5V 0.05 — 2.0 V mV IIN Input current Power on — — ±10 µA VOH Output high voltage for VOP or VOM RT = 100 Ohm — 1.375 — V VOL Output low voltage for VOP or VOM RT = 100 Ohm 0.90 1.025 — V VOD Output voltage differential (VOP - VOM), RT = 100 Ohm 250 350 450 mV VOD Change in VOD between high and low VOS Output voltage offset VOS Change in VOS between H and L IOSD Output short circuit current (VOP - VOM)/2, RT = 100 Ohm VOD = 0V driver outputs shorted — — 50 mV 1.125 1.20 1.395 V — — 50 mV — — 24 mA LVDS Emulation FPGA section outputs can support LVDS outputs via emulation (LVDS25E). The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3 is one possible solution for LVDS standard implementation. Resistor values in Figure 3 are industry standard values for 1% resistors. Figure 3. LVDS Using External Resistors (LVDS25E) VCCIO = 2.5 158 8 mA Zo = 100 VCCIO = 2.5 158 140 100 8 mA On-chip Off-chip Off-chip Emulated LVDS Buffer Note: All resistors are ±1%. 19 On-chip Platform Manager 2 In-System Programmable Hardware Management Controller Table 2. LVDS25E DC Conditions Over Recommended Operating Conditions Typ. Units ZOUT Parameter Output impedance Description 20 Ohms RS Driver series resistor 158 Ohms RP Driver parallel resistor 140 Ohms RT Receiver termination 100 Ohms VOH Output high voltage 1.43 V VOL Output low voltage 1.07 V VOD Output differential voltage 0.35 V VCM Output common mode voltage 1.25 V ZBACK Back impedance 100.5 Ohms IDC DC output current 6.03 mA BLVDS FPGA section outputs support the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 4 is one possible solution for bi-directional multi-point differential signals. Figure 4. BLVDS Multi-point Output Example Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential 2.5 V 2.5 V 80 45-90 ohms 45-90 ohms 16 mA 16 mA 80 2.5 V 2.5 V 80 16 mA 16 mA 80 80 80 .. 2.5 V 2.5 V 16 mA 2.5 V 16 mA 2.5 V 16 mA 20 80 . 16 mA Platform Manager 2 In-System Programmable Hardware Management Controller Table 3. BLVDS DC Conditions1 Over Recommended Operating Conditions Nominal Zo = 45 Zo = 90 Units ZOUT Symbol Output impedance Description 10 10 Ohms RS Driver series resistance 80 80 Ohms RTLEFT Left end termination 45 90 Ohms RTRIGHT Right end termination 45 90 Ohms VOH Output high voltage 1.376 1.480 V VOL Output low voltage 1.124 1.020 V VOD Output differential voltage 0.253 0.459 V VCM Output common mode voltage 1.250 1.250 V IDC DC output current 11.236 10.204 mA 1. For input buffer, see LVDS table. LVPECL FPGA section outputs support the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 5 is one possible solution for point-to-point signals. Figure 5. Differential LVPECL VCCIO = 3.3 V 93 ohms 16 mA VCCIO = 3.3 V 196 ohms 100 ohms 93 ohms 16 mA Transmission line, Zo = 100 ohm differential On-chip Off-chip Off-chip 21 On-chip Platform Manager 2 In-System Programmable Hardware Management Controller Table 4. LVPECL DC Conditions1 Over Recommended Operating Conditions Symbol Description Nominal Units ZOUT Output impedance 10 Ohms RS Driver series resistor 93 Ohms RP Driver parallel resistor 196 Ohms RT Receiver termination 100 Ohms VOH Output high voltage 2.05 V VOL Output low voltage 1.25 V VOD Output differential voltage 0.80 V VCM Output common mode voltage 1.65 V ZBACK Back impedance 100.5 Ohms IDC DC output current 12.11 mA 1. For input buffer, see LVDS table. For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet. RSDS FPGA section outputs support the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 6 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in Figure 6 are industry standard values for 1% resistors. Figure 6. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5 V 294 8 mA Zo = 100 VCCIO = 2.5 V 121 100 294 8 mA On-chip Off-chip Off-chip Emulated RSDS Buffer 22 On-chip Platform Manager 2 In-System Programmable Hardware Management Controller Table 5. RSDS DC Conditions Parameter Description Typical Units ZOUT Output impedance 20 Ohms RS Driver series resistor 294 Ohms RP Driver parallel resistor 121 Ohms RT Receiver termination 100 Ohms VOH Output high voltage 1.35 V VOL Output low voltage 1.15 V VOD Output differential voltage 0.20 V VCM Output common mode voltage 1.25 V ZBACK Back impedance 101.5 Ohms IDC DC output current 3.66 mA Typical Building Block Function Performance1 Pin-to-Pin Performance (LVCMOS25 12 mA Drive) Function Timing Units 8.9 ns Basic Functions 16-bit decoder 4:1 MUX 7.5 ns 16:1 MUX 8.3 ns Timing Units Register-to-Register Performance Function Basic Functions 16:1 MUX 412 MHz 16-bit adder 297 MHz 16-bit counter 324 MHz 64-bit counter 161 MHz 183 MHz 500 MHz Embedded Memory Functions 1024x9 True-Dual Port RAM (Write Through or Normal, EBR output registers) Distributed Memory Functions 16x4 Pseudo-Dual Port RAM (one PFU) 1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with device and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 23 Platform Manager 2 In-System Programmable Hardware Management Controller FPGA External Switching Characteristics1, 2, 3 Over Recommended Operating Conditions Symbol Parameter Device Min Max. Units 388 MHz Primary Clocks fMAX_PR4 Frequency for Primary Clock Tree tW_PRI Clock Pulse Width for Primary Clock LPTM21 tSKEW_PRI Primary Clock Skew Within a Device LPTM21 868 ps LPTM21 6.72 ns 7.44 ns LPTM21 0.5 ns Pin-LUT-Pin Propagation Delay tPD Best case propagation delay through one LUT-4 General I/O Pin Parameters tCO Clock to Output – PIO Output Register LPTM21 tSU Clock to Data Setup – PIO Input Register LPTM21 –0.17 ns tH Clock to Data Hold – PIO Input Register LPTM21 1.88 ns tSU_DEL Clock to Data Setup – PIO Input Register with Data Input Delay LPTM21 1.63 ns tH_DEL Clock to Data Hold – PIO Input Register with Input Data LPTM21 Delay –0.24 ns fMAX_IO Clock Frequency of I/O and PFU Register 1. 2. 3. 4. LPTM21 388 MHz Exact performance may vary with device and design implementation. General I/O timing numbers based on LVCMOS 2.5, 8 mA, 0pf load. The tSU_DEL and tH_DEL values use the SCLK_ZERHOLD default step size. Each step is 105 ps. This number for general purpose usage. Duty cycle tolerance is +/–10%. sysCLOCK PLL Timing Over Recommended Operating Condition Parameter Descriptions Conditions Min. Max. Units fIN Input Clock Frequency (CLKI, CLKFB) 7 400 MHz fOUT Output Clock Frequency (CLKOP, CLKOS, CLKOS2) 1.5625 400 MHz fOUT2 Output Frequency (CLKOS3 cascaded from CLKOS2) 0.0122 400 MHz fVCO PLL VCO Frequency 200 800 MHz fPFD Phase Detector Input Frequency 7 400 MHz AC Characteristics tDT Output Clock Duty Cycle Without duty trim selected3 45 55 % tDT_TRIM Edge Duty Trim Accuracy –75 75 % tPH4 Output Phase Accuracy –6 6 % 7 24 Platform Manager 2 In-System Programmable Hardware Management Controller sysCLOCK PLL Timing (Cont.) Over Recommended Operating Condition Parameter Descriptions Output Clock Period Jitter Output Clock Cycle-to-cycle Jitter tOPJIT1, 8 Output Clock Phase Jitter Min. Max. Units fOUT > 100MHz — 150 ps p-p fOUT < 100MHz — 0.007 UIPP fOUT > 100MHz — 180 ps p-p fOUT < 100MHz — 0.009 UIPP fPFD > 100MHz — 160 ps p-p fPFD < 100MHz — 0.011 UIPP fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP Output Clock Cycle-to-cycle Jitter (Fractional-N) fOUT > 100MHz — 230 ps p-p fOUT < 100MHz — 0.12 UIPP Static Phase Offset Divider ratio = integer –120 120 ps Output Clock Period Jitter (Fractional-N) tSPO Conditions 3 tW Output Clock Pulse Width 0.9 — ns tLOCK2, 5 PLL Lock-in Time At 90% or 10% — 15 ms tUNLOCK PLL Unlock Time — 50 ns tIPJIT6 Input Clock Period Jitter fPFD 20 MHz — 1,000 ps p-p fPFD < 20 MHz — 0.02 UIPP tHI Input Clock High Time 90% to 90% 0.5 — ns tLO Input Clock Low Time 10% to 10% 0.5 — ns tSTABLE5 STANDBY High to PLL Stable — 15 ms tRST RST/RESETM Pulse Width 1 — ns tRSTREC RST Recovery Time 1 — ns tRST_DIV RESETC/D Pulse Width 10 — ns tRSTREC_DIV RESETC/D Recovery Time 1 — ns tROTATE-SETUP PHASESTEP Setup Time 10 — ns tROTATE_WD 4 — VCO Cycles PHASESTEP Pulse Width 1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. CLKOS as compared to CLKOP output for one phase step at the maximum VCO frequency. See TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide for more details. 5. At minimum fPFD. As the fPFD increases the time will decrease to approximately 60% the value listed. 6. Maximum allowed jitter on an input clock. PLL unlock may occur if the input jitter exceeds this specification. Jitter on the input clock may be transferred to the output clocks, resulting in jitter measurements outside the output specifications listed in this table. 7. Edge Duty Trim Accuracy is a percentage of the setting value. Settings available are 70 ps, 140 ps, and 280 ps in addition to the default value of none. 8. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise. 25 Platform Manager 2 In-System Programmable Hardware Management Controller Analog Sense and Control Propagation Delays Symbol Parameter Conditions Min Typ. Max. Units Voltage Monitors tVMONtoFPGA tVMONtoOCB 2 Propagation delay VMON Glitch Filter Off input to signal update at FPGA Glitch Filter ON 48 µs 96 µs Propagation delay VMON Glitch Filter Off input to output update at OCB Glitch Filter ON 16 µs 64 µs Current Monitors tIMONtoFPGA Propagation delay IMON input Glitch Filter Off to signal update at FPGA Glitch Filter ON tIMONtoOCB2 Propagation delay IMON input Glitch Filter Off to output update at OCB Glitch Filter ON 16 µs 64 µs tIMONFtoOCB2 Propagation delay IMONF input to output update at OCB 1 µs 48 µs 96 µs Temperature Monitors tTMONtoFPGA Propagation delay TMON input to signal update at FPGA1 Monitor Alarm Filter Depth = 1 15 ms Monitor Alarm Filter Depth = 16 240 ms 32 µs GPIO – Inputs tGPIOtoFPGA Propagation delay GPIO input to signal update at FPGA tGPIOtoOCB3 Propagation delay GPIO input to output update at OCB 50 ns GPIO – Outputs tFPGAtoGPIO Propagation delay FPGA signal update to GPIO output tOCBtoGPIO2 Propagation delay OCB input to output update at GPIO 32 µs 50 ns HVOUT tFPGAtoHVOUT Propagation delay FPGA signal update to HVOUT output tOCBtoHVOUT4 Propagation delay OCB input to output update at HVOUT 32 µs 110 ns TRIM DAC tFPGAtoTrimOE Propagation delay FPGA signal update to TRIM-OE update 32 1. Propagation delay based on one TMON enabled. For multiple TMONs, propagation delay can be multiplied by the number of enabled TMON channels. 2. OCB output propagation delays measured using time delay to GPIO output from OCB. Propagation delay is measured on falling GPIO outputs. Rising output propagation will be dependent on external pull-up resistor. 3. OCB input propagation delays measured using time delay from GPIO input to OCB. 4. HVOUT propagation delay measured with HVOUT in open-drain mode, with switched mode disabled. Propagation delay in charge pump mode is dependent on external load and HVOUT settings. 26 µs Platform Manager 2 In-System Programmable Hardware Management Controller JTAG Port Timing Specifications Symbol fMAX Parameter TCK clock frequency Min. Max. Units — 25 MHz tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 10 — ns tBTH TCK [BSCAN] hold time 8 — ns tBTCO TAP controller falling edge of clock to valid output — 10 ns tBTCODIS TAP controller falling edge of clock to valid disable — 10 ns tBTCOEN TAP controller falling edge of clock to valid enable — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 20 — ns tBUTCO BSCAN test update register, falling edge of clock to valid output — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to valid disable — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to valid enable — 25 ns Figure 7. JTAG Port Timing Waveforms TMS TDI tBTS tBTCPH tBTH tBTCP tBTCPL TCK tBTCO tBTCOEN TDO Valid Data tBTCRS Data to be captured from I/O tBTCODIS Valid Data tBTCRH Data Captured tBTUPOEN tBUTCO Data to be driven out to I/O Valid Data 27 tBTUODIS Valid Data Platform Manager 2 In-System Programmable Hardware Management Controller I2C Port Timing Specifications1, 2 Symbol fMAX Parameter Maximum SCL clock frequency Min. Max. Units — 400 kHz 1. Platform Manager 2 supports the following modes: • Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode) • Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode) 2. Refer to the I2C specification for timing requirements. Switching Test Conditions — FPGA Section Figure 8 shows the output test load used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 6. Figure 8. Output Test Load, LVTTL and LVCMOS Standards VT R1 DUT Test Poi nt CL Table 6. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and LVCMOS settings (L -> H, H -> L) R1 CL 0pF Timing Ref. VT LVTTL, LVCMOS 3.3 = 1.5 V — LVCMOS 2.5 = VCCIO/2 — LVCMOS 1.8 = VCCIO/2 — LVCMOS 1.5 = VCCIO/2 — LVCMOS 1.2 = VCCIO/2 — LVTTL and LVCMOS 3.3 (Z -> H) 1.5 VOL LVTTL and LVCMOS 3.3 (Z -> L) 1.5 VOH Other LVCMOS (Z -> H) VCCIO/2 VOL Other LVCMOS (Z -> L) 188 0pF VCCIO/2 VOH LVTTL + LVCMOS (H -> Z) VOH - 0.15 VOL LVTTL + LVCMOS (L -> Z) VOL - 0.15 VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 28 Platform Manager 2 In-System Programmable Hardware Management Controller Theory of Operation Hardware Management System The Platform Manager 2 is a fast-reacting, programmable logic based hardware management controller. The Platform Manager 2 includes an Analog Sense and Control (ASC) section and an FPGA section, allowing it to address the Power Management, Thermal Management and Digital Control Plane requirements of a circuit board. The Platform Manager 2 FPGA section includes the hardware management control logic and other plug-in IP components to support functions like Fan Control, Voltage by Identification (VID), and time stamped fault logging to internal or external memory. The FPGA also includes the ASC Interface logic (ASC-I/F) used to communicate with the ASC section (internal to the device) and additional ASC hardware management expanders. The Platform Manager 2 supports a scalable, star-architecture implementation with centralized sequencing and control. This is accomplished by adding additional ASC hardware management expanders to the circuit board. The basic system concept is shown in Figure 9. The necessary connections are shown in detail in the System Connections section. Figure 9. Hardware Management System Analog Sense and Control Section FPGA Section MOSFET & Digital I/O Drive Output Control Block FPGA LUTs (IP Components) Current Sense ASC Interface (ASC-I/F) Fan Control Component Power Sequencing To additional ASCs Temperature Sense Voltage Sense ADC ADC Non Volatile Fault Log Time Stamp Fault Log Component I2C Interface Voltage / Current Monitoring VID / Voltage Scaling User Logic FPGA I/O Ports SPI JTAG I2C Trim & Margin Control To additional ASCs, Microcontrollers, etc. The Hardware Management System is configured using Platform Designer, a part of Lattice Diamond software. Platform Designer provides an easy to use graphical and spreadsheet based interface. Platform Designer automatically generates the device memory configuration based on the options selected in the software. See the For Further Information section for more details 29 Platform Manager 2 In-System Programmable Hardware Management Controller Voltage Monitor Inputs The ASC provides ten independently programmable voltage monitor input circuits. There are nine standard voltage channels and one high voltage channel. The standard voltage channels are shown in Figure 10, while the high voltage channel is described in the High Voltage Monitor section. Two individually programmable trip-point comparators are connected to each voltage monitoring input. Each comparator reference has programmable trip points over the range of 0.075 V to 5.734 V. The 75 mV ‘zero-detect’ threshold allows the voltage monitors to determine if a monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to a substantially inactive condition after it has been switched off. Figure 10. ASC Voltage Monitors To ADC Differential Input Buffer X* CompA/Window Select Comp A VMONx VMONx_A Logic Signal Trip Point A MUX VMONxGS* Glitch Filter Comp B VMONx_B Logic Signal Glitch Filter Trip Point B Analog Input TO ASC-I/F & OCB Window Control Filtering VMONx Status 2 I C Interface Unit *Differential Input Buffer X and VMONxGS pins are not present for single-ended VMON x inputs. Figure 10 shows the functional block diagram of one of the nine voltage monitor inputs - ‘x’ (where x = 1...9). Each voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section provides a differential input buffer to monitor the power supply voltage through VMONx (to sense the positive terminal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inaccuracies in voltage measurement with ADC and monitor thresholds due to the potential difference between the Platform Manager 2 device ground and the ground potential at the sensed node on the circuit board. The voltage output of the differential input buffer is monitored by two individually programmable trip-point comparators, shown as Comp A and Comp B. The differential input buffer shown above is not present for any of the singleended VMON inputs. VMON1-4 are differential inputs, while VMON5-9 are single-ended. Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its programmed trip point setting; otherwise it outputs a LOW signal. The VMON4A and VMON9A comparators also output their status signals to the OCB. Hysteresis is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting. Table 7 lists the typical hysteresis versus voltage monitor trip-point. AGOOD Logic Signal All the VMON, IMON and TMON comparators auto-calibrate following a power-on reset event. During this time, the digital glitch filters are also initialized. This process completion is signaled by an internally generated logic signal: AGOOD. The ASC-I/F will not begin communicating valid VMON status bits or receiving GPIO control signals until the AGOOD signal is initialized. 30 Platform Manager 2 In-System Programmable Hardware Management Controller Programmable Over-Voltage and Under-Voltage Thresholds Figure 11 shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. Monitored Power Supply Voltage Figure 11. Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output (a) and Corresponding to Upper and Lower Trip Points (b) UTP LTP (a) (b) Comparator Logic Output During power supply ramp-up the comparator output changes from logic zero to one when the power supply voltage crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state one to zero when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. The upper and lower trip points are automatically selected in software depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. Table 7 shows the comparator hysteresis versus the trip-point range. Table 7. Voltage Monitor Comparator Hysteresis vs. Trip-Point Trip-point Range (V) Hysteresis (mV) Low Limit High Limit 0.66 0.79 8 0.79 0.9 10 0.94 1.12 12 1.12 1.33 14 1.33 1.58 17 1.58 1.88 20 1.88 2.24 24 2.24 2.66 28 2.66 3.16 34 3.16 3.76 40 4.05 4.82 51 4.82 5.73 61 0.075 0.57 0 (Disabled) 31 Platform Manager 2 In-System Programmable Hardware Management Controller The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed” with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’ comparator. Table 8 shows the operation of window function logic. Table 8. Voltage Monitoring Window Logic Comp A Comp B Window (B and Not A) Comment VIN < Trip-Point B < Trip-Point A 0 0 0 Outside window, low Trip-Point B <VIN < Trip-Point A 0 1 1 Inside window Trip-Point B < Trip-Point A < VIN 1 1 0 Outside window, high Input Voltage Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the windowing function by determining if the input is above or below the windowing range. The third section in the voltage monitor circuit is a glitch filter. When enabled, glitches of less than 64 µs will not result in the comparator output changing. This results in a comparator output delay of 64 µs (typical) for all comparator transitions. This is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16 µs (typical). See the Analog Sense and Control Propagation Delays section for more details. The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C Interface section of this data sheet. 32 Platform Manager 2 In-System Programmable Hardware Management Controller Current Monitor Inputs The ASC provides two current monitor circuits as shown in Figure 12. This includes a low-voltage current monitor (with a common mode voltage up to around 6 V, see VIN_IMONP in Recommended Operating Conditions1 section) and a high-voltage current monitor (with a common mode voltage range of up to around 13 V, see VIN_HIMONP in Recommended Operating Conditions1 section). The low-voltage and high-voltage current monitors share the same basic functional blocks, which are described in this section. Only the low-voltage current monitor supports the lowside sensing mode (shown in Figure 12). The high voltage current monitor shares input pins with the high voltage monitor described in the next section. The current monitor circuits have a differential input that is connected to an external shunt resistor. The differential input goes to a pair of programmable gain amplifiers (PGA) and a fast comparator. The output of PGA A is connected to the ADC and the programmable trip point comparator A. The output of PGA B is connected to the programmable trip point comparator B. The output of the fast comparator is routed to the on-chip Output Control Block (OCB). This signal is useful for fast overcurrent or short circuit shutdown scenarios. Figure 12. ASC Current Monitor ASC Low-Side Sense Mode** Trip Point F HIMON_F / IMON_F To OCB (Fast Fault Detection) FAST To ADC External Current Sense Resistor HIMONP IMON1P Comp A Window Mode Select PGA A HIMONN_HVMON IMON1N MUX Trip Point A Glitch Filter TO ASC-I/F and OCB HIMON_B / IMON1_B Logic Signal PGA B Comp B Direction of current flow Glitch Filter Trip Point B To HVMON* Voltage Monitor Pre-Amplified Input HIMON_A / IMON1_A Logic Signal Window Control Amplified Input Filtering IMON Status *HVMON signal is only present in HIMON Current Monitor **Low-Side Sense is only present in low-voltage IMON1 Current Monitor 2 I C Interface Unit The Current Monitors can be divided into four sections: Pre-Amplified Input, Amplified Input, Window Control, and Filtering. The first section includes the differential input pins IMON1P and IMON1N (low voltage current monitor) or HIMONP and HIMONN_HVMON (high voltage current monitor). These pins are connected to the PGA circuits as well as the direct differential connection to the Fast Fault Detector. The differential input is monitored by the fast fault detector. The fast fault detector has coarse accuracy and eight programmable trip points. The key feature of the fast fault detector is its response time. The fast fault detector outputs a HIGH signal to the OCB if the differential voltage across the current sensing shunt exceeds the programmed trip point setting. The current shunt is normally connected on the high-side of the input voltage. However, the lowvoltage current monitor also supports low-side sensing. The low-side sensing mode should be enabled when sensing negative voltage supplies (such as –48 V) or if the current sense resistor is placed in the return line between the load and ground. This insures proper operation of the fast comparator in a low-side sensing circuit. Table 9 shows the available trip points for the fast fault detector vs. three frequently used sense resistor values. 33 Platform Manager 2 In-System Programmable Hardware Management Controller Table 9. Fast Fault Detector Current Trip Points vs. Frequently Used Sense Resistor Values Current Sense Resistor Value Trip Point Setting 1 Milliohm 5 Milliohm 10 Milliohm 50 mV 50 A 10 A 5A 100 mV 100 A 20 A 10 A 150 mV 150 A 30 A 15 A 200 mV 200 A 40 A 20 A 250 mV 250 A 50 A 25 A 300 mV 300 A 60 A 30 A 400 mV 400 A 80 A 40 A 500 mV 500 A 100 A 50 A The Programmable Gain Amplifiers have gain settings of 10x, 25x, 50x, and 100x. The PGA circuits amplify the voltage differential across the current shunt and pass the results to the amplified input section of the current monitor. The Amplified Input section provides two individually programmable trip-point comparators, shown as Comp A and Comp B above. Each comparator supports four different trip points. Combining these trip points with the respective PGA settings, 16 unique threshold levels are selected for each current monitor. Table 10 shows the available voltage differential trip points. Table 10. Comparator Trip Points Trip Point Setting Programmable Gain Amplifier Setting (V/V) 10 x 25 x 50 x 100 x 1 75 mV 30.5 mV 15.5 mV 8 mV 2 100 mV 40.5 mV 20.5 mV 10.5 mV 3 140 mV 56.5 mV 28.5 mV 14.5 mV 4 190 mV 77 mV 39 mV 20 mV The output of PGA A is also passed to the on-chip ADC. The current is measured and averaged by the ADC at regular intervals, as described in the Current Measurement with ADC section of the datasheet. The window control section of the current monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed” with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware, similar to the voltage monitor window function. Through the use of the multiplexer, the current monitor’s ‘A’ output may be set to report either the status of the ‘A’ comparator, or the window function of both comparator outputs. The current monitor’s ‘A’ output indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’ comparator. Table 11 shows the operation of window function logic. Table 11. IMON Window Mode Behavior Input Voltage Comp A Comp B Window (B and Not A) IIN < Trip-Point B < Trip-Point A 0 0 0 Outside window, low Trip-Point B <IIN < Trip-Point A 0 1 1 Inside window Trip-Point B < Trip-Point A < IIN 1 1 0 Outside window, high 34 Comment Platform Manager 2 In-System Programmable Hardware Management Controller Note that when the ‘A’ output of the current monitor circuit is set to windowing mode, the ‘B’ output continues to monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the windowing function by determining if the input is above or below the windowing range. The fourth section in the current monitor circuit is a glitch filter. When enabled, glitches of less than 64 µs will not result in the comparator output changing. This results in a comparator output delay of 64 µs (typical) for all comparator transitions. This is especially useful for reducing the possibility of false triggering from noise that may be present on the currents being monitored. When the filter is disabled, the comparator output will be delayed by 16 µs (typical). See the Analog Sense and Control Propagation Delays section for more details. The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C Interface section of this data sheet. High Voltage Monitor The High Voltage Monitor circuit is a single-ended high voltage monitor (HVMON) which is connected to the same input pin as the High Voltage Current Monitor (HIMONN_HVMON). Figure 13 shows the single-ended monitor circuit, which monitors the voltage on the HIMONN_HVMON pin. Figure 13. HVMON Monitor Circuit From Current Monitor HIMONN_HVMON To ADC Comp A Comp A/Window Select HVMON_A Logic Signal MUX Trip Point A Glitch Filter TO ASC-I/F HVMON_B Logic Signal Comp B Glitch Filter Trip Point B Analog Input Window Control Filtering VMONx Status I2C Interface Unit The HVMON follows the same structure as the Voltage Monitor circuits. Two individually programmable trip-point comparators are connected to the HIMONN_HVMON pin voltage. Each of the comparator references has 408 programmable trip points, over a range of 0.227 V to 13.226 V. The functional block diagram, shown in Figure 13, is a similar structure to the other single-ended Voltage Monitor circuits. Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its programmable trip point setting. A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering. Table 12 shows a typical hysteresis versus voltage monitor trip point. 35 Platform Manager 2 In-System Programmable Hardware Management Controller Table 12. HVMON Hysteresis vs Trip Point Range Trip-point Range (V) Hysteresis (mV) Low Limit High Limit 1.91 2.27 22 2.27 2.7 28 2.69 3.2 30 3.16 3.76 38 3.72 4.43 44 4.40 5.24 52 5.18 6.17 61 6.04 7.20 72 7.08 8.43 84 8.29 9.87 99 9.68 11.52 115 11.17 13.2 133 0.23 1.28 0 (Disabled) The Over-Voltage and Under-Voltage thresholds, along with the window mode and glitch filter, are identical to the features described in the voltage monitor section. VMON and IMON Measurement with the On-Chip Analog to Digital Converter (ADC) The ASC section of Platform Manager 2 has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs or the currents at the IMON inputs. This ADC is also used in closed loop trimming of DC-DC converters. Closed loop trimming is covered later in this document. Figure 14. ADC Monitoring VMON and IMON HIMON PGA Output + VMON1 _ IMON1 PGA Output ÷3 / ÷1 HVMON* ADC MUX VMON5 Programmable Analog Attenuation VMON MUX + VMON4 _ Programmable Digital Multiplier x8 / x4 x3 / x1 ADC To I2C ADC Readout Register Internal VREF 2.048 V ÷8 / ÷4 IMON/HIMON Averaging VMON9 To closed Loop Trim Circuit To I2C IMON/HIMON Average Register ADC Control Logic From Closed Loop Trim Circuit From I2C ADC MUX Address Figure 14 shows the ADC circuit arrangement within the ASC device. The ADC can measure all analog input voltages up to 2.048 V through the multiplexer, ADC MUX. The ADC MUX receives inputs from the High Voltage IMON Programmable Amplifier (PGA), the IMON1 PGA, the High Voltage Monitor (HVMON) at the HIMONN_HVMON pin, and the VMON MUX. The VMON voltages can be attenuated (divided by three) or unattenuated (divided by 36 Platform Manager 2 In-System Programmable Hardware Management Controller one). The divided-by-three setting is used to measure voltages from 0 V to 6 V range and divided-by-one setting is used to measure the voltages from 0 V to 2 V range. The HVMON voltage requires attenuation, with settings for divided by eight (voltages between 8 V and 13.2 V) or divided by four (voltages between 8 V and 0 V). The HIMON and IMON PGA output voltages must be kept below 2.0 V for proper ADC operation since they are not attenuated. The ADC control logic manages the MUX and attenuation settings. The control logic manages conversion requests from I2C and the Closed Loop Trim Circuit. The control logic also schedules regular IMON1 and HIMON conversions, which are subsequently averaged and stored for user access. These IMON conversions are configured through the I2C bus and filtered using an eight sample, weighted averaging scheme. The control logic also sets the digital multiplication factor. This results in VMON and HVMON voltages, regardless of attenuation setting, maintaining a 2 mV per LSB scale. (See the Calculation section for more details). The IMON1/HIMON voltages are not multiplied. A microcontroller or FPGA IP can place a request for any VMON or IMON voltage measurement at any time through the I2C bus. After the receipt of an I2C command, the control logic will connect the ADC to the I2C selected VMON or IMON through the ADC MUX. The ADC output is then latched into the I2C readout registers. Calculation The algorithm to convert the ADC code to the corresponding VMON / HVMON voltage takes into consideration the relevant attenuation setting. In other words, if the attenuation is set to divide-by-eight, then the 10-bit ADC result is automatically multiplied by eight to calculate the actual voltage at that VMON input. Thus, the I2C readout register is 13 bits instead of 10 bits. The other attenuator settings are also automatically compensated using the digital multiplier. The following formula can always be used to calculate the actual voltage from the ADC code. Voltage at the VMONx Pins VMON= ADC code (13 bits, converted to decimal) * 2 mV The ADC code includes the ADC_VALUE_HIGH (8 bits) and ADC_VALUE_LOW (5 bits) read from I2C interface. Calculating the HIMON or IMON current is slightly more complex, and requires knowledge about the current PGA setting and the resistance value of the current sense shunt resistor. The PGA has four settings (x10, x25, x50, and x100), while the current sensing resistance is chosen by the customer. Current at the HIMON / IMON1 Pins IMON current = ADC code (13 bits, converted to decimal) * 2 mV / (PGAsetting x Rsense) 37 Platform Manager 2 In-System Programmable Hardware Management Controller Temperature Monitor Inputs The ASC provides two external temperature monitor inputs and one internal temperature monitor as shown in Figure 15. Figure 15. Temperature Monitor Ideality Offset TMON1 TMON MUX TMON2 Temperature Sensor Interface Temperature Conversion ADC Measurement Average Filter I2C Register TMON_INT Comp A Trip Point A Monitor Alarm Filter To ASC-I/F Monitor Alarm Filter To ASC-I/F Hysteresis A Comp B Trip Point B Hysteresis B The independently programmable temperature monitor inputs can be used with internal substrate diodes on microprocessors, FPGAs, ASICs, or with low cost external NPN or PNP transistors. The temperature sensor interface block includes programmable support for a variety of sensor configurations as shown in Figure 16. The sensor configuration settings available in the design software are described in Table 13. Figure 16. Remote TMON Diode Configurations a TMON_p b c TMON_p TMON_p TMON_n TMON_n TMON_n Recommended Configurations d e TMON_p Not Recommended 38 TMON_p Platform Manager 2 In-System Programmable Hardware Management Controller Table 13. Remote TMON Diode Configurations Figure Number Auto- Compensation Series Resistance Compensation 16-a Effective Effective Specified in recommended operating conditions Differential PNP or NPN or Diode 16-b / 16-c Not effective Effective Dependent on variance Single Ended 16-d / 16-e Not effective Not Effective Sensor Configuration Beta Compensated PNP Accuracy Not specified The temperature sensor interface block also has built-in circuits to automatically compensate for the series resistance of the PCB traces to the sensor as well as the intrinsic device resistance. In addition, the interface block has circuits to compensate for the variable Beta () of the transistor sensor when it is connected in the configuration shown in Figure 16-a. (In order for the variable compensation circuit to be effective it must be able to measure the base current separately from the collector current.) For a discrete PNP or NPN transistor with high (approximately 100 or greater) the effect of variable beta is typically negligible. However, most substrate diode temperature sensors will have a low value which can vary considerably over temperature and current density making this a very useful feature. The temperature signal information is converted to digital data by the dedicated TMON ADC. The digital data is scaled and converted to a two’s complement, 11-bit temperature reading by the Temperature Conversion block. The measurement resolution is 0.25 oC per bit. The temperature conversion block takes into account the user entered ideality factor and offset value. The ideality factor (also known as the emission coefficient or the N-factor) is a measure of how closely a real diode follows the ideal diode equation. In a real diode imperfections allow some recombination to occur in the junctions or by other methods which are not accounted for in the ideal equation. The ASC temperature conversion block is optimized for an ideality factor of 1 so any errors in the actual ideality factor of the sensor will produce a proportional error in the temperature value (in Kelvins). The diode ideality factor can be programmed in the range from 0.9 to 2.0 to match the actual ideality factor of the sensor. An approximate value for the ideality factor for a 2N3904 NPN transistor is 1.004 and for a 2N3906 PNP transistor is 1.008. A substrate diode temperature sensor will typically have an ideality factor published in its data sheet. Uncertainty can be introduced in temperature measurement by using an approximate value rather than the actual value for a 2N3904 or a 2N3906 transistor. This can lead to an error of around 0.4 oC. If the ideality factor for the transistor being used is not published it can be determined by the ASC using the following procedure. 1. Force the system temperature to a known value (Tref). 2. With the ASC ideality factor set to 1.000, record the temperature value calculated (Tnocal). 3. Convert the Tref and Tnocal to Kelvin. 4. Divide the Tnocal (K) by Tref (K). The result will be the actual ideality factor to be entered for the given TMON channel in the design software. Note: The calibration is only as accurate as the Tref value. Any errors in the test equipment used will be transferred to the ASC readings. The temperature conversion block also provides user programmable temperature offset from –64 ºC to 63.75 ºC for each channel’s digital data to mitigate errors due to self-heating of the sensor, systematic offset and other unforeseen errors. 39 Platform Manager 2 In-System Programmable Hardware Management Controller The conversion block also includes programmable output values for detected short or open conditions at the monitor input. The output levels are shown in Table 14. Table 14. Temperature Measurement Fault Readings Fault Short Open 0 –255.75 oC 255.75 oC 1 255.75 oC –255.75 oC The converted temperature data for each channel is stored in two registers and can be read out via I2C, after the programmable Measurement Averaging filter. See the Measurement and Control Register Access section for more details about the data register format. The programmable measurement filter performs exponential averaging. Data is available immediately after one update cycle and is continually averaged using the programmable filter coefficients of 1, 8, or 16 per channel. The filtering equation is shown below: FiltCo – 1 TempMeas x TempAve x = ---------------------------------------- + TempAve x – 1 -----------------------FiltCo FiltCo When the temperature input changes it will require some settling time for the new value to be fully reflected in the results register due to the averaging filter. The settling time will vary depending upon how many channels are enabled and the programmed averaging coefficient. The settling time for various averaging coefficients and number of channels is shown in Table 15. Table 15. Temperature Measurement Settling Time1 Measurement Averaging Coefficient Number of Channels Enabled Average Settling Time (ms) 1 1 14.2 8 1 114 16 1 228 1 2 28.4 8 2 227 16 2 454 1 3 42.6 8 3 341 16 3 682 1. Values are approximate and are not guaranteed by characterization. In addition to the direct temperature measurement the ASC has a temperature comparison function. The digital data of each channel is monitored by two trip-point comparators, shown as Comp A and Comp B in Figure 15. The digital temperature data monitored at the comparators is not processed by the measurement averaging filters. Each comparator reference has programmable trip points over the range of –64 ºC to 155 ºC with resolution of 1ºC. Whenever the monitored temperature is above the trip point, the comparator output is set to one. The comparator outputs are transmitted over the ASC-I/F to the FPGA, depending on the setting of the Alarm Filter. The two comparators each support programmable Hysteresis of 0 ºC to 63 ºC. When a comparator is used for overtemperature monitoring the programmed hysteresis value is subtracted from the trip point and when the comparator is used for under-temperature monitoring the programmed hysteresis value is added to the trip point. The hysteresis behavior is displayed in Figure 17 (Overtemperature setting with Hysteresis) and Figure 18 40 Platform Manager 2 In-System Programmable Hardware Management Controller (Undertemperature setting with Hysteresis).Each comparator can be individually selected as either over-temperature or under-temperature operation. Monitored Temperature Figure 17. Monitor Alarm Signal Behavior - Overtemperature (OT) Setting Trip Point Hysteresis Trip Point - Hysteresis Monitor Alarm Signal Monitored Temperature Figure 18. Monitor Alarm Signal Behavior - Undertemperature (UT) Setting Trip Point + Hysteresis Hysteresis Trip Point Monitor Alarm Signal A programmable Alarm Filter (separate from the measurement averaging filter) is available at the output of the comparators. The depth of this filter is programmable from one to 16. The filter monitors the comparator alarm output each time the temperature measurement is refreshed. The filter counts up each time the comparator alarm value is 1, and down each time the comparator alarm value is 0. When the filter counter reaches the programmed filter depth, the TMONx_A or TMONx_B signal are set to one. 41 Platform Manager 2 In-System Programmable Hardware Management Controller Digital Inputs/Outputs The ASC section of Platform Manager 2 has four dedicated digital outputs (HVOUTs) and ten General Purpose Input/Output (GPIO) pins. The four HVOUT pins can be configured as high-voltage FET drivers or Open Drain outputs. This provides a high degree of flexibility when interfacing to power supply control inputs or other external logic signals. The ten GPIO pins can be configured as inputs or Open Drain outputs. Figure 19 shows a block diagram of the GPIO circuitry. When configured as inputs, GPIO1 through GPIO10 are registered and made available to the FPGA using the ASC-I/F. GPIO5 through GPIO10 are also made available to the Output Control Block (OCB) directly without being registered. Table 16 shows a summary of the input and output sources for each GPIO pin. Table 16. GPIO Input and Output Sources GPIO ASC-I/F Input OCB Input ASC-I/F output OCB output Hysteretic control GPIO1 Y N Y N N GPIO2 Y N Y Y Y GPIO3 Y N Y Y Y GPIO4 Y N Y N N GPIO5 Y Y Y N N GPIO6 Y Y Y N N GPIO7 Y Y Y N N GPIO8 Y Y Y N N GPIO9 Y Y Y N N GPIO10 Y Y Y N N Figure 19. GPIO Block Diagram Input Buffer Digital Input To OCB ** Digital Input To ASC-I/F GPIOx Pin Digital Control From ASC-I/F or From OCB * Open Drain Output Buffer * Digital Control comes from OCB for GPIO 2 and 3. Digital Control comes from ASC-I/F for remaining GPIO. ** Only available for GPIO 5, 6, 7, 8, 9 and 10. 42 Platform Manager 2 In-System Programmable Hardware Management Controller Output Control Block The ASC Output Control Block (OCB) is used to control GPIO2, GPIO3, and the four HVOUTs. The Output Control Block has two modes of operation available; Direct Output control and Hysteretic Feedback control as shown in Figure 20. Direct Output control is supported by various inputs which include the I2C registers, GPIO pins 5-10 (when configured as inputs), the VMON4A and VMON9A comparator output signals, and the Fast IMON1 and Fast HIMON comparator output signals. These inputs are individually selectable for each of the outputs. When these inputs are used with the Direct Output control mode they provide a fast path for control which has very low propagation delay. The outputs in the OCB can also be controlled from the FPGA Logic over the ASC Interface (ASC-I/F) with the normal propagation delays. See the Analog Sense and Control Propagation Delays section for more details. Figure 20. Output Control Block – Simplified Diagram FPGA Logic (ASC–I/F) GPIO2 I 2C GPIO5-10 Direct Output Control GPIO3 VMON4 and VMON9 Output Routing Fast HIMON, IMON FPGA Logic (ASC–I/F) VMON5 and VMON6 HVOUT1 HVOUT2 HVOUT3 Hysteretic Feedback Control HVOUT4 HIMON, IMON The OCB outputs can also be configured for Hysteretic Feedback control if desired. In the Hysteretic Feedback control mode the output will be switched on and off based upon the feedback signal chosen. The available feedback signals are the HIMON, IMON1, VMON5, or VMON6 trip points. As the feedback signal changes it will turn the output on or off depending upon whether it is above or below the chosen set-point and depending upon the output polarity. The user logic can switch between the high and low trip points of a signal to provide additional flexibility. In addition, the FPGA Logic can be dynamically selected to provide the feedback signal over the ASC-I/F which allows the user logic to change from a conditional output to a static value. One example of how the Hysteretic feedback control feature can be used is to modulate a high-voltage FET driver using the FPGA logic and the trip points to control the rate of modulation over different voltage ranges - such as in a Hot Swap application. The design software provides an easy to use interface for configuring the device as a hot swap controller. The software will generate the required device settings and control algorithm automatically. 43 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 21. HVOUT Output Routing MUX Block Diagram OCB Routing MUX FPGA Logic (ASC-I/F) 0 I2C 1 GPIO5 2 GPIO6 3 GPIO7 4 GPIO8 5 GPIO9 6 GPIO10 7 IMON_F 8 HIMON_F 9 VMON4_A 10 VMON9_A 11 HIMON – HCM1 12 IMON – HCM2 13 VMON5 – HCM3 14 VMON6 – HCM4 15 Polarity MUX 1 PWM HVOUT (1 - 4) 0 Configuration Memory Configuration Memory Figure 21 is a generic HVOUT routing diagram that applies to all the HVOUTs and provides a bit more detail than the simplified diagram in Figure 20. The MUX on the left is configured by Platform Designer software and selects from either the 12 direct control signals at the top or the four Hysteretic Control Module (HCM) signals at the bottom. The software is also used to select normal or inverted control. The features and configuration of the PWM and HVOUT blocks are covered in the High Voltage Outputs section. If PWM is enabled then the output of the Polarity MUX will enable or disable the PWM; otherwise the HVOUT will be on or off based on the Polarity Mux output signal. 44 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 22. GPIO Output Routing MUX Block Diagram OCB Routing MUX FPGA Logic (ASC-I/F) 0 I2C 1 GPIO5 2 GPIO6 3 GPIO7 4 GPIO8 5 GPIO9 6 GPIO10 7 IMON_F 8 HIMON_F 9 VMON4_A 10 VMON9_A 11 HIMON – HCM1 12 IMON – HCM2 13 VMON5 – HCM3 14 VMON6 – HCM4 15 Polarity MUX 1 GPIO (2 – 3) 0 Configuration Memory Configuration Memory Figure 22 is a generic GPIO routing diagram that applies to GPIO2 & GPIO3 and it provides a bit more detail than the simplified diagram in Figure 20. The MUX on the left is configured by Platform Designer software and selects from either the 12 direct control signals at the top or the four Hysteretic Control Module (HCM) signals at the bottom. The software is also used to select normal or inverted control. The GPIO pin will be on or off based on the Polarity Mux output signal. Figure 23 is a diagram of Hysteretic Control Module #1 (HCM1) which is a little more complex than the other HCMs in the device. It is unique in that it is the only HCM that supports a dynamic selection of the Trip Point from the table; while the other HCMs can only dynamically switch between two comparator outputs (for example a low and high setting). The software configures the Trip Point MUX to either use a fixed configuration HIMON trip point or the dynamic HIMON trip point which is set by the FPGA Logic based upon the operating conditions. The output of the HIMON comparator is inverted before sending it to the Hysteretic Enable MUX. 45 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 23. OCB HIMON HCM1 Block Diagram OCB Inverter HIMON_A Trip Point MUX Configuration Memory Trip Point 0 FPGA Logic Trip Point (ASC-I/F) 1 HIMON Comparator* Configuration Memory Static Control MUX Hysteretic Enable MUX 1 Control Signals from FPGA Logic (ASC-I/F) GPIO2 0 GPIO3 1 HVOUT1 2 HVOUT2 3 HVOUT3 4 HVOUT4 5 HIMON – HCM1 (To Output Routing Muxes) 0 FPGA Logic (ASC-I/F) 6 7 Configuration Memory * HIMON Windowing and Glitch Filters are not shown in this diagram for clarity. The input to the OCB inverter is from the glitch filter. The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The HIMON comparator signal is selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage sensed at the HIMON input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over the ASCI/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output being controlled by the HCM. For example, if HCM1 is selected for HVOUT2, then the Static Control MUX would also be set to HVOUT2. In this manner when Hysteretic Mode is disabled it is just like setting the OCB Routing MUX to zero where the FPGA Logic controls the HVOUT or GPIO over the ASC-I/F. 46 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 24. OCB IMON1 HCM2 Block Diagram IMON1 Configuration Memory Trip Point A Comparator MUX 0 OCB Inverter IMON1 Comparators* 1 Configuration Memory Trip Point B FPGA Logic (ASC-I/F) Static Control MUX Hysteretic Enable MUX 1 Control Signals from FPGA Logic (ASC-I/F) GPIO2 0 GPIO3 1 HVOUT1 2 HVOUT2 3 HVOUT3 4 HVOUT4 5 0 IMON1 – HCM2 (To Output Routing Muxes) FPGA Logic (ASC-I/F) 6 7 Configuration Memory * IMON Windowing and Glitch Filters are not shown in this diagram for clarity. The input to the comparator MUX is from the glitch filters. Figure 24 is a diagram of Hysteretic Control Module #2 (HCM2) which is also an IMON based HCM. The software is used to select both the A and B trip points, while the FPGA Logic is used to dynamically switch between the two comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable MUX. The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The Comparator MUX output signal is selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage sensed at the IMON1 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output being controlled by the HCM. When using the hysteretic mode in hot swap applications, the design software will automatically configure the muxes and generate the control algorithm. See the For Further Information section for more details. 47 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 25. OCB VMON5 HCM3 Block Diagram VMON5 Configuration Memory Trip Point A Comparator MUX 0 OCB Inverter VMON5 Comparators* 1 Configuration Memory Trip Point B FPGA Logic (ASC-I/F) Static Control MUX Hysteretic Enable MUX 1 Control Signals from FPGA Logic (ASC-I/F) GPIO2 0 GPIO3 1 HVOUT1 2 HVOUT2 3 HVOUT3 4 HVOUT4 5 0 VMON5 – HCM3 (To Output Routing Muxes) FPGA Logic (ASC-I/F) 6 7 Configuration Memory * VMON5 Windowing and Glitch Filters are not shown in this diagram for clarity. The input to the comparator MUX is from the glitch filters. Figure 25 is a diagram of Hysteretic Control Module #3 (HCM3) which is a VMON based HCM. The software is used to select both the A and B trip points, while the FPGA Logic is used to dynamically switch between the two comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable MUX. The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The Comparator MUX output signal is selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage sensed at the VMON5 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output being controlled by the HCM. 48 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 26. OCB VMON6 HCM4 Block Diagram VMON6 Configuration Memory Trip Point A Comparator MUX 0 OCB Inverter VMON6 Comparators* 1 Configuration Memory Trip Point B FPGA Logic (ASC-I/F) Static Control MUX Hysteretic Enable MUX 1 Control Signals from FPGA Logic (ASC-I/F) GPIO2 0 GPIO3 1 HVOUT1 2 HVOUT2 3 HVOUT3 4 HVOUT4 5 0 VMON6 – HCM4 (To Output Routing Muxes) FPGA Logic (ASC-I/F) 6 7 Configuration Memory * VMON6 Windowing and Glitch Filters are not shown in this diagram for clarity. The input to the comparator MUX is from the glitch filters . Figure 26 is a diagram of Hysteretic Control Module #4 (HCM4) which is a second VMON based HCM. The software is used to select both the A and B trip points but, the FPGA Logic is used to dynamically switch between the two comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable MUX. The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. When the Comparator MUX output signal is selected the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage sensed at the VMON6 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output being controlled by the HCM. The Platform Designer software has component interfaces that are used to simplify the task of configuring the OCB blocks discussed in this section. For example, the Hot Swap component provides a functional interface for the designer while setting the trip points for VMONs and IMONs, and routing them to HVOUTs using OCB paths. 49 Platform Manager 2 In-System Programmable Hardware Management Controller High Voltage Outputs In addition to being usable as digital Open Drain outputs the four HVOUT pins can be configured as high-voltage FET drivers. Figure 27 shows the details of the HVOUT circuitry. Figure 27. HVOUT Block Diagram Charge Pump Vpp ISOURCE HVOUTx Pin ISINK Switched Mode Select Digital Control from OCB Switched Mode Control HVOUT / Open Drain Select When the HVOUT is configured as a high-voltage FET driver the output either sources current from a charge pump or sinks current. The output level at the pin can rise to a configurable maximum voltage. The maximum voltage levels that are required depend on the gate-to-source threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET’s source with the source pin of the FET tied to the supply of the target board. Using this arrangement allows the system to provide a wide range of ramp rates for the FET driver. The HVOUT FET driver outputs a configurable source current (ISOURCE) in order to charge the FET gate. When the driver is turned off, it outputs a configurable sink current (ISINK) to discharge the FET gate. The Isink setting also includes a fast turn off setting. See the High Voltage FET Drivers section in DC and Switching Characteristics for more details. The four HVOUT pins can also be configured as switched mode outputs in either the high-voltage FET driver or Open Drain mode. This is useful when the HVOUT is driving a High side MOSFET controlling a supply greater than 6V. This feature is also useful for driving a MOSFET in a charge pump circuit to generate voltages above 12 volts. The switched output duty cycle can be configured from 6.25% up to 93.75% in step sizes of 6.25% and the frequency can be configured as either 15.625 or 31.25 kHz. This flexibility allows the output to be configured to drive a wide variety of circuit components for a design. The rise and fall of the switched mode outputs may not complete with certain combinations of the charge pump settings (VPP, ISOURCE, ISINK) and the switched mode settings (Duty Cycle and Frequency). The configuration should be chosen with the output circuit in mind. 50 Platform Manager 2 In-System Programmable Hardware Management Controller Safe State During power-up the ASC GPIO will be configured as outputs and will be in the “Safe-State” as defined in Table 17. The HVOUTs will be configured in the FET driver mode during power-up. When the ASC completes the power up sequence then the HVOUT and GPIO control is transferred to the ASC-I/F or OCB depending upon the configuration. The ASC section will indicate that it has completed the power up sequence by asserting the AGOOD signal to the FPGA section using the ASC-I/F. Table 17. ASC GPIO and HVOUT Safe-State Definitions I/O SAFE-STATE HVOUT1 Low HVOUT2 Low HVOUT3 Low HVOUT4 Low GPIO1 Low GPIO2 Low GPIO3 Low GPIO4 Low GPIO5 Low GPIO6 Low GPIO7 Hi-Z GPIO8 Hi-Z GPIO9 Hi-Z GPIO10 Low Controlling Power Supply Output Voltage by Trim and Margin Block One of the key features of the ASC is its ability to make adjustments to the power supplies that it may also be monitoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device. As shown in Figure 28 the Trim and Margin Block can adjust voltages of four different power supplies through the DACs built-in the Trim Cells. The DC-DC blocks in the figure represent virtually any type of DC power supply that has a trim or feedback input. This can be an off-the-shelf unit or custom circuit designed around a switching regulator IC. The interface between ASC and the power supply shown in diagram by a resistor actually represents a resistor network. The individual ASC-I/F control signals for each Trimcell are: • ASCx_TRIMx_CLTE — This is a closed loop trim enable signal of a TrimCell. When ASCx_TRIMx_CLTE =1 the closed loop trimming for the DC-DC power supply connected to the TrimCell is enabled. • ASCx_TRIMx_P0 and ASCx_TRIMx_P1 — These are two closed loop Trim Profile select signals used to select the active voltage profile of a TRIM cell. • ASCx_TRIMx_OE — This control signal enables the DAC output of a TrimCell. When ASCx_TRIMx_OE =1 the DAC output of the Trim cell is active. Other inputs to the TrimCell are: • ADC — This input to the Trim cell is from the ADC which converts each VMON voltage into digital. The ADC input is used by the Trim Cell for controlling the closed loop trim operation. • I2C interface — Internal registers of the TrimCell can be accessed via I2C interface. The Platform Designer software provides control signals which can be programmed to restrict I2C access to the ASC. 51 Platform Manager 2 In-System Programmable Hardware Management Controller Next to each DC-DC converter, three example voltages are shown. These example voltages correspond to the operating voltage profile of the corresponding TrimCell. As shown in Figure 28, the active operating profile for each TrimCell is selected independently (of other TrimCells) using TRIMx_P0 and TRIMx_P1 signals. Figure 28. ASC Margin/Trim Block DC-DC Output Voltage Controlled by Profiles ASC Margin/Trim Block VIN VOUT TRIM1_CLTE TRIM1_P0, TRIM1_P1 TrimCell #1 DAC Trim 1 DC-DC R1* Trim-in TRIM1_OE ADC Input from VMON1 TrimCell #2 VIN DAC Trim 2 DC-DC R2* TrimCell #3 I2C VIN DAC Trim 3 DC-DC R3* Trim-in TrimCell #4 1 1.05 Voltage profile 2 1 0 0.96 TRIM2_P1 TRIM2_P0 VOUT Voltage profile 0 0 0 1.2 Voltage profile 1 0 1 1.28 Voltage profile 2 1 0 1.14 TRIM3_P1 TRIM3_P0 VOUT Voltage profile 0 0 0 1.5 Voltage profile 1 0 1 1.57 Voltage profile 2 1 0 1.42 VOUT VIN DAC Trim 4 R4* DC-DC Trim-in TRIM4_OE ADC Input from VMON4 0 I2C TRIM4_CLTE TRIM4_P0, TRIM4_P1 Voltage profile 1 VOUT TRIM3_OE ADC Input from VMON3 1 Trim-in TRIM3_CLTE TRIM3_P0, TRIM3_P1 VOUT 0 VOUT TRIM2_OE ADC Input from VMON2 TRIM1_P0 0 I2C TRIM2_CLTE TRIM2_P0, TRIM2_P1 TRIM1_P1 Voltage profile 0 I2C *Indicates resistor network, see Figure 29. 52 TRIM4_P1 TRIM4_P0 VOUT Voltage profile 0 0 0 3.3 Voltage profile 1 0 1 3.46 Voltage profile 2 1 0 3.13* Platform Manager 2 In-System Programmable Hardware Management Controller There are four independently enabled TrimCells in the ASC section of LPTM21 for controlling individual power supplies. Each Trimcell can generate up-to three trimming voltages to control the output voltage of the DC-DC converter. Figure 29. TrimCell Driving a Typical DC-DC Converter VOUT VIN VOUT DC-DC Converter R3 TrimCell #N R1 DAC Trim R2 Figure 29 shows an example resistor network between the TrimCell #N in the ASC and the DC-DC converter. The values of these resistors depend on the type of DC-DC converter used and its operating voltage range. The calculation to determine the values of the resistors R1, R2, and R3 is performed automatically in the Platform Designer software. 53 Platform Manager 2 In-System Programmable Hardware Management Controller TrimCell Architecture The TrimCell block diagram is shown in Figure 30. Each TrimCell consists of a programmable Voltage Setpoint Register, closed loop trim control logic and one 8-bit DAC at the output. The Closed Loop Trim logic compares the Voltage Setpoint Register with the VMON voltage (converted to digital by the ADC) and adjusts the 8 bit DAC output, which provides the trimming voltage required to set the output voltage of a programmable supply. The Closed Loop Trim is enabled on a per channel basis, depending on the ASC-I/F signal TRIMx_CLTE. Figure 30. TrimCell Architecture DAC Codes PROFILE 2 DAC CODE (Configuration Memory) 8 PROFILE 1 DAC CODE (Configuration Memory) 8 TRIMCELL ARCHITECTURE 01 00 PROFILE MUX 10 8 8 PROFILE 0 DAC CODE (Configuration Memory) 2 I2C Voltage Register 2 ASC I C Write TRIMx_P0, TRIMx_P1 (ASC-I/F) I2C Controller Voltage Profiles 12 10 01 00 PROFILE 0 Setpoint (Configuration Memory) 12 Voltage Setpoint Register Digital Closed Loop Trim Logic 12 8 8 DAC Register PROFILE 1 Setpoint (Configuration Memory) MUX 12 PROFILE MUX PROFILE 2 Setpoint (Configuration Memory) 8 TRIMx DAC 12 12 2 I2C Voltage Register/ VID Setpoint TRIMx_CLTE (ASC-I/F) ASC I2C Write TRIMx_OE (ASC-I/F) ADC Output (VMONx) Trim Configuration Mode (BYPASS - Configuration Memory) TRIMx_P0, TRIMx_P1 (ASC-I/F) I2C Controller Profile0, Profile1 and Profile2 are 12-bit setpoints, which are written in the EEPROM memory during programming. The active profile for each TrimCell is independently chosen based on ASC-I/F signals TRIMx_P0 / TRIMx_P1. This profile is copied to the Voltage Setpoint Register whenever the TRIMx_P0, TRIMx_P1 signals change. As shown the Profile0 Setpoint written in configuration memory can be overwritten by I2C commands during runtime. The I2C access to the Profile0 Setpoint can be restricted based on the ASC I2C write feature during configuration. See the I2C Interface section for more details. The DAC output of the Trimcell is enabled using ASC-I/F signal TRIMx_OE. The DAC register value is converted to an analog voltage output by the DAC. The DAC register is written either by the closed loop trim logic or by user defined DAC code.The input to the DAC register is determined based on the Trim configuration mode setting. The "Trim Calculator" configuration mode (set in the Platform Designer software), selects the DAC input based on the Closed Loop Trim Logic. The "Manual" (or Bypass) configuration mode selects the user defined DAC codes. 54 Platform Manager 2 In-System Programmable Hardware Management Controller The DAC output values vs. configuration settings are shown in Table 18. See the Closed Loop Trim logic section for more details. Table 18. DAC Output Value vs. Configuration Settings Trim Configuration Mode (Platform Designer Software) CLTE_x (ASC –I/F) TRIMx_OE (ASC- I/F) x x 0 Hi-Z Manual x 1 DAC Voltage Profile Trim 0 1 Held at last updated value by Closed Loop Trim Logic. Reset value is 80h. Trim 1 1 Dynamically updated based on measured VMONx voltage and Closed Loop Trim Logic. DAC Output Value VID Selection The ASC can be configured to support VID (Voltage Identification) control using the TRIM block. The control signals and VID tables are created using the Platform Designer software. As shown in Figure 31, the VID mechanism uses the I2C interface to control the VID Setpoint (duplicated as PROFILE 0 Setpoint). The I2C access to the VID Setpoint can be restricted based on the ASC I2C write feature during configuration. Digital Closed Loop Trim Mode Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of the DC-DC converter with the internally stored Voltage Setpoint. The difference between the Voltage Setpoint and the actual DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter output voltage toward the Voltage Setpoint. This operation iterates until the Voltage Setpoint and the DC-DC converter voltage are equal. The closed loop trim hardware then continues monitoring the converter voltage and adjusts the converter output voltage as necessary. Figure 31 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update Rate Control register) the ASC device initiates the closed loop power supply voltage correction cycle through the following blocks • Volatile Voltage Setpoint Register stores the desired output voltage (set by the TRIMx_P0 and TRIMx_P1 ASC-I/ F signals) • On-chip ADC is used to measure the voltage of the DC-DC converter • Three-state comparator is used to compare the measured voltage from the ADC with the Voltage Setpoint Register contents. The output of the three state comparator can be one of the following: – +1 if the setpoint voltage is greater than the DC-DC converter voltage – –1 if the setpoint voltage is less than the DC-DC converter voltage – 0 if the setpoint voltage is equal to the DC-DC converter voltage • Channel polarity control determines the polarity of the error signal (Polarity is set on a per channel basis in configuration memory) • Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage. The contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity and the three-state comparator output. If the three-state comparator output is 0, the closed loop trim register contents are left unchanged. • The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter output voltage. 55 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 31. Digital Closed Loop Trim Operation DAC PROFILE MUX OUTPUT TRIMx UPDATE POLARITY (Configuration Memory) UPDATE RATE CONTROL DAC Register +/-1 MUX Three-State DIGITAL COMPARE (+1/0/-1) TRIMx BYPASS CONTROL (Configuration Memory) CLT Register Setpoint Register PROFILE SETPOINT MUX OUTPUT ASC TRIMx TRIMIN DAC VMONx DC-DC COMVERTER VOUT TRIMx ACTIVE SETPOINT (12C) ADC GND CLT UPDATE RATE* (Configuration Memory) CLTE_X (ASC Interface) * CLT UPDATE RATE parameter is shared between all four TRIM Cells The closed loop trim cycle interval is programmable and is set by the update rate control register. Table 19 lists the programmable update interval that can be selected by the update rate register. The update rate register is set in configuration memory and is shared between all TRIM cells. Table 19. Closed Loop Trim Update Rates CLT Update Rate Settings 860 µs 1.72 ms 13.8 ms 27.6 ms There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3 must be used to monitor its output power supply voltage. The closed loop operation can only be started by asserting the TRIMx_CLTE ASC-I/F signal. TrimCell at Start-up The status of registers and the TrimCell output during start-up or POR of the ASC is as follows. 1. The TRIM DAC output is High-Z. 2. DAC register is based on Trim configuration Mode. Trim Configuration Mode for TRIMx channel (Platform Designer Software) Manual Trim TRIMx DAC register Profile 0 DAC code is copied to the DAC register. Value of 80h (Bipolar-zero) is copied to the DAC register. 3. The Closed Loop Trim Logic is disabled. 4. Profile 0 Setpoint is copied to the Voltage Setpoint Register. The DAC output mode can be enabled (TRIMx_OE) at any time by the user logic, depending on the application requirements. Normally the chosen profile (TRIMx_P0, TRIMx_P1) setpoint should be loaded and the DAC output enabled when the application is ready for trimming. If closed loop trimming is to be used, the user logic should enable the closed loop trim (TRIMx_CLTE) after the DAC output and trim profile have already been configured. 56 Platform Manager 2 In-System Programmable Hardware Management Controller Details of the Digital to Analog Converter (DAC) Each trim cell has an 8-bit bipolar DAC to set the trimming voltage as shown in Figure 32. The full-scale output voltage of the DAC is +/– 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value. The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied to the trim output buffer. The offset voltage is typically selected to be approximately equal to the DC-DC converter open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range. The programmed offset value can be set to 0.6 V, 0.8 V, 1.0 V or 1.25 V. This value selection is stored in configuration memory. The configuration memory is loaded with the value set in EEPROM memory at power-on. It can be updated during runtime via I2C commands. The combined offset and DAC output is applied to the TRIM cell output buffer. Each output buffer is controlled by a unique TRIMx_OE signal via the ASC-I/F. When TRIMx_OE = 0, the corresponding TRIMx Pad will be placed in a high impedance state. Setting TRIMx_OE = 1 will enable the output buffer, resulting in the combined offset and DAC output being applied to the TRIM output pin. The default state at power-on reset is TRIMx_OE = 0. The TRIM cell will maintain this setting until the ASC-I/F communication is successfully established. This ensures that the TRIM function will remain in a passive, high impedance state, until it is enabled the user control logic. Figure 32. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage TRIM Cell TRIMx Setpoint Register 8 DAC 7 bits + Sign (-320 mV to +320 mV) TRIMx Pad Offset (0.6 V, 0.8 V, 1.0 V, 1.25 V) Configuration Memory 57 TRIMx_OE (from ASC-I/F) Platform Manager 2 In-System Programmable Hardware Management Controller Fault Logging and User Tag Memory The ASC contains the following storage space used with Fault Logging or User Tag operation: • Non-volatile EEPROM memory array which has 16 rows where each row stores 7 bytes of data. • A volatile memory register which stores 7 bytes of data. The ASC can be configured to choose this memory, either for User Tag Operation or Fault Log Operation through Platform Designer Software. Figure 33 shows the interface to the EEPROM memory and Volatile register for data access. Figure 33. Access to EEPROM and Volatile Memory for Fault Logging/User Tag Operation Fault Log Mode (I2C Read/Erase/Enable) Volatile Register 1 X 7 Bytes User Tag Mode (I2C Read/Write/Erase) Fault Log Mode ASC(I/F) • Fault Record Data • Fault Trigger • Fault Log Full • Fault Log in Progress EEPROM 16 X 7 Bytes User Tag Memory When the ASC is configured for User Tag Mode, the memory block can be used as a scratch pad memory for critical data, board serialization, board revision logs, programmed pattern identification or as general data storage in EEPROM. As shown in Figure 33, in the User Tag Mode, data can be read, written or erased from the EEPROM or Volatile Register via the I2C interface of the ASC. For more details, please refer to the User Tag Memory Access section of the datasheet. Fault Log Memory When the ASC is configured for Fault Log Mode, the memory block is used to record the status of the ASC GPIOs, VMON, IMON, TMON and other significant logic signals on the occurrence of the user defined fault trigger condition. The ASC can also be used with Platform Manager 2 or MachXO2 devices to log faults to User Flash Memory (UFM) or external SPI flash. See TN1277, Fault Logging Using Platform Manager 2 for more details. Each fault record has seven bytes, six bytes of ASC specific data and one byte of user specified FPGA signals. The ASC Fault Log Record Memory Map is shown in Table 20. Erased fault records and fault records which have not yet been written will read all zeros. 58 Platform Manager 2 In-System Programmable Hardware Management Controller Table 20. Fault Log Record Memory Map Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 User bit7 User bit6 User bit5 User bit4 User bit3 User bit2 User bit1 User bit0 1 AGOOD GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 2 GPIO3 GPIO2 GPIO1 HVOUT4 HVOUT3 HVOUT2 HVOUT1 IMON1B 3 IMON1A HIMONB HIMONA HVMONB HVMONA VMON9B VMON9A VMON8B 4 VMON8A VMON7B VMON7A VMON6B VMON6A VMON5B VMON5A VMON4B 5 VMON4A VMON3B VMON3A VMON2B VMON2A VMON1B VMON1A TMON2B 6 TMON2A TMON1B TMON1A TMONINB TMONINA 1 0 1 The ASC can be configured to store fault log data either in the EEPROM array or the Volatile register. The EEPROM memory array can store up to 16 fault log records. When the fault log memory is full no further fault log records can be stored in the EEPROM and any future trigger signals will be ignored. The volatile register can also be used to store faults. The volatile fault log contains only one record of 7 bytes and each time the trigger signal is asserted the current data will be stored in the register overwriting any previous data. In order to preserve the volatile register fault log data it must be read back prior to the next assertion of the trigger signal. The following control signals for ASC based Fault Logging are defined in the Platform Designer software for use in the FPGA logic: • Fault_Log_Trigger: This user defined signal is used to initiate fault log recording. Recording is initiated by toggling the fault log trigger signal high based on the FPGA logic. The Fault log trigger signal should be set high for a minimum period (see Recommended Operating Conditions1 section). The fault log trigger signal initiates fault log recording for all ASCs in the system. Readback must be disabled for the fault log recording to begin. • ASCx_Fault_Log_Full: This ASC-I/F signal reports to the user logic when the EEPROM for the given ASC is full. • ASCx_Fault_Log_In_Progress: This ASC-I/F signal reports to the user logic when a fault log operation for the given ASC is in progress. When the ASC is configured for Fault Log Operation, the Fault Record Data frame, as shown in Table 20, is captured every 16 us. When the fault log trigger signal is asserted, the captured data is stored in the selected memory. This includes the user bits in the fault record. These user bits are not used for any other ASC functions. The read-back function of the Fault Log must be enabled in order to read or erase the Fault Log. The read-back is enabled using the I2C interface. As shown in Figure 33, the Fault Log contents can be read or erased from the EEPROM or the volatile register via the I2C interface of the ASC. When the user enables the read-back of the fault log contents, the fault log recording is disabled and must be reenabled by the user after the read-back is completed in order to store future fault log events. For more information about reading, erasing and enabling the fault log recording refer to the Fault Log Memory Access section. 59 Platform Manager 2 In-System Programmable Hardware Management Controller FPGA Architecture Overview The Platform Manager 2 family architecture is based on the MachXO2 family architecture. This architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The Platform Manager 2 also includes blocks of sysMEM Embedded Block RAM (EBRs). Figure 34 shows the block diagram of the LPTM21 FPGA section. Figure 34. LPTM21 FPGA Section Block Diagram Embedded Function Block (EFB) User Flash Memory (UFM) sysCLOCK PLL sysMEM Embedded Block RAM (EBR) On-chip Configuration Flash Memory Programmable Function Units with Distributed RAM (PFUs) PIOs Arranged into sysIO Banks The Programmable Functional Unit (PFU) logic blocks, and sysMEM EBR blocks are arranged in a two-dimensional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in four sysIO banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The PFU, EBR, and PIO blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocate these routing resources. The LPTM21 provides one sysCLOCK Phase Locked Loop (PLL). The PLL has multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. The Platform Manager 2 devices provide commonly used hardened functions such as SPI controller, I2C controller, timer/counter, and User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I2C and JTAG ports. The Platform Manager 2 family devices have a JTAG port that supports programming and configuration of the device as well as access to the user logic. The Platform Manager 2 operates on a 3.3 V power supply. The Platform Manager 2 contains an on-chip DC-DC Buck converter which, when combined with external components, allows the device and additional ASC hardware management expanders to be supplied directly from a higher supply voltage such as 12 V. See the DC-DC Converter section for more details. The device can also be powered directly by 3.3 V, bypassing the DC-DC converter. 60 Platform Manager 2 In-System Programmable Hardware Management Controller PFU Blocks The Platform Manager 2 uses a Lookup Table (LUT) architecture. The core of the Platform Manager 2 consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM, and distributed ROM functions. Each PFU consists of four interconnected slices and each slice contains two LUTs and 2 registers. The LUTs in each slice can be configured as 4-input combinatorial lookup tables and can be used to implement 4-input logic functions. Larger input functions are implemented by combining LUTs together. The slices can also be configured to operate as Distributed RAM or ROM memory if desired. The Diamond software design tool will automatically place the logic functions for the design and route the connections required between the PFUs and to other resources. See DS1035, MachXO2 Family Data Sheet for more details on the PFU Blocks. Clock Resources There are eight dedicated primary clock routing lines available in the Platform Manager 2 architecture which allows the software to route the clocks in the most efficient manner. The input clock signals should be connected to the primary clock input pins (PCLK) for the most efficient use of the primary clock resources. There are six PCLK input pins available for user logic in the Platform Manager 2 and a seventh PCLK pin is reserved for system use by the ASCCLK signal (An eighth PCLK pin is used by the primary I2C port). When using a single-ended clock input only the true clock pin (PCLKT) can directly drive the primary clock lines. The primary clock lines can also be driven by internal resources such as the PFU connections for added flexibility. The eight primary clock lines in the primary clock network can drive throughout the entire device to provide clocks for all the resources within the device. For the most efficient designs, the clock signals that are used by the largest number of resources (LUTs, EBRs, or I/O cells) should utilize the primary clock routing resources. Each of the primary clock routing lines has a Dynamic Clock enable feature which can be utilized if desired. In addition, two of the eight primary clock lines have dynamic clock switches to allow switching between two different clock sources. Any of the primary clock input pins can drive any of the eight primary clock lines so the user does not have to be concerned about which clock pin to use in order to use the dynamic clock switches. There are also eight secondary high fan-out routing lines available for signals which go to many PFUs such as local resets or clock enables. These secondary routing lines can be driven by internal logic or from a PCLK pin. There is one programmable Phase Locked Loop, sysCLOCK PLL, available in the LPTM21 device which can be used to generate higher or lower clock frequencies for the design if desired. The PLL can be driven by the system clock input, from an external PLL clock input pin, or from internal routing. The PLL has 4 outputs available and each has its own output divider, thus allowing the PLL to generate different frequencies for each output. The outputs can be used to drive the clock distribution network, other internal routing resources, or external output pins. The PLL provides a wide range of configurable features - for more information see TN1199, MachXO2 sysClock PLL Design and Usage Guide. There is one programmable internal Oscillator available in the Platform Manager 2 FPGA section which can be used to generate a clock source for internal logic or other uses. The internal oscillator frequency ranges from 2.08 MHz up to 133 MHz. sysIO Resources The FPGA section of Platform Manager 2 has four I/O banks. The I/O buffers in each bank can support singleended and differential I/O standards. The VCCIO voltage for each I/O bank can be independent to allow the designer to use different I/O standards in different banks if desired. Multiple input standards can be supported in a bank as shown in Table 21. The output standards used in each bank must match the bank VCCIO voltages shown in Table 22. The I/O resources in each bank are arranged in groups called a Programmable I/O Cell (PIC) block. Each PIC block has four programmable I/Os, grouped into two pairs. Each pair can form a pair of complementary output drivers. One pair is labeled as the A and B pins while the other is labeled as the C and D pins. The pins within the pair are also designated as a True and a Complementary pin for use with the differential I/O standards. In some cases not all the pins within a PIC are available as package pins. 61 Platform Manager 2 In-System Programmable Hardware Management Controller The I/O buffers support individually configurable drive strength and bus maintenance (weak pull-up, weak pulldown, or bus keeper) circuits for most standards. See TN1202, MachXO2 sysIO Usage Guide for more detailed information about the use of the I/O resources in the FPGA sections. Table 21. Supported Input Standards VCCIO (typical) Input Standard 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V LVTTL Y Y2 Y2 Y2 LVCMOS33 Y Y2 Y2 Y2 LVCMOS25 2 Y Y 2 Y Y2 LVCMOS18 Y2 Y2 Y Y2 LVCMOS15 2 Y 2 Y 2 Y Y Y2 LVCMOS12 Y2 Y2 Y2 Y2 Y Single-Ended Interfaces PCI 1 Y SSTL25 (Class I, Class II) Y SSTL18 (Class I, Class II) Y HSTL18 (Class I, Class II) Y Differential Interfaces LVDS Y Y BLVDS, MLVDS, LVPECL, RSDS Y Y Differential SSTL25 Class I, II Y Differential SSTL18 Class I, II Y Differential HSTL18 Class I, II Y 1. Bank 2 of LPTM21 only. 2. Reduced functionality. Refer to TN1202, MachXO2 sysIO Usage Guide for more details. 62 Platform Manager 2 In-System Programmable Hardware Management Controller Table 22. Supported Output Standards Output Standard VCCIO (Typical) Single-Ended Interfaces LVTTL 3.3 LVCMOS33 3.3 LVCMOS25 2.5 LVCMOS18 1.8 LVCMOS15 1.5 LVCMOS12 1.2 LVCMOS33, Open Drain LVCMOS12, Open Drain — — — — — PCI33 3.3 SSTL25 (Class I) 2.5 LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain SSTL18 (Class I) 1.8 HSTL18 (Class I) 1.8 Differential Interfaces LVDS1, 2 2.5, 3.3 2 BLVDS, MLVDS, RSDS 2.5 LVPECL2 3.3 Differential SSTL25 2.5 Differential SSTL18 1.8 Differential HSTL18 1.8 1. LPTM21 device has dedicated LVDS output buffers in bank 0 only. 2. These interfaces can be emulated with external resistors in all banks of LPTM21. sysMEM Embedded Block RAM Memory (EBR) The Platform Manager 2 contains sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-Kbit RAM with dedicated input and output registers. These EBRs can implement single port, dual port, or First-In First-Out (FIFO) memories in a variety of depths and widths. Larger and deeper blocks of RAM can be created by cascading the EBRs together. Typically the Lattice design software will cascade memory transparently based upon the specific design inputs. If desired, the contents of the EBR RAM can be pre-loaded during device configuration. The EBR can also be used as ROM if required. The FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize the LUT usage. For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2 Devices. 63 Platform Manager 2 In-System Programmable Hardware Management Controller Embedded Hardened IP Functions and User Flash Memory The Platform Manager 2 provides embedded hardened functions such as SPI, I2C, Timer/Counter and User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 35. Figure 35. Embedded Blocks Interface Core Logic / Routing Configuration Power Logic Control EFB text I 2C (Primary) I/ Os for I 2 C (Primary) I 2C (Secondary) I/ Os for I 2 C (Secondary) WISHBONE SPI Interface SPI Timer /Counter PLL UFM The Platform Manager 2 contains two I2C IP cores, the primary and secondary I2C IP cores. Each core can be configured either as an I2C master or as an I2C slave. The main difference between the two IP cores is that the primary core has pre-assigned I/O pin whereas users can assign I/O pins for the secondary core. The hardened SPI core can be configured as either a SPI master or slave. The Timer/Counter is a general purpose, bi-directional, 16-bit timer/counter module with independent output compare units and PWM support. For details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices. User Flash Memory (UFM) The Platform Manager 2 provides a User Flash Memory block (UFM) which contains up to 64 Kbits of non-volatile memory. The UFM can be used for a variety of applications including storing the time stamped fault log, storing EBR initialization data, or as general purpose user flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. The UFM can also be accessed through the JTAG, SPI, and the primary I2C ports of the device. For more information on the UFM, please refer to TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices. 64 Platform Manager 2 In-System Programmable Hardware Management Controller System Resources Usage The Platform Manager 2 can be configured for different functions as required by the customer’s requirements. The Lattice Diamond software and Platform Designer tool provide a flexible interface to configure the hardware management functions of the device. The device configuration that is produced by the software will automatically assign certain device resources. As a result, certain resources in the device may not be available for general use. The following resources may be fully or partially assigned depending on the selected functions in the design software. • EBRs • Timer / Counter • Primary I2C • PLL • SPI • UFM For more details on the programmable logic architecture, see DS1035, MachXO2 Family Data Sheet. 65 Platform Manager 2 In-System Programmable Hardware Management Controller System Connections The Platform Manager 2 is a fast-reacting, programmable logic based hardware management controller. The Platform Manager 2 can be paired with the L-ASC10 (ASC) hardware management expander to expand the number of resources available to the hardware management system. In order for the Platform Manager 2 to function properly as a hardware management controller, there are a number of mandatory system connections. The overall set of required connections between the Platform Manager 2 and ASC hardware expanders are shown in Figure 36 below. The required connections include Clock, Reset, ASC Interface (ASC-I/F) and I2C. These connections are assigned and managed using Diamond software and the Platform Designer tool. Each of the connection requirements is described below. Figure 36. System Connections - ASC and Platform Manager 2 ASC2 +3.3 V VCC VCCIO _0 VCCIO _1 VCCA ASCCLK WRCLK WDAT RDAT PIOx1 PIOx2 PIOx3 +3.3 V RESETb PIOx4 VCCA (+3.3 V) (Optional ASC) I2C_ADDR LPTM21 GND ASC1 ASCCLK WRCLK WDAT RDAT PIOx 5 PIOx 6 PIOx 7 PIOx 8 ASC Section (ASC0) RESETb VCCA ASCCLK 4.4 k SCL SDA SCL _M SDA_M +3.3 V VCCA RESETb (Mandatory ASC) I2C_ADDR SCL _S* SDA _S* SCL SDA 2.2 k GND Note: Hardware connections may require additional passive components not shown, see TN1225, Platform Manager 2 Hardware Checklist for more details. Clock requirements The ASC has an internal 8 MHz clock source which is used by the device during startup. Once startup has successfully completed, the ASC will switch to the ASC-I/F system clock signal (WRCLK) for operation. The Platform Manager 2 provides the WRCLK signal for each ASC in the system. This ensures that the system is fully synchronized to a common clock source to minimize any differences in timing. The ASC has a built-in detection circuit for WRCLK loss. If a loss of WRCLK is detected, the ASC will reset itself and pull RESETb low. The device I/O will return to safe state, as described in the Safe State section. The ASC clock signal connected internally in the Platform Manager 2 device (see Figure 36), making the ASCCLK pin a no-connect in Platform Manager 2 systems. All ASC devices (both optional and mandatory) in the system will disable their ASCCLK output signal and this pin should be treated as a no connect. An external 8 MHz clock source can be used as the system clock instead of the ASCCLK. In this case, the ASCCLK output will be disabled and the external clock should be connected to the ASCCLK pin on Platform Manager 2. The user must specify that an external clock source is being used in software. 66 Platform Manager 2 In-System Programmable Hardware Management Controller RESET requirements The ASC RESETb pin is used for synchronizing the ASC section with the Platform Manager 2 FPGA section and other ASC hardware management expanders. The RESETb pin should not be driven by any external device as this will adversely affect the system operation. A software reset signal for the internal logic can be created using a PIO pin on the Platform Manager 2. The ASC section RESETb must be externally connected to a PIO signal from the FPGA section of Platform Manager 2. This PIO must be assigned as the ASC0_RSTN signal in the design software. External ASCs used in a system can be designated as either Mandatory or Optional. The Mandatory or Optional designation determines how the RESETb pins must be connected and how the system will treat the Reset signal from each ASC. The Mandatory or Optional designation must be specified in the design software. A Mandatory ASC is required to be present at system start-up. The RESETb pins for all mandatory ASCs must be connected to the RESETb pin on the Platform Manager 2 (as shown in Figure 36). The internal ASC section of Platform Manager 2 is always designated as ASC0 and is always mandatory. If any one of the mandatory ASCs cannot be detected by the hardware management controller, the system will be held in reset. Any of the mandatory ASCs which experience a critical issue (such as loss of WRCLK signal) will hold the Reset signal low, keeping the system in reset. An Optional ASC is not required to be present at system start-up. This designation can be used for ASCs placed on plug in modules or optional boards in a system. The RESETb pin of each optional ASC should be connected to a unique PIO pin on the Platform Manager 2. Each reset signal is treated individually, so that only the registers associated with a particular Optional ASC will reset when the reset input is driven low. The rest of the system, both Mandatory and other Optional ASCs, will continue to operate normally without interruption. ASC Interface and I2C Connections The ASC uses two communication links to transfer information between the ASC and the Platform Manager 2. These are the ASC Interface (ASC-I/F) and I2C bus. These two links are used for different types of information and both must be connected properly for the system to operate correctly. The ASC-I/F bus uses three signals: WRCLK, WDAT, and RDAT. The ASC-I/F bus operates at 8 MHz and includes error checking and reporting capabilities. The ASC and FPGA sections of Platform Manager 2 have an internal ASC-I/F connection which is automatically setup by the design software. The ASC-I/F pins on external ASC devices must be connected to three PIO pins on the Platform Manager 2. These three PIO pins are assigned in the design software. The design software will automatically instantiate the interface for communicating with the ASC devices. Each ASC device requires its own unique ASC-I/F link, as shown in Figure 36. The VCCA, VCC, VCCIO-0, and VCCIO-1 pins should be connected together. Care should be taken that Bank 1 (the bank used for the internal connection of the FPGA and ASC sections) is not exposed to significant SSO noise, as this can degrade the performance of the analog monitors. See TN1225, Platform Manager 2 Hardware Checklist for more details. The I2C bus uses the SDA and SCL pins and operates at 100 to 400 kHz. The user must connect the SDA and SCL pins on the ASC to the SDA_M/SCL_M pins on the Platform Manager 2 (as shown in Figure 36). The Platform Manager 2 also requires connections between the SDA_M/SCL_M and the SDA_S/SCL_S pins. Table 23 details the I2C_ADDR pin connections based how many hardware expanders are included in the system. External pull-up resistors to VCCA are required in all configurations. See the I2C Interface section for full details. 67 Platform Manager 2 In-System Programmable Hardware Management Controller Table 23. Raddr Value vs. ASC Device Number Raddr Value 3 LSB of I2C Slave Address ASC Device Number None (On-Chip) 000 0 2.2 kΩ 001 1 4.4 kΩ 010 2 7 kΩ 011 3 10 kΩ 100 4 14 kΩ 101 5 18 kΩ 110 6 None (Tie to VCCA) 111 7 DC-DC Converter Platform Manager 2 provides the control circuitry to implement a DC-DC converter. The converter steps an input voltage (from 4.5 V to 13.2 V) down to 3.3 V. The 3.3 V output of the converter is used to source the VCC/VCCA rails of the Platform Manager 2 IC and any additional ASC Hardware Management Expanders in the system. It should not be used to provide 3.3 V for additional external components. The DC-DC is a Buck Converter which should be operated only in the recommended configuration. The converter uses the VDC, HDRV, and VCCA pins that work with external components to generate the 3.3 V supply. Figure 37 shows the recommended configuration of the DC-DC converter. The VDC pin is connected to the input voltage of the system. The input voltage is also connected to the drain side of an N-Channel MOSFET (Q1) in this configuration. The HDRV pin outputs a PWM signal which is used to step down the input voltage. In the recommended configuration, the HDRV output is passed to a FET Driver IC (U1). This driver boosts the HDRV output to switch the Q1 gate. The recommended configuration uses a schottky diode (D1) to perform the rectification required by the DC-DC converter. The output of the converter is passed to the VCCA pin of Platform Manager 2. VCCA provides power for the ASC section of Platform Manager 2 and is used as feedback for the DC-DC converter. The buck converter architecture requires an inductor / capacitor pair at the output voltage, to maintain stable current and voltage delivery. For recommendations on the size and type of these components, as well as part number recommendations for U1, Q1, and D1, see the For Further Information section of the data sheet. Figure 37. DC-DC Converter - Recommended Configuration Input Voltage (4.75 V to 13.2 V) ASC1 ASC2 VCCA VCCA VDC 3.3 V To all Platform Manager 2 VCC/VCCA U1* Q1 HDRV FET Driver L1 D1 C1 * U1 may an integrated FET driver or a discrete circuit, see For Further Information. The converter can also be bypassed in applications where a 3.3 V source is already available. In these cases, the VDC, and HDRV pins can all be left open. The 3.3 V source should be supplied directly to the VCC/VCCA pins of the device. 68 Platform Manager 2 In-System Programmable Hardware Management Controller I2C Interface I2C is a low-speed serial interface protocol designed to enable communications among a number of devices on a circuit board. The ASC section of Platform Manager 2 supports the I2C communications protocol 7-bit addressing. The I2C interface of the ASC section is used for programming by the Platform Manager 2 or other system processor. The interface is also used for accessing measurement and control functions and fault log memory on the device. Figure 38 shows a typical I2C configuration, in which the Platform Manager 2 I2C master and slave ports are connected together. Additional ASC hardware management expanders may be slaved to a Platform Manager 2 Hardware Management Controller as shown. SDA is used to carry data signals, while SCL provides a synchronous clock signal. The 7-bit address of the ASC is formed by the 4 most significant bits which are programmable in EEPROM, while the bottom 3 bits of the address fixed to zero. Figure 38. Platform Manager 2 Device on an I2C Bus V+ SDA (DATA) SCL (CLOCK) SDA_M SCL_M SDA_S SCL_S To Other I2 C Devices USER SDA* SDA USER SCL* SCL ASC1 (I2C SLAVE) Platform Manager 2 (I2C MASTER/SLAVE) SDA SCL ASC2 (I2C SLAVE) * - Adding a USER_SDA and USER_SCL is application dependent and not required for all systems. This port is for accessing FPGA logic resources over I2C. In the I2C protocol, the bus is controlled by a single MASTER device at any given time. This master device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ASC section of the Platform Manager 2 is designed as an I2C slave. In a multiple ASC system configuration, all ASCs share the same I2C bus. This shared I2C bus is used by the Platform Manager 2 master to program the ASC devices. Each slave device is assigned a unique address. Any 7-bit address can be assigned to the ASC section, however one should note that several addresses are reserved by the I2C standard and should not be assigned to the ASC to ensure bus compatibility. These are shown in Table 24. Table 24. I2C Reserved Slave Device Addresses I2C Function Description Address R/W bit 0000 000 0 General Call Address 0000 000 1 Start Byte 0000 001 X CBUS Address 0000 010 X Reserved 0000 011 X Reserved 0000 1xx X HS-mode master code 1111 0xx 1 10-bit addressing 1111 1xx X Device ID 69 Platform Manager 2 In-System Programmable Hardware Management Controller The ASC supports a dedicated 8-bit instruction set. These instructions are divided as follows among device programming instructions, measurement and control access, and fault log/user tag memory access. The ASC also supports configuration memory protection. The ASC’s I2C interface allows data to be both written to and read from the device. A data write transaction, as shown in Figure 39, consists of the following operations: 1. Start the bus transaction 2. Transmit the slave address (7 bits) along with a low write bit 3. Transmit the instruction code as described in Table 25 (8 bits) 4. Transmit the first data byte to be written (8 bits). Note some instructions do not include data bytes, while others support multiple data bytes. For information on which instructions support multiple data bytes, see individual instruction details 5. Stop the bus transaction To start the transaction, the master device holds the SCL line high while pulling SDA low. Address, instruction code and data bits are then transferred on each successive SCL pulse, in consecutive byte frames of 9 SCL pulses. Data is transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. The first frame contains the 7-bit slave address, with bit 8 held low to indicate a write operation. The second frame contains the instruction code indicating the type of data to be written. The remaining frames contain the actual data to be written. The number of allowed or required data frames is determined by the instruction code used and is described in the Instruction Codes section. Figure 39. I2C Write Operation SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA A6 A5 A4 A3 A2 A1 A0 R/W ACK C7 C6 C5 C4 C3 C2 C1 C0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START DEVICE ADDRESS (7 BITS) INSTRUCTION CODE (8 BITS) DATA BYTE (8 BITS) OPTIONAL ADDITIONAL DATA BYTES STOP Note: Shaded Bits Asserted by Slave See Individual Instruction Descriptions for Data Byte Details Reading a data byte from the ASC requires two separate bus transactions, as shown in Figure 40. The first transaction writes the device address with write bit, and then the instruction code indicating the type of data to be read. This transaction typically ends after the second frame since no data is being written to the slave. However, some instruction codes include additional frames, such as address information for the type of data to be read. See the Instruction Codes section for more information about the number of allowed or required data frames. No stop condition is issued at the end of the first step, to ensure that the full read operation is completed properly. The second transaction performs the actual read, beginning with the issuing of a repeated start condition. A repeated start is a start condition issued by the master which does not follow a stop condition. This prevents the bus from being released by the master. The first frame contains the 7-bit slave address with the R/W bit held high. In the second frame, the ASC asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ASC. Depending on the instruction code, the ASC may assert additional data bytes in response to additional SCL frames depending on the instruction as detailed in the Instruction Codes section. The master completes the transaction by issuing a stop condition. 70 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 40. I2C Read Operation STEP 1: WRITE INSTRUCTION CODE FOR READ OPERATION SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SDA A6 A5 A4 A3 A2 A1 A0 R/W ACK C7 C6 C5 C4 C3 C2 C1 C0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK START SLAVE ADDRESS (7 BITS) OPTIONAL: ADDRESS BYTE (8 BITS) INSTRUCTION CODE (8 BITS) STEP 2: READ DATA FROM THAT REGISTER SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 SDA A6 A5 A4 A3 A2 A1 A0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 REPEATED START SLAVE ADDRESS (7 BITS) 9 ACK* DATA BYTE (8 BITS) Note: Shaded Bits Asserted by Slave See Individual Instruction Descriptions for Data and Address Byte Details * After final data byte read, master should NACK before issuing the STOP command. 71 OPTIONAL ADDITIONAL DATA BYTES STOP NO STOP ISSUED Platform Manager 2 In-System Programmable Hardware Management Controller Instruction Codes The ASC device supports a set of 8-bit instruction codes. These instructions are used to access EEPROM programming functions, shadow register programming functions, measurement and control functions, and User Tag or Fault Log memories. The instruction space is shown in Table 25. Each set of instructions is described in more detail in the following sections. Do not read or write to instruction codes marked reserved. Table 25. I2C Instruction Summary Instruction Code 0x01 Instruction Name 0x02 READ_ID 0x03 READ_STATUS 0x04 ENABLE_PROG 0x05 ENABLE_USER 0x06-0x24 0x25 0x26-0x30 0x31 RESERVED WRITE_CFG_REG_wMASK 0x34 READ_ALL_CFG_REG 0x35 LOAD_CFG_REG TRIM1_CLT_P0_SET 0x42 TRIM2_CLT_P0_SET 0x43 TRIM3_CLT_P0_SET 0x44 TRIM4_CLT_P0_SET N/A Closed Loop Trim Setpoint Access RESERVED 0x51 WRITE_MEAS_CTRL 0x52 READ_MEAS_CTRL N/A Measurement and Control Register Access RESERVED N/A ERASE_USER_TAG_EEPROM 0x62 WRITE_USER_TAG_REG 0x63 READ_USER_TAG_REG 0x64 PROG_USER_TAG_EEPROM 0x65 READ_USER_TAG_EEPROM 0x66-0x70 N/A ASC Configuration Memory Access RESERVED 0x41 0x61 N/A ASC Configuration Memory Access WRITE_CFG_REG READ_CFG_REG 0x53-0x60 Device Status and Mode Management RESERVED 0x32 0x45-0x50 N/A READ_CFG_EEPROM 0x33 0x36-0x40 Instruction Group RESERVED User Tag Memory Access RESERVED 0x71 ERASE_FAULT_EEPROM N/A Fault Log Memory Access 0x72 RESERVED 0x73 READ_FAULT_VOLATILE_REG 0x74 READ_FAULT_ENABLE 0x75 READ_FAULT_RECORD_EEPROM 0x76 READ_ALL_FAULT_EEPROM 0x77-0xFF N/A Fault Log Memory Access RESERVED N/A 72 Platform Manager 2 In-System Programmable Hardware Management Controller Each instruction is described in detail in the following sections. The description includes information about the individual instruction code, the instruction format and any associated write or read addresses or data. The instruction format uses the following notation: I2C Instruction Format Key (See Figure 40 for details of each condition or bit): • S – Start Condition • A[6:0] – Slave Address • W – Write Bit (Logic 0) • A – Acknowledge Bit • NA – Not Acknowledge Bit • Sr – Repeated Start Condition • R – Read Bit (Logic 1) • P – Stop Bit • Shaded Bits (A) – Bits asserted by the slave Device Status and Mode Management There are several miscellaneous registers from the programming flow which are useful or required for completing separate operations (such as entering the programming mode to enable the User Tag memory access). These are shown in Table 26. Table 26. Device Status and Mode Management Instruction Codes Instruction Code Instruction Name Read/Write Description 0x01 RESERVED N/A 0x02 READ_ID R Read the device ID Code 0x03 READ_STATUS R Read the ASC Status Register 0x04 ENABLE_PROG W Enable the programming mode (correct two byte key required) 0x05 ENABLE_USER W Enable the device user mode The READ_ID instruction is used to verify that the slave device is an ASC or the ASC section of Platform Manager 2. The device IDCODES are shown in Table 27. The format for the READ_ID instruction is shown in Figure 41. Figure 41. READ_ID Instruction Format SLAVE ADDRESS S A[6:0] SLAVE ADDRESS INSTRUCTION CODE W A 0x02 A Sr A[6:0] DEVICE ID R A ID[7:0] NA P Table 27. ASC ID Codes Device ID Code ASC Hardware Management Expander 0x88 ASC Section of LPTM21 0x8A The READ_STATUS instruction provides readout access to the two byte status register of the ASC. The READ_STATUS instruction provides information about the status of the ASC fault log memory, the current chip mode (Programming Mode or User Mode), and the status of the DONE bit of the I2C address resolution and the configuration memory. The READ_STATUS instruction format is shown in Figure 42. The ASC_Status_Register bit mapping is shown in Figure 43. 73 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 42. READ_STATUS - I2C Instruction Format SLAVE ADDRESS S A[6:0] W A 0x03 A Sr A[6:0] ASC_STATUS REGISTER_LO ASC_STATUS REGISTER_HI SLAVE ADDRESS INSTRUCTION CODE R A R[15:8] A R[7:0] NA P Figure 43. ASC_Status Register ASC_STATUS_REGISTER_LO (Read) DUALBOOT_CRC _ERROR CFGARRAY_ DONE I2CSA_DONE PROG_MODE RESERVED CFG_SHADOW_ REG_REFRESH RESERVED ERASE b7 b6 b5 b4 b3 b2 b1 b0 ASC_STATUS_REGISTER_HI (Read) PROGRAM FAULT_UT_ ERASE FAULT_PROG FAULT_LOG_ FULL FAULT_CNT[3] FAULT_CNT[2] FAULT_CNT[1] FAULT_CNT[0] b15 b14 b13 b12 b11 b10 b9 b8 The individual status bits are described below: • DUALBOOT_CRC_ERROR – Reset to logic 0 at power up and at the beginning of a dual-boot configuration write I2C instruction. Logic 1 when a CRC error is encountered during dual-boot configuration. • CFGARRAY_DONE – Logic 1 if the configuration memory done bit has been programmed (set to 1 at the proper completion of an EEPROM programming operation) • I2CSA_DONE – Logic 1 if the chip I2C slave address I2CSADone has been programmed (set to 1 at the proper completion of an EEPROM programming operation) • PROG_MODE – Logic 1 if the chip is in programming mode, Logic 0 if the chip is in user mode • RESERVED • CFG_SHADOW_REG_REFRESH –Set to Logic 1 if Configuration EEPROM data was copied into corresponding shadow registers just after a Reset or after the shadow register refresh I2C instruction is given. This bit is cleared just after the status register is read out. • ERASE – Logic 1 if any EEPROM Erase operation is in progress • PROGRAM – Logic 1 if any EEPROM Program operation is in progress • FAULT_UT_ERASE – Logic 1 if the ASC Fault Log or User Tag memory is currently being erased • FAULT_PROG – Logic 1 if the ASC Fault Log data is being programmed into Fault Log EEPROM array • FAULT_LOG_FULL – Logic 1 if all rows of the ASC Fault Log EEPROM have been programmed • FAULT_CNT [3:0] – 4-bit value that is equal to the last row of ASC Fault Log EEPROM that has been programmed with fault log data. Row 0 up to Row FAULT_CNT have been programmed with Fault Log Data. 74 Platform Manager 2 In-System Programmable Hardware Management Controller The ENABLE_PROG instruction places the ASC into the programming mode. The instruction requires that a specific key code is written along with it in order to ensure that the programming mode is not entered unintentionally. The ENABLE_PROG instruction should only be used by the Lattice delivered programming algorithms or to write or erase the User Tag memory. The ASC_PROG_KEY is a two byte value of 0xE53D. The ENABLE_PROG instruction format is shown in Figure 44. Figure 44. ENABLE_PROG - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x04 PROG_KEY LOW A 0x3D PROG_KEY HIGH A 0xE5 A P After completing a user tag operation, it is important to exit the programming mode and return to user mode. This will prevent unintentional programming operations. The ENABLE_USER instruction will return the ASC to the user mode. The ENABLE_USER instruction format is shown in Figure 45. Figure 45. ENABLE_USER - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x05 A P ASC Configuration Memory Access The I2C interface is used for programming the ASC device. The ASC device includes an EEPROM configuration memory which stores the device configuration in non-volatile memory. The ASC device also includes a set of shadow registers, which are used during runtime by the device to determine operational thresholds, output controls, etc. At power-on reset, the device automatically copies the EEPROM configuration memory to the shadow registers, provided the EEPROM done bit is set in the ASC Status Register. The EEPROM configuration settings are automatically generated by the Platform Designer software tool. The I2C interface unit provides access to both the non-volatile EEPROM memory and the configuration shadow registers for erase, programming, and verify operations. The EEPROM memory is background programmed. It can be copied to the configuration shadow registers at the end of programming by an additional I2C instruction. The EEPROM configuration memory map is automatically generated by the Platform Designer software. The flow and usage of the EEPROM instructions is handled by the Lattice Diamond Programmer software (for PC-based programming) or the Lattice deployment tool (for programming the device via a tester or an on-board microcontroller using the I2C embedded solution). Lattice recommends using these software tools to access the EEPROM configuration programming instruction space. The I2C interface can also be used to re-configure the shadow registers directly. These instructions provide access to individual voltage monitor thresholds, temperature measurement settings, and other device configuration parameters. Some configuration shadow registers are implemented as master/slave pairs. These shadow registers do not update operational parameters immediately after I2C configuration writes to the master shadow register. They support an additional load instruction which updates all slave shadow registers from the master shadow registers at the same time. Other shadow registers are implemented as a single master-only register. These registers update their operation (or reset the associated circuit) immediately after an I2C configuration write. The configuration memory architecture is shown in Figure 46. The ASC Configuration Registers section details which registers support the additional load instruction. The configuration registers can be accessed in user mode, although overwriting the registers can be protected through additional device settings. The configuration register access instructions are shown in Table 28. 75 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 46. Configuration Memory Architecture To TRIM Circuits To VMON Circuits I2C_LOAD_ CFG_REG Configuration Shadow Registers (Master) Configuration EEPROM Configuration Shadow Registers (Slave) Power On Reset To IMON Circuits To HVOUT, OCB, GPIO Circuits To TRIM Circuits Configuration Shadow Registers (Master-Only) To TMON Circuits I2C_READ_CFG_REG I2C_READ_ALL_CFG_REG Programming Algorithms* I2C_WRITE_CFG_REG I2C_WRITE_CFG_REG_wMASK * - EEPROM access algorithms generated by Lattice Design Software Table 28. Configuration Register Instruction Codes Instruction Code Instruction Name Read/Write 0x25 READ_CFG_EEPROM R Read out the selected configuration EEPROM byte or bytes Description 0x31 WRITE_CFG_REG W Write configuration data byte to addressed register 0x32 WRITE_CFG_REG_wMASK W Write masked configuration data bits to addressed register 0x33 READ_CFG_REG R Read addressed configuration register 0x34 READ_ALL_CFG_REG R Read all configuration registers, starting at address 0x00 0x35 LOAD_CFG_REG W Load the slave shadow configuration registers from the I2C master shadow configuration registers (not all registers supported, see Table 29) The configuration registers and address map are shown in the tables in the ASC Configuration Registers section. The tables in this section also describe which registers support the LOAD_CFG_REG instruction. Special configuration memory parameters (such as the Write Protect setting, User Tag / Fault Log mode, and UES bits) can only be modified in EEPROM. They cannot be modified using configuration register instructions. This increases the reliability of the device operation. The READ_CFG_EEPROM instruction is used to readout the contents of an addressed byte or bytes of configuration EEPROM. This instruction will readout the configuration data stored in the EEPROM memory – this is not necessarily the current device configuration. The current device configuration can be readout using the READ_CFG_REG or READ_ALL_CFG_REG commands. The address map for the configuration EEPROM is the same as the configuration register map. The READ_CFG_EEPROM instruction is the only mechanism for reading out the User Electronic Signature (described in Table 77). The READ_CFG_EEPROM is a two-step transaction operation, as shown in Figure 47. In the first step, a write transaction is performed with the 0x25 instruction, and an 76 Platform Manager 2 In-System Programmable Hardware Management Controller 8-bit address code corresponding to a specific memory address (defined in the ASC Configuration Registers section). In the second step, a read transaction is used to read the EEPROM memory contents. The memory address will auto-increment to support reading multiple bytes in a single transaction. This means a single transaction can support reading the entire configuration address map (120 bytes), if the starting address of 0x00 is used. A stop condition will complete the read transaction, this can be issued after any number of bytes have been read. Figure 47. READ_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x25 A M_A[7:0] A Sr A[6:0] DATA [ADDRESS +1] DATA [ADDRESS] SLAVE ADDRESS MEMORY ADDRESS R A D0[7:0] A D1[7:0] A* P Optional: Read up to 120 additional data bytes * After final data byte read, master should NACK before issuing the STOP command The WRITE_CFG_REG instruction is used to write configuration data to an addressed register. The instruction format includes an address byte and at least one data byte, as shown in Figure 48. Additional data bytes can be written in a single transaction as the configuration register address will increment automatically. A stop condition will complete the write transaction, this can be issued after any number of bytes have been written. The WRITE_CFG_REG instruction should be used with caution, as many of the configuration registers are used to define multiple device options. In many cases, the WRITE_CFG_REG_wMASK instruction is a more reliable method for updating a single configuration parameter. For configuration registers which support the LOAD_CFG_REG instruction, the slave shadow registers will not be updated until the LOAD_CFG_REG instruction is executed. Master-only shadow registers will be updated immediately, and in some cases will reset their circuitry (see the ASC Configuration Registers section). Figure 48. WRITE_CFG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x31 REGISTER ADDRESS A R_A[7:0] DATA [ADDRESS] A D0[7:0] DATA [ADDRESS + 1] A D1[7:0] A P Optional: Write up to 100 additional data bytes The WRITE_CFG_REG_wMASK instruction is used to write the masked configuration data bits to an addressed master register. The instruction format includes an address byte and at least one mask byte / data byte pair, as shown in Figure 49. Additional mask and data byte pairs can be written in a single transaction as the configuration register address will increment automatically. A stop condition will complete the write transaction, this can be issued after any number of data and mask pairs have been written. This instruction will not modify the configuration bits set to 1 in the mask byte. Those configuration bits will keep their current value. Bit locations set to 0 in the mask byte will be modified by the data byte. For configuration registers which support the LOAD_CFG_REG instruction, the slave shadow registers will not be updated until the LOAD_CFG_REG instruction is executed. Master-only shadow registers will be updated immediately, and in some cases will reset their circuitry. Figure 49. WRITE_CFG__REG_wMASK - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x31 DATA [ADDRESS] REGISTER ADDRESS A R_A[7:0] A D0[7:0] DATA [ADDRESS + 1] A D1[7:0] A P Optional: Write up to 100 additional data bytes 77 Platform Manager 2 In-System Programmable Hardware Management Controller Using the WRITE_CFG_REG_wMASK Instruction Format The WRITE_CFG_REG_wMASK instruction is the preferred instruction for updating a single programmable device parameter. As an example, the following I2C write transaction can be used to update only the VMON4_A threshold. The example will update the A_TRIP_FINE to a value of hex 0x0A (binary 001010). See Table 35 for more details. 1. Start the bus transaction. 2. Transmit the device address (7 bits) along with a low write bit. 3. Transmit the 0x32 instruction code (WRITE_CFG_REG_wMASK.) 4. Transmit the 0x1F address byte (VMON4_CFG0 register as defined by Table 35). 5. Transmit 0x3F as the MASK0 byte (only A_TRIP_FINE[1:0] will be modified, B_TRIP_SELECT[5:0] will maintain its current configuration). 6. Transmit the data to be written to the two highest bits of VMON4_CFG0 (0x80 corresponds to A_TRIP_FINE[1:0] = 10). 7. Transmit 0xF0 as the next mask byte (address will auto-increment to 0x20, the VMON4_CFG1 register). Only A_TRIP_FINE[5:2] will be modified. Other VMON4_CFG1 parameters will be unchanged. 8. Transmit the data to be written to the four lowest bits of VMON4_CFG1 (0x02 corresponds to A_TRIP_FINE[5:2] = 0010). 9. Stop the bus transaction. 10. Start an additional bus transaction using the LOAD_CFG_REG instruction (see Figure 52). The configuration register settings can also be readout over I2C. This is accomplished using the READ_CFG_REG instruction and the READ_ALL_CFG_REG instruction. The READ_CFG_REG is a two-step transaction operation, as shown in Figure 50. In the first step, a write transaction is performed with the 0x33 instruction, and an 8-bit address code corresponding to a specific register address (defined in the ASC Configuration Registers section). In the second step, a read transaction is used to read the register contents. The register address will auto-increment to support reading multiple registers in a single transaction. This means a single transaction can support reading the entire configuration address map (102 bytes), if the starting address of 0x00 is used. A stop condition will complete the read transaction, this can be issued after any number of bytes have been read. Figure 50. READ_CFG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x33 A R_A[7:0] A Sr A[6:0] DATA [ADDRESS +1] DATA [ADDRESS] SLAVE ADDRESS MEMORY ADDRESS R A D0[7:0] A D1[7:0] A* P Optional: Read up to 101 additional data bytes * After final data byte read, master should NACK before issuing the STOP command. 78 Platform Manager 2 In-System Programmable Hardware Management Controller The READ_ALL_CFG instruction works in a similar way to the READ_CFG_REG. The difference is that the READ_ALL_CFG instruction always starts at register address 0x00. Multiple data bytes can be read out in a single transaction, with the register address auto-incrementing after each byte is read. The entire configuration register memory space can be read out with a single transaction (102 data bytes). A stop condition will complete the read transaction, this can be issued after any number of bytes have been read. The format for the READ_ALL_CFG_REG instruction is shown in Figure 51. Figure 51. READ_ALL_CFG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] W A 0x34 DATA DATA [ADDRESS = 0x00] [ADDRESS = 0x01] SLAVE ADDRESS INSTRUCTION CODE A Sr A[6:0] R A D0[7:0] A D1[7:0] A* P Optional: Read up to 101 additional data bytes * After final data byte read, master should NACK before issuing the STOP command The LOAD_CFG_REG instruction is used to load the data from the I2C master shadow registers to the slave shadow registers. All the slave shadow registers are loaded at once when the instruction is received. The LOAD_CFG_REG instruction should be used after WRITE_CFG_REG and WRITE_CFG_REG_wMask updates to the I2C configuration registers are completed. This instruction is useful for updating multiple parameters which affect the operation of a single circuit (such as a VMON or IMON), as these parameters are often spread across multiple configuration addresses. Note that certain configuration registers (such as temperature monitor or trim profiles) do not support this instruction. These master-only shadow registers are updated immediately by a WRITE_CFG_REG instruction, they do not require a LOAD_CFG_REG instruction. The format for the LOAD_CFG_REG instruction is shown in Figure 52. Figure 52. LOAD_CFG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x35 A P 79 Platform Manager 2 In-System Programmable Hardware Management Controller ASC Configuration Registers The ASC Configuration registers are grouped below by function and shown in the following tables: • Table 29, Trim Configuration Register Summary • Table 35, Voltage Monitor Configuration Register Summary • Table 44, Current Monitor Configuration Register Summary • Table 50, Temperature Monitor Configuration Register Summary • Table 58, High Voltage Output Configuration Register Summary • Table 67, Output Control Block Configuration Register Summary • Table 72, GPIO Input Configuration Register Summary • Table 74, Write Protect and User Tag Configuration Register • Table 77, UES Memory Summary • Table 78, Reserved Configuration Addresses The configuration register address space is 8-bits (0x00-0xFF). The registers contain the configuration information for all the analog blocks in the ASC. These registers are automatically populated with their configuration information at power on reset, either from the ASC EEPROM memory or external memory via Dual Boot algorithm. These registers should not be confused with the "Measurement and Control" registers described in a later section. The measurement and control registers are used to read voltage, current, and temperature measurements and are accessed with a different set of instructions. Table 29. Trim Configuration Register Summary Register Address Register Name Bit7 Bit6 Bit5 0x00 Trim1_P1_Lo 0x01 Trim1_Trim2_P1_Hi Trim1_P1_Set[11:8] 0x02 Trim2_P1_Lo Trim2_P1_Set [7:0] 0x03 Trim3_P1_Lo Trim3_P1_Set [7:0] 0x04 Trim3_Trim4_P1_Hi Trim3_P1_Set [11:8] 0x05 Trim4_P1_Lo Trim4_P1_Set [7:0] 0x06 Trim1_P2_Lo Trim1_P2_Set [7:0] 0x07 Trim1_Trim2_P2_Hi Trim1_P2_Set[11:8] 0x08 Trim2_P1_Lo Trim2_P2_Set [7:0] 0x09 Trim3_P2_Lo Trim3_P2_Set [7:0] 0x0A Trim3_Trim4_P2_Hi Trim3_P2_Set [11:8] 0x0B Trim4_P1_Lo Trim4_P1_Set [7:0] 0x0C Trim1_P0_Lo Trim1_P0_Set [7:0] Bit4 Bit3 Bit2 Bit1 Bit0 Reconfiguration Details Trim1_P1_Set [7:0] 0x0D Trim1_P0_Hi_Cfg POL 0x0E Trim2_P0_Lo Trim2_P0_Set [7:0] BYP 0x0F Trim2_P0_Hi_Cfg POL 0x10 Trim3_P0_Low Trim3_P0_Set [7:0] 0x11 Trim3_P0_Hi_Cfg POL 0x12 Trim4_P0_Low Trim4_P0_Set [7:0] 0x13 Trim4_P0_Hi_Cfg POL 0x14 Trim_CLT_Rate 0x15 Trim_DAC_BPZ BYP BYP BYP ATT ATT ATT ATT Trim2_P1_Set[11:8] Trim3_P1_Set [11:8] Master-Only (Immediate Update) Trim1_P2_Set[11:8] Trim3_P2_Set [11:8] x Trim1_P0_Set[11:8] x Trim2_P0_Set[11:8] x Trim3_P0_Set[11:8] x Trim4_P0_Set[11:8] RATE[1:0] D4_BPZ[1:0] D3_BPZ[1:0] D2_BPZ[1:0] D1_BPZ[1:0] 80 Master/Slave (LOAD_CFG_REG supported) Platform Manager 2 In-System Programmable Hardware Management Controller Closed Loop Trim Configuration Registers The ASC configuration memory specifies the operation of the closed loop trim circuitry, described in the Controlling Power Supply Output Voltage by Trim and Margin Block section. Each of the configurable parameters, shown in Table 29, are described in the following section. Trimx_Py_Set [11:0] (Trim1_P0 … Trim4_P2) – Trim Channel Profile Setpoints 0, 1 and 2 The Trim profile setpoints are configured as 12 bit numbers, where each bit corresponds to 2 mV. The equation below (which is a reversal of the calculation equation found in the ADC section) describes how to calculate the trim target. TRIM_SETPOINT_CODE (12_bits, converted to binary) = ROUND (Target Voltage / 2 mV) Each of the 4 Trim channels supports three separate programmable setpoints, as shown in Table 29. The P1 and P2 setpoints for each channel do not support the LOAD_CFG_REG instruction and are updated immediately after being written by I2C instructions. It is not recommended to update these registers during operation. Updating the trim setpoint is best accomplished using the Closed Loop Trim Register Access instructions. POL – Polarity The Polarity setting for each trim channel determines the closed loop trim behavior of trim voltage control versus output voltage feedback, as shown in Figure 31. The polarity settings are described in Table 30. Table 30. POL Setting vs Closed Loop Trim Polarity POL Closed Loop Trim Polarity 0 Positive 1 Negative BYP – Bypass The Bypass setting for each trim channel determines whether the trim output voltage is controlled by the closed loop trim circuitry or by the stored profile DAC codes, as shown in Figure 30. The bypass settings are described in Table 31. Table 31. BYP Setting vs Trim Voltage Source BYP Trim Voltage Source 0 Closed Loop Trim Logic 1 Profile DAC Code ATT – Attenuator Enable The Attenuator Enable setting for each trim channel determines whether the monitored DC-DC output voltage needs to be attenuated before ADC measurement, as shown in Figure 14. DC-DC output voltages above 2 V need to be attenuated. The attenuator settings are described in Table 32. Table 32. ATT Setting vs Attenuation Value ATT Attenuation Value 0 ÷ 1 (no attenuation) 1 ÷3 81 Platform Manager 2 In-System Programmable Hardware Management Controller RATE[1:0] – Closed Loop Trim Update Rate The Closed Loop Trim update rate is a common setting for all four trim channels. The available settings are shown in Table 33. Table 33. RATE[1:0] Setting vs Closed Loop Trim Update Rate RATE[1:0] Update Rate 00 860 us 01 1.72 ms 10 13.8 ms 11 27.6 ms Dx_BPZ (DAC1_BPZ … DAC4_BPZ) – DAC Bi-Polar Zero Output Voltage The DAC Bi-Polar Zero Output Voltage for each channel determines the Trim outputs Bi-Polar Zero voltage as shown in Figure 32. There are four available settings shown in Table 34. Table 34. Dx_BPZ[1:0] Setting vs DAC Bi-Polar Zero Output Voltage Dx_BPZ[1:0] DAC BPZ Voltage 00 0.6 V 01 0.8 V 10 1.0 V 11 1.25 V 82 Platform Manager 2 In-System Programmable Hardware Management Controller Voltage Monitor Configuration Registers Table 35. Voltage Monitor Configuration Register Summary Register Address Register Name Bit7 Bit6 Bit5 Bit4 0x16 VMON1_Config0 V1_ATF[1:0] V1_BTF[5:0] 0x17 VMON1_Config1 1 0x18 VMON1_Config2 V1_ATC[3:0] 1 GBP WM VMON2_Config0 V2_ATF[1:0] V2_BTF[5:0] 0x1A VMON2_Config1 1 GBP WM 0x1B VMON2_Config2 V2_ATC[3:0] 0x1C VMON3_Config0 V3_ATF[1:0] V3_BTF[5:0] 0x1D VMON3_Config1 1 0x1E VMON3_Config2 V3_ATC[3:0] 1 GBP WM VMON4_Config0 V4_ATF[1:0] V4_BTF[5:0] VMON4_Config1 1 0x21 VMON4_Config2 V4_ATC[3:0] 0x22 VMON5_Config0 V5_ATF[1:0] V5_BTF[5:0] 0x23 VMON5_Config1 1 0x24 VMON5_Config2 V5_ATC[3:0] 0x25 VMON6_Config0 V6_ATF[1:0] V6_BTF[5:0] 0x26 VMON6_Config1 1 0x27 VMON6_Config2 V6_ATC[3:0] 0x28 VMON7_Config0 V7_ATF[1:0] V7_BTF[5:0] 0x29 VMON7_Config1 1 0x2A VMON7_Config2 V7_ATC[3:0] 1 1 GBP WM GBP WM GBP WM V2_ATF[5:2] V3_ATF[5:2] V4_ATF[5:2] V5_ATF[5:2] Master/Slave (LOAD_CFG_REG supported) V6_ATF[5:2] V6_BTC[3:0] GBP WM V7_ATF[5:2] V7_BTC[3:0] VMON8_Config0 V8_ATF[1:0] V8_BTF[5:0] VMON8_Config1 1 0x2D VMON8_Config2 V8_ATC[3:0] 0x2E VMON9_Config0 V9_ATF[1:0] V9_BTF[5:0] 0x2F VMON9_Config1 1 0x30 VMON9_Config2 V9_ATC[3:0] GBP WM V8_ATF[5:2] V8_BTC[3:0] GBP WM V9_ATF[5:2] V9_BTC[3:0] 0x31 HVMON_Config0 HV_ATF[1:0] HV_BTF[5:0] 0x32 HVMON_Config1 1 0x33 HVMON_Config2 HV_ATC[3:0] 1 V1_ATF[5:2] V5_BTC[3:0] 0x2C 1 Reconfiguration Details V4_BTC[3:0] 0x2B 1 Bit0 V3_BTC[3:0] 0x20 1 Bit1 V2_BTC[3:0] 0x1F 1 Bit2 V1_BTC[3:0] 0x19 1 Bit3 GBP WM HV_ATF[5:2] HV_BTC[3:0] The ASC configuration memory specifies the operation of the voltage monitor (VMON), described in the Voltage Monitor Inputs section. The voltage monitor (VMON1-VMON9 and HVMON) trip points, glitch filter setting, and window mode are configurable over I2C. The configuration registers are summarized in Table 35. Vx_ATF[5:0], Vx_ATC[3:0], Vx_BTF[5:0], Vx_BTC[3:0] (V1_ATF … V9_BTC) – Voltage Monitor Fine and Coarse, A and B Trip Points Each voltage monitor includes programmable trip points A and B, corresponding to the two comparators for each voltage monitor input pin. The A and B trip points of the Differential Voltage Monitors (VMON1 - VMON4) are defined based on the fine and coarse settings shown in Table 36 (for over-voltage monitoring) and Table 37 (for under-voltage monitoring). The A and B trip points of the Single-Ended Voltage Monitors (VMON5-VMON9) are defined based on the fine and coarse settings shown in Table 38 (for over-voltage monitoring) and Table 39 (for under-voltage monitoring). Fine and Coarse settings outside of the table range are prohibited. There is no program- 83 Platform Manager 2 In-System Programmable Hardware Management Controller mable setting for over or under voltage. Based on the type of voltage monitoring, choose the applicable table. For more details on over and under voltage monitoring, see the Programmable Over-Voltage and Under-Voltage thresholds discussion in the voltage monitor inputs section. Setting the trip point to the Low-Voltage sense row (Fine Range 0x21) disables hysteresis for that voltage monitor input for both under and over voltage detection. Table 36. Trip Point for Over-Voltage Detection (Differential VMON1-VMON4) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0x00 0.795 0.947 1.127 1.341 1.589 1.897 2.259 2.677 3.172 3.779 4.848 5.775 0x01 0.790 0.942 1.121 1.334 1.581 1.887 2.247 2.663 3.156 3.759 4.822 5.744 0x02 0.786 0.937 1.115 1.327 1.572 1.876 2.235 2.648 3.139 3.739 4.797 5.713 0x03 0.782 0.931 1.109 1.320 1.564 1.866 2.223 2.634 3.122 3.719 4.771 5.683 0x04 0.778 0.926 1.103 1.313 1.555 1.856 2.211 2.620 3.105 3.699 4.746 5.652 0x05 0.773 0.921 1.097 1.306 1.547 1.846 2.199 2.605 3.088 3.679 4.720 5.621 0x06 0.769 0.916 1.091 1.299 1.538 1.836 2.187 2.591 3.071 3.658 4.694 5.590 0x07 0.765 0.911 1.085 1.291 1.530 1.826 2.175 2.577 3.055 3.638 4.668 5.559 0x08 0.761 0.906 1.079 1.284 1.521 1.816 2.163 2.563 3.038 3.618 4.642 5.529 0x09 0.756 0.901 1.073 1.277 1.513 1.806 2.151 2.548 3.021 3.598 4.616 5.498 0x0A 0.752 0.896 1.067 1.270 1.504 1.796 2.139 2.534 3.004 3.578 4.590 5.468 0x0B 0.748 0.891 1.061 1.263 1.497 1.786 2.127 2.520 2.987 3.558 4.565 5.437 0x0C 0.744 0.886 1.055 1.256 1.488 1.775 2.115 2.505 2.970 3.537 4.539 5.406 0x0D 0.739 0.881 1.049 1.249 1.480 1.765 2.103 2.492 2.953 3.517 4.513 5.375 0x0E 0.735 0.876 1.043 1.241 1.472 1.755 2.091 2.478 2.936 3.497 4.487 5.345 0x0F 0.731 0.871 1.037 1.234 1.463 1.745 2.079 2.464 2.919 3.478 4.462 5.314 0x10 0.727 0.866 1.031 1.227 1.455 1.735 2.066 2.449 2.902 3.458 4.436 5.283 0x11 0.723 0.861 1.025 1.220 1.446 1.725 2.054 2.435 2.885 3.438 4.410 5.252 0x12 0.718 0.856 1.019 1.213 1.438 1.715 2.042 2.421 2.868 3.417 4.384 5.221 0x13 0.714 0.851 1.013 1.206 1.429 1.705 2.030 2.406 2.851 3.397 4.359 5.191 0x14 0.710 0.846 1.007 1.199 1.421 1.695 2.018 2.392 2.835 3.377 4.333 5.160 0x15 0.706 0.841 1.001 1.191 1.412 1.685 2.006 2.378 2.819 3.357 4.307 5.130 0x16 0.701 0.836 0.995 1.184 1.404 1.674 1.994 2.364 2.802 3.337 4.281 5.099 0x17 0.697 0.831 0.989 1.177 1.395 1.664 1.982 2.349 2.785 3.317 4.255 5.068 0x18 0.693 0.826 0.983 1.170 1.387 1.654 1.970 2.335 2.768 3.296 4.229 5.038 0x19 0.689 0.821 0.977 1.163 1.378 1.644 1.958 2.321 2.751 3.276 4.203 5.007 0x1A 0.684 0.816 0.971 1.156 1.370 1.634 1.946 2.307 2.734 3.256 4.178 4.976 0x1B 0.680 0.810 0.965 1.149 1.362 1.624 1.934 2.292 2.717 3.236 4.153 4.945 0x1c 0.676 0.805 0.959 1.141 1.353 1.614 1.922 2.278 2.700 3.216 4.127 4.914 0x1d 0.672 0.800 0.953 1.134 1.345 1.604 1.910 2.264 2.683 3.196 4.101 4.884 0x1e 0.668 0.795 0.947 1.127 1.336 1.594 1.898 2.249 2.666 3.176 4.075 4.853 0.252 0.300 0.356 0.457 0.545 Low-Voltage Sense 0x21 0.075 0.089 0.106 0.126 0.150 0.178 84 0.212 Platform Manager 2 In-System Programmable Hardware Management Controller Table 37. Trip Point for Under-Voltage Detection (Differential VMON1-VMON4) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0x00 0.786 0.937 1.115 1.327 1.572 1.876 2.235 2.648 3.139 3.739 4.797 5.713 0x01 0.782 0.931 1.109 1.320 1.564 1.866 2.223 2.634 3.122 3.719 4.771 5.683 0x02 0.778 0.926 1.103 1.313 1.555 1.856 2.211 2.620 3.105 3.699 4.746 5.652 0x03 0.773 0.921 1.097 1.306 1.547 1.846 2.199 2.605 3.088 3.679 4.720 5.621 0x04 0.769 0.916 1.091 1.299 1.538 1.836 2.187 2.591 3.071 3.658 4.694 5.590 0x05 0.765 0.911 1.085 1.291 1.530 1.826 2.175 2.577 3.055 3.638 4.668 5.559 0x06 0.761 0.906 1.079 1.284 1.521 1.816 2.163 2.563 3.038 3.618 4.642 5.529 0x07 0.756 0.901 1.073 1.277 1.513 1.806 2.151 2.548 3.021 3.598 4.616 5.498 0x08 0.752 0.896 1.067 1.270 1.504 1.796 2.139 2.534 3.004 3.578 4.590 5.468 0x09 0.748 0.891 1.061 1.263 1.497 1.786 2.127 2.520 2.987 3.558 4.565 5.437 0x0A 0.744 0.886 1.055 1.256 1.488 1.775 2.115 2.505 2.970 3.537 4.539 5.406 0x0B 0.739 0.881 1.049 1.249 1.480 1.765 2.103 2.492 2.953 3.517 4.513 5.375 0x0C 0.735 0.876 1.043 1.241 1.472 1.755 2.091 2.478 2.936 3.497 4.487 5.345 0x0D 0.731 0.871 1.037 1.234 1.463 1.745 2.079 2.464 2.919 3.478 4.462 5.314 0x0E 0.727 0.866 1.031 1.227 1.455 1.735 2.066 2.449 2.902 3.458 4.436 5.283 0x0F 0.723 0.861 1.025 1.220 1.446 1.725 2.054 2.435 2.885 3.438 4.410 5.252 0x10 0.718 0.856 1.019 1.213 1.438 1.715 2.042 2.421 2.868 3.417 4.384 5.221 0x11 0.714 0.851 1.013 1.206 1.429 1.705 2.030 2.406 2.851 3.397 4.359 5.191 0x12 0.710 0.846 1.007 1.199 1.421 1.695 2.018 2.392 2.835 3.377 4.333 5.160 0x13 0.706 0.841 1.001 1.191 1.412 1.685 2.006 2.378 2.819 3.357 4.307 5.130 0x14 0.701 0.836 0.995 1.184 1.404 1.674 1.994 2.364 2.802 3.337 4.281 5.099 0x15 0.697 0.831 0.989 1.177 1.395 1.664 1.982 2.349 2.785 3.317 4.255 5.068 0x16 0.693 0.826 0.983 1.170 1.387 1.654 1.970 2.335 2.768 3.296 4.229 5.038 0x17 0.689 0.821 0.977 1.163 1.378 1.644 1.958 2.321 2.751 3.276 4.203 5.007 0x18 0.684 0.816 0.971 1.156 1.370 1.634 1.946 2.307 2.734 3.256 4.178 4.976 0x19 0.680 0.810 0.965 1.149 1.362 1.624 1.934 2.292 2.717 3.236 4.153 4.945 0x1A 0.676 0.805 0.959 1.141 1.353 1.614 1.922 2.278 2.700 3.216 4.127 4.914 0x1B 0.672 0.800 0.953 1.134 1.345 1.604 1.910 2.264 2.683 3.196 4.101 4.884 0x1c 0.668 0.795 0.947 1.127 1.336 1.594 1.898 2.249 2.666 3.176 4.075 4.853 0x1d 0.663 0.790 0.941 1.120 1.328 1.584 1.886 2.235 2.649 3.156 4.049 4.822 0x1e 0.659 0.785 0.935 1.113 1.319 1.573 1.874 2.221 2.632 3.136 4.023 4.792 0.252 0.300 0.356 0.457 0.545 Low-Voltage Sense 0x21 0.075 0.089 0.106 0.126 0.150 0.178 85 0.212 Platform Manager 2 In-System Programmable Hardware Management Controller Table 38. Trip Point for Over-Voltage Detection (Single-Ended VMON5-VMON9) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0x0 0.799 0.952 1.133 1.347 1.597 1.907 2.270 2.688 3.185 3.794 4.868 5.798 0x1 0.794 0.947 1.126 1.340 1.589 1.897 2.258 2.674 3.168 3.774 4.842 5.767 0x2 0.790 0.942 1.120 1.333 1.580 1.886 2.246 2.659 3.151 3.754 4.816 5.736 0x3 0.786 0.936 1.114 1.326 1.572 1.875 2.234 2.645 3.134 3.734 4.790 5.706 0x4 0.782 0.931 1.108 1.319 1.563 1.865 2.222 2.631 3.117 3.714 4.765 5.675 0x5 0.777 0.926 1.102 1.312 1.555 1.855 2.210 2.616 3.100 3.694 4.739 5.644 0x6 0.773 0.921 1.096 1.305 1.546 1.845 2.198 2.602 3.083 3.673 4.713 5.613 0x7 0.769 0.916 1.090 1.297 1.538 1.835 2.186 2.588 3.067 3.653 4.687 5.582 0x8 0.765 0.911 1.084 1.290 1.529 1.825 2.174 2.574 3.050 3.633 4.661 5.552 0x9 0.760 0.906 1.078 1.283 1.521 1.815 2.162 2.559 3.033 3.613 4.635 5.521 0xa 0.756 0.901 1.072 1.276 1.512 1.805 2.150 2.545 3.016 3.593 4.609 5.489 0xb 0.752 0.896 1.066 1.269 1.504 1.795 2.138 2.531 2.999 3.573 4.584 5.458 0xc 0.748 0.891 1.060 1.262 1.495 1.784 2.125 2.516 2.982 3.552 4.558 5.427 0xd 0.743 0.886 1.054 1.255 1.487 1.774 2.113 2.501 2.965 3.532 4.532 5.396 0xe 0.739 0.881 1.048 1.247 1.479 1.764 2.101 2.487 2.948 3.512 4.506 5.366 0xf 0.735 0.875 1.042 1.240 1.470 1.754 2.089 2.473 2.931 3.491 4.479 5.335 0x10 0.731 0.870 1.036 1.233 1.462 1.744 2.076 2.458 2.914 3.471 4.453 5.304 0x11 0.727 0.865 1.030 1.226 1.453 1.734 2.064 2.444 2.897 3.451 4.427 5.273 0x12 0.722 0.860 1.024 1.219 1.445 1.724 2.052 2.430 2.880 3.430 4.401 5.242 0x13 0.718 0.855 1.018 1.212 1.436 1.714 2.040 2.415 2.863 3.410 4.376 5.212 0x14 0.714 0.850 1.012 1.205 1.428 1.704 2.028 2.401 2.847 3.390 4.350 5.181 0x15 0.710 0.845 1.006 1.197 1.419 1.694 2.016 2.387 2.830 3.370 4.324 5.150 0x16 0.705 0.840 1.000 1.190 1.411 1.683 2.004 2.373 2.813 3.350 4.298 5.119 0x17 0.701 0.835 0.994 1.183 1.402 1.673 1.992 2.358 2.796 3.330 4.272 5.088 0x18 0.697 0.830 0.988 1.176 1.394 1.663 1.980 2.344 2.779 3.309 4.246 5.058 0x19 0.693 0.825 0.982 1.169 1.385 1.653 1.968 2.330 2.762 3.289 4.220 5.027 0x1a 0.688 0.820 0.976 1.162 1.376 1.643 1.956 2.316 2.745 3.269 4.195 4.996 0x1b 0.684 0.814 0.970 1.155 1.368 1.633 1.944 2.301 2.728 3.249 4.169 4.965 0x1c 0.680 0.809 0.964 1.147 1.359 1.622 1.932 2.287 2.711 3.229 4.143 4.934 0x1d 0.676 0.804 0.958 1.140 1.351 1.612 1.920 2.273 2.694 3.209 4.117 4.904 0x1e 0.672 0.799 0.952 1.133 1.342 1.602 1.908 2.258 2.677 3.189 4.091 4.873 0.262 0.310 0.370 0.475 0.565 Low-Voltage Sense 0x21 0.080 0.093 0.110 0.132 0.155 0.186 86 0.220 Platform Manager 2 In-System Programmable Hardware Management Controller Table 39. Trip Point for Under-Voltage Detection (Single-Ended VMON5-VMON9) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0x0 0.790 0.942 1.120 1.333 1.580 1.886 2.246 2.659 3.151 3.754 4.816 5.736 0x1 0.786 0.936 1.114 1.326 1.572 1.875 2.234 2.645 3.134 3.734 4.790 5.706 0x2 0.782 0.931 1.108 1.319 1.563 1.865 2.222 2.631 3.117 3.714 4.765 5.675 0x3 0.777 0.926 1.102 1.312 1.555 1.855 2.210 2.616 3.100 3.694 4.739 5.644 0x4 0.773 0.921 1.096 1.305 1.546 1.845 2.198 2.602 3.083 3.673 4.713 5.613 0x5 0.769 0.916 1.090 1.297 1.538 1.835 2.186 2.588 3.067 3.653 4.687 5.582 0x6 0.765 0.911 1.084 1.290 1.529 1.825 2.174 2.574 3.050 3.633 4.661 5.552 0x7 0.760 0.906 1.078 1.283 1.521 1.815 2.162 2.559 3.033 3.613 4.635 5.521 0x8 0.756 0.901 1.072 1.276 1.512 1.805 2.150 2.545 3.016 3.593 4.609 5.489 0x9 0.752 0.896 1.066 1.269 1.504 1.795 2.138 2.531 2.999 3.573 4.584 5.458 0xa 0.748 0.891 1.060 1.262 1.495 1.784 2.125 2.516 2.982 3.552 4.558 5.427 0xb 0.743 0.886 1.054 1.255 1.487 1.774 2.113 2.501 2.965 3.532 4.532 5.396 0xc 0.739 0.881 1.048 1.247 1.479 1.764 2.101 2.487 2.948 3.512 4.506 5.366 0xd 0.735 0.875 1.042 1.240 1.470 1.754 2.089 2.473 2.931 3.491 4.479 5.335 0xe 0.731 0.870 1.036 1.233 1.462 1.744 2.076 2.458 2.914 3.471 4.453 5.304 0xf 0.727 0.865 1.030 1.226 1.453 1.734 2.064 2.444 2.897 3.451 4.427 5.273 0x10 0.722 0.860 1.024 1.219 1.445 1.724 2.052 2.430 2.880 3.430 4.401 5.242 0x11 0.718 0.855 1.018 1.212 1.436 1.714 2.040 2.415 2.863 3.410 4.376 5.212 0x12 0.714 0.850 1.012 1.205 1.428 1.704 2.028 2.401 2.847 3.390 4.350 5.181 0x13 0.710 0.845 1.006 1.197 1.419 1.694 2.016 2.387 2.830 3.370 4.324 5.150 0x14 0.705 0.840 1.000 1.190 1.411 1.683 2.004 2.373 2.813 3.350 4.298 5.119 0x15 0.701 0.835 0.994 1.183 1.402 1.673 1.992 2.358 2.796 3.330 4.272 5.088 0x16 0.697 0.830 0.988 1.176 1.394 1.663 1.980 2.344 2.779 3.309 4.246 5.058 0x17 0.693 0.825 0.982 1.169 1.385 1.653 1.968 2.330 2.762 3.289 4.220 5.027 0x18 0.688 0.820 0.976 1.162 1.376 1.643 1.956 2.316 2.745 3.269 4.195 4.996 0x19 0.684 0.814 0.970 1.155 1.368 1.633 1.944 2.301 2.728 3.249 4.169 4.965 0x1a 0.680 0.809 0.964 1.147 1.359 1.622 1.932 2.287 2.711 3.229 4.143 4.934 0x1b 0.676 0.804 0.958 1.140 1.351 1.612 1.920 2.273 2.694 3.209 4.117 4.904 0x1c 0.672 0.799 0.952 1.133 1.342 1.602 1.908 2.258 2.677 3.189 4.091 4.873 0x1d 0.667 0.794 0.946 1.125 1.334 1.592 1.896 2.244 2.660 3.168 4.065 4.842 0x1e 0.663 0.789 0.940 1.118 1.325 1.581 1.884 2.230 2.643 3.148 4.039 4.811 0.262 0.310 0.370 0.475 0.565 Low-Voltage Sense 0x21 0.080 0.093 0.110 0.132 0.155 0.186 87 0.220 Platform Manager 2 In-System Programmable Hardware Management Controller GBP – Glitch Filter Bypass Each of the voltage monitors include a glitch filter at each of the trip point comparator outputs as shown in Figure 10. This glitch filter can be bypassed dependent on the GBP setting shown in Table 40. Table 40. GBP Setting vs Glitch Bypass Behavior GBP Glitch Filter Setting 0 Glitch Filter On 1 Glitch Filter Bypassed WM – Window Mode Each of the voltage monitors include a selectable window mode, as described in Table 8. The window mode setting is shown in Table 41. Table 41. WM Setting vs Window Mode Value WM Window Mode 0 Off 1 On HV_ATF[5:0], HV_ATC[3:0], HV_BTF[5:0], HV_BTC[3:0] – High Voltage Monitor Fine and Coarse, A and B Trip Points The High Voltage Monitor (HVMON) is configured in a similar fashion to the low voltage monitor inputs. The key difference from the low voltage monitor inputs is the trip point table. The HVMON range is up to 13.2 V, as reflected in Table 42 (Over-Voltage Trip Points) and Table 43 (Under-Voltage Trip Points). Setting the trip point to the Low-Voltage sense row (Fine Range 0x21) disables hysteresis for that voltage monitor input for both under and over voltage detection. 88 Platform Manager 2 In-System Programmable Hardware Management Controller Table 42. Trip Point for Over-Voltage Detection (HVMON) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0x0 2.269 2.694 3.193 3.748 4.421 5.207 6.137 7.160 8.382 9.819 11.455 13.218 0x1 2.257 2.680 3.176 3.729 4.398 5.179 6.104 7.121 8.337 9.767 11.394 13.147 0x2 2.245 2.666 3.159 3.709 4.374 5.152 6.071 7.083 8.293 9.714 11.333 13.077 0x3 2.233 2.651 3.142 3.689 4.351 5.124 6.039 7.045 8.248 9.662 11.272 13.007 0x4 2.221 2.637 3.125 3.669 4.327 5.096 6.006 7.007 8.204 9.610 11.212 12.936 0x5 2.208 2.623 3.108 3.649 4.304 5.068 5.974 6.969 8.159 9.558 11.151 12.866 0x6 2.196 2.608 3.091 3.629 4.280 5.041 5.941 6.931 8.114 9.505 11.090 12.796 0x7 2.184 2.594 3.074 3.609 4.257 5.013 5.908 6.893 8.070 9.453 11.029 12.725 0x8 2.172 2.580 3.057 3.589 4.233 4.985 5.876 6.855 8.025 9.401 10.968 12.655 0x9 2.160 2.565 3.040 3.569 4.210 4.958 5.843 6.817 7.981 9.349 10.907 12.585 0xa 2.148 2.551 3.023 3.549 4.186 4.930 5.810 6.779 7.936 9.297 10.846 12.515 0xb 2.136 2.537 3.006 3.529 4.163 4.902 5.778 6.741 7.891 9.244 10.785 12.444 0xc 2.124 2.522 2.989 3.509 4.139 4.875 5.745 6.703 7.847 9.192 10.724 12.374 0xd 2.112 2.508 2.972 3.489 4.116 4.847 5.712 6.664 7.802 9.140 10.663 12.304 0xe 2.100 2.494 2.955 3.469 4.092 4.819 5.680 6.626 7.758 9.088 10.602 12.233 0xf 2.088 2.479 2.938 3.449 4.069 4.791 5.647 6.588 7.713 9.035 10.541 12.163 0x10 2.076 2.465 2.921 3.429 4.045 4.764 5.614 6.550 7.669 8.983 10.480 12.093 0x11 2.064 2.451 2.904 3.410 4.021 4.736 5.582 6.512 7.624 8.931 10.419 12.022 0x12 2.052 2.436 2.887 3.390 3.998 4.708 5.549 6.474 7.579 8.879 10.358 11.952 0x13 2.040 2.422 2.870 3.370 3.974 4.681 5.517 6.436 7.535 8.826 10.298 11.882 0x14 2.027 2.408 2.853 3.350 3.951 4.653 5.484 6.398 7.490 8.774 10.237 11.811 0x15 2.015 2.393 2.836 3.330 3.927 4.625 5.451 6.360 7.446 8.722 10.176 11.741 0x16 2.003 2.379 2.819 3.310 3.904 4.598 5.419 6.322 7.401 8.670 10.115 11.671 0x17 1.991 2.365 2.803 3.290 3.880 4.570 5.386 6.284 7.356 8.618 10.054 11.601 0x18 1.979 2.350 2.786 3.270 3.857 4.542 5.353 6.246 7.312 8.565 9.993 11.530 0x19 1.967 2.336 2.769 3.250 3.833 4.515 5.321 6.207 7.267 8.513 9.932 11.460 0x1a 1.955 2.322 2.752 3.230 3.810 4.487 5.288 6.169 7.223 8.461 9.871 11.390 0x1b 1.943 2.307 2.735 3.210 3.786 4.459 5.255 6.131 7.178 8.409 9.810 11.319 0x1c 1.931 2.293 2.718 3.190 3.763 4.431 5.223 6.093 7.134 8.356 9.749 11.249 0x1d 1.919 2.279 2.701 3.170 3.739 4.404 5.190 6.055 7.089 8.304 9.688 11.179 0x1e 1.907 2.264 2.684 3.150 3.716 4.376 5.157 6.017 7.044 8.252 9.627 11.108 0.692 0.810 0.949 1.108 1.28 Low-Voltage Sense 0x21 0.220 0.260 0.308 0.361 0.425 0.504 89 0.593 Platform Manager 2 In-System Programmable Hardware Management Controller Table 43. Trip Point for Under-Voltage Detection (HVMON) Fine Range Setting Coarse Range Setting 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0x0 2.245 2.666 3.159 3.709 4.374 5.152 6.071 7.083 8.293 9.714 11.333 13.077 0x1 2.233 2.651 3.142 3.689 4.351 5.124 6.039 7.045 8.248 9.662 11.272 13.007 0x2 2.221 2.637 3.125 3.669 4.327 5.096 6.006 7.007 8.204 9.610 11.212 12.936 0x3 2.208 2.623 3.108 3.649 4.304 5.068 5.974 6.969 8.159 9.558 11.151 12.866 0x4 2.196 2.608 3.091 3.629 4.280 5.041 5.941 6.931 8.114 9.505 11.090 12.796 0x5 2.184 2.594 3.074 3.609 4.257 5.013 5.908 6.893 8.070 9.453 11.029 12.725 0x6 2.172 2.580 3.057 3.589 4.233 4.985 5.876 6.855 8.025 9.401 10.968 12.655 0x7 2.160 2.565 3.040 3.569 4.210 4.958 5.843 6.817 7.981 9.349 10.907 12.585 0x8 2.148 2.551 3.023 3.549 4.186 4.930 5.810 6.779 7.936 9.297 10.846 12.515 0x9 2.136 2.537 3.006 3.529 4.163 4.902 5.778 6.741 7.891 9.244 10.785 12.444 0xa 2.124 2.522 2.989 3.509 4.139 4.875 5.745 6.703 7.847 9.192 10.724 12.374 0xb 2.112 2.508 2.972 3.489 4.116 4.847 5.712 6.664 7.802 9.140 10.663 12.304 0xc 2.100 2.494 2.955 3.469 4.092 4.819 5.680 6.626 7.758 9.088 10.602 12.233 0xd 2.088 2.479 2.938 3.449 4.069 4.791 5.647 6.588 7.713 9.035 10.541 12.163 0xe 2.076 2.465 2.921 3.429 4.045 4.764 5.614 6.550 7.669 8.983 10.480 12.093 0xf 2.064 2.451 2.904 3.410 4.021 4.736 5.582 6.512 7.624 8.931 10.419 12.022 0x10 2.052 2.436 2.887 3.390 3.998 4.708 5.549 6.474 7.579 8.879 10.358 11.952 0x11 2.040 2.422 2.870 3.370 3.974 4.681 5.517 6.436 7.535 8.826 10.298 11.882 0x12 2.027 2.408 2.853 3.350 3.951 4.653 5.484 6.398 7.490 8.774 10.237 11.811 0x13 2.015 2.393 2.836 3.330 3.927 4.625 5.451 6.360 7.446 8.722 10.176 11.741 0x14 2.003 2.379 2.819 3.310 3.904 4.598 5.419 6.322 7.401 8.670 10.115 11.671 0x15 1.991 2.365 2.803 3.290 3.880 4.570 5.386 6.284 7.356 8.618 10.054 11.601 0x16 1.979 2.350 2.786 3.270 3.857 4.542 5.353 6.246 7.312 8.565 9.993 11.530 0x17 1.967 2.336 2.769 3.250 3.833 4.515 5.321 6.207 7.267 8.513 9.932 11.460 0x18 1.955 2.322 2.752 3.230 3.810 4.487 5.288 6.169 7.223 8.461 9.871 11.390 0x19 1.943 2.307 2.735 3.210 3.786 4.459 5.255 6.131 7.178 8.409 9.810 11.319 0x1a 1.931 2.293 2.718 3.190 3.763 4.431 5.223 6.093 7.134 8.356 9.749 11.249 0x1b 1.919 2.279 2.701 3.170 3.739 4.404 5.190 6.055 7.089 8.304 9.688 11.179 0x1c 1.907 2.264 2.684 3.150 3.716 4.376 5.157 6.017 7.044 8.252 9.627 11.108 0x1d 1.895 2.250 2.667 3.130 3.692 4.348 5.125 5.979 7.000 8.200 9.566 11.038 0x1e 1.883 2.236 2.650 3.110 3.669 4.321 5.092 5.941 6.955 8.148 9.505 10.968 0.692 0.810 0.949 1.108 1.28 Low-Voltage Sense 0x21 0.220 0.260 0.308 0.361 0.425 0.504 90 0.593 Platform Manager 2 In-System Programmable Hardware Management Controller Current Monitor Configuration Registers The ASC configuration memory defines the operation of the current monitor (IMON/HIMON) circuitry, described in the Theory of Operation section. The low and high voltage current monitor trip points, glitch filter setting, and window mode are configurable over I2C. The IMON1 (low voltage) also includes a Low-Side bit, which configures the low-side sense setting on IMON1. The configuration registers are described in Table 44. Table 44. Current Monitor Configuration Register Summary Register Address Register Name Bit7 Bit6 0x34 IMON1_Config0 FAST_TH[2:0] 0x35 IMON1_Config1 A_TH[1:0] 0x36 HIMON_Config0 FAST_TH[2:0] 0x37 HIMON_Config1 A_TH[1:0] Bit5 Bit4 GBP B_TH[1:0] Bit3 WM Bit2 Bit1 LSS 0 Bit0 0 A_GAIN[1:0] B_GAIN[1:0] GBP B_TH[1:0] WM X Reconfiguration Details 0 0 Master/Slave (LOAD_CFG_REG supported) A_GAIN[1:0] B_GAIN[1:0] A_TH[1:0], B_TH[1:0], A_GAIN[1:0], B_GAIN[1:0] – Threshold and Gain Setting for A and B Comparators The A and B current monitor trip points are defined by the combination of the threshold and gain settings. Table 45 shows the trip point settings for both the IMON and HIMON current monitor circuits. Table 45. Current Monitor Trip Points (Differential Voltage) A_TH/B_TH[1:0] GAIN[1:0] 00 (GAIN = 100V/V) 01 (GAIN = 50V/V) 10 (GAIN = 25V/V) 11 (GAIN = 10V/V) 00 8 mV 15.5 mV 30.5 mV 75 mV 01 10.5 mV 20.5 mV 40.5 mV 100 mV 10 14.5 mV 28.5 mV 56.5 mV 140 mV 11 20 mV 39 mV 77 mV 190 mV GBP – Glitch Filter Bypass Each of the current monitors include a glitch filter at each of the trip point comparator outputs as shown in Figure 12. This glitch filter can be bypassed dependent on the GBP setting shown in Table 46. Table 46. GBP Setting vs Glitch Bypass Behavior GBP Glitch Filter Setting 0 Glitch Filter On 1 Glitch Filter Bypassed WM – Window Mode Each of the current monitors include a selectable window mode, as described in Table 11. The window mode setting is shown in Table 47. Table 47. WM Setting vs Window Mode Value WM Window Mode 0 Off 1 On 91 Platform Manager 2 In-System Programmable Hardware Management Controller LSS – Low Side Sense Mode The IMON1 current monitor includes a low side sense mode, as shown in Figure 12. The low side sense settings are shown in Table 48. Table 48. LSS Setting vs Low Side Sensing Mode LSS Low Side Sense Mode 0 Disabled 1 Enabled FAST_TH[2:0] - Fast Comparator Threshold The fast trip point for both IMON1 and HIMON is set according to the FAST_TH[2:0] code. Table 49 shows the fast trip point settings vs the FAST_THRESH code for both IMON1 and HIMON current monitor circuits. Table 49. Fast Current Monitor Trip Points (Differential Voltage) FAST_TH[2:0] Trip Point 000 50 mV 001 100 mV 010 150 mV 011 200 mV 100 250 mV 101 300 mV 110 400 mV 111 500 mV 92 Platform Manager 2 In-System Programmable Hardware Management Controller Temperature Monitor Configuration Registers Table 50. Temperature Monitor Configuration Register Summary Register Address 0x38 Register Name TMON1_Config0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reconfiguration Details Ideality_Code[13:6] 0x39 TMON1_Config1 Ideality_Code[5:0] 0x3A TMON1_Config2 Off[8:1] 0x3B TMON1_Config3 Th_A[8:2] 0x3C TMON1_Config4 Th_B[8:3] X Off[0] Th_A[1:0] 0x3D TMON1_Config5 X 0x3E TMON1_Config6 FilterA[3:0] 0x3F TMON1_Config7 X HystA[6:0] 0x40 TMON1_Config8 X HystB[6:0] 0x41 TMON2_Config0 Ideality_Code[13:6] 0x42 TMON2_Config1 Ideality_Code[5:0] 0x43 TMON2_Config2 Off[8:1] 0x44 TMON2_Config3 Th_A[8:2] FLT Th_B[2:0] Cfg[1:0] Off[0] TMON2_Config4 Th_B[8:3] 0x46 TMON2_Config5 X 0x47 TMON2_Config6 FilterA[3:0] 0x48 TMON2_Config7 X HystA[6:0] 0x49 TMON2_Config8 X HystB[6:0] 0x4A TMONint_Config0 Ideality_Code[13:6] 0x4B TMONint_Config1 Ideality_Code[5:0] 0x4C TMONint_Config2 Off[8:1] 0x4D TMONint_Config3 Th_A[8:2] 0x4E TMONint_Config4 Th_B[8:3] X AVE[1:0] FilterB[3:0] 0x45 X Cfg[1:0] Th_A[1:0] FLT AVE[1:0] Th_B[2:0] Master-Only (TMON circuit resets after each time configuration update) FilterB[3:0] Cfg[1:0] Off[0] Th_A[1:0] 0x4F TMONint_Config5 X 0x50 TMONint_Config6 FilterA[3:0] FLT 0x51 TMONint_Config7 X HystA[6:0] 0x52 TMONint_Config8 X HystB[6:0] AVE[1:0] Th_B[2:0] FilterB[3:0] The temperature monitor circuit (TMON) configuration registers can be updated over I2C. The definition and function of these parameters is described in the Temperature Monitor Inputs section. There are nine configuration registers per TMON channel (TMON1, TMON2, and TMON_int). The diode ideality factor, transducer configuration, temperature offset, A and B monitor characteristics (threshold, filter, hysteresis) and measurement averaging and fault behavior are all configurable according to the format in Table 50. A description of how to calculate each parameter follows the register format. The temperature monitor circuit will reset each time a configuration parameter is updated over I2C. Ideality_Code[13:0] - Ideality Factor Setting The Temperature Monitor inputs support a programmable ideality factor (emission coefficient) for interfacing to different remote transistor diodes. The programmable ideality factor is calculated based on a 14-bit code. The allowed range of ideality factors is 0.9 to 2.0, values outside this range are not allowed. Calculating the code for a given ideality factor is done using the following calculation: Ideality_Code (14-bits, converted to binary) = ROUND (4572 / ideality factor) 93 Platform Manager 2 In-System Programmable Hardware Management Controller Table 51 shows some common ideality factors and their corresponding codes. Table 51. Ideality Factor vs Ideality Code Setting Ideality_Code[13:0] Ideality Factor 0x08EE 2.0000 --------- 0x11B6 1.0083 0x11B7 1.0082 0x11B8 1.0079 --------- 0x11C8 1.0044 0x11C9 1.0042 0x11CA 1.0039 --------- 0x11D9 1.0007 0x11DA 1.0004 0x11DB 1.0002 0x11DC 1.0000 0x11DD 0.9998 0x11DE 0.9996 0x11DF 0.9993 --------- 0x13D8 0.9000 Cfg[1:0] - Temperature Monitor Diode Configuration As described in the Temperature Monitor Input section, the TMON supports different transistor-based diode configurations for connection to the ASC Temperature Monitors. The two bit value Tran_cfg[1:0], corresponds to the supported configurations as shown in Table 52. Table 52. Temperature Monitor Diode Configuration Settings Cfg[1:0] Diode Configuration 00 TMON disabled 01 Beta Compensated PNP 10 Differential PNP or NPN 11 Single-Ended (Not recommended) Off[8:0] - Temperature Monitor Offset The TMON supports a 9-bit programmable temperature offset, which is applied to the temperature measurement for both readout and the A and B monitor comparison. The programmable offset range is from –64oC to 63.75oC, with a resolution of 0.25oC. The offset is stored as a 2’s complement number, with the 9th bit as the signed bit. Table 53 shows the settings associated with several different offset temperatures. 94 Platform Manager 2 In-System Programmable Hardware Management Controller Table 53. Temperature Monitor Offset Settings Off[8:0] Offset Temperature oC 0x0FF 63.75 0x0FE 63.50 ------------------------- 0x002 0.50 0x001 0.25 0x000 0.00 0x1FF –0.25 0x1FE –0.50 ------------------------ 0x101 –63.75 0x100 –64.00 Th_A[8:0], Th_B[8:0] - Comparator Thresholds for A and B alarms The TMON includes two individually programmable comparators, TMONA and TMONB. The 9-bit alarm thresholds range for each of these monitors is –64oC to 155oC, with a resolution of 1oC. The thresholds are stored as 2’s complement numbers, with the 9th bit as the signed bit. Values above 155oC or below –64oC are not valid threshold settings. Table 54 shows the settings associated with several different threshold temperatures. Table 54. Temperature Monitor Thresholds Settings Th_A / Th_B[8:0] Threshold Temperature oC 0x09B 155 0x09A 154 ------------------------- 0x002 2 0x001 1 0x000 0 0x1FF –1 0x1FE –2 ------------------------ 0x1C1 –63 0x1C0 –64 FLT - Fault Reading Setting The TMON circuit includes open and short fault detection circuitry for the remote diode channels. (The fault detect is not applicable for the internal temperature monitor, TMON_INT). The 1-bit programmable fault setting determines the measurement readout behavior of both open and short faults. The readout values compared to the fault setting is shown in Table 55. Table 55. Temperature Monitor Fault Setting FLT Short Condition Reading Open Condition Reading °C Code °C Code 0 255.75 0x3FF –255.75 0x401 1 –255.75 0x401 255.75 0x3FF 95 Platform Manager 2 In-System Programmable Hardware Management Controller AVE[1:0] - Average Filter Coefficient The TMON temperature measurement can be read out over I2C. The TMON circuit includes a programmable exponential averaging filter that is applied before the measurement readout. The Average parameter can be programmed to three different averaging coefficients, as shown in Table 56. Table 56. Temperature Monitor Measurement Average Settings AVE[1:0] Coefficient 00 1 01 8 10 16 11 N/A FilterA[3:0] / FilterB[3:0] - Monitor Alarm Filter The TMONA and TMONB comparators each support programmable monitor alarm filters. The depth of the alarm filter can be programmed between 1 and 16, based on the Filter[3:0] setting. The relationship between the filter code and the filter depth is given by the following equation: DEPTH = Filter[3:0] + 1 HystA[3:0] / HystB[3:0] - Temperature Monitor Hysteresis The TMONA and TMONB comparators each support programmable temperature hysteresis. The 7-bit hysteresis range for each of these monitors is –64oC to 63oC, with a resolution of 1oC. (The negative hysteresis range should be applied to over-temperature comparisons, while the positive hysteresis should be applied to under-temperature comparisons.) The hysteresis settings are stored as 2’s complement numbers, with the 7th bit as the signed bit. Table 57 shows the settings associated with several different hysteresis temperatures. Table 57. Temperature Monitor Hysteresis Settings Temperature Hysteresis oC Hyst[6:0] 0x3F 63 0x3E 62 ----------------- 0x02 2 0x01 1 0x00 0 0x7F –1 0x7E –2 ----------------- 0x41 –63 0x40 –64 96 Platform Manager 2 In-System Programmable Hardware Management Controller High Voltage Output (HVOUT) Configuration Registers Table 58. High Voltage Output Configuration Register Summary Register Address Register Name Bit7 OCB Bit6 1 Bit5 Bit4 I_SRC[1:0] Bit3 Bit2 0x53 HVOUT1_Config0 0x54 HVOUT1_Config1 SW FR OD 0x55 HVOUT2_Config0 OCB 1 I_SRC[1:0] I_SNK[1:0] 0x56 HVOUT2_Config1 SW FR OD DUTY[3:0] 0x57 HVOUT3_Config0 OCB 1 I_SRC[1:0] 0x58 HVOUT3_Config1 SW FR OD 0x59 HVOUT4_Config0 OCB 1 I_SRC[1:0] I_SNK[1:0] 0x5A HVOUT4_Config1 SW FR OD DUTY[3:0] X I_SNK[1:0] Bit1 Bit0 Reconfiguration Details VPP[1:0] DUTY[3:0] X X I_SNK[1:0] VPP[1:0] VPP[1:0] Master/Slave (LOAD_CFG_REG supported) DUTY[3:0] X VPP[1:0] The High Voltage Output pins (HVOUT) configuration registers can be updated over I2C. The definition and function of these parameters is described in the High Voltage Outputs section. There are two configuration registers per HVOUT (HVOUT1, HVOUT2, HVOUT3, HVOUT4). The open-drain/charge pump setting, charge pump voltage, source and sink current, switched/static mode, and switched mode duty cycle and frequency are all configurable according to the format in Table 58. A description of how to calculate each parameter follows the register format. OCB - Output Control Block Source The OCB parameter is used to select the control signal source for the HVOUT pin from either the Output Control Block (OCB) or the ASC-I/F. Table 59 shows the available settings. Table 59. OCB Setting vs HVOUT Source Selection OCB HVOUT Source 0 ASC-I/F Signal 1 OCB I_SRC[1:0] - HVOUT Source Current The I_SRC[1:0] setting is used to choose between the four supported source currents for the HVOUT in charge pump mode. The available choices are shown in Table 60. Table 60. HVOUT Source Current Settings I_SRC[1:0] Output Source Current 00 12.5 uA 01 25 uA 10 50 uA 11 100 uA I_SNK[1:0] - HVOUT Sink Current The I_SNK[1:0] setting is used to choose between the four supported sink currents for the HVOUT in charge pump mode. The available choices are shown in Table 61. 97 Platform Manager 2 In-System Programmable Hardware Management Controller Table 61. HVOUT Sink Current Settings I_SNK[1:0] Output Sink Current 00 100 uA 01 250 uA 10 500 uA 11 3000 uA VPP[1:0] - Charge Pump Output Voltage Settings The VPP[1:0] setting is used to choose between the four programmable output voltage levels for the HVOUT in charge pump mode. The available choices are shown in Table 62. Table 62. HVOUT Output Voltage Settings VPP[1:0] Output Voltage 00 6V 01 8V 10 10 V 11 12 V SW - Switched Output Setting The SW parameter configures the HVOUT pin for either static drive mode (on or off) or switched mode (either switched at the programmed frequency and duty, or off). Table 63 shows the available settings. Table 63. SW Setting vs HVOUT Mode SW HVOUT Mode 0 On/Off 1 Switched FR - Output Frequency Select (Switched Mode Only) The FR parameter configures the output frequency of the HVOUT when the device is placed in switched mode. Table 64 shows the available settings. Table 64. FR Setting vs HVOUT Output Frequency (Switched Mode only) FR Frequency 0 31.25 kHz 1 15.625 kHz OD - Open Drain Output Mode Setting The OD parameter is used to configure the output mode of the device. Table 65 shows the available settings. Table 65. OD Setting vs HVOUT Output Mode OD HVOUT Output Mode 0 Charge-Pump Mode 1 Open-Drain Mode 98 Platform Manager 2 In-System Programmable Hardware Management Controller DUTY[3:0] - Duty Cycle Selection (Switched Mode Only) The Duty_Cycle[3:0] setting is used to choose between the sixteen programmable duty cycles for the HVOUT in switched mode. The available choices are shown in Table 66. Table 66. HVOUT Switched Output Duty Cycle Settings Duty_Cycle[3:0] Duty Cycle % 0x0 6.25% 0x1 12.5% 0x2 18.75% 0x3 25% 0x4 31.25% 0x5 37.55% 0x6 43.75% 0x7 50.00% 0x8 56.25% 0x9 62.50% 0xA 68.75% 0xB 75.00% 0xC 81.25% 0xD 87.50% 0xE 93.75% 0xF 50.00% 99 Platform Manager 2 In-System Programmable Hardware Management Controller Output Control Block Configuration Registers Table 67. Output Control Block Configuration Register Summary Register Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reconfiguration Details 0x5B OCB_Config0 GPIO3_src[3:0] GPIO2_src[2:0] 0x5C OCB_Config1 HVOUT2_src[3:0] HVOUT1_src[3:0] 0x5D OCB_Config2 HVOUT4_src[3:0] HVOUT3_src[3:0] 0x5E OCB_Config3 X X Master/Slave IM_HCM_CTRL[2:0] HI_HCM_CTRL[2:0] (LOAD_CFG_REG supported) 0x5F OCB_Config4 X X V6_HCM_CTRL[2:0] V5_HCM_CTRL[2:0] 0x60 OCB_Config5 X HI_T H4i H3i H2i H1i G3i G2i The Output Control Block (OCB) configuration registers can be updated over I2C. The definition and function of these parameters is described in the “Output Control Block” section. There are 6 total configuration registers for the output control block. The settings in the six registers define the operation of the output control block output muxes, the hysteretic control muxes, and the dynamic threshold management. Registers 0x5B-0x5D define the out control muxes according to the format shown in Table 67. OUTPUT_src[3:0] - Output Channel Source Signal Select The output control source for each of the six OCB based outputs is defined by the four bit _src[3:0] code. The outputs selected by each code are shown in Table 68. Table 68. Output Control Block – Output Source Signals OUTPUT_src[3:0] Source Signal 0x0 ASC-I/F 0x1 I2C 0x2 GPIO5 0x3 GPIO6 0x4 GPIO7 0x5 GPIO8 0x6 GPIO9 0x7 GPIO10 0x8 HIMON_F 0x9 IMON1_F 0xA VMON_4A 0xB VMON_9A 0xC HIMON_HCM 0xD IMON1_HCM 0xE VMON5_HCM 0xF VMON6_HCM 100 Platform Manager 2 In-System Programmable Hardware Management Controller HCM_CTRL - Hysteretic Mux Configuration for IMON1, HIMON, VMON6 and VMON5 Registers 0x5E and 0x5F define the control signal inputs for the 4 Hysteretic Control Muxes (HCM). The register format is shown in Table 67. The control signals selected by the _HCM_CTRL[2:0] code are shown in Table 69. Table 69. Output Control Block – Hysteretic Control Mux Settings HCM_CTRL[2:0] ASC-I/F Source Signal 000 GPIO2 001 GPIO3 010 HVOUT1 011 HVOUT2 100 HVOUT3 101 HVOUT4 110 N/A 111 N/A H4i / H3i / H2i / H1i/ G3i / G2i - Output Invert Control The OCB outputs can be inverted with respect to their control signals. As shown in Table 67, the register 0x60 defines the programmable invert option for each of the outputs.The invert setting parameter is shown in Table 70. Table 70. H4i … G2i Setting vs OCB Output Behavior H4i / H3i / H2i / H1i/ G3i / G2i OCB Output 0 Normal 1 Inverted HI_T - HIMON_A Threshold Source Register 0x60 also defines the programmable threshold source select for the HIMON circuit. The threshold source can be selected as either the configuration memory or the ASC-I/F, as shown in Table 71. Table 71. HI_T Setting vs HIMONA Threshold Source HI_T HIMONA Threshold Source 0 Configuration Memory 1 ASC-I/F 101 Platform Manager 2 In-System Programmable Hardware Management Controller GPIO Input Configuration Registers Table 72. GPIO Input Configuration Register Summary Register Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x62 GPIO_Config0 X G4in X G3in X G2in X G1in 0x63 GPIO_Config1 X G8in X G7in X G6in X G5in 0x64 GPIO_Config2 X X X X X G10in X G9in Reconfiguration Details Master/Slave (LOAD_CFG_REG supported) The GPIO pins can be configured as input or output. The GPIO configuration registers can be updated over I2C. The registers at addresses 0x62, 0x63, and 0x64 include single configuration bit for each of the GPIO. When the device is configured as an input, the GPIO pin is put into a Hi-Z state and a weak pulldown is enabled. The input setting is described in Table 73. The input status can still be read at the pin, regardless of the Gxin setting. The format for registers 0x62, 0x63, and 0x64 is shown in Table 72. Table 73. Gxin Setting vs GPIO Input Setting Gxin GPIO Setting 0 Output – Weak Pulldown Disabled 1 Input – Weak Pulldown Enabled Write Protect and User Tag Configuration Register Table 74. Write Protect and User Tag Configuration Register Register Address Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 0x66 WRITEPROTECT_USERTAG X X X X X UT_E N Bit1 Bit0 WP[1:0] Reconfiguration Details Read Only The Write Protect and User Tag modes are defined by the bit settings in register 0x66 (shown in Table 74). This register cannot be written using the configuration register commands. It can only be overwritten in the EEPROM memory. UT_EN - User Tag Enable The UT_EN bit configures the device for either User Tag Memory mode or Fault Logging mode, as described in Table 75. The User Tag and Fault Log features are described in more details in the Fault Logging and User Tag Memory section Table 75. UT_EN vs Fault Log / User Tag Mode UT_EN Fault Log / User Tag Mode 0 Fault Log Enabled / User Tag Disabled 1 User Tag Enabled / Fault Log Disabled 102 Platform Manager 2 In-System Programmable Hardware Management Controller WP[1:0] - Write Protect Setting The write protect setting bits are defined in Table 76. The write protect function is described in detail later in the I2C Write Protection section. Table 76. Write Protect Settings WP[1:0] Write Protect Settings 00 No protection 01 No protection 10 Protection based on GPIO1 level 11 I2C write disabled User Electronic Signature (UES) Registers Table 77. UES Memory Summary Register Address Register Name Bit7 Bit6 0x70 UES0 UES[7:0] 0x71 UES1 UES[15:8] 0x72 UES2 UES[23:16] 0x73 UES3 UES[31:24] 0x74 UES4 UES[39:32] 0x75 UES5 UES[47:40] 0x76 UES6 UES[55:48] 0x77 UES7 UES[63:56] Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reconfiguration Details EEPROM Read Only The ASC includes a User Electronic Signature feature in the EEPROM memory of the device. This consists of 64bits that can be configured by the user to store unique data such as ID codes, revision numbers, or inventory control data. The UES code can only be written and readout using the EEPROM memory access commands. The UES storage format is shown in Table 77. Reserved Configuration Addresses The configuration memory map includes several reserved addresses, which should not be read or written to. The reserved addresses are shown in Table 78 below. Table 78. Reserved Configuration Addresses Register Address Register Name 0x61 RESERVED Bit7 Bit6 Bit5 Bit4 Bit3 RESERVED 0x65 RESERVED RESERVED 0x67-0x6F RESERVED RESERVED 0x78-0xFF RESERVED RESERVED 103 Bit2 Bit1 Bit0 Reconfiguration Details Do not read or write to these addresses Platform Manager 2 In-System Programmable Hardware Management Controller Closed Loop Trim Register Access The Trim and Margin block provides for I2C access to write closed loop trim profile 0 target values for each Trim channel on-chip as shown in Table 79. The 12-bits of each closed trim setpoint register can be updated and read back atomically using the dedicated instructions below. Table 79. Closed Loop Trim Access Instructions Instruction Code Instruction Name Read/Write Description 0x41 TRIM1_CLT_P0_SET R/W Update and readback of TRIM1 closed loop trim profile 0 setpoint register[11:0] 0x42 TRIM2_CLT_P0_SET R/W Update and readback of TRIM2 closed loop trim profile 0 setpoint register[11:0] 0x43 TRIM3_CLT_P0_SET R/W Update and readback of TRIM3 closed loop trim profile 0 setpoint register[11:0] 0x44 TRIM4_CLT_P0_SET R/W Update and readback of TRIM4 closed loop trim profile 0 setpoint register[11:0] The format for these instructions is shown in Figure 53 below. Figure 53. TRIMx_CLT_P0_SET - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x4x TRIM HIGH BYTE TRIM LOW BYTE A D[7:0] A D[11:8] A Sr A[6:0] TRIM HIGH BYTE TRIM LOW BYTE SLAVE ADDRESS R A D[7:0] A D[11:8] NA P The new trim target will be latched in the hardware at the completion of this sequence. The Trim targets are 12-bit numbers where each bit corresponds to 2 mV. See the Closed Loop Trim Configuration Registers section for details on calculating the trim target voltage. Measurement and Control Register Access The measurement and control section of the ASC is accessed via two different I2C instructions. The WRITE_MEAS_CTRL instruction is used to write the measurement selection for voltage and current measurements, the selection for reading the monitor status, and the control selection for the output control block. The READ_MEAS_CTRL is used to read the measurement result selected by the WRITE_MEAS_CTRL instruction. The instructions are used to access the register set shown in Table 80. The instructions use the register addresses in Table 80 and follow the format shown in Figure 54 for WRITE_MEAS_CTRL and Figure 55 for READ_MEAS_CTRL. Figure 54. WRITE_MEAS_CTRL - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x51 REGISTER ADDRESS A R_A[7:0] DATA [ADDRESS] A D[7:0] 104 A P Platform Manager 2 In-System Programmable Hardware Management Controller Figure 55. READ_MEAS_CTRL - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x52 A R_A[7:0] A Sr A[6:0] DATA [ADDRESS +1] DATA [ADDRESS] SLAVE ADDRESS REGISTER ADDRESS R A D0[7:0] A D1[7:0] A* P Optional: Read up to 8 additional data bytes * After final data byte read, master should NACK before issuing the STOP command. The measurement and control register address map is shown in Table 80. These register are used to read voltage and current measurements from the ADC, read temperature measurements from the TMON circuit, and control I/Os configured for I2C control. These registers should not be confused with the configuration registers, which are accessed with a different set of instructions and comprise a completely separate 8-bit address space. Table 80. Measurement and Control Register Overview Register Address Register Name Read/Write R/W Description Value after POR 0x00 adc_mux ADC Attenuator and SEL[4:0] 0000 0000 0x01 adc_value_low 0x02 adc_value_high R ADC Result [4:0] and status 0000 0000 R ADC Result [12:5] 0000 0000 0x03 imon_average_ctrl 0x04 imon_average_select R/W Average Control [3:0] 0000 0000 R/W IMON MUX[1:0] 0000 0000 0x05 imon_average_result_low R IMON moving average [7:0] 0000 0000 0x06 imon_average_result_hig h R IMON moving average [9:8] 0000 0000 0x07 monitor_select R/W Monitor Select[3:0] 0000 0000 0x08 monitor_ record R Monitor Record[7:0] 0000 0000 0x09-0x6F RESERVED 0x70 output_control_block HVOUT1-4 and GPIO2-3 control 0000 0000 0x71-0x7F RESERVED 0x80 tmon_meas_1_high R TMON_1 Measurement [15:8] 1110 0000 0x81 tmon_meas_1_low R TMON_1 Measurement [7:5] 0000 0000 0x82 tmon_meas_2_high R TMON_2 Measurement [15:8] 1110 0000 0x83 tmon_meas_2_low R TMON_2 Measurement [7:5] 0000 0000 0x84 tmon_meas_int_high R TMON_int Measurement [15:8] 1110 0000 0x85 tmon_meas_int_low1 R TMON_int Measurement [7:5] 0000 0000 0x86 tmon_stat_a1 R TMON_A Status [2:0] 0000 0000 0x87 tmon_stat_b R TMON_B Status [2:0] 0000 0000 0x88-0xFF RESERVED R/W 1. Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed by an additional READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C read command. 105 Platform Manager 2 In-System Programmable Hardware Management Controller The registers shown in Figure 56 are provided for interfacing to the ADC. Figure 56. ADC Registers 0x00 – ADC_MUX (Read/Write) ATTEN 0 0 SEL4 SEL3 SEL2 SEL1 SEL0 b7 b6 b5 b4 b3 b2 b1 b0 0x01 – ADC_VALUE_LOW (Read) D4 D3 D2 D1 D0 Pending Active Done b7 b6 b5 b4 b3 b2 b1 b0 0x02 – ADC_VALUE_HIGH (Read) D12 D11 D10 D9 D8 D7 D6 D5 b7 b6 b5 b4 b3 b2 b1 b0 To perform an A/D conversion, one must set the input attenuator and channel selector. For VMON input voltage conversions, two input ranges may be set using the attenuator, 0-2.048V and 0-5.9V. For conversion of the HVMON input voltage, the available attenuator ranges are 0-8.192V and 0-13.2V. These settings are shown in Table 81. Table 81. ADC Input Attenuator Control VMON1-VMON9 ATTEN(ADC_MUX.b7) HVMON Resolution Full Scale Range Resolution Full Scale Range 0 2 mV 0-2.048 V 8 mV 0-8.192 1 6 mV 0-5.9 V 16 mV 0-13.2 The input selector may be set to monitor any of the VMON input voltages, the VCCA or VDC supply voltage, or the IMON differential voltages. The selectable input channels are shown in Table 82. Do not read or write to ADC_MUX selections not shown in the table. Table 82. ADC Input Selection SEL[4:0] (ADC_MUX Selection) Input Channel 0x00 VMON1 0x01 VMON2 0x02 VMON3 0x03 VMON4 0x04 VMON5 0x05 VMON6 0x06 VMON7 0x07 VMON8 0x08 VMON9 0x09 HVMON 0x0C VCCA 0x0F VDC (Attenuated by 8) 0x10 IMON1 0x13 HIMON 106 Platform Manager 2 In-System Programmable Hardware Management Controller Writing a value to the ADC_MUX register using the WRITE_MEAS_CTRL instruction to set the input attenuator and selector will automatically initiate a conversion. The PENDING bit will be set to 1 when a conversion is requested but not yet active. The ACTIVE bit will be set to 1 when the requested conversion is the active conversion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.b0) will be reset to 0. When the conversion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by performing two I2C read operations using the READ_MEAS_CTRL instruction; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion instruction only after the completion of the current conversion operation (Waiting for the DONE bit to be set to 1). The example flow below shows the necessary instructions to complete an ADC read. Voltage Monitor ADC Readout Over I2C 1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x00, and the ADC Channel and Attenuator setting from Table 82. This will initiate the ADC conversion. 2. Perform an I2C Read Operation with Instruction 0x52, Register Address 0x01 to check that the DONE bit is set. Repeat if Register 0x01, bit 0 is not set to 1. Read ADC Data[4:0] for ADC low byte. 3. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x02 to read ADC Data [12:5] for ADC high byte The Current Monitor (IMON1 and HIMON) averaging measurement hardware is also accessed through the I2C interface. The IMON1/HIMON averaging is controlled by dedicated hardware and is managed separately from the single conversion IMON1/HIMON access through the ADC registers. The IMON1/HIMON averaging registers are shown in Figure 57. Figure 57. IMON Average Control Registers 0x03 – IMON_AVG_CTRL (Read/Write) 0 0 HIMON AVG_EN 0 0 IMON1 AVG_EN SMPL_ INT_1 SMPL_ INT_0 b7 b6 b5 b4 b3 b2 b1 b0 0x04 – IMON_AVG_SELECT (Read/Write) 0 0 0 0 0 0 SEL1 SEL0 b7 b6 b5 b4 b3 b2 b1 b0 0x05 – IMON_AVG_RESULT_LOW (Read) D7 D6 D5 D4 D3 D2 D1 D0 b7 b6 b5 b4 b3 b2 b1 b0 0x06 – IMON_AVG_RESULT_HIGH (Read) 0 0 0 0 0 0 D9 D8 b7 b6 b5 b4 b3 b2 b1 b0 To perform a moving average read, first enable the moving average for the given channel in the IMON_AVG_CTRL register. When the averaging is enabled the averaging hardware will begin to compute a binary exponential weighted moving average, as shown below: CurrentMeas x 7 CurrentAve x = ---------------------------------------------- + CurrentAve x – 1 --8 8 107 Platform Manager 2 In-System Programmable Hardware Management Controller The IMON_AVG_CTRL register is used to enable the averaging operation and set the sample period of the averaging. The HIMON and IMON1 averaging operations are enabled independently by setting the HIMON_AVG_EN and IMON1_AVG_EN respectively. Setting these bits to 1 enables the 1/8 moving averaging for that input channel. The SMPL_PER[1:0] is used to select the sampling interval from the values shown in Table 83. Table 83. IMON Average Sample Interval Values SMPL_INT[1:0] Sample Interval 00 1 ms 01 2 ms 10 4 ms 11 8 ms Once the averaging is enabled, the IMON_AVG_SELECT register is used to select between the HIMON and IMON1 average values for readout (see Table 84). Table 84. Selected IMON Average Readout Channel SELECT[1:0] Channel 00 IMON1 01 Not Used 10 Not Used 11 HIMON After writing to the IMON_AVG_SELECT register, the selected channels 10-bit moving average can be read out of the IMON_AVG_RESULT_LOW and IMON_AVG_RESULT_HIGH registers. The value in the IMON_AVG_SELECT register will remain active until overwritten by another I2C instruction (or power on reset). The updated 10-bit moving average for the previously selected channel can be readout from the result registers without re-writing the SELECT register. Current Monitor Moving Average Readout Over I2C 1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x03, and enable the HIMON averaging and configure the sampling period. This will enable the HIMON averaging. See Table 83 and Table 84. 2. Moving average results are available immediately based on limited samples. Waiting additional sample periods ensures that the averaging filter has time to settle. After enough time has elapsed, perform an I2C Write Operation with Instruction 0x51, Register Address 0x04, and select the HIMON channel for readout. 3. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x05 to read IMON_AVG_RESULT_LOW[7:0] for HIMON low byte. 4. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x06 to read IMON_AVG_RESULT_HIGH[9:8] for HIMON high byte. The status of the voltage, current, and temperature monitor alarms, as well as the GPIO input status, can be read out over I2C. Access to the alarm signals is controlled by the MONITOR_SELECT register. To read out the alarm or GPIO status over I2C, write the applicable selection to the MONITOR_SELECT register as shown in Table 85. After writing the corresponding value to the MONITOR_SELECT, you can read the monitor signal status from the MONITOR_RECORD register. These registers are shown in Figure 58. The MONITOR_SELECT also includes a valid bit. This bit is set to 1 once the MONITOR_RECORD register includes the monitor signals selected in the MONITOR_SELECT register. The monitor signals are refreshed much faster than the I2C access time, so normally the valid bit will read as 1. If the device is in safe state and ASC-I/F communication has not started properly, the valid bit will read as 0. The MONITOR_RECORD register will continue to include the latest status of the specified alarm signals, as specified in the MONITOR_SELECT register. 108 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 58. Monitor Signal Access Registers 0x07 – MONITOR_SELECT (Read/Write) Valid 0 0 0 SEL3 SEL2 SEL1 SEL0 b7 b6 b5 b4 b3 b2 b1 b0 0x08 – MONITOR_RECORD (Read) D7 D6 D5 D4 D3 D2 D1 D0 b7 b6 b5 b4 b3 b2 b1 b0 The register map of the monitor data is shown in Table 85 below. An example for how to read out selected data is shown after the table. Table 85. MONITOR_RECORD Byte Selection MONITOR_RECORD[7:0] MONITOR_ SELECT [3:0] D7 D6 D5 D4 D3 D2 D1 D0 0x0 0 Fault_Log_ Full Fault_Log_ Busy 0 0 1 X 1 0x1 AGOOD GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 0x2 GPIO3 GPIO2 GPIO1 HVOUT4 HVOUT3 HVOUT2 HVOUT1 HIMON_b 0x3 HIMON_a IMON1_b IMON1_a HVMON_b HVMON_a VMON9_b VMON9_a VMON8_b 0x4 VMON8_a VMON7_b VMON7_a VMON6_b VMON6_a VMON5_b VMON5_a VMON4_b 0x5 VMON4_a VMON3_b VMON3_a VMON2_b VMON2_a VMON1_b VMON1_a TMON2_b 0x6 TMON2_a TMON1_b TMON1_a TMONint_b TMONint_a 1 0 1 Monitor Record Readout Over I2C 1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x07, and write the selected data byte for readout. This will populate the MONITOR_RECORD register, Address 0x08, with the latest sampled data of the chosen bits as described in Table 85. 2. Perform an I2C Read Operation with Instruction 0x52, Register Address 0x08 to read the selected Monitor Record. The output signals for HVOUT1-4 and GPIO2-3 can be controlled via I2C instruction, dependent on their Output Control Block configuration. The OUTPUT_CONTROL_BLOCK register (shown in Figure 59) is used to set the I2C control input to the Output Control Block. Outputs which are not configured for I2C control will ignore the setting in the I2C register. See the Output Control Block section for more details. Figure 59. Output Control Block Register 0x70 – OUTPUT_CONTROL_BLOCK (Read/Write) 0 0 HVOUT4 HVOUT3 HVOUT2 HVOUT1 GPIO3 GPIO2 b7 b6 b5 b4 b3 b2 b1 b0 Several registers are provided for accessing the temperature monitor measurements. Each temperature monitor channel has a TMON_MEAS_CHx_LO and TMON_MEAS_CHx_HI register for accessing the 11-bit temperature reading (shown in Figure 60). Provided the temperature monitor is enabled, these registers are updated automatically with the latest temperature reading. The update rate of the temperature reading is dependent on the number of channels enabled (see the Temperature Monitors section for more details). 109 Platform Manager 2 In-System Programmable Hardware Management Controller The temperature measurement hardware will latch its latest reading after the TMON_MEAS_CHx_HIGH byte is read over I2C. This will ensure that the corresponding TMON_MEAS_CHx_LOW byte is from the same measurement as the TMON_MEAS_CHx_HIGH byte. The HIGH byte should be read first in the I2C transaction, followed by the LOW byte. This will ensure the two bytes are from the same measurement reading. Figure 60. Temperature Monitor Measurement Registers 0x80 – TMON_MEAS_CH1_HIGH (Read) D10 D9 D8 D7 D6 D5 D4 D3 b7 b6 b5 b4 b3 b2 b1 b0 0x81 – TMON_MEAS_CH1_LOW (Read) D2 D1 D0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0x82 – TMON_MEAS_CH2_HIGH (Read) D10 D9 D8 D7 D6 D5 D4 D3 b7 b6 b5 b4 b3 b2 b1 b0 0x83 – TMON_MEAS_CH2_LOW (Read) D2 D1 D0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0x84 – TMON_MEAS_INT_HIGH (Read) D10 D9 D8 D7 D6 D5 D4 D3 b7 b6 b5 b4 b3 b2 b1 b0 0x85 – TMON_MEAS_INT_LOW (Read) D2 D1 D0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 The format of the 11-bit temperature measurement is shown in Table 86 along with some example values. The measurement format is 2-complement, with bit D10 used as the sign bit. The measurement resolution is 0.25oC per bit. Temperature monitor circuits which are reset or disabled will always readout –64oC. Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed by an additional READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C read command. 110 Platform Manager 2 In-System Programmable Hardware Management Controller Table 86. Temperature Measurement Data Format D[10:0] Measured Temperature (oC) 0x3FF 160.00* 0x26C 155.00 0x26B 154.75 ------------------------- 0x002 0.50 0x001 0.25 0x000 0.00 0x7FF –0.25 0x7FE –0.50 ------------------------ 0x701 –63.75 0x700 –64.00* Note: Measurements above 160oC will limit to 0x3FF. There is no lower limit, although the TMON accuracy is unguaranteed below –64oC. The temperature monitor alarm signals are also available to be read out over I2C directly. The A comparator alarm signals for each temperature monitor can be read out from the TMON_STAT_A register while the B comparator alarm signals can be read out from the TMON_STAT_B. The register format is shown in Figure 61. Figure 61. Temperature Monitor Status Registers 0x86 – TMON_STAT_A (Read) 0 0 0 0 0 TMONINT_A TMON2_A TMON1_A b7 b6 b5 b4 b3 b2 b1 b0 0x87 – TMON_STAT_B (Read) 0 0 0 0 0 TMONINT_B TMON2_B TMON1_B b7 b6 b5 b4 b3 b2 b1 b0 Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed by an additional READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C read command. 111 Platform Manager 2 In-System Programmable Hardware Management Controller User Tag Memory Access The I2C interface is used to access the User Tag memory feature of the ASC. The User Tag memory block consists of a 7 byte User Tag register, a programming hardware block, and a 16 row x 7 byte EEPROM memory. The User Tag memory block architecture is shown in Figure 62, along with the I2C access instructions. The User Tag feature cannot be used when the ASC Fault Log is enabled. These features use the same memory array and only one of the two features can be enabled at a given time. The User Tag instructions shown below are only applicable for accessing the memory in User Tag mode. Access to the memory in Fault Log Mode should follow the Fault Log instructions detailed in the next section. Table 87 shows the User Tag access instructions. The instructions are used to access either the User Tag register or the User Tag EEPROM memory block. Accessing the User Tag memory requires that the ASC is placed into programming mode (see the ENABLE_PROG instruction). The format for each instruction is in the section that follows. Table 87. User Tag Memory Access Instructions Instruction Code 0x61 Instruction Name Read/Write Description ERASE_USER_TAG_EEPROM W Erase the User Tag EEPROM array 0x62 WRITE_USER_TAG_REG W Write to the User Tag data register 0x63 READ_USER_TAG_REG R Read out the contents of the User Tag data register 0x64 PROG_USER_TAG_EEPROM W Program the selected row of EEPROM bits with the tag data register 0x65 READ_USER_TAG_EEPROM R Read out the selected row of User Tag EEPROM bits Figure 62. User Tag Memory Architecture with I2C Instruction Access USER TAG EEPROM USER TAG REGISTER READ_USER_TAG_EEPROM (ROW_ADDR[7:4]) WRITE_USER_TAG_REG (BYTE0-BYTE7) 7 BYTES 16 ROWS x 7 BYTES Program Row READ_USER_TAG_REG (BYTE0-BYTE7) PROG_USER_TAG_EEPROM (ROW ADDR[7:4]) ERASE_USER_TAG_EEPROM The ERASE_USER_TAG_EEPROM instruction is used to erase the entire User Tag EEPROM array. The User Tag can only be erased as a full block. A row must be erased prior to programming it. The instruction format for ERASE_USER_TAG_EEPROM is shown in Figure 63. Figure 63. ERASE_USER_TAG_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x71 A P The User Tag EEPROM is programmed in a two-step process. First the data which is to be programmed is written into the User Tag register space, as shown in Figure 64. Up to 7 bytes (known as a data “row”) can be written into the User Tag register space in a single write transaction. The WRITE_USER_TAG_REG instruction is used for writing the User Tag register space. 112 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 64. WRITE_USER_TAG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x62 DATA BYTE_0 A DATA BYTE_1 D0[7:0] A D1[7:0] A P Optional: Write up to 6 additional data bytes The READ_USER_TAG_REG instruction is used to read out the User Tag register bytes as shown in Figure 65. Up to 7 bytes can be read out from the User Tag register space in a single read transaction. The bytes are read back in order from byte 0 to byte 6. Figure 65. READ_USER_TAG_REG - I2C Instruction Format SLAVE ADDRESS S A[6:0] W A 0x63 A Sr A[6:0] DATA BYTE_1 DATA BYTE_0 SLAVE ADDRESS INSTRUCTION CODE R A D0[7:0] A D1[7:0] A* P Optional: Read up to 6 additional data bytes * After final data byte read, master should NACK before issuing the STOP command The second step of the User Tag programming is writing to the EEPROM from the User Tag registers. This is accomplished using the PROGRAM_USER_TAG_EEPROM instruction. The data in the User Tag registers is copied by the programming block to the EEPROM row specified by the R_A[7:4] bits in the data byte as shown in Figure 66. The 4 bit code corresponds to Row 0 to Row 15 in the User Tag EEPROM memory block, as shown in the User Tag block diagram in Figure 62. Figure 66. PROG_USER_TAG_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x64 ROW ADDRESS* A R_A[7:0] A P Note: The Row Address R_A[7:0] contains the 4-bit address code in bits [7:4]. Bits [3:0] are always zero. The READ_USER_TAG_EEPROM I2C instruction provides the mechanism to readback data stored in the User Tag memory. The READ_USER_TAG_EEPROM is a two step read transaction operation. In the first step, a write transaction is performed with the 0x65 instruction, and a 4-bit address code [7:4]. The address code corresponds to Row 0 to Row 15 as shown in the User Tag block diagram in Figure 67. In the second step, the row can be read out in 7 bytes, from byte 0 to byte 6, using a read transaction. The row address will auto-increment to support reading multiple rows in a single transaction. This means a single transaction can support reading the entire user tag array, if the starting address of Row 0 is used. A stop condition will complete the read transaction, this can be issued after any number of rows and bytes have been read. Figure 67. READ_USER_TAG_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x65 A R_A[7:0] A Sr A[6:0] DATA BYTE1 [ROW_ADDR] DATA BYTE0 [ROW_ADDR] SLAVE ADDRESS ROW ADDRESS* R A D0[7:0] A D1[7:0] A* P Optional: Read 6 additional bytes for complete record, Read 112 data bytes (16 rows by 7 bytes) for the entire fault log memory. * After final data byte read, master should NACK before issuing the STOP command 113 Platform Manager 2 In-System Programmable Hardware Management Controller User Tag Access Example This example describes the steps necessary to program 7 Data Bytes to Row 4 of the EEPROM array: 1. Perform an I2C Write with the ENABLE_PROG instruction (0x04), with the 2-byte key code 0xE53D. This will place the chip in programming mode, a required step for User Tag access. 2. (Optional) Perform an I2C Write with the ERASE_USER_TAG_EEPROM instruction (0x61). This is only required if data has already been written to Row 4. 3. Perform an I2C Write with the WRITE_USER_TAG_REG instruction (0x62), with the 7 data bytes to be written. 4. Optional) Perform an I2C Read with the READ_USER_TAG_REG instruction (0x63) to confirm that the 7 Data Bytes were properly written the USER_TAG_REGISTER. 5. Perform an I2C Write with the PROGRAM_USER_TAG_EEPROM instruction (0x64), with an R_A[0x40], row address 4. This copies the data from the USER_TAG_REG into Row 4 of the USER_TAG_EEPROM array. 6. (Optional) Perform an I2C Read with the READ_USER_TAG_EEPROM instruction (0x65), with an address of 0x04. You can use this operation to verify the EEPROM programming. 7. Perform an I2C Write with the ENABLE_PROG instruction (0x05). This operation will place the ASC back in User Mode, in order to prevent accidental programming access. 114 Platform Manager 2 In-System Programmable Hardware Management Controller Fault Log Memory Access The ASC includes a fault logging block. The fault logging block consists of fault recording hardware, a volatile memory register which holds one 7 byte fault log record, a programming block, and a 16 row by 7 byte EEPROM memory for fault record storage. The fault logging block, including I2C access instructions is shown in Figure 68. The fault logging block is described in detail in the fault log section. The ASC Fault Log cannot be used when the user tag feature is enabled. These features use the same memory array and only one of the two features can be enabled at a given time. The Fault Log instructions shown below are only applicable for accessing the memory in Fault Log mode. Access to the memory in User Tag Mode should follow the User Tag instructions detailed in the previous section. Table 88 shows the Fault Log access instructions. The instructions are used to read out or erase either the fault log register or the fault log EEPROM memory block. The format for each instruction is in the section that follows. Writing fault logs to the EEPROM memory is triggered by the ASC-I/F. Faults can be recorded in either the fault logging register or in the EEPROM (for more details see the Fault Log / User Tag EEPROM section). The fault log recording hardware has priority access to the fault log EEPROM memory, and needs to be disabled via the READ_FAULT_ENABLE instruction prior to accessing the fault log via I2C. The fault log recording process also takes precedence over the reconfiguration/programming of the device. If a fault log record process is active, the device will reject reconfiguration requests. You can avoid that scenario by executing the READ_FAULT_ENABLE instruction prior to starting the reconfiguration process. The fault log instructions are summarized in Table 88 below, with individual instruction details in the following section. Table 88. Fault Log Access Instructions Instruction Code Instruction Name Read/Write Description 0x71 ERASE_FAULT_EEPROM 0x73 READ_FAULT_VOLATILE_REG 0x74 READ_FAULT_ENABLE 0x75 READ_FAULT_RECORD_EEPROM R Read out the selected record of Fault Log Array EEPROM bits 0x76 READ_ALL_FAULT_EEPROM R Reads out all records of the Fault Log EEPROM Array 115 W Erase the entire fault log memory R Read the fault log volatile register contents R/W Disables the fault log recording hardware and enables the ERASE and READ instructions Platform Manager 2 In-System Programmable Hardware Management Controller Figure 68. Fault Log Memory Block with I2C Access Instructions ASC-I/F-Fault_Log_Mode FAULT LOG EEPROM FAULT LOG REGISTER I2C_READ_ALL_FAULT_EEPROM ASC-I/F-Fault_Log_Trigger 16 ROWS x 7 BYTES RECORD COPY TO EEPROM* 7 BYTES I2C_READ_FAULT_RECORD_EEPROM (RECORD ADD[7:4]) ASC-I/F-Fault_Log_USER ASC-I/F Fault_Log_Full I2C_READ_ FAULT_ENABLE ASC-I/F Fault_Log_Busy I2C_ERASE_FAULT_EEPROM I2C_READ_FAULT_ VOLATILE_REG * - Fault Log record programming number is automatically incremented each time a fault log is recorded in the memory. The next programming row is recorded in the status register, accessed by the READ_STATUS I2C command. The ERASE_FAULT_EEPROM instruction is used to erase the entire fault log EEPROM record storage. The ASC must be in programming mode in order to execute this instruction (See the PROGRAM_MODE instruction). The READ_FAULT_ENABLE instruction must also have been sent to the ASC in order to disable recording of new faults. The format for the ERASE_FAULT_EEPROM is shown in Figure 69 below. Figure 69. ERASE_FAULT_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x71 A P The READ_FAULT_VOLATILE_REG instruction is used to read back the contents of the fault logging register. The 7 bytes are read back in order from Byte 0 to Byte 7. The READ_FAULT_ENABLE instruction must have been sent to the ASC in order to disable recording of new faults, prior to executing a READ_FAULT_VOLATILE_REG instruction. The format is shown in Figure 70. Figure 70. READ_FAULT_VOLATILE_REG - I2C Instruction Format S A[6:0] W A 0x73 A Sr A[6:0] DATA BYTE_1 DATA BYTE_0 SLAVE ADDRESS INSTRUCTION CODE SLAVE ADDRESS R A D0[7:0] A D1[7:0] A* P Optional: Read up to 6 additional data bytes * After final data byte read, master should NACK before issuing the STOP command The READ_FAULT_ENABLE instruction is used to disable the fault log recording hardware, and to enable the readback and erase of the fault logging memory block and fault log register. The READ_FAULT_ENABLE instruction is a write instruction with readback. The first transaction is a write transaction, as shown in Figure 71 below. The Address Byte with W=0 is sent, followed by the 0x74 instruction byte, followed by a keycode value of 0xAC. This key code is required to enable reading out or erasing of faults and disable fault recording. Sending any other keycode will disable reading and enable fault recording. Sending an incorrect keycode is the mechanism used to reenable fault log recording without resetting the device. The second transaction is a read transaction, with the Address Byte with R=1 sent, followed by a readback of the Fault Log Status Register. The Fault Log status register is described in Figure 72. 116 Platform Manager 2 In-System Programmable Hardware Management Controller Figure 71. READ_FAULT_ENABLE - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x74 A FAULT STATUS_REG SLAVE ADDRESS FAULT READ ENABLE KEY 0xAC A Sr A[6:0] R A R[7:0] NA P Figure 72. Fault Log Status Register Fault Log Status Register (Read Only) REQ[1] REQ[0] EN[1] EN[0] 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 The Fault Log status register is a read-only register which indicates the status of the fault log hardware. The register bits indicate whether reading of fault logs is enabled or disabled. The possible readout combinations of the register are shown in Table 89. Table 89. Fault Log Status Details REQ[1] REQ[0] EN[1] EN[0] 0 0 0 0 ASC device is in safe state, or ERASE_FAULT operation is active. 0 0 1 1 Fault Logging is active, reading faults is disabled 1 1 0 0 Future fault logging is disabled and fault log read enable is requested. Reading fault logs will be enabled pending completion of in progress fault log recording or other EEPROM erase/program operation on-chip 1 1 1 1 Reading of fault logs via I2C is now enabled. Fault log recording is disabled All other values Fault Log Status Invalid reading The READ_FAULT_RECORD_EEPROM instruction provides the mechanism to readback fault log records stored in the EEPROM memory. The READ_FAULT_RECORD_EEPROM is a two-step read transaction instruction, as shown in Figure 73. In the first step, a write transaction is performed with the 0x75 instruction, and a 4-bit address code [7:4]. The address code corresponds to fault log record 0 to 15, as shown in the fault log block diagram in Figure 68. In the second step, the fault log record can be read out in 7 bytes, from byte 0 to byte 6, using a read transaction. The record address will auto-increment to support reading multiple records in a single transaction. A stop condition will complete the read transaction, this can be issued after any number of rows and bytes have been read.The fault record is organized according to Table 20, in the Fault Logging section. This means a single transaction can support reading the all 15 fault log memory records, if the starting address of Record 0 is used. The READ_FAULT_RECORD_EEPROM instruction will be ignored if the READ_FAULT_ENABLE instruction has not been used to disable active fault recording. Figure 73. READ_FAULT_RECORD_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] INSTRUCTION CODE W A 0x75 A R_#[7:0] A Sr A[6:0] DATA BYTE1 [RECORD#] DATA BYTE0 [RECORD#] SLAVE ADDRESS RECORD* NUMBER R A D0[7:0] A D1[7:0] A** P Optional: Read 6 additional bytes for complete record, Read 112 data bytes (16 rows by 7 bytes) for the entire fault log memory, depending on starting row *The Record Number R_#[7:0] contains the 4-bit record number code in bits [7:4]. Bits [3:0] are always zero. ** After final data byte read, master should NACK before issuing the STOP command 117 Platform Manager 2 In-System Programmable Hardware Management Controller The READ_ALL_FAULT_EEPROM is similar to the READ_FAULT_RECORD_EEPROM instruction and provides an alternative mechanism for reading back fault log records stored in EEPROM memory. The READ_ALL_FAULT_EEPROM instruction always starts the readback at Record 0 and does not support requesting an individual fault log record request. During the read transaction, shown in Figure 74, fault log row 0 can be read out in 7 bytes. The row address will auto-increment to allow reading out the entire fault log array in a single transaction. A stop condition will complete the read transaction, this can be issued after any number of rows and bytes have been read. The READ_ALL_FAULT_EEPROM instruction will be ignored if the READ_FAULT_ENABLE instruction has not been used to disable active fault recording. Figure 74. READ_ALL_FAULT_EEPROM - I2C Instruction Format SLAVE ADDRESS S A[6:0] W A 0x76 DATA BYTE0 [RECORD # = 0] SLAVE ADDRESS INSTRUCTION CODE A Sr A[6:0] R A D0[7:0] DATA BYTE1 [RECORD # = 0] A D1[7:0] A* P Optional: Read 6 additional bytes for complete record, Read 112 data bytes (16 rows by 7 bytes) for the entire fault log memory. * After final data byte read, master should NACK before issuing the STOP command Fault Log Memory Readout Example This example describes the steps necessary to read the fault log EEPROM array over I2C. Note that the device must be in fault logging mode or it will not respond to these instructions. 1. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with the 1-byte key code 0xAC. Complete the READ_FAULT_ENABLE operation by reading back the Fault Log Status Register. Repeat this operation until the Fault Log Status register reads as 0xF0 (Fault Log Reading is Enabled). When reading is enabled, fault log recording will be disabled. 2. Perform an I2C Read with the READ_STATUS instruction (0x03). The ASC_STATUS_REGISTER_LO[7:4] bits (FAULT_CNT[3:0]) are equal to the number of fault log records which have been written to the EEPROM memory array by the recording hardware. ASC_STATUS_REGISTER_LO[3] (FAULT_LOG_FULL) is set to 1 when all sixteen records have been used for fault logging. 3. Perform an I2C READ with the READ_ALL_FAULT_EEPROM instruction (0x76). Read out the fault logs starting at Record 0, Byte 0. Continue reading data until you reach the last populated fault record (given by FAULT_CNT[3:0] in step 3), byte 6. 4. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with any keycode besides 0xAC. This disables fault log I2C access and returns the device to fault log recording mode. Repeat this operation until the Fault Log Status register reads as 0x00 (Fault Log Recording is Enabled). Fault Log Memory Erase Example This example describes the steps necessary to erase the fault log EEPROM array. Note that the device must be in fault logging mode or it will not respond to these instructions. 1. Perform an I2C Write with the ENABLE_PROGRAM instruction (0x04), with the 2-byte key code 0xE53D. This will place the chip in programming mode, a required step to erase the fault log EEPROM array. 2. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with the 1-byte key code 0xAC. Complete the READ_FAULT_ENABLE operation by reading back the Fault Log Status Register. Repeat this operation until the Fault Log Status register reads as 0xF0 (Fault Log Reading is Enabled). 3. Perform an I2C Write with the ERASE_FAULT_EEPROM instruction (0x71). This will erase the fault log EEPROM memory. 118 Platform Manager 2 In-System Programmable Hardware Management Controller 4. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with any keycode besides 0xAC. This disables fault log I2C access and return the device to fault log recording mode. Repeat this operation until the Fault Log Status register reads as 0x00 (Fault Log Recording is Enabled). 5. Perform an I2C Write with the ENABLE_USER instruction (0x05). This operation places the ASC back in User Mode in order to prevent accidental programming access. I2C Write Protection The ASC includes multiple protection mechanisms to prohibit accidental or incorrect access to the active device configuration. The active device configuration access protections are set during the initial programming of the device (also described in Table 76). There are three possible protection modes: • I2C Configuration Write Enabled – The ASC configuration parameters can be freely overwritten by I2C commands • I2C Configuration Write Disabled – The ASC configuration parameters cannot be overwritten by I2C instructions • I2C Configuration Write Controlled by GPIO1 Pin State – The ASC configuration parameters can only be overwritten by I2C instructions when GPIO1 is pulled high by an external device (Platform Manager 2 or Microcontroller) These protection modes control the configuration access by the following I2C instructions: WRITE_CFG_REG, WRITE_CFG_REG_wMASK, and TRIMx_CLT_P0_SET. This protection does not prevent EEPROM access instructions. EEPROM access is protected by the ENABLE_PROG_MODE instruction and instruction key. Figure 75 shows the typical configuration for working in the “Configuration Write Controlled by GPIO1 pin State” protection mode. Figure 75. I2C Write Protect by GPIO1 VDD I2C_SDA I2C_SDA 2 Platform I C_SCL Manager 2 GPIO1 I2C_SCL ASC1 GPIO1 PIOx I2C Handler pulls PIOx high prior to executing a configuration command I2C_SDA I2C_SCL ASC2 GPIO1 119 Platform Manager 2 In-System Programmable Hardware Management Controller The ASC device will still provide ACK bits in I2C write transmissions, even when the configuration write is disabled (by either the GPIO1 state or configuration setting). Even though the device presents ACK bits, the configuration memory will not be overwritten. When using Write Protect by GPIO1 with WRITE_CFG_REG or WRITE_CFG_REG_wMASK, the GPIO1 signal should be asserted before transmission of the 7-bit slave address. It should be de-asserted after the STOP or RESTART signaling that marks the end of the write access. For TRIMx_CLT_P0_SET access, the GPIO1 signal should be asserted before transmission of the 7-bit slave address of the write phase. It should be de-asserted during or after the transmission of the slave address at the start of the readback phase (See the Closed Loop Trim Register Access section for more details). 120 Platform Manager 2 In-System Programmable Hardware Management Controller Pin Descriptions LPTM21 Table 90. LPTM21 - Logic Signal Connections Ball/Pin Function LPTM21 237-Ball ftBGA PB11A N6 2 PCLKT2_1 TRUE PB11B P6 2 PCLKC2_1 COMP Bank Dual Function Differential Input / Complementary Output Pairs PB11C T4 2 TRUE PB11D P5 2 COMP PB15A R5 2 TRUE PB15B R6 2 COMP PB15C N7 2 TRUE PB15D M7 2 COMP PB18A T7 2 TRUE PB18B R7 2 COMP PB18C P7 2 TRUE PB18D P8 2 COMP PB20A N8 2 TRUE PB20B M8 2 COMP PB20C T9 2 SN TRUE PB20D R9 2 SI/SISPI COMP PB4A R1 2 TRUE PB4B P1 2 COMP PB4C P2 2 PB4D M5 2 CSSPIN TRUE PB6A P3 2 TRUE PB6B T2 2 COMP PB6C R3 2 MCLK/CCLK TRUE PB6D T3 2 SO/SPISO COMP PB9A P4 2 PCLKT2_0 TRUE PB9B R4 2 PCLKC2_0 COMP PB9C N5 2 TRUE PB9D M6 2 COMP PL10A M1 3 TRUE PL10B N1 3 COMP PL10C N2 3 TRUE PL10D M2 3 COMP PL2A E2 3 L_GPLLT_FB TRUE PL2B D2 3 L_GPLLC_FB COMP PL2C D1 3 L_GPLLT_IN TRUE PL2D E1 3 L_GPLLC_IN COMP PL3A F2 3 PCLKT3_2 TRUE PL3B F3 3 PCLKC3_2 COMP PL3C F1 3 TRUE PL3D G1 3 COMP COMP 121 Platform Manager 2 In-System Programmable Hardware Management Controller Ball/Pin Function LPTM21 237-Ball ftBGA Bank PL4A G2 3 TRUE PL4B G3 3 COMP PL4C H3 3 TRUE PL4D H2 3 COMP PL5A J2 3 PCLKT3_1 TRUE PL5B J3 3 PCLKC3_1 COMP PL8A K3 3 TRUE PL8B K2 3 COMP PL8C K1 3 TRUE PL8D L1 3 COMP Dual Function Differential Input / Complementary Output Pairs PL9A L3 3 PCLKT3_0 TRUE PL9B L2 3 PCLKC3_0 COMP PR10A N10 1 TRUE PR10B P10 1 COMP PR10C P9 1 TRUE PR10D R10 1 COMP PR2A D10 1 TRUE PR2B C10 1 COMP PR2C C11 1 TRUE PR2D D11 1 COMP PR3A E10 1 TRUE PR3B E9 1 COMP PR4A E11 1 TRUE PR4B F10 1 COMP PR5D B10 1 PR8D N9 1 PR9A L10 1 TRUE PR9B T10 1 COMP PCLKC1_0 N/A N/A PR9C M9 1 TRUE PR9D M10 1 COMP PT10A D3 0 TRUE PT10B E4 0 COMP PT10C B3 0 TDO TRUE PT10D A3 0 TDI COMP PT11A D5 0 TRUE PT11B E6 0 COMP PT11C C4 0 TCK TRUE PT11D B4 0 TMS COMP PT12A A4 0 PCLKT0_1 TRUE PT12B C5 0 PCLKC0_1 COMP PT12C D6 0 SCL_M TRUE PT12D C6 0 SDA_M COMP PT15A B5 0 TRUE PT15B B6 0 COMP 122 Platform Manager 2 In-System Programmable Hardware Management Controller Ball/Pin Function LPTM21 237-Ball ftBGA Bank PT15C D7 0 JTAGENB TRUE PT15D E7 0 PROGRAMN COMP PT16A A7 0 TRUE PT16B B7 0 COMP PT16C C7 0 TRUE COMP Dual Function Differential Input / Complementary Output Pairs PT16D C8 0 PT17A D8 0 TRUE PT17B E8 0 COMP PT17C C9 0 INITN TRUE PT17D D9 0 DONE COMP PT9A B1 0 TRUE PT9B C1 0 COMP PT9C C2 0 TRUE PT9D B2 0 COMP Table 91. LPTM21 - Analog Sense and Control Signals Ball/Pin Function LPTM21 237-Ball ftBGA Pin Type SCL_S0 P12 Digital I/O Description SDA_S0 N12 Digital I/O I2C Serial Clock Bi-directional Pin I2C Serial Data, Bi-Directional Pin ASCCLK P11 Digital I/O 8 MHz ASC Clock Output (Tristate) CMOS NC_FT1 B11 Digital I/O ASC Interface Test Point NC_FT2 F11 Digital I/O ASC Interface Test Point NC_FT3 G11 Digital I/O ASC Interface Test Point RESETb F13 Digital I/O ASC Reset (Active Low) HVOUT1 D12 Analog / Digital Out Current Source / Open Drain Output, reset Low HVOUT2 C13 Analog / Digital Out Current Source / Open Drain Output, reset Low HVOUT3 K11 Analog / Digital Out Current Source / Open Drain Output, reset Low HVOUT4 L11 Analog / Digital Out Current Source / Open Drain Output, reset Low GPIO1 A14 Digital I/O Digital Input / Write Protect Input / Open Drain Output, reset Low GPIO2 F12 Digital I/O Digital Input / Open Drain Output, reset Low GPIO3 E13 Digital I/O Digital Input / Open Drain Output, reset Low GPIO4 G12 Digital I/O Digital Input / Open Drain Output, reset Low GPIO5 B13 Digital I/O Digital Input / Open Drain Output, reset Low GPIO6 C12 Digital I/O Digital Input / Open Drain Output, reset Low GPIO7 B12 Digital I/O Digital Input / Open Drain Output, reset Hi-Z GPIO8 R11 Digital I/O Digital Input / Open Drain Output, reset Hi-Z GPIO9 M11 Digital I/O Digital Input / Open Drain Output, reset Hi-Z GPIO10 N11 Digital I/O VMON1 P16 Analog Input VMON1GS R16 Analog Input Voltage Monitor Input Ground Sense VMON2 L15 Analog Input Voltage Monitor Input VMON2GS M15 Analog Input Voltage Monitor Input Ground Sense VMON3 K16 Analog Input Voltage Monitor Input 123 Digital Input / Open Drain Output, reset Low Voltage Monitor Input Platform Manager 2 In-System Programmable Hardware Management Controller Ball/Pin Function LPTM21 237-Ball ftBGA Pin Type Description VMON3GS L16 Analog Input Voltage Monitor Input Ground Sense VMON4 H16 Analog Input Voltage Monitor Input VMON4GS J16 Analog Input Voltage Monitor Input Ground Sense VMON5 G15 Analog Input Voltage Monitor Input VMON6 E15 Analog Input Voltage Monitor Input VMON7 E16 Analog Input Voltage Monitor Input VMON8 C16 Analog Input Voltage Monitor Input VMON9 B16 Analog Input Voltage Monitor Input HIMONP T13 Analog Input 12 V Current Monitor Input Source HIMONN_HVMON T14 Analog Input 12 V Current Monitor Input Return/ Voltage Monitor Input IMON1P R14 Analog Input Low Voltage Current Monitor Input source IMON1N P14 Analog Input Low Voltage Current Monitor Input return TMON1P T15 Analog Input Temperature Monitor Input source TMON1N R15 Analog Input Temperature Monitor Input Return TMON2P P15 Analog Input Temperature Monitor Input source TMON2N N15 Analog Input TRIM1 B15 Analog Output TRIM2 A15 Analog Output Trim DAC Output TRIM3 F14 Analog Output Trim DAC Output TRIM4 G14 Analog Output Trim DAC Output VDC D13 Power 5 V-12 V DC-DC Converter Input Voltage HDRV A11 Power DC-DC Converter – High –Side PWM Driver Temperature Monitor Input Return Trim DAC Output Table 92. LPTM21 - Power and Ground Connections Ball/Pin Function LPTM21 237-Ball ftBGA Bank Description VCC G5 N/A Digital Supply VCC G6 N/A Digital Supply VCC G7 N/A Digital Supply VCC K5 N/A Digital Supply VCC K6 N/A Digital Supply VCC K7 N/A Digital Supply VCCA G16 N/A Analog Supply VCCA H12 N/A Analog Supply VCCA J12 N/A Analog Supply GND A16 N/A Device Ground GND H14 N/A Device Ground GND J14 N/A Device Ground GND T16 N/A Device Ground GND A13 N/A Device Ground GND H11 N/A Device Ground GND J11 N/A Device Ground GND T12 N/A Device Ground GND A1 N/A Device Ground 124 Platform Manager 2 In-System Programmable Hardware Management Controller Ball/Pin Function LPTM21 237-Ball ftBGA Bank Description GND A6 N/A Device Ground GND E3 N/A Device Ground GND F6 N/A Device Ground GND H5 N/A Device Ground GND H6 N/A Device Ground GND H7 N/A Device Ground GND J1 N/A Device Ground GND J5 N/A Device Ground GND J6 N/A Device Ground GND J7 N/A Device Ground GND L6 N/A Device Ground GND M3 N/A Device Ground GND T1 N/A Device Ground GND T6 N/A Device Ground VCCIO0 A5 0 IO-0 Supply VCCIO0 F4 0 IO-0 Supply VCCIO0 F5 0 IO-0 Supply VCCIO0 F7 0 IO-0 Supply VCCIO0 F8 0 IO-0 Supply VCCIO1 G8 1 IO-1 Supply VCCIO1 H8 1 IO-1 Supply VCCIO1 J8 1 IO-1 Supply VCCIO1 K8 1 IO-1 Supply VCCIO2 L4 2 IO-2 Supply VCCIO2 L5 2 IO-2 Supply VCCIO2 L7 2 IO-2 Supply VCCIO2 L8 2 IO-2 Supply VCCIO2 T5 2 IO-2 Supply VCCIO3 J4 3 IO-3 Supply VCCIO3 K4 3 IO-3 Supply NC A10 N/A Not Used NC A2 N/A Not Used NC A8 N/A Not Used NC A9 N/A Not Used NC A12 N/A Not Used (Do not connect) NC B14 N/A Not Used NC B8 N/A Not Used NC B9 N/A Not Used NC C14 N/A Not Used NC C15 N/A Not Used NC C3 N/A Not Used NC D14 N/A Not Used NC D15 N/A Not Used NC D16 N/A Not Used 125 Platform Manager 2 In-System Programmable Hardware Management Controller LPTM21 237-Ball ftBGA Bank Description NC D4 N/A Not Used NC E12 N/A Not Used NC E14 N/A Not Used NC E5 N/A Not Used NC F15 N/A Not Used NC F16 N/A Not Used NC H15 N/A Not Used NC J15 N/A Not Used NC K12 N/A Not Used NC K14 N/A Not Used NC K15 N/A Not Used NC L12 N/A Not Used Ball/Pin Function NC L14 N/A Not Used NC M12 N/A Not Used NC M14 N/A Not Used NC M16 N/A Not Used NC M4 N/A Not Used NC N14 N/A Not Used NC N16 N/A Not Used NC N3 N/A Not Used NC N4 N/A Not Used NC R12 N/A Not Used NC R2 N/A Not Used NC R8 N/A Not Used NC T11 N/A Not Used NC T8 N/A Not Used NC H1 N/A Not Used NC G4 N/A Not Used NC H4 N/A Not Used 126 Platform Manager 2 In-System Programmable Hardware Management Controller Part Number Description LPTM2a – bb cccc d Platform Manager 2 Operating Conditions C = Commercial I = Industrial Logic Capacity - LUTs 1 = 1280 LUTs Package and Pins/Balls FTG237 = 237 ball FTBGA Performance Grade - 1A = Standard Ordering Information Halogen-Free Packaging Commercial Part Number LUTs Package Pins/Balls 1280 Halogen-Free FTBGA 237 Part Number LUTs Package Pins/Balls LPTM21-1A FTG237 I 1280 Halogen-Free FTBGA 237 LPTM21-1A FTG237 C Industrial 127 Platform Manager 2 In-System Programmable Hardware Management Controller For Further Information For further information on the FPGA section of Platform Manager 2, consult the MachXO2 family datasheet and technical notes on the Lattice Website. • DS1042, L-ASC10 Data Sheet • DS1035, MachXO2 Family Data Sheet • TN1198, Power Estimation and Management for MachXO2 Devices • TN1202, MachXO2 sysIO Usage Guide • TN1225, Platform Manager 2 Hardware Checklist • TN1204, MachXO2 Programming and Configuration Usage Guide • TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Section May 2016 1.4 I2C Interface April 2015 1.3 Multiple System Connections Change Summary Updated Measurement and Control Register Access section to address restrictions on READ_MEAS_CTRL command with addresses 0x85 and 0x86. Deleted all references to LPTM20. Modified Figure 36, System Connections - ASC and Platform Manager 2 Added Table 23, Raddr Value vs. ASC Device Number to clarify I2C_ADDR pin connections. I2C Interface May 2014 01.2 — Multiple Updated ASC Configuration Registers section. Updated Polarity bit setting in Table 30, POL Setting vs Closed Loop Trim Polarity. Data sheet status changed from preliminary to final. Renamed IMON to IMON1. Updated ASC-IF TRIM control signal names. DC and Switching Characteristics Theory of Operation Populated specifications with characterization results. Added additional FPGA timing sections. Removed IMON Hysteresis feature. Expanded Output Control Block section. Updated System Connections section. 2 I C Interface Corrected error in Table 81, ADC Input Selection for IMON1 and HIMON SEL bits. Update VMON and IMON tables with final device trip points. March 2014 01.1 DC and Switching Characteristics December 2013 01.0 — Added preliminary ESD Performance section. Preliminary release. 128