Trusted Platform Module TPM SLB 9670 TCG Rev. 116 SLB 9670VQ1.2 SLB 9670XQ1.2 Data Sheet Revision 1.0, 2015-11-05 Chip Card and Security SLB 9670 TPM1.2 Trusted Platform Module Revision History Page or Item Subjects (major changes since previous revision) Revision 1.0, 2015-11-05 Initial version. Data Sheet 2 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Table of Contents Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Device Types / Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 4.1 4.2 4.3 4.4 4.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 11 12 13 5 5.1 5.2 5.3 Package Dimensions (VQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 Data Sheet 3 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module List of Figures List of Figures Figure 3-1 Figure 3-2 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Data Sheet Pinout of the SLB 9670VQ1.2 and SLB 9670XQ1.2 (PG-VQFN-32-13 Package, Top View) . . . . . . . . 7 Typical Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package Dimensions PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Tape & Reel Dimensions PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Recommended Footprint PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip Marking PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module List of Tables List of Tables Table 2-1 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Data Sheet Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Not Connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC Characteristics of SPI Interface Pins (SCLK, CS#, MISO, MOSI, RST#, PIRQ#) . . . . . . . . . . . . . . 11 DC Characteristics of GPIO and PP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Characteristics of SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Overview 1 Overview The SLB 9670 is a Trusted Platform Module and is based on advanced hardware security technology. This TPM implementation has achieved CC EAL4+ certification and serves as a basis for other TPM products and firmware upgrades. It is available in PG-VQFN-32-13 package. It supports an SPI interface with a transfer rate of up to 43 MHz. The SLB 9670 is a TPM based on TCG family 1.2 specifications (see [1] and [2]). • Compliant to TPM Main Specification, Version 1.2, Rev. 116 • SPI interface • Approved for Google Chromebook / Chromebox • Standard (-20..+80°C) and Enhanced temperature range (-40..+85°C) • PG-VQFN-32-13 package • Optimized for battery operated devices: low standby power consumption (typ. 110µA) • 24 PCRs • 6 kByte free NV memory • Up to 10 concurrent sessions • Up to eight 2048-bit keys can be loaded into volatile storage • 16 slots for keys of up to 2048-bit • 8 monotonic counters • 1280 Byte I/O buffer • Built-in support by Linux Kernel 1.1 Power Management In the SLB 9670, power management is handled internally; no explicit power-down or standby mode is available. The device automatically enters a low-power state after each successful command/response transaction. If a transaction is started on the SPI bus from the host platform, the device will wake immediately and will return to the low-power mode after the transaction has been finished. 2 Device Types / Ordering Information The SLB 9670 product family features devices using a VQFN package. Table 2-1 shows the different versions. Table 2-1 Device Configuration Device Name Package Remarks SLB 9670VQ1.2 PG-VQFN-32-13 Standard temperature range SLB 9670XQ1.2 PG-VQFN-32-13 Enhanced temperature range Data Sheet 6 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description Pin Description NC I NC I NC I NC I NC NC NC I GND 30 NCI/VDD 26 MISO 1 GND TPM SLB 9670VQ1.2 NCI NCI GND 22 VDD MOSI NCI CS# PG-VQFN-32-13 GPIO PP 18 7 VDD SCLK 10 PIRQ # RST# 15 Pinning_VQFN-32-13_SLB9670.vsd 3 NC I/GND NC I NC I/VDD NC I NC I NC I NC I GND Figure 3-1 Pinout of the SLB 9670VQ1.2 and SLB 9670XQ1.2 (PG-VQFN-32-13 Package, Top View) Table 3-1 Buffer Types Buffer Type Description TS Tri-State pin ST Schmitt-Trigger pin OD Open-Drain pin Table 3-2 I/O Signals Pin Number Name Pin Type Buffer Type Function 20 CS# I ST Chip Select The SPI chip select signal (active low). 19 SCLK I ST SPI Clock The SPI clock signal. Only SPI mode 0 is supported by the device. 21 MOSI I ST Master Out Slave In (SPI Data) SPI data which is received from the master. 24 MISO O TS Master In Slave Out (SPI Data) SPI data which is sent to the SPI bus master. 18 PIRQ# O OD Interrupt Request Interrupt request signal to the host. The pin has no internal pull-up resistor. The interrupt is active low. PG-VQFN-32-13 Data Sheet 7 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description Table 3-2 I/O Signals (continued) Pin Number Name Pin Type Buffer Type Function 17 RST# I ST Reset External reset signal. Asserting this pin unconditionally resets the device. The signal is active low and is typically connected to the PCIRST# signal of the host. This pin has a weak internal pull-up resistor. 6 GPIO I/O TS GPIO-Express-00 Signal This pin is a general purpose I/O pin. It is defined as GPIO-Express-00, please refer to [2] and the PCISIG ECN “Trusted Configuration Space for PCI Express”. This pin may be left unconnected; it has an internal pullup resistor. 7 PP I ST Physical Presence This pin should be connected to a jumper. The standard position of the jumper should connect the pin to GND. If the pin is connected to VDD, some special commands are enabled (for instance, the command TPM_ForceClear, also refer to [1]). This pin may be left unconnected; it has an internal pulldown resistor. Name Pin Type Buffer Type Function 8, 22 VDD PWR — Power Supply All VDD pins must be connected externally and should be bypassed to GND via 100 nF capacitors. 2, 9, 23, 32 GND GND — Ground All GND pins must be connected externally. Name Pin Type Buffer Type Function 29, 30 NC NU — No Connect All pins must not be connected externally (must be left floating). 3 - 5, 10 - 13, 15, 25 - 28, 31 NCI — — Not Connected Internally All pins are not connected internally (can be connected externally). PG-VQFN-32-13 Table 3-3 Power Supply Pin Number PG-VQFN-32-13 Table 3-4 Not Connected Pin Number PG-VQFN-32-13 Data Sheet 8 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Pin Description Table 3-4 Not Connected (continued) Pin Number Name Pin Type Buffer Type Function 1, 14 NCI/VDD — — Not Connected Internally/VDD All pins are not connected internally (can be connected externally). Note that pins 1 and 14 are defined as VDD in the TCG specification [5]. To be compliant, VDD can be connected to these pins. 16 NCI/GND — — Not Connected Internally/GND This pin is not connected internally (can be connected externally). Note that pin 16 is defined as GND in the TCG specification [5]. To be compliant, GND can be connected to this pins. PG-VQFN-32-13 3.1 Typical Schematic Figure 3-2 shows the typical schematic for the SLB 9670. The power supply pins should be bypassed to GND with capacitors located close to the device. The physical presence input may be connected to a jumper as shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent). 3.3V (1.8V) SCLK SCLK TPM_CS# CS# MISO MISO MOSI MOSI PIRQ# PIRQ# RESET# RST# GPIO GPIO VDD 1 µF GND 2x 100 nF (place close to device VDD/GND pins) J1 3.3V (1.8V) PP NC/NCI SLB 9670 Schematic_SLB9670.vsd Figure 3-2 Typical Schematic Data Sheet 9 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Electrical Characteristics 4 Electrical Characteristics This chapter lists the maximum and operating ranges for various electrical and timing parameters. 4.1 Absolute Maximum Ratings Table 4-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Supply Voltage VDD -0.3 – 7.0 V – Voltage on any pin Vmax -0.3 – VDD+0.3 V – -0.5 – VDD+0.5 V VDD = 3.3V ± 10%; pins MISO, MOSI, SCLK and CS# Ambient temperature TA -20 – 85 °C Standard temperature devices Ambient temperature TA -40 – 85 °C Enhanced temperature devices Storage temperature TS -40 – 125 °C – ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM – – 2000 V According to EIA/JESD22-A114-B ESD robustness VESD,CDM – – 500 V According to ESD Association Standard STM5.3.1 - 1999 Latchup immunity Ilatch 100 mA According to EIA/JESD78 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 4.2 Functional Operating Range Table 4-2 Functional Operating Range Parameter Symbol Supply Voltage VDD Values Unit Note or Test Condition Min. Typ. Max. 3.0 3.3 3.6 V – 1.65 1.8 1.95 V – Ambient temperature TA -20 – 85 °C Standard temperature devices Ambient temperature TA -40 – 85 °C Enhanced temperature devices – – 5 y Operating lifetime – – 5 y Average TA over lifetime – 55 – °C 1) Useful lifetime 1) 1) The useful lifetime of the device is 5 (five) years with a duty cycle (that means, a power-on time) of 100%. A useful lifetime of 7 (seven) years can be guaranteed for a duty cycle of 70%. For both scenarios, it is assumed that the device will be used for calculations for approximately 5% of the maximum useful lifetime. Data Sheet 10 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Electrical Characteristics 4.3 DC Characteristics TA = 25°C, VDD = 3.3V ± 0.3V or VDD = 1.8V ± 0.15V unless otherwise noted. Table 4-3 Current Consumption Parameter Symbol Values Min. Typ. Current Consumption in IVDD_Active Active Mode Unit Max. 25 mA 110 Current Consumption in IVDD_Sleep Sleep Mode Note or Test Condition µA Pin PP = GND, pins GPIO, RST# and PIRQ# = VDD, CS# inactive (=VDD), MOSI, MISO and SCLK don't care Note: Current consumption does not include any currents flowing through resistive loads on output pins! Table 4-4 DC Characteristics of SPI Interface Pins (SCLK, CS#, MISO, MOSI, RST#, PIRQ#) Parameter Symbol Values Min. Input voltage high Input voltage low Input leakage current VIH VIL ILEAK Typ. Unit Note or Test Condition Max. 0.7 VDD VDD+0.5 V VDD,typ = 3.3V, only pins SCLK, MISO, MOSI and CS# 0.7 VDD VDD+0.3 V VDD,typ = 3.3V, pin RST# 0.7 VDD VDD+0.3 V VDD,typ = 1.8V -0.5 0.3 VDD V VDD,typ = 3.3V, only pins SCLK, MISO, MOSI and CS# -0.3 0.3 VDD V VDD,typ = 3.3V, pin RST# -0.3 0.3 VDD V VDD,typ = 1.8V -20 20 µA 0V < VIN < VDD -150 150 µA Pins SCLK, CS#, MISO, MOSI -0.5V < VIN < VDD+0.5V VDD,typ = 3.3V -150 150 µA Pin RST# -0.5V < VIN < VDD+0.3V VDD,typ = 3.3V -150 150 µA -0.3V < VIN < VDD+0.3V VDD,typ = 1.8V V IOH = -100µA IOL = 1.5mA Output high voltage VOH Output low voltage VOL 0.1 VDD V Pad input capacitance CIN 10 pF 40 pF 0.9 VDD Output load capacitance CLOAD Data Sheet 11 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Electrical Characteristics Table 4-5 DC Characteristics of GPIO and PP Pins Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Input voltage high VIH 0.7 VDD VDD+0.3 V Pins GPIO and PP Input voltage low VIL -0.3 0.2 VDD V Pins GPIO and PP Input leakage current ILEAK -20 20 µA 0V < VIN < VDD -150 150 µA -0.3V < VIN < VDD + 0.3V V IOH = -1mA, pin GPIO Output high voltage VOH Output low voltage VOL 0.3 V IOL < 1mA, pin GPIO Pad input capacitance CIN 10 pF Pins GPIO and PP 4.4 0.7 VDD AC Characteristics TA = 25°C, VDD = 3.3V ± 0.3V or VDD = 1.8V ± 0.15V unless otherwise noted. Table 4-6 Device Reset Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Reset Pulse Width tRST 80 µs Cold (power-on) reset Reset Pulse Width tRST 2 µs Warm reset Unit Note or Test Condition 43 MHz VDD,typ = 3.3V 22.5 MHz VDD,typ = 1.8V 1/fCLK + 5% µs Rising edge to rising edge, measured at VIN = 0.5 VDD Table 4-7 AC Characteristics of SPI Interface Parameter Symbol Values Min. SCLK frequency Typ. Max. fCLK SCLK period tCLK 1/fCLK 5% SCLK low time tCLKL 0.45 tCLK µs Falling edge to rising edge, measured at VIN = 0.5 VDD SCLK high time tCLKL 0.45 tCLK µs Rising edge to falling edge, measured at VIN = 0.5 VDD SCLK slew rate (rising/falling) tSLEW 1 V/ns between 0.2 VDD and 0.6 VDD CS# high time tCS 50 ns Rising edge to falling edge CS# setup time tCSS 5 ns CS# falling edge to SCLK rising edge CS# hold time tCSH 5 ns SCLK falling edge to CS# rising edge Data Sheet 1/fCLK 4 12 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Electrical Characteristics Table 4-7 AC Characteristics of SPI Interface (continued) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. MOSI setup time tSU 2 ns Data setup time to SCLK rising edge MOSI hold time tH 3 ns Data hold time from SCLK rising edge MISO hold time tHO 0 ns Output hold time from SCLK falling edge MISO valid delay time tV 0 0.7 tCLKL ns 4.5 Output valid delay from SCLK falling edge Timing Some pads are disabled after deassertion of the reset signal for up to 500 µs. Data Sheet 13 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Package Dimensions (VQFN) 5 Package Dimensions (VQFN) All dimensions are given in millimeters (mm) unless otherwise noted. The packages are “green” and RoHS compliant. 5 7 x 0.5 = 3.5 A 0.5 0.9 MAX. 0.1 A 2x B 17 32x 0.05 C 0.1 C 24 25 0.1 B 2x SEATING PLANE 5 3.6 ±0.1 16 Index Marking 9 32 8 1 3.6 ±0.1 C (0.2) Index Marking 32x 0.25 +0.05 -0.07 0.1 M A B C 0.05 M C (4.2) 0.4 ±0.05 0.05 MAX. PG-VQFN-32-13-PO V01 Figure 5-1 Package Dimensions PG-VQFN-32-13 5.1 Packing Type PG-VQFN-32-13: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel 0.3 5.25 12 8 5.25 Index Marking 1.1 PG-VQFN-32-13-TP V01 Figure 5-2 Tape & Reel Dimensions PG-VQFN-32-13 5.2 Recommended Footprint Figure 5-3 shows the recommended footprint for the PG-VQFN-32-13 package. The exposed pad of the package is internally connected to GND. It shall be connected to GND externally as well. 4.1 3.6 0.5 4.1 3.6 0.7 Package outline 5 x 5 0.25 PG-VQFN-32-13-FP V01 Figure 5-3 Recommended Footprint PG-VQFN-32-13 Data Sheet 14 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Package Dimensions (VQFN) 5.3 Chip Marking Line 1: SLB9670 Line 2: VQ12 yy or XQ12 yy (see Table 2-1), the <yy> is an internal FW indication (only at manufacturing due to field upgrade option) Line 3: <Lot number> H <datecode> Infineon 1234567 VQ12 YY XXH Softwarecode Lot Code ChipMarking _VQFN.vsd Figure 5-4 Chip Marking PG-VQFN-32-13 For details and recommendations regarding assembly of packages on PCBs, please refer to http://www.infineon.com/cms/en/product/technology/packages/ Data Sheet 15 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module References References [1] —, “TPM Main Specification”, Version 1.2, Rev. 116, 2011-03-01, TCG (parts 1-3) [2] —, “TCG PC Client TPM Interface Specification (TIS)”, Version 1.3, 2013-03-21, TCG [3] —, “PC Client Implementation Specification”, Version 1.2, 2005-07-13, TCG [4] —, “TCG Software Stack Specification (TSS)”, Version 1.2, 2005-11-02, TCG [5] —, “TCG PC Client Platform TPM Profile (PTP) Specification”, Rev. 00.43, 2014-08-04, TCG Data Sheet 16 Revision 1.0 2015-11-05 SLB 9670 TPM1.2 Trusted Platform Module Terminology Terminology ESW Embedded Software HMAC Hashed Message Authentication Code LPC Low Pin Count (bus) PCR Platform Configuration Register PUBEK Public Endorsement Key SPI Serial Peripheral Interface (bus) TCG Trusted Computing Group TPM Trusted Platform Module TSS TCG Software Stack Data Sheet 17 Revision 1.0 2015-11-05 Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PROFET™, PROSIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™. Other Trademarks µVision™, AMBA™, ARM™, KEIL™, MULTI-ICE™, THUMB™ of ARM Limited, UK. AUTOSAR™ of AUTOSAR development partnership. CIPURSE™ of OSPT Alliance. EMV™ of EMVCo, LLC (Visa Holdings Inc.). FLEXGO™ of Microsoft Corporation. HYPERTERMINAL™ of Hilgraeve Incorporated. IrDA™ of Infrared Data Association Corporation. MCS™ of Intel Corp. MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc. TEAKLITE™ of CEVA, Inc. VXWORKS™ of WIND RIVER SYSTEMS, INC. Chrome OS™ of Google, Inc. Trademarks Update 2014-07-17 www.infineon.com Edition 2015-11-05 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: [email protected] Document reference Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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