P3P18S19B Notebook LCD Panel EMI Reduction IC Product Description The P3P18S19B is a Versatile Spread Spectrum Frequency Modulator designed specifically for input clock frequencies from 20 to 40 MHz. (Refer to “Input Frequency and Modulation Rate” Table). The P3P18S19B reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of downstream clock and data dependent signals. The P3P18S19B allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass EMI regulations. The P3P18S19B modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘Spread Spectrum Clock Generation’. The P3P18S19B uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. www.onsemi.com 8 1 SOIC−8 NB CASE 751 PIN CONFIGURATION XIN / CLKIN 1 VSS 2 8 XOUT 7 VDD P3P18S19B SRS 3 6 PD# ModOUT 4 5 REF Applications The P3P18S19B is targeted towards EMI management for memory and LVDS interfaces in mobile graphic chipsets and high−speed digital applications such as PC peripheral devices, consumer electronics, and embedded controller systems. MARKING DIAGRAM 8 ABS ALYWX G Features • FCC Approved Method of EMI Attenuation • Provides up to 15 dB EMI Reduction • Generates a Low EMI Spread Spectrum Clock and a Non−spread • • • • • • • • • • Reference Clock of the Input Frequency Optimized for Frequency Range from 20 to 40 MHz Internal Loop Filter Minimizes External Components and Board Space Low Inherent Cycle−to−Cycle Jitter Two Spread % Selections: −1.25% to −1.75% 3.3 V Operating Voltage CMOS Design Supports Notebook VGA and other LCD Timing Controller Applications Power Down Function for Mobile Application Available in 8−pin SOIC Package These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2015 February, 2015 − Rev. 1 1 1 ABS A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Publication Order Number: P3P18S19B/D P3P18S19B Block Diagram VDD SRS PD# PLL Modulation XIN/CLKIN XOUT Crystal Oscillator Frequency Divider Phase Detector Feedback Divider Loop Filter Output Divider VCO ModOUT REF VSS Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin # Pin Name Type Description 1 XIN / CLKIN I Crystal Connection or external frequency input. This pin has dual functions. It can be connected to either an external crystal or an external reference clock. 2 VSS P Ground Connection. Connect to system ground. 3 SRS I Spread range select. Digital logic input used to select frequency deviation (Refer to Spread Deviation Selection Table). This pin has an internal pullup resistor. 4 ModOUT O Spread spectrum clock output. (Refer to Input Frequency and Modulation Rate Table and Spread Deviation Selection Table) 5 REF O Non−modulated Reference clock output of the input frequency. 6 PD# I Power down control pin. Pull LOW to enable Power−Down mode. This pin has an internal pull−up resistor. 7 VDD P Power Supply for the entire chip. 8 XOUT O Crystal Connection. Input connection for an external crystal. If using an external reference, this pin must be left unconnected. Table 2. INPUT FREQUENCY AND MODULATION RATE Part Number Input Frequency Range Output Frequency Range Modulation Rate P3P18S19B 20 MHz to 40 MHz 20 MHz to 40 MHz Input Frequency / 512 Table 3. SPREAD DEVIATION SELECTION Part Number SRS Spread Deviation P3P18S19B 0 −1.25% (DOWN) 1 −1.75% (DOWN) www.onsemi.com 2 P3P18S19B Table 4. ABSOLUTE MAXIMUM RATINGS Symbol VDD, VIN TSTG Parameter Rating Unit Voltage on any pin with respect to Ground −0.5 to +4.6 V Storage temperature −65 to +125 °C °C Ts Max. Soldering Temperature (10 sec) 260 TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Parameter Min Typ Max Unit VIL Input Low voltage VSS – 0.3 0.8 V VIH Input High voltage 2.0 VDD + 0.3 V IIL Input Low current (inputs PD#, SRS) −60.0 −20.0 mA IIH Input High current 1.0 mA IXOL XOUT Output low current @ 0.4 V, VDD = 3.3 V 3 mA IXOH XOUT Output high current @ 2.5 V, VDD = 3.3 V 3 mA VOL Output Low voltage VDD = 3.3 V, IOL = 20 mA VOH Output High voltage VDD = 3.3 V, IOH = 20 mA ICC Dynamic supply current normal mode 3.3 V and 25 pF probe loading IDD Static supply current standby mode 4.5 mA VDD Operating Voltage 3.3 V tON Power up time (first locked clock cycle after power up) 0.18 mS 50 W ZOUT 0.4 2.5 V 7.1 fIN − min Clock Output impedance V 26.9 fIN − max mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Table 6. AC ELECTRICAL CHARACTERISTICS Symbol fIN Parameter Min Typ Max Unit Input Frequency 20 40 MHz fOUT Output Frequency 20 40 MHz tLH* Output Rise time (Measured from 0.8 V to 2.0 V) 0.66 nS tHL* Output Fall time (Measured from 2.0 V to 0.8 V) 0.65 nS tJC Jitter (Cycle−to−cycle) tD Output Duty cycle −200 45 50 200 pS 55 % Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. * tLH and tHL are measured into a capacitive load of 15 pF Table 7. ORDERING INFORMATION Part Number P3P18S19BF−08SR Marking ABS Package Type 8 pin SOIC, TAPE & REEL, Pb Free Temperature 0°C to +70°C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. www.onsemi.com 3 P3P18S19B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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