MT9D015 D

MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
1/5-Inch 2 Mp CMOS Digital Image Sensor
MT9D015 Datasheet, Rev. M
For the latest datasheet, please visit www.onsemi.com
Features
Table 1:
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Parameter
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Superior low light performance
High sensitivity
Low dark current
Simple two-wire serial interface
Auto black level calibration
Programmable controls: gain, frame size/rate,
exposure, left–right and top–bottom image reversal,
window size and panning
Data interface: CCP2 compliant sub-low-voltage
differential signaling (sub-LVDS) or single lane serial
mobile industry processor interface (MIPI)
SMIA 1.0 compatible; MIPI 1.0 compliant
On-chip phase-locked loop (PLL) oscillator
Bayer-pattern down-size scaler
Integrated lens shading correction
Internal power switch for ultra-low standby
current consumption
30 fps at full resolution
2D defect pixel correction
2624-bit one-time programmable memory (OTPM)
for storing module information and lens shading
correction.
Active imager size
2.828 mm (H) x 2.128 (V)
Active pixels
1608 H x 1208 V
Pixel size
1.75 x 1.75 m
Color filter array
RGB Bayer pattern
Shutter type
Electronic rolling shutter (ERS)
Input clock frequency
6–27 MHz
Maximum data rate
640 Mb/s (CCP) and 768 Mb/s (MIPI)
UXGA
(1600 x 1200)
Programmable up to 21 fps in profile
0 mode (RAW10)
Programmable up to 30 fps in profile
1/2 mode (RAW10)
XGA
(1024 x 768)
Programmable up to 42 fps in profile
0 mode (RAW10)
Programmable up to 61 fps in profile
1/2 mode (RAW10)
HD (1280 x 720)
30 fps
UXGA
(1600 x 1200)
30 fps (RAW10)
VGA (640 x 480)
60 fps (RAW10)
QVGA (320X240) 120 fps (RAW10)
HD (1280 x 720)
Cellular phones
Digital still cameras
PC cameras
PDAs
MT9D015_DS Rev. M Pub. 4/15 EN
1/5-inch UXGA (4:3)
ADC resolution
Applications
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4356.15 m (H) x 4354.85 m (V)
Optical format
MIPI
frame
rate
The ON Semiconductor MT9D015 is a 1/5-inch
UXGA-format CMOS active-pixel digital image
sensor with a pixel array of 1600H x 1200V
(1608H x 1208V including border pixels). It incorporates sophisticated on-chip camera functions such as
windowing, mirroring, column and subsampling
modes. It is programmable through a simple two-wire
serial interface and has very low power consumption.
1
Value
Die size
CCP
frame
rate
General Description
Key Performance Parameters
30 fps (RAW10)
10-bit
Responsivity
0.86 V/lux-sec
Dynamic range
62 dB
SNRMAX
38.7 dB
Supply Analog
voltage Digital
1.70–1.90 V (1.80 V nominal)
Power consumption
272 mW at 30 fps (TYP)
Operating temperature
–30°C to +70°C
Packaging
Bare die
2.40–2.90 V (2.80 V nominal)
©Semiconductor Components Industries, LLC,2015
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
MT9D015D00STCMC25BC1-200
2 MP 1/4" CIS
Die Sales, 200m Thickness
MT9D015D00STCPC25BC1-400
2 MP 1/4" CIS
Die Sales, 400m Thickness
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Table of Contents
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Embedded Data Format and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Control of the Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Sensor Core Digital Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Digital Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Timing Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Chief Ray Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SMIA and MIPI Specification Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
List of Figures
List of Figures
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Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Typical Configuration (Connection) – Serial Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Configuration (Connection) – MIPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Sequential Write, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Effect of Limiter on the SMIA Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Timing of SMIA Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MT9D015 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
MT9D015 SMIA Profile 1/2 Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
MT9D015 SMIA Profile 0 Clocking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Full Resolution Frame Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of horizontal_mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Effect of vertical_flip on Readout Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Effect of x_odd_inc = 3 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Pixel Readout (No Subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Pixel Readout (x_odd_inc = 3, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
100 Percent Color Bars Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Fade-to-Gray Color Bars Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Test Cursor Behavior when image_orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Soft Standby and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Definition of Timing for Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Internal Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Chief Ray Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
List of Tables
List of Tables
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Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Address Space Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Embedded Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Definitions for Programming Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Programming Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PLL in System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Signal State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Streaming/STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Row Address Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Minimum Row Time and Blanking Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Minimum Frame Time and Blanking Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
fine_integration_time Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Gain Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Electrical Characteristics (EXTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Two-Wire Serial Interface Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Two-Wire Serial Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Electrical Characteristics (Serial CCP2 Pixel Data Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Electrical Characteristics (Serial MIPI Pixel Data Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power-On Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
DC Electrical Definitions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Absolute Maximum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
General Description
General Description
The MT9D015 digital image sensor features ON Semiconductor’s breakthrough low
noise CMOS imaging technology that achieves near-CCD image quality (based on
signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost,
and integration advantages of CMOS.
When operated in its default mode, the sensor generates a UXGA image at 21 frames per
second (fps) when ext_clk_freq_mhz = 16 MHz. An on-chip analog-to-digital converter
(ADC) generates a 10-bit value for each pixel.
Functional Overview
The MT9D015 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between 6 and 27 MHz. The maximum
pixel rate is 64 Mp/s, corresponding to a video timing pixel clock rate of 91.4 MHz. A
block diagram of the sensor is shown in Figure 1.
Figure 1:
Block Diagram
Active-Pixel
Sensor (APS)
Array
Analog Processing
Sync
Signals
Timing Control
Shading
Correction
ADC
Scaler
Control Registers
Limiter
FIFO
Data
Out
Two-wire
Serial Interface
The core of the sensor is a 2Mp active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row in turn. In
the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between
reset and readout. Once a row has been read, the data from the columns is sequenced
through an analog signal chain (providing offset correction and gain), and then through
an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain (which provides further data
corrections and applies digital gain).
The pixel array contains optically active and light-shielded (dark) pixels. The dark pixels
are used to provide data for on-chip offset-correction algorithms (black level control).
The sensor contains a set of control and status registers that can be used to control many
aspects of the sensor behavior including the frame size, exposure, and gain setting.
These registers can be accessed through a two-wire serial interface.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Functional Overview
The output from the sensor is a Bayer pattern; alternate rows are a sequence of either
green and red pixels or blue and green pixels. The offset and gain stages of the analog
signal chain provide per-color control of the pixel data.
The control registers, timing and control, and digital processing functions shown in
Figure 1 on page 6 are partitioned into three logical parts:
• A sensor core that provides array control and data path corrections.
• A digital shading correction block to compensate for color/brightness shading introduced by the lens or CRA curve mismatch.
• Functionality to support the SMIA standard. This includes a horizontal and vertical
image scaler, a limiter, a data compressor, an output FIFO, and a serializer.
The output FIFO prevents data bursts by keeping the data rate continuous.
Pixel Array
The sensor core uses a Bayer color pattern, as shown in Figure 2. The even-numbered
rows contain green and red pixels; odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels; odd-numbered columns
contain red and green pixels.
Figure 2:
Pixel Color Pattern Detail (Top Right Corner)
Column Readout Direction
..
.
Black Pixels
First clear
pixel
Row
Readout
Direction
Gr R Gr R Gr
...
B Gb B Gb B
Gr R Gr R Gr
B Gb B Gb B
MT9D015_DS Rev. M Pub. 4/15 EN
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Operating Modes
Operating Modes
The MT9D015 can operate in either serial CCP2 or serial MIPI mode (preconfigured at
the factory). In both cases, the sensor has a SMIA-compatible register interface while the
I2C device address is compliant with SMIA or MIPI requirements as appropriate. The
reset level on the TEST pin must be tied in a way that is compatible with the configured
serial interface of the sensor, for instance TEST = 0 for CCP2 and TEST = 1 for MIPI.
Typical configurations are shown in Figure 3 and Figure 4 on page 9. These operating
modes are described in “Control of the Signal Interface” on page 32.
For low-noise operation, the MT9D015 requires separate power supplies for analog and
digital. Incoming digital and analog ground conductors can be tied together next to the
die. Both power supply rails should be decoupled from ground using capacitors as close
as possible to the die. The use of inductance filters is not recommended on the power
supplies or output signals.
R PULL-UP
1.5kΩ2
Typical Configuration (Connection) – Serial Output Mode
1.5kΩ2
Figure 3:
Twowire
serial
interface
Digital
power1
Analog
power1
VDD
VAA
VDD_PLL VAA_PIX
SDATA
SCLK
DATA_N
DATA_P
Active LOW reset
To
controller
CLK_N
XSHUTDOWN4
CLK_P
External clock in
(6–27 MHz)
General
purpose inputs
No connect X
No connect X
EXTCLK
GPI[3:0]5
ATEST1
ATEST2
TEST3
AGND
DGND
Digital power6 Analog power6
Notes:
MT9D015_DS Rev. M Pub. 4/15 EN
1.
2.
3.
4.
5.
All power supplies must be adequately decoupled.
A resistor value of 1.5kis recommended, but it may be greater for slower two-wire speed.
TEST must be tied to GND for SMIA configuration.
Also referred to as RESET_BAR.
The GPI pins can be statically pulled HIGH or LOW and used as module IDs. All GPI pins must be
driven to avoid leakage current.
6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
8
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Operating Modes
7. VPP, which can be used during the module manufacturing process, is not shown in Figure 3. This
pad is left unconnected during normal operation.
8. ATEST1 and ATEST2 must be floating.
R PULL-UP
1.5kΩ2
Typical Configuration (Connection) – MIPI Mode
1.5kΩ2
Figure 4:
Twowire
serial
interface
Digital
power1
Analog
power1
VDD
VAA
VDD_PLL VAA_PIX
SDATA
SCLK
DATA_N
DATA_P
Active LOW reset
To
controller
CLK_N
XSHUTDOWN4
CLK_P
External clock in
(6–27 MHz)
EXTCLK
GPI[3:0]5
General
purpose inputs
ATEST1
ATEST2
TEST3
No connect X
No connect X
AGND
DGND
Digital power6 Analog power6
Notes:
MT9D015_DS Rev. M Pub. 4/15 EN
1.
2.
3.
4.
5.
All power supplies must be adequately decoupled.
A resistor value of 1.5kis recommended, but it may be greater for slower two-wire speed.
TEST must be tied to VDD for MIPI configuration.
Also referred to as RESET_BAR.
The GPI pins can be statically pulled HIGH or LOW and used as module IDs. All GPI pins must be
driven to avoid leakage current.
6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
7. VPP, which can be used during the module manufacturing process, is not shown in Figure 3. This
pad is left unconnected during normal operation.
8. ATEST1 and ATEST2 must be floating.
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Signal Descriptions
Signal Descriptions
Table 3 provides signal descriptions for MT9D015 die. For pad location and aperture
information, refer to the MT9D015 die data sheet.
Table 3:
Signal Descriptions
Pad Name
Pad Type
Description
EXTCLK
Input
Master clock input. PLL input clock. 6–27 MHz.
RESET_BAR
(XSHUTDOWN)
Input
Asynchronous active LOW reset. When asserted, data output stops and all internal
registers are restored to their factory default settings.
SCLK
Input
Serial clock for access to control and status registers.
GPI[3:0]
Input
General purpose inputs.
After reset, these pads are powered up (enabled—see R0x301A) by default; these pads
must be bonded to a HIGH or LOW state.
Failure to bond as required will result in excessive power consumption.
TEST
Input
Enable manufacturing test modes. Connect to DGND for normal operation of the
CCP2-configured sensor, or connect to VDD power for the MIPI configured sensor.
SDATA
I/O
Serial data for reads from and writes to control and status registers.
DATA_P
Output
Differential CCP2/MIPI (sub-LVDS) serial data (positive).
DATA_N
Output
Differential CCP2/MIPI (sub-LVDS) serial data (negative).
CLK_P
Output
Differential CCP2/MIPI (sub-LVDS) serial clock/strobe (positive).
CLK_N
Output
Differential CCP2/MIPI (sub-LVDS) serial clock/strobe (negative).
VAA
Supply
Analog power supply.
VDD_PLL
Supply
PLL power supply.
VAA_PIX
Supply
Analog power supply.
AGND
Supply
Analog ground.
VDD
Supply
Digital power supply.
DGND
Supply
Digital ground.
VPP
Supply
OTPM programming power supply
MT9D015_DS Rev. M Pub. 4/15 EN
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The two-wire serial interface bus enables read/write access to control and status registers within the sensor. This interface is designed to be compatible with the SMIA 1.0 Part
2: CCP2 Specification camera control interface (CCI), which uses the electrical characteristics and transfer protocols of the I2C specification.
The protocols described in the I2C specification allow the slave device to drive SCLK
LOW; the sensor uses SCLK as an input only and therefore never drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of
low-level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the MT9D015 for the MIPI configured sensor are 0x6C (write
address) and 0x6D (read address) in accordance with the MIPI specification. But for the
CCP2 configured sensor, the default slave addresses used are 0x20 (write address) and
0x21 (read address) in accordance with the SMIA specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA LOW
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
SMIA CCI.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is LOW and must be stable while SCLK is HIGH.
Typical Sequence
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a READ, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit READ slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each
8-bit transfer. The slave’s internal register address is automatically incremented after
every 8 bits are transferred. The data transfer is stopped when the master sends a
no-acknowledge bit.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Single READ from Random Location
This sequence (Figure 5) starts with a dummy WRITE to the 16-bit address that is to be
used for the READ. The master terminates the WRITE by generating a restart condition.
The master then sends the 8-bit READ slave address/data direction byte and clocks out
1 byte of register data. The master terminates the READ by generating a no-acknowledge
bit followed by a stop condition. Figure 5 shows how the internal register address maintained by the MT9D015 is loaded and incremented as the sequence proceeds.
Figure 5:
Single READ from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
M+1
Read Data
A P
slave to master
master to slave
Single READ from Current Location
This sequence (Figure 6) performs a read using the current value of the MT9D015
internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent read
sequences.
Figure 6:
Single READ from Current Location
Previous Reg Address, N
S
Slave Address
1 A
Reg Address, N+1
Read Data
A P
S
Slave Address
N+2
1 A
Read Data
A P
Sequential READ, Start from Random Location
This sequence (Figure 7) starts in the same way as the single READ from random location (Figure 5). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte reads until L bytes have been read.
Figure 7:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Read Data
MT9D015_DS Rev. M Pub. 4/15 EN
M+2
A
Read Data
A
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
M+L-2
M+3
Read Data
A
13
1 A
M+L-1
A
Read Data
M+1
Read Data
A
M+L
A P
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Two-Wire Serial Register Interface
Sequential READ, Start from Current Location
This sequence (Figure 8) starts in the same way as the single READ from current location
(Figure 6 on page 13). Instead of generating a no-acknowledge bit after the first byte of
data has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until L bytes have been read.
Figure 8:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
1 A
N+1
Read Data
A
N+2
Read Data
A
N+L-1
Read Data
A
Read Data
N+L
A P
Single WRITE to Random Location
This sequence (Figure 9) begins with the master generating a start condition. The slave
address/data direction byte signals a WRITE and is followed by the HIGH then LOW
bytes of the register address that is to be written. The master follows this with the byte of
write data. The WRITE is terminated by the master generating a stop condition.
Figure 9:
Single WRITE to Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
A
M+2
Write Data
A
Reg Address, M
Reg Address[7:0]
Write Data
A
A
M+L-2
M+3
Write Data
M+1
Write Data
A
M+L-1
Write Data
A
M+L
A
P
A
Sequential WRITE, Start at Random Location
This sequence (Figure 10) starts in the same way as the single WRITE to random location
(Figure 9). Instead of generating a stop condition after the first byte of data has been
transferred, the master continues to perform byte writes until L bytes have been written.
The WRITE is terminated by the master generating a stop condition.
Figure 10:
Sequential Write, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
MT9D015_DS Rev. M Pub. 4/15 EN
M+2
A
Write Data
A
Reg Address, M
Reg Address[7:0]
A
Write Data
M+L-2
M+3
Write Data
A
14
M+1
A
M+L-1
A
Write Data
M+L
A
P
A
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Registers
Registers
Note:
The detailed register lists and descriptions are in a separate document, the MT9D015
Register Reference.
The MT9D015 provides a 32-bit register address space accessed through a serial interface (“Single READ from Random Location” on page 13). Each register location is 8 or 16
bits in size.
The address space is divided into the five major regions shown in Table 4.
Table 4:
Address Space Regions
Address Range
Description
0x0000–0x0FFF
Configuration registers
(read-only and read-write dynamic registers)
Parameter limit registers
(read-only static registers)
Image statistics registers
(none currently defined)
Manufacturer-specific registers
(read-only and read-write dynamic registers)
Reserved (undefined)
0x1000–0x1FFF
0x2000–0x2FFF
0x3000–0x3FFF
0x4000–0xFFFF
Register Notation
The underlying mechanism for reading and writing registers provides byte write capability. However, it is convenient to consider some registers as multiple adjacent bytes.
The MT9D015 uses 8-bit, 16-bit, and 32-bit registers, all implemented as 1 or more bytes
at naturally aligned, contiguous locations in the address space.
In this document, registers are described either by address or by name. When registers
are described by address, the size of the registers is explicit. For example, R0x3024 is an
8-bit register at address 0x3024, and R0x3000–1 is a 16-bit register at address 0x3000–
0x3001. When registers are described by name, refer to the register table to determine
their size.
Register Aliases
A consequence of the internal architecture of the MT9D015 is that some registers are
decoded at multiple addresses. Some registers in “configuration space” are also decoded
in “manufacturer-specific space.” To provide unique names for all registers, the name of
the register within manufacturer-specific register space has a trailing underscore. For
example, R0x0000–1 is model_id, and R0x3000–1 is model_id_ (see the register table for
more examples). The effect of reading or writing a register through any of its aliases is
identical.
Bit Fields
Some registers provide control of several different pieces of related functionality, making
it necessary to refer to bit fields within registers. As an example of the notation used for
this, the least significant 4 bits of the model_id register are referred to as model_id[3:0] or
R0x0000–1[3:0].
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Registers
Bit Field Aliases
In addition to the register aliases described in “Register Aliases” on page 15, some
register fields are aliased in multiple places. For example, R0x0100 (mode_select) has
only one operational bit, R0x0100[0]. This bit is aliased to R0x301A–B[2]. The effect of
reading or writing a bit field through any of its aliases is identical.
Byte Ordering
Registers that occupy more than 1 byte of address space are shown with the lowest
address in the highest-order byte lane to match the byte-ordering on the SMIA bus. For
example, the model_id register is R0x0000–1. In the register table the default value is
shown as 0x1501. This means that a READ from address 0x0000 would return 0x15, and a
READ from address 0x0001 would return 0x01. When reading this register as two 8-bit
transfers on the serial interface, the 0x15 will appear on the serial interface first, followed
by the 0x01.
Address Alignment
All register addresses are aligned naturally. Registers that occupy 2 bytes of address space
are aligned to even 16-bit addresses, and registers that occupy 4 bytes of address space
are aligned to 16-bit addresses that are an integer multiple of 4.
Bit Representation
For clarity, 32-bit hex numbers are shown with an underscore between the upper and
lower 16 bits. For example: 0x3000_01AB.
Data Format
Most registers represent an unsigned binary value or set of bit fields. For all other register
formats, the format is stated explicitly at the start of the register description. The notation for these formats is shown in Table 5.
Table 5:
Name
Description
FIX16
Signed fixed-point, 16-bit number: two’s complement number,
8 fractional bits. Examples: 0x0100 = 1.0, 0x8000 = –128, 0xFFFF = –0.0039065
UFIX16
FLP32
MT9D015_DS Rev. M Pub. 4/15 EN
Data Formats
Unsigned fixed-point, 16-bit number: 8.8 format. Examples: 0x0100 = 1.0, 0x280 =
2.5
Signed floating-point, 32-bit number: IEEE 754 format. Example: 0x4280_0000 =
64.0
16
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Registers
Register Behavior
Registers vary from “read-only,” “read/write,” and “read, write-1-to-clear.”
Double-Buffered Registers
Some sensor settings cannot be changed during frame readout. For example, changing
R0x0344–5 (x_addr_start) partway through frame readout would result in inconsistent
row lengths within a frame. To avoid this, the MT9D015 double-buffers many registers
by implementing a “pending” and a “live” version. READs and WRITEs access the
pending register. The live register controls the sensor operation.
The value in the pending register is transferred to a live register at a fixed point in the
frame timing, called frame start. Frame start is defined as the point at which the first
dark row is read out internally to the sensor. In the register tables the “Sync’d” column
shows which registers or register fields are double-buffered in this way.
Using grouped_parameter_hold
Register grouped_parameter_hold (R0x0104) can be used to inhibit transfers from the
pending to the live registers. When the MT9D015 is in streaming mode, write “1” to this
register before making changes to any group of registers where a set of changes is
required to take effect simultaneously. When this register is set to “0,” all transfers from
pending to live registers take place on the next frame start.
An example of the consequences of failing to set this bit follows:
– An external auto exposure algorithm might want to change both gain and integration time between two frames. If the next frame starts between these operations, it
will have the new gain, but not the new integration time, which would return a
frame with the wrong brightness that might lead to a feedback loop with the AE
algorithm resulting in flickering.
Bad Frames
A bad frame is a frame where all rows do not have the same integration time or where
offsets to the pixel values have changed during the frame.
Many changes to the sensor register settings can cause a bad frame. For example, when
line_length_pck (R0x0342–3) is changed, the new register value does not affect sensor
behavior until the next frame start. However, the frame that would be read out at that
frame start will have been integrated using the old row width, so reading it out using the
new row width would result in a frame with an incorrect integration time.
In the register tables, the “Bad Frame” column shows where changing a register or
register field will cause a bad frame. The following notation is used:
N—No. Changing the register value will not produce a bad frame.
Y—Yes. Changing the register value might produce a bad frame.
YM—Yes; but the bad frame will be masked out when mask_corrupted_frames
(R0x0105) is set to “1.”
MT9D015_DS Rev. M Pub. 4/15 EN
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Registers
Changes to Integration Time
If the integration time is changed while FRAME_VALID (FV) is asserted for frame n, the
first frame output using the new integration time is frame (n + 2). The sequence is as
follows:
1. During frame n, the new integration time is held in the pending register.
2. At the start of frame (n + 1), the new integration time is transferred to the live register.
Integration for each row of frame (n + 1) has been completed using the old integration
time.
3. The earliest time that a row can start integrating using the new integration time is
immediately after that row has been read for frame (n + 1). The actual time that rows
start integrating using the new integration time is dependent upon the new value of
the integration time.
4. When frame (n + 2) is read out, it will have been integrated using the new integration
time.
If the integration time is changed on successive frames, each value written will be
applied for a single frame; the latency between writing a value and it affecting the frame
readout remains at two frames.
Changes to Gain Settings
Usually, when the gain settings are changed, the gain is updated on the next frame start.
When the integration time and the gain are changed at the same time, the gain update is
held off by one frame so that the first frame output with the new integration time also
has the new gain applied. In this case, a new gain should not be set during the extra
frame delay. There is an option to turn off the extra frame delay by setting reset_register[14] bit.
Embedded Data
The current values of implemented registers in the address range 0x0000–0x0FFF can be
generated as part of the pixel data. This embedded data is enabled by default when the
serial pixel data interface is enabled.
The current value of a register is the value that was used for the image data in that frame.
In general, this is the live value of the register. The exceptions are:
• The integration time is delayed by one further frame, so that the value corresponds to
the integration time used for the image data in the frame. See “Changes to Integration
Time” on page 18.
• The PLL timing registers are not double-buffered, because the result of changing
them in streaming mode is undefined. Therefore, the pending and live values for
these registers are equivalent.
MT9D015_DS Rev. M Pub. 4/15 EN
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Embedded Data Format and Control
When the serial pixel data path is selected, the first two rows of the output image contain
register values that are appropriate for the image. In this mode, the first two lines and the
last line of data are not equally spaced. The format of this data is shown in Table 6. In the
table, 8-bit (RAW8) and 10-bit (RAW10) versions of the data are shown. The 10-bit format
places the data byte in bits [9:2] and sets bits [1:0] to a constant value of 01. Register
values that are shown as “??” are dynamic and may change from frame to frame.
When the parallel pixel data path is selected and R0x306E-F[2:0]= 2 (parallel pixel data
output MUX selects FIFO data). The output image contains two rows of embedded data.
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
0
0X029
1
2
8-Bit
Two-wire
Serial
Interface
Address
Comment
10-Bit
8-Bit
Twowire
Serial
Interface
Address
Comment
0X0A
2-byte tagged data format
(embedded data)
0X029
0X0A
0X2A9
0XAA
cci register index msb
0X2A9
0XAA
CCI register index MSB
0X001
0X00
address 00xx
0X009
0X02
Address 02xx
3
0X295
0XA5
cci register index lsb
0X295
0XA5
CCI register index LSB
4
0X001
0X00
address xx00
0X001
0X00
Address xx00
5
0X169
0X5A
auto increment
0X169
0X5A
auto increment
6
0X055
0X15
7
0X169
0X5A
8
0X005
0X01
9
0X169
0X5A
10
0X080
0X20
11
0X169
0X5A
12
0X019
0X06
13
0X169
0X5A
14
0X029
15
0X169
16
??
17
0X169
18
??
19
0X169
20
??
21
0X169
22
0X001
23
0X169
MT9D015_DS Rev. M Pub. 4/15 EN
0X0A
0
model_id hi
1
model_id lo
2
revision_number
3
4
manufacturer_id
smia_version
0X5A
??
5
frame_count
0X5A
??
6
pixel_order
0X5A
??
7
reserved
0X5A
0X00
8
data_pedestal_hi
0X5A
19
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
2-byte tagged data format
(embedded data)
200
fine_integration_time hi
201
fine_integration_time lo
202
coarse_integration_time hi
203
coarse_integration_time lo
204
analogue_gain_code_glob
al hi
205
analogue_gain_code_glob
al lo
206
analogue_gain_code_gree
nR hi
207
analogue_gain_code_gree
nR lo
208
analogue_gain_code_red
hi
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
24
0X0A9
25
0X2A9
26
0X001
27
0X295
28
0X041
29
0X169
30
0X005
8-Bit
0X2A
9
0XAA
Comment
data_pedestal lo
cci register index msb
0X00
address 00xx
0XA5
cci register index lsb
0X10
address xx10
0X5A
0X01
31
0X169
32
0X001
33
0X169
0X5A
34
0X001
0X00
35
0X169
0X5A
36
0X001
0X00
37
0X169
0X5A
auto increment
10
revision_number_minor
0X5A
0X00
38
0X001
0X00
39
0X169
0X5A
40
0X001
0X00
41
0X169
0X5A
42
0X001
0X00
43
0X169
0X5A
44
0X001
0X00
45
0X169
0X5A
46
0X005
0X01
47
0X169
0X5A
48
0X001
0X00
49
0X169
0X5A
50
0X001
0X00
51
0X169
0X5A
52
??
??
53
0X169
0X5A
54
0X001
0X00
55
0X169
0X5A
56
0X001
0X00
57
0X169
0X5A
58
0X001
0X00
MT9D015_DS Rev. M Pub. 4/15 EN
Two-wire
Serial
Interface
Address
11
smia_pp_version
12
module_date_year
13
module_date_month
14
module_date_day
15
module_date_phase
16
sensor_model_id hi
17
sensor_model_id lo
18
sensor_revision_number
19
sensor_manufacturer_id
1A
sensor_firmwave_version
1B
reserved
1C
serial_number_0 hi
1D
serial_number_0 lo
1E
serial_number_1 hi
20
10-Bit
8-Bit
Twowire
Serial
Interface
Address
??
??
209
analogue_gain_code_red
lo
0X169
0X5A
??
??
020a
analogue_gain_code_blue
hi
0X169
0X5A
??
??
020b
analogue_gain_code_blue
lo
0X169
0X5A
??
??
020c
analogue_gain_code_gree
nB hi
0X169
0X5A
??
??
020d
analogue_gain_codegreen
B lo
0X169
0X5A
??
??
020e
digital_gain_greenR hi
0X169
0X5A
020f
digital_gain_greenR lo
210
digital_gain_red hi
211
digital_gain_red lo
212
digital_gain_blue hi
213
digital_gain_blue lo
214
digital_gain_greenB hi
215
digital_gain_greenB lo
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
Comment
??
??
0X2A9
0XAA
CCI register index MSB
0X00D
0X03
Address 03xx
0X295
0XA5
CCI register index LSB
0X001
0X00
Address xx00
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
auto increment
300
vt_pix_clk_div hi
301
vt_pix_clk_div lo
302
vt_sys_clk_div hi
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
8-Bit
59
0X169
0X5A
60
0X001
0X00
61
0X2A9
0XAA
Two-wire
Serial
Interface
Address
1F
Comment
serial_number_1 lo
cci register index msb
62
0X001
0X00
address 00xx
63
0X295
0XA5
cci register index lsb
64
0X101
0X40
address xx40
65
0X169
0X5A
auto increment
66
0X005
0X01
67
0X169
0X5A
68
0X049
69
0X169
70
??
71
0X169
72
??
73
0X169
74
??
75
0X169
76
??
77
0X169
78
??
79
0X169
80
??
81
0X169
82
0X001
83
0X169
84
0X001
85
0X169
86
0X001
87
0X169
88
0X001
MT9D015_DS Rev. M Pub. 4/15 EN
0X12
40
frame_format_model_type
41
frame_format_model_subtyp
e
42
frame_format_descriptor_0
hi
43
frame_format_descriptor_0
lo
0X5A
??
0X5A
??
0X5A
??
44
frame_format_descriptor_1
hi
0X5A
??
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
0X2A9
0XAA
frame_format_descriptor_2
hi
0X00D
0X03
0X295
0XA5
47
frame_format_descriptor_2
lo
0X101
0X40
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
48
frame_format_descriptor_3
hi
49
frame_format_descriptor_3
lo
004a
frame_format_descriptor_4
hi
004b
frame_format_descriptor_4
lo
0X5A
0X00
??
0X5A
46
0X5A
0X00
??
0X169
??
0X5A
0X00
0X5A
??
0X5A
0X00
0X169
frame_format_descriptor_1
lo
0X5A
??
8-Bit
45
0X5A
??
10-Bit
21
Twowire
Serial
Interface
Address
Comment
303
vt_sys_clk_div lo
304
pre_pll_clk_div hi
305
pre_pll_clk_div lo
306
pll_multiplier_hi
307
308
309
030a
030b
pll_multiplier_lo
op_pix_clk_div hi
op_pix_clk_div lo
op_sys_clk_div hi
op_sys_clk_div lo
CCI register index MSB
Address 03xx
CCI register index LSB
Address xx40
auto increment
340
341
342
343
frame_length_lines hi
frame_length_lines lo
line_length_pck hi
line_length_pck lo
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
8-Bit
89
0X169
0X5A
90
0X001
91
0X169
92
0X001
93
0X169
94
0X001
95
0X169
96
0X001
97
0X169
98
0X001
99
0X169
100
0X001
101
0X169
102
0X001
103
0X169
104
0X001
105
0X169
106
0X001
107
0X169
108
0X001
109
0X169
110
0X001
111
0X169
112
0X001
113
0X169
114
0X001
115
0X169
116
0X001
MT9D015_DS Rev. M Pub. 4/15 EN
0X00
Two-wire
Serial
Interface
Address
004c
Comment
frame_format_descriptor_5
hi
0X5A
0X00
004d
frame_format_descriptor_5
lo
004e
frame_format_descriptor_6
hi
0X5A
0X00
0X5A
0X00
004f
frame_format_descriptor_6
lo
0X5A
0X00
50
frame_format_descriptor_7
hi
0X5A
0X00
51
frame_format_descriptor_7
lo
52
frame_format_descriptor_8
hi
0X5A
0X00
0X5A
0X00
53
frame_format_descriptor_8
lo
0X5A
0X00
54
frame_format_descriptor_9
hi
0X5A
0X00
55
frame_format_descriptor_9
lo
56
frame_format_descriptor_10
hi
0X5A
0X00
0X5A
0X00
57
frame_format_descriptor_10
lo
0X5A
0X00
58
frame_format_descriptor_11
hi
0X5A
0X00
59
frame_format_descriptor_11
lo
22
10-Bit
8-Bit
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X2A9
0XAA
0X00D
0X03
0X295
0XA5
0X201
0X80
Twowire
Serial
Interface
Address
344
345
346
347
348
349
034a
034b
034c
034d
034e
034f
Comment
x_addr_start hi
x_addr_start lo
y_addr_start hi
y_addr_start lo
x_addr_end hi
x_addr_end lo
y_addr_end hi
y_addr_end lo
x_output_size hi
x_output_size lo
y_output_size hi
y_output_size lo
CCI register index MSB
Address 02xx
CCI register index LSB
Address xx80
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
8-Bit
117
0X169
0X5A
118
0X001
119
0X169
120
0X001
0X00
Two-wire
Serial
Interface
Address
005a
Comment
frame_format_descriptor_12
hi
0X5A
0X00
005b
frame_format_descriptor_12
lo
005c
frame_format_descriptor_13
hi
121
0X169
122
0X001
0X5A
123
0X169
124
0X001
125
0X169
126
0X001
127
0X169
128
0X001
129
0X2A9
0XAA
cci register index msb
130
0X001
0X00
address 00xx
131
0X295
0XA5
cci register index lsb
132
0X201
0X80
address xx80
0X00
0X5A
0X00
005d
frame_format_descriptor_13
lo
0X5A
0X00
005e
frame_format_descriptor_14
hi
0X5A
0X00
133
0X169
0X5A
134
0X001
0X00
005f
frame_format_descriptor_14
lo
8-Bit
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
Comment
auto increment
380
381
382
383
384
385
x_even_inc hi
x_even_inc lo
y_odd_inc hi
y_odd_inc lo
y_even_inc hi
y_even_inc lo
386
x_odd_inc hi
387
x_odd_inc lo
auto increment
0X2A9
0XAA
CCI register index MSB
80
analogue_gain_capability hi
0X011
0X04
Address 04xx
0X295
0XA5
CCI register index LSB
81
analogue_gain_capability lo
0X001
0X00
Address xx00
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
135
0X169
0X5A
136
0X005
0X01
137
0X2A9
0XAA
cci register index msb
138
0X001
0X00
address 00xx
139
0X295
0XA5
cci register index lsb
140
0X211
0X84
address xx84
141
0X169
0X5A
142
0X001
0X00
143
0X169
0X5A
144
0X021
0X08
145
0X169
0X5A
146
0X001
0X00
147
0X169
0X5A
148
0X1FD
0X7F
149
0X169
0X5A
150
0X001
0X00
MT9D015_DS Rev. M Pub. 4/15 EN
10-Bit
Twowire
Serial
Interface
Address
auto increment
84
analogue_gain_code_min hi
85
analogue_gain_code_min lo
86
analogue_gain_code_max hi
0X169
0X5A
87
analogue_gain_code_max lo
??
??
0X169
0X5A
88
analogue_gain_code_step hi
0X001
0X00
23
auto increment
400
scaling_mode hi
401
scaling_mode lo
402
spatial_sampling hi
403
spatial_sampling lo
404
scale_m hi
405
scale_m lo
406
scale_n hi
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
8-Bit
151
0X169
0X5A
152
0X005
0X01
153
0X169
0X5A
154
0X001
0X00
155
0X169
0X5A
156
0X001
0X00
157
0X169
0X5A
158
0X001
0X00
159
0X169
0X5A
160
0X005
0X01
161
0X169
0X5A
162
0X001
0X00
163
0X169
0X5A
164
0X001
0X00
165
0X169
0X5A
166
0X001
0X00
167
0X169
0X5A
168
0X001
0X00
169
0X169
0X5A
170
0X001
0X00
171
0X169
0X5A
172
0X021
0X08
173
0X2A9
0XAA
Two-wire
Serial
Interface
Address
89
008a
008b
008c
008d
008e
008f
90
91
92
93
Comment
analogue_gain_code_step lo
analogue_gain_type hi
analogue_gain_type lo
analogue_gain_m0 lo
analogue_gain_m0 lo
analogue_gain_c0 lo
analogue_gain_c0 lo
analogue_gain_m1 lo
analogue_gain_m1 lo
analogue_gain_c1 lo
address 00xx
cci register index lsb
176
0X301
0XC0
address xxc0
177
0X169
0X5A
auto increment
180
0X00D
0X03
181
0X169
0X5A
182
0X029
0X0A
183
0X169
0X5A
184
0X029
0X0A
185
0X169
0X5A
186
0X021
0X08
187
0X169
0X5A
188
0X021
0X08
189
0X169
0X5A
MT9D015_DS Rev. M Pub. 4/15 EN
00C0
00c1
00c2
00c3
00c4
00c5
CCI register index MSB
0X015
0X05
Address 05xx
0X295
0XA5
CCI register index LSB
0X001
0X00
Address xx00
0X169
0X5A
auto increment
0X00
0X169
0X5A
data_format_model_type
data_format_model_subtype
data_format_descriptor_0 hi
data_format_descriptor_0 lo
data_format_descriptor_1 hi
data_format_descriptor_1 lo
24
scale_n lo
500
compression_mode hi
501
compression_mode lo
0X005
0X01
0X2A9
0XAA
CCI register index MSB
0X019
0X06
Address 06xx
0X295
0XA5
CCI register index LSB
0X001
0X00
Address xx00
0X169
0X5A
auto increment
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
0X00
0X01
0X10
0XAA
0X5A
0XA5
0X5A
0X041
0X001
407
Comment
0X2A9
??
0X001
0X005
0X5A
0X169
0X295
0X169
0X169
analogue_gain_c1 lo
175
179
8-Bit
cci register index msb
174
178
10-Bit
Twowire
Serial
Interface
Address
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
600
test_pattern_mode hi
601
test_pattern_mode lo
602
test_data_red hi
603
test_data_red lo
604
test_data_greenR hi
605
test_data_greenR lo
606
test_data_blue hi
607
test_data_blue lo
608
test_data_greenB hi
609
test_data_greenB lo
060a
horizontal_cursor_width hi
060b
horizontal_cursor_width lo
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Offset
10-Bit
190
0X029
8-Bit
0X0A
191
0X169
192
0X021
193
0X169
0X5A
194
0X001
0X00
195
0X169
0X5A
196
0X001
0X00
197
0X169
0X5A
Two-wire
Serial
Interface
Address
00c6
Comment
data_format_descriptor_2 hi
0X5A
0X08
198
0X001
0X00
199
0X169
0X5A
200
0X001
0X00
201
0X169
0X5A
202
0X001
0X00
00c7
00c8
00c9
00ca
00cb
00cc
data_format_descriptor_2 lo
data_format_descriptor_3 hi
data_format_descriptor_3 lo
data_format_descriptor_4 hi
data_format_descriptor_4 lo
data_format_descriptor_5 hi
203
0X169
0X5A
204
0X001
0X00
205
0X169
0X5A
206
0X001
0X00
207
0X169
0X5A
208
0X001
0X00
209
0X2A9
0XAA
cci register index msb
210
0X005
0X01
address 01xx
211
0X295
0XA5
cci register index lsb
00cd
data_format_descriptor_5 lo
00ce
data_format_descriptor_6 hi
00cf
data_format_descriptor_6 lo
212
0X001
0X00
address xx00
213
0X169
0X5A
auto increment
214
??
215
0X169
216
??
217
0X169
??
??
0X169
0X5A
220
0X001
0X00
221
0X169
0X5A
222
??
223
0X169
??
0X2A9
MT9D015_DS Rev. M Pub. 4/15 EN
101
image_orientation
102
reserved
103
software_reset
104
grouped_parameter_hold
??
??
060c
horizontal_cursor_position
hi
0X169
0X5A
??
??
060d
horizontal_cursor_position
lo
0X169
0X5A
060e
vertical_cursor_width hi
060f
vertical_cursor_width lo
610
vertical_cursor_position hi
611
vertical_cursor_position lo
??
??
0X169
0X5A
??
??
0X169
0X5A
??
??
0X169
0X5A
Comment
??
??
0X01D
0X07
Null Data
0X01D
0X07
Null Data - up to end-ofline
0X5A
219
225
mode_select
8-Bit
0X5A
??
218
224
100
10-Bit
Twowire
Serial
Interface
Address
??
??
0X5A
??
0XAA
105
mask_corrupted_frames
cci register index msb
25
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Embedded Data Format and Control
Table 6:
Embedded Data
ROW 1
Row 0
Two-wire
Serial
Interface
Address
Offset
10-Bit
8-Bit
226
0X005
0X01
address 01xx
227
0X295
0XA5
cci register index lsb
228
0X041
0X10
address xx10
229
0X169
230
??
231
0X169
232
??
233
0X169
234
??
235
0X169
236
??
237
0X2A9
0XAA
cci register index msb
238
0X005
0X01
address 01xx
239
0X295
0XA5
cci register index lsb
240
0X081
0X20
address xx20
0X5A
??
Comment
10-Bit
Comment
auto increment
110
ccp2_channel_identifier
111
ccp2_signalling_mode
112
ccp_data_format_hi
113
ccp_data_format_lo
0X5A
??
0X5A
??
0X5A
??
241
0X169
0X5A
242
0X001
0X00
243
0X169
244
??
245
0X01D
0X07
null data
246
0X01D
0X07
null data - up to end-of-line
MT9D015_DS Rev. M Pub. 4/15 EN
8-Bit
Twowire
Serial
Interface
Address
auto increment
120
gain_mode
121
reserved
0X5A
??
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Programming Restrictions
Programming Restrictions
The SMIA specification imposes a number of programming restrictions. An implementation naturally imposes additional restrictions. Table 7 shows a list of programming
rules that must be adhered to for correct operation of the MT9D015. ON Semiconductor
recommends that these rules are encoded into the device driver stack—either implicitly
or explicitly.
Table 7:
Table 8:
Definitions for Programming Rules
Name
Definition
xskip
xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3
yskip
yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3
Programming Rules
Parameter
Minimum Value
Maximum Value
Origin
coarse_integration_time
coarse_integration_time_min
frame_length_lines coarse_integration_time_max_margin
SMIA
fine_integration_time
fine_integration_time_min
line_length_pck fine_integration_time_max_margin
SMIA
digital_gain_*
digital_gain_min
digital_gain_max
SMIA
digital_gain_* is an integer
multiple of
digital_gain_step_size
frame_length_lines
SMIA
min_frame_length_lines
max_frame_length_lines
SMIA
min_line_length_pck
line_length_pck
frame_length_lines
((x_addr_end - x_addr_start +
x_odd_inc)/xskip) +
min_line_blanking_pck
max_line_length_pck
((y_addr_end - y_addr_start +
y_odd_inc)/yskip) +
min_frame_blanking_lines
SMIA
SMIA
x_addr_start
x_addr_min
x_addr_max
SMIA
x_addr_end
x_addr_start
x_addr_max
SMIA
(x_addr_end - x_addr_start+
x_odd_inc)
must be positive
must be positive
SMIA
x_addr_start[0]
0
0
SMIA
x_addr_end[0]
1
1
SMIA
y_addr_start
y_addr_min
y_addr_max
SMIA
y_addr_end
y_addr_start
y_addr_max
SMIA
(y_addr_end - y_addr_start +
y_odd_inc)/
must be positive
must be positive
SMIA
y_addr_start[0]
0
0
SMIA
y_addr_end[0]
1
1
SMIA
x_even_inc
min_even_inc
max_even_inc
SMIA
x_even_inc[0]
1
1
SMIA
y_even_inc
min_even_inc
max_even_inc
SMIA
y_even_inc[0]
1
1
SMIA
x_odd_inc
min_odd_inc
max_odd_inc
SMIA
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Programming Restrictions
Table 8:
Programming Rules (continued)
Parameter
Minimum Value
Maximum Value
Origin
x_odd_inc[0]
y_odd_inc
1
1
SMIA
min_odd_inc
max_odd_inc
SMIA
y_odd_inc[0]
1
1
SMIA
scale_m
scaler_m_min
scaler_m_max
SMIA
scale_n
scaler_n_min
scaler_n_max
SMIA
x_output_size
256
1608
Minimum from
SMIA FS Section
5.2.2.5.
Maximum is a
consequence of
the output FIFO
size on this
implementation.
x_output_size[0]
0
(this is enforced in hardware:
bit[0] is read-only)
0
SMIA FS Section
5.2.2.2.
y_output_size
2
frame_length_lines
Minimum ensures
1 Bayer row-pair.
Maximum avoids
output frame
being longer than
pixel array frame.
y_output_size[0]
0
(this is enforced in hardware:
bit[0] is read-only)
0
SMIA FS Section
5.2.2.2
Notes:
1. With subsampling, start and end pixels must be addressed (impact on x/y start/end addresses,
function of image orientation bits). SMIA FS Errata see “Subsampling” on page 44.
Output Size Restrictions
The SMIA CCP2 specification imposes the restriction that an output line shall be a
multiple of 32 bits in length. This imposes an additional restriction on the legal values of
x_output_size:
• When ccp_format[7:0] = 8 (RAW8 data), x_output_size must be a multiple of 4 (x_output_size[1:0] = 0).
• When ccp_format[7:0] = 10 (RAW10 data), x_output_size must be a multiple of 16
(x_output_size[3:0] = 0).
This restriction can be met by rounding up x_output_size to an appropriate multiple.
Any extra pixels in the output image as a result of this rounding contain undefined pixel
data but are guaranteed not to cause false synchronization on the CCP2 data stream.
There is an additional restriction that x_output_size must be small enough such that the
output row time (set by x_output_size, the framing and CRC overhead of 12 bytes, the
ccp_signalling_mode and the output clock rate) must be less than the row time of the
video array (set by line_length_pck and the video timing clock rate).
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Programming Restrictions
Effect of Scaler on Legal Range of Output Sizes
When the scaler is enabled, it is necessary to adjust the values of x_output_size and
y_output_size to match the image size generated by the scaler. The MT9D015 will not
operate properly if the x_output_size and y_output_size are significantly larger than the
output image. To understand the reason for this, consider the situation where the sensor
is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the
number of pixels in each direction). This situation is shown in Figure 11.
Figure 11:
Effect of Limiter on the SMIA Data Path
Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
Scaler output: scaled to half size
LINE_VALID
PIXEL_VALID
Limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
In Figure 11, three different stages in the SMIA data path (see “Digital Data Path” on
page 61) are shown. The first stage is the output of the sensor core. The core is running at
full resolution and x_output_size is set to match the active array size. The LINE_VALID
(LV) signal is asserted once per row and remains asserted for N pixel times. The
PIXEL_VALID signal toggles with the same timing as LV, indicating that all pixels in the
row are valid.
The second stage is the output of the scaler, when the scaler is set to reduce the image
size by one-half in each dimension. The effect of the scaler is to combine groups of
pixels. Therefore, the row time remains the same, but only half the pixels out of the
scaler are valid. This is signalled by transitions in PIXEL_VALID. Overall, PIXEL_VALID is
asserted for (N/2) pixel times per row.
The third stage is the output of the limiter when the x_output_size is still set to match the
active array size. Because the scaler has reduced the amount of valid pixel data without
reducing the row time, the limiter attempts to pad the row with (N/2) additional pixels. If
this has the effect of extending LV across the whole of the horizontal blanking time, the
MT9D015 will cease to generate output frames.
A correct configuration is shown in Figure 12 on page 30, in addition to showing the
x_output_size reduced to match the output size of the scaler. In this configuration, the
output of the limiter does not extend LV.
Figure 12 on page 30 also shows the effect of the output FIFO, which forms the final stage
in the SMIA data path. The output FIFO merges the intermittent pixel data back into a
contiguous stream. Although not shown in this example, the output FIFO is also capable
of operating with an output clock that is at a different frequency from its input clock.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Programming Restrictions
Figure 12:
Timing of SMIA Data Path
Core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1
LINE_VALID
PIXEL_VALID
Scaler output: scaled to half size
LINE_VALID
PIXEL_VALID
Limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2
LINE_VALID
PIXEL_VALID
Output FIFO: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2
LINE_VALID
PIXEL_VALID
Effect of CCP2 Class on Legal Range of Output Sizes/Frame Rate
The pixel array readout rate is set by line_length_pck x frame_length_lines. With the
default register values, one frame time takes 2360 x 1283 = 3027880 pixel periods. This
value includes vertical and horizontal blanking times so that the full-size image
1600 x 1202 (1200 lines of pixel data, 2 lines of embedded information) forms a subset of
these pixels.
When the internal clock is running at 64 MHz, this frame time corresponds to
3027880/64e6 = 47.31 ms, giving rise to a frame rate of 21.14 fps.
Each pixel is 10 bits, by default. As a result, the serial data rate is required to transmit
faster than the pixel rate. However, the SMIA CCP2 class 2 specifications has a maximum
of 650 Mb/s, which cannot be exceeded.
The SMIA CCP2 specification shows that class 0 (data/clock) runs up to 208 Mb/s.
Therefore, it is not possible to transmit full-resolution images at 15 fps using CCP2 class
0. Changing the ccp_data_format (to use 8 bits per pixel) reduces the bandwidth requirement, but is not enough to allow full-resolution operation.
The only way to get a full image out is to reduce the pixel clock rate until it is appropriate
for the maximum CCP2 class 0 data rate. This requires the pixel rate to be reduced to
20.8 MHz. This has the side effect of reducing the frame rate. Repeating the calculation
above, at 20.8 MHz internal clock, this corresponds to 3027880/20.8e6 = 145 ms, giving
rise to a frame rate of 6.87 fps.
To use CCP2 class 0 with an internal clock of 64 MHz, it is necessary to reduce the
amount of output data. This can be achieved by changing x_output_size, y_output_size
so that less data comes out per frame. A change to the output size can be done in
conjunction with windowing the image from the sensor (by adjusting x_addr_start,
x_addr_end, y_addr_start, y_addr_end) or by enabling the scaler.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Programming Restrictions
Output Data Timing
The output FIFO acts as a boundary between two clock domains. Data is written to the
FIFO in the VT (video timing) clock domain. Data is read out of the FIFO in the OP
(output) clock domain.
When the scaler is disabled, the data rate in the VT clock domain is constant and
uniform during the active period of each pixel array row readout. When the scaler is
enabled, the data rate in the VT clock domain becomes intermittent, corresponding to
the data reduction performed by the scaler.
Maximum frame rate is achieved by setting the video timing clock (vt_clk_freq_mhz) to
91 MHz and using the FIFO to reduce horizontal blanking data rate to 640 Mb/s. At this
setting, a maximum frame rate of 30 fps can be achieved.
A key constraint when configuring the clock for the output FIFO is that the frame rate
out of the FIFO must exactly match the frame rate into the FIFO. When the scaler is
disabled, this constraint can be met by imposing the rule that the row time on the CCP2
data stream must be greater than or equal to the row time at the pixel array. The row time
on the CCP2 data stream is calculated from the x_output_size and the ccp_data_format
(8 or 10 bits per pixel), and must include the time taken in the CCP2 data stream for start
of frame/row, end of row/frame and checksum symbols.
Caution
If this constraint is not met, the FIFO will either underrun or overrun. FIFO underrun or overrun is a fatal error condition that is signalled through the data path_status register
(R0x306A).
Changing Registers while Streaming
The following registers should only be reprogrammed while the sensor is in software
standby:
• ccp2_channel_identifier
• ccp2_signalling_mode
• ccp_data_format
• scale_m
• vt_pix_clk_div
• vt_sys_clk_div
• pre_pll_clk_div
• pll_multiplier
• op_pix_clk_div
• op_sys_clk_div
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Control of the Signal Interface
Control of the Signal Interface
This section describes the operation of the signal interface in all functional modes.
Serial Register Interface
The serial register interface uses the following signals:
• SCLK
• SDATA
SCLK is an input-only signal and must always be driven to a valid logic level for correct
operation; if the driving device can place this signal in High-Z state, an external pull-up
resistor should be connected on this signal.
SDATA is a bidirectional signal. An external pull-up resistor should be connected on this
signal.
This interface is described in detail in “EXTCLK” on page 66.
Default Power-Up State
The MT9D015 provides interfaces for pixel data through the CCP2 high-speed serial
interface described by the SMIA specification or the MIPI serial interface.
At power up and after a hard or soft reset, the reset state of the MT9D015 is to enable the
SMIA CCP2 high speed serial interface for a CCP2-configured sensor, and CSI-2 high
speed serial interface for a MIPI-configured sensor.
The CCP2 and MIPI serial interfaces share pins, and only one can be enabled at time.
This is done at the factory.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Control of the Signal Interface
Serial Pixel Data Interface
The serial pixel data interface uses the following output-only signal pairs:
• DATA_P
• DATA_N
• CLK_P
• CLK_N
The signal pairs are driven differentially using sub-LVDS switching levels. This interface
conforms to the MIPI 1.0 CSI-2 and SMIA CCP2 requirements and supports both data/
clock signalling and data/strobe signalling.
The serial pixel data interface is enabled by default at power up and after reset. DATA_P
and DATA_N are the data pair for the CCP2 or MIPI serial interface.
The DATA_P, DATA_N, CLK_P, and CLK_N pads are turned off if the SMIA serial disable
bit is asserted (R0x301A–B[12] = 1) or when the sensor is in the soft standby state.
In data/clock mode, the clock remains HIGH when no data is being transmitted. In data/
strobe mode before frame start, clock is LOW and data is HIGH.
R0x0112-3 (ccp_data_format) The following data formats are supported:
• 0x0A0A – sensor supports RAW10 uncompressed data format.
• 0x0808 – sensor supports RAW8 uncompressed data format. A sensor with a 10-bit ADC
can support this mode by discarding all but the upper 8 bits of a pixel value.
• 0x0A08 – sensor supports RAW8 data format in which an adaptive compression algorithm is used to perform 10-bit to 8-bit compression on the upper 10 bits of each pixel
value.
Also, the ccp_serial_format register (R0x31AE) register controls which serial interface is
in use when the serial interface is enabled (reset_register[12] = 0). The following serial
formats supported:
• 0x0101 – sensor supports single-lane CCP2 operation.
• 0x0201 – sensor supports single-lane MIPI operation.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Control of the Signal Interface
System States
The system states of the MT9D015 are represented as a state diagram in Figure 13 and
described in subsequent sections. The effect of RESET_BAR on the system state and the
configuration of the PLL in the different states are shown in Table 9 on page 35.
The sensor’s operation is broken down into three separate states: hardware standby, soft
standby, and streaming. The transition between these states might take a certain
amount of clock cycles as outlined in Table 9.
Figure 13:
MT9D015 System States
Power supply turned off
(asynchronous from
every state )
Powered Off
Powered On
Hardware reset active
Hardware
Standby
Reset transition 1-> 0
(asynchronous from
every state )
Hardware reset released
POR not yet completed
POR Active
POR completed
INIT not completed
Internal Init
(1200 EXTCLKs)
Software reset
Init finished
Software
Standby
Mode_Select =1
PLL aquiring Lock
PLL Lock
(16000 EXTCLKs)
Lock acquired
Frame in progress
Wait for
Frame/Row End
Streaming
Mode_Select = 0
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Control of the Signal Interface
Table 9:
PLL in System States
State
Powered off
Hardware standby
POR active
Internal initialization
Software standby
PLL lock
Streaming
Wait for frame end
Note:
EXTCLKs
PLL
1200
VCO powered down
16000
VCO powering up and locking, PLL output bypassed
VCO running, PLL output active
VCO = voltage-controlled oscillator.
Power-On Reset Sequence
When power is applied to the MT9D015, it enters a low-power hardware standby state.
Exit from this state is controlled by the later of two events:
1. The negation of the RESET_BAR input.
2. A timeout of the internal power-on reset circuit.
It is possible to hold RESET_BAR permanently negated and rely upon the internal
power-on reset circuit.
When RESET_BAR is asserted, it asynchronously resets the sensor, truncating any frame
that is in progress.
When the sensor leaves the hardware standby state, it waits for power-on reset and
performs an internal initialization sequence that takes 1200 EXTCLK cycles. After this
time, it enters a low-power soft standby state. While the initialization sequence is in
progress, the MT9D015 will not respond to READ transactions on its two-wire serial
interface. Therefore, a method to determine when the initialization sequence has
completed is to poll a sensor register; for example, R0x0000. While the initialization
sequence is in progress, the sensor will not respond to its device address and READs
from the sensor will result in a NACK on the two-wire serial interface bus. When the
sequence has completed, READs will return the operational value for the register
(0x1501 if R0x0000 is read).
When the sensor leaves soft standby mode and enables the VCO, an internal delay will
keep the PLL disconnected for up to 16000 EXTCLKs so that the PLL can lock.
Soft Reset Sequence
The MT9D015 can be reset under software control by writing “1” to software_reset
(R0x0103). A software reset asynchronously resets the sensor, truncating any frame that
is in progress. The sensor starts the internal initialization sequence, while the PLL and
analog blocks are turned off. At this point, the behavior is exactly the same as for the
power-on reset sequence.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Control of the Signal Interface
Signal State During Reset
Table 10 shows the state of the signal interface during hardware standby (RESET_BAR
asserted) and the default state during soft standby (after exit from hardware standby and
before any registers within the sensor have been changed from their default power-up
values).
Table 10:
Signal State During Reset
Pad Name
Pad Type
Hardware Standby
Software Standby
EXTCLK
RESET_BAR
(XSHUTDOWN)
SCLK
SDATA
Input
Input
Self-biased. Can be left disconnected/floating.
Enabled. Must be driven to a valid logic level.
Input
I/O
Enabled. Must be pulled up or driven to a valid logic level.
Enabled as an input. Must be pulled up or
driven to a valid logic level.
DATA_P
DATA_N
CLK_P
CLK_N
GPI[3:0]
TEST
Output
Output
Output
Output
Input
Input
CCP2: High-Z
MIPI: Ultra Low-Power State (ULPS), represented
as an LP-00 state on the output (both wires at 0V)
Powered up. Must be connected to VDD or DGND.
Enabled. Must be driven to a logic 0 for a serial CCP2-configured
sensor, or 1 for a serial MIPI-configured sensor.
General Purpose Inputs
The MT9D015 provides four general purpose inputs. After reset, the input pads associated with these signals are powered on by default, requiring the pads to be tied to a
defined logic level.
The general purpose inputs are disabled by setting reset_register[8] (R0x301A–B). Once
disabled, the inputs can be left floating. The state of the general purpose inputs can be
read through gpi_status[3:0] (R0x3026–7).
Streaming/Standby Control
The MT9D015 can be switched between its soft standby and streaming states under
register control, as shown in Table 11. The state diagram for transitions between soft
standby and streaming states is shown in Figure 13 on page 34.
Table 11:
MT9D015_DS Rev. M Pub. 4/15 EN
Streaming/STANDBY
Streaming R0x301A–B[2] or R0x0100[0]
Description
0
1
Soft standby
Streaming
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Clocking
Clocking
The MT9D015 contains a PLL for timing generation and control. The PLL contains a
prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler
output, and a set of dividers to generate the output clocks.
Profile 0 Behavior
ON Semiconductor SMIA sensors are profile 2 sensors and have separate video timing
and output clock domains.
If the video timing and output clock domains are programmed with the same dividers,
the part will operate in profile 0 mode as indicated by R0x306E–F[7]. For example, if
Equation 1 is true, then the PLL will have profile 0 behavior:
Profile0_behavior = (vt_sys_clk_div == op_sys_clk_div)
(EQ 1)
& (vt_pix_clk_div == op_pix_clk_div)
When the PLL is programmed to be in profile 0 behavior then the output clock domain is
connected internally to the video timing domain thus ensuring that the sensor behave
as an profile 0 sensor with respect to the PLL.
In profile 0 mode the number of bits between one sync code and the subsequent one are
guaranteed to be equal.
Note that legacy sensors used the profile bit in the datapath_select register R0x306E[7] to
set this behavior. The new behavior of profile 0 mode is equivalent with the old one once
it is set by the host system.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Clocking
Figure 14:
MT9D015 SMIA Profile 1/2 Clocking Structure
External Input Clock
ext_clk_freq_mhz
EXTCLK
PLL Input Clock
pll_ip_clk_freq_mhz
Pre PLL
Divider
Pre_pll_clk_div
2(1, 2, 3.....64)
PLL Output Clock
pll_op_clk_freq_mhz
PLL
Multiplier
PLL_multiplier
80(16,18 .....256)
Video Timing System Clock
vt_sys_clk_freq_mhz
vt _sys_clk
Divider
vt _ pix _clk
Divider
vt_sys_clk_div
1 (1, 2,4,6 ... 16)
vt_pix_clk_div
10 (4, 5, 6...16)1
op_sys _clk
Divider
op _pix _clk
Divider
op_sys_clk_div
1(1,2,4,6...16)
vt_pix_clk
op_pix_clk
op _pix _clk _div
10( 8, 10)
vt_sys_clk_freq_mhz
op_sys_clk
Notes:
1. The combinations vt_sys_clk_div = 1 and vt_pix_clk_div = (4,5, 6,... 16) are also supported even
though the capability register does not advertise this.
2. The pll_multiplier only accepts even values when ccp2_class is set to data/clock signalling. Odd values will be rounded down to the first even number by setting LSB to “0.”
3. The default value for vt_sys_clk_div is outside the range of legal values defined by the capability
registers. This results in correct behavior for the cases listed in Note 1. The default setting is
selected to ensure profile 0 behavior as default with the highest possible frame rate.
The parameter limit register space contains registers that declare the minimum and
maximum allowable values for:
• The frequency allowable on each clock
• The divisors that are used to control each clock
The following factors determine what are valid values, or combinations of valid values,
for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met.
• The minimum/maximum value for the divider/multiplier must be met.
• The value of pll_multiplier should be a multiple of 2 for Data/Strobe signalling.
• The op_pix_clk must never run faster than the vt_pix_clk to ensure that the CCP2
output data stream is contiguous.
• Given the maximum programmed line length, the minimum blanking time, the
maximum image width, the available PLL divisor/multiplier values, and the requirement that the output line time (including the necessary blanking) must be output in a
time equal to or less than the time defined by line_length_pck, the valid combinations
of the clock divisors.
PLL input clock frequency range, after the pre-PLL divider stage, is 2.0–24 MHz.
The usage of the output clocks is:
• vt_pix_clk is used by the sensor core to control the timing of the pixel array. The
sensor core produces one 10-bit pixel each vt_pix_clk period. The line length
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Clocking
(line_length_pck) and fine integration time (fine_integration_time) are controlled in
increments of the vt_pix_clk period.
• op_pix_clk is used to load parallel pixel data from the output FIFO (see Figure 26 on
page 61) to the CCP2 serializer. The output FIFO generates one pixel each op_pix_clk
period. The pixel is either 8-bit or 10-bit depending upon the output data format,
controlled by R0x0112-3 (ccp_data_format).
• op_sys_clk is used to generate the serial data stream on the CCP2 output. The relationship between this clock frequency and the op_pix_clk frequency is dependent
upon the output data format.
In profile 1/2, the output clock frequencies can be calculated as:
Figure 15:
ext_clk_freq_mhz*pll_multiplier
vt_pix_clk_freq_mhz = ----------------------------------------------------------------------------------------------------------------pre_pll_clk_div*vt_sys_clk_div*vt_pix_clk_div
(EQ 2)
ext_clk_freq_mhz*pll_multiplier
op_pix_clk_freq_mhz = --------------------------------------------------------------------------------------------------------------------pre_pll_clk_div*op_sys_clk_div*op_pix_clk_div
(EQ 3)
ext_clk_freq_mhz*pll_multiplier
op_sys_clk_freq_mhz = ------------------------------------------------------------------------------pre_pll_clk_div*op_sys_clk_div
(EQ 4)
MT9D015 SMIA Profile 0 Clocking Structure
External Input Clock
ext_clk_freq_mhz
PLL Input Clock
pll_ip_clk_freq_mhz
Pre PLL
Divider
EXTCLK
Pre_pll_clk_div
2 (1,2,3,4....64)
PLL Output Clock
pll_op_clk_freq_mhz
PLL
Multiplier
PLL_multiplier
80 (16,18....256)
Video Timing System Clock
vt_sys_clk_freq_mhz
vt_sys_ clk
Divider
vt_pix_clk
Divider
vt_sys_clk_div
1 (1, 2,4,6...16)
vt_pix_clk_div
10 (4,5, 6...16)
vt_pix_clk
op_sys_clk
Notes:
1. The legal range yielding profile 0 behavior is limited to the PLL values where the “vt domain” equals
the “op domain”. The vt_sys_clk_div values in the parentheses are therefore the legal values for
both vt_sys_clk_div and op_sys_clk_div, and the vt_pix_clk_div values in the parentheses are legal
values for both vt_pix_clk_div and op_pix_clk_div.
2. The default value for vt_sys_clk_div is outside the range of legal values defined by the capability
registers. This will result in correct behavior for the cases listed in Note 1. The default setting is
selected to ensure profile 0 behavior as default with the highest possible frame rate.
When the video timing domain and the output timing domain have the same divider
values, the PLL is equivalent to the SMIA profile 0 clocking structure. This is achieved by
driving the op_sys_clk domain from the vt_sys_clk output and by driving the op_pix_clk
domain from the vt_pix_clk output.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Clocking
Programming the PLL Divisors
The PLL divisors should be programmed while the MT9D015 is in the soft standby state.
After programming the divisors, it is necessary to wait for the VCO lock time before
enabling the PLL. The PLL is enabled by entering the streaming state.
An external timer needs to delay the entering of streaming mode by 1ms so that the PLL
can lock.
The effect of programming the PLL divisors while the MT9D015 is in the streaming state
is undefined.
Influence of ccp_data_format
R0x0112-3 (ccp_data_format) controls whether the pixel data interface will generate 10
bits per pixel or 8 bits per pixel. The raw output of the sensor core is 10 bits per pixel; the
two 8-bit modes represent a compressed data mode and a mode in which the two least
significant bits of the 10-bit data are discarded.
When the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be
programmed with the value 8. When the pixel data interface is generating 10 bits perpixel, op_pix_clk_div must be programmed with the value 10.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Features
Lens Shading Correction (LC)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The MT9D015 has an embedded shading correction module that can be
programmed to counter the shading effects on each individual Red, GreenB, GreenR,
and Blue color signal.
The Correction Function
Color-dependent solutions are calibrated using the sensor, lens system, and an image of
an evenly illuminated, featureless grey calibration field. From the resulting image the
color correction functions can be derived.
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
Pcorrected  row, col = Psensor(row,col) * f(row,col)
(EQ 5)
where P are the pixel values and f is the color-dependent correction function for each
color channel.
Each function includes a set of color-dependent coefficients defined by registers
R0x3600–3726. The function's origin is the center point of the function used in the
calculation of the coefficients. Using an origin near the central point of symmetry of the
sensor response provides the best results.
The correct sequence to write to the LC registers is as follows:
1. Set R0x3780–1 = 0x0000.
2. Load LC coefficients.
3. Set R0x3780–1 = 0x8000.
To read the LC coefficients, disable LC (set R0x3780–1 = 0x0000) before reading the
register values.
One-Time Programmable Memory (OTPM)
The MT9D015 has 2624 bits of OTP memory that can be used during module manufacturing to store specific module information. This feature enables system integrators and
module manufacturers to label and distinguish various module types based on lenses,
IR-cut filters, or other properties. MT9D015 can support one set of LSC to save in OTPM.
For OTPM programming details, please refer TN-09-248.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Figure 16:
OTPM Block Diagram
Actual OTPM
memory in
hardware - 2624 bits
Registers
(Cache) for
transferring the
data to OTPM
4 Kbits maximum
(R0x3800 to
R0x39FE)
Trigger to Write or
Read OTPM
Record
Type
OTPM Control
(R0x304A)
Data
0x30
1 bit to 4 Kbits
0x31
1 bit to 4 Kbits
0xFE
1 bit to 4 Kbits
Write or Read Data from OTPM after Trigger
Record Type
range from
0x30 - 0x39,
0x50--0xFF, and
0x15--0x1F
(R0x304C)
Program the
record Type
0xFF
1 bit to 4 Kbits
Image Acquisition Modes
The MT9D015 supports ERS mode. When the MT9D015 is streaming, it generates frames
at a fixed rate, and each frame is integrated (exposed) using the ERS. Timing and control
logic within the sensor sequences through the rows of the array, resetting and then
reading each row in turn. In the time interval between resetting a row and subsequently
reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each
row in a frame, the time between row reset and row readout is fixed, leading to a uniform
integration time across the frame. When the integration time is changed (by using the
two-wire serial interface to change register settings), the timing and control logic
controls the transition from old to new integration time in such a way that the stream of
output frames from the MT9D015 switches cleanly from the old integration time to the
new while only generating frames with uniform integration.
Window Control
The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. The output image size is controlled by the x_output_size and y_output_size registers.
Pixel Border
The default settings of the sensor provide a 1600H x 1200V image. A border of up to
4 pixels on each edge can be enabled by reprogramming the x_addr_start, y_addr_start,
x_addr_end, y_addr_end, and x_output_size and y_output_size registers accordingly.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Full Resolution Frame Structure With Embedded Data
Figure 17 shows a full resolution frame structure example. The embedded data enable or
disable is controlled by R0x3064[8], when set the bit to "1", two lines of embedded data
will output on start of image frame.
Figure 17:
Full Resolution Frame Structure Example
FS
2 Embedded Data Lanes
Visible Pixels
Up to 1608 x 1208
Checksums
LE
LS
Line Blanking
N Manufacture Specific Rows
FE
Frame Blanking
Readout Modes
Horizontal Mirror
When the horizontal_mirror bit is set in the image_orientation register, the order of pixel
readout within a row is reversed, so that readout starts from x_addr_end and ends at
x_addr_start. Figure 18 shows a sequence of 6 pixels being read out with horizontal_mirror = 0 and horizontal_mirror = 1. Changing horizontal_mirror causes the Bayer
order of the output image to change; the new Bayer order is reflected in the value of the
pixel_order register.
Figure 18:
Effect of horizontal_mirror on Readout Order
LINE_VALID
MT9D015_DS Rev. M Pub. 4/15 EN
horizontal_mirror = 0
DOUT(9:0)
G0 [9:0]
R0 [9:0]
G1 [9:0]
R1 [9:0]
G2 [9:0]
R2 [9:0]
horizontal_mirror = 1
DOUT(9:0)
R2 [9:0]
G2 [9:0]
R1 [9:0]
G1 [9:0]
R0 [9:0]
G0 [9:0]
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Vertical Flip
When the vertical_flip bit is set in the image_orientation register, the order in which
pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends
at y_addr_start. Figure 19 shows a sequence of 6 rows being read out with
vertical_flip = 0 and vertical_flip = 1. Changing vertical_flip causes the Bayer order of the
output image to change; the new Bayer order is reflected in the value of the pixel_order
register.
Figure 19:
Effect of vertical_flip on Readout Order
FRAME_VALID
vertical_flip = 0
DOUT(9:0)
Row0 [9:0] Row1 [9:0]
Row2 [9:0] Row3 [9:0] Row4 [9:0]
Row5 [9:0]
vertical_flip = 1
DOUT(9:0)
Row5 [9:0] Row4 [9:0]
Row3 [9:0] Row2 [9:0] Row1 [9:0]
Row0 [9:0]
Subsampling
The MT9D015 supports subsampling. Subsampling reduces the amount of data
processed by the analog signal chain in the MT9D015 thereby allowing the frame rate to
be increased. Subsampling is enabled by setting x_odd_inc and/or y_odd_inc. Values of
1 and 3 can be supported. Setting both of these variables to 3 reduces the amount of row
and column data processed. Figure 20 shows a sequence of 8 columns being read out
with x_odd_inc = 3 and y_odd_inc = 1.
Figure 20:
Effect of x_odd_inc = 3 on Readout Sequence
LINE_VALID
x_odd_inc = 1
DOUT[9:0]
G0 [9:0]
R0 [9:0]
G1 [9:0]
R1 [9:0]
G0 [9:0]
R0 [9:0]
G2 [9:0]
R2 [9:0]
G2 [9:0]
R2 [9:0]
G3 [9:0]
R3 [9:0]
LINE_VALID
x_odd_inc = 3
DOUT[9:0]
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Figure 21:
Pixel Readout (No Subsampling)
Y incrementing
X incrementing
Figure 22:
Pixel Readout (x_odd_inc = 3, y_odd_inc = 3)
Y incrementing
X incrementing
Programming Restrictions when Subsampling
When subsampling is enabled as a viewfinder mode and the sensor is switched back and
forth between full resolution and subsampling, ON Semiconductor recommends that
line_length_pck be kept constant between the two modes. This allows the same integration times to be used in each mode.
When subsampling is enabled, it may be necessary to adjust the x_addr_end, x_addr_start and y_addr_end settings: the values for these registers are required to correspond with rows/columns that form part of the subsampling sequence. The adjustment
should be made in accordance with the following rules:
• x_addr_start must be a multiple of 2 for example 0, 4, 6, 8, and x_addr_start = 2 is not
supported
Example:
To achieve 1600 x 1200 full resolution without subsampling, the recommended register
settings are:
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
[full resolution starting address with (4, 4)]
REG=0x0104, 1
//GROUPED_PARAMETER_HOLD
REG=0x0382, 1
//X_ODD_INC
REG=0x0386, 1
//Y_ODD_INC
REG=0x0344, 4
//X_ADDR_START
REG=0x0346, 4
//Y_ADDR_START
REG=0x0348, 1603
//X_ADDR_END
REG=0x034A, 1203
//Y_ADDR_END
REG=0x034C, 1600
//X_OUTPUT_SIZE
REG=0x034E, 1200
//Y_OUTPUT_SIZE
REG=0x0104, 0
//GROUPED_PARAMETER_HOLD
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
To achieve a 800 x 600 resolution with 1/2 subsampling, the recommended register
settings are:
[1/2 subsampling starting address with (8, 8)]
REG=0x0104, 1
//GROUPED_PARAMETER_HOLD
REG=0x0382, 3
//X_ODD_INC
REG=0x0386, 3
//Y_ODD_INC
REG=0x0344, 8
//X_ADDR_START
REG=0x0346, 8
//Y_ADDR_START
REG=0x0348, 1605
//X_ADDR_END
REG=0x034A, 1205
//Y_ADDR_END
REG=0x034C, 800
// X_OUTPUT_SIZE
REG=0x034E, 600
//Y_OUTPUT_SIZE
REG=0x0104, 0
//GROUPED_PARAMETER_HOLD
Table 12 shows the row address sequencing for normal and subsampled readout. The
same sequencing applies to column addresses for subsampled readout. There are two
possible subsampling sequences for the rows (because the subsampling sequence only
read half of the rows) depending upon the alignment of the start address.
Table 12:
Row Address Sequencing
MT9D015_DS Rev. M Pub. 4/15 EN
odd_inc = 1
odd_inc = 3
Normal
Normal
start = 0
start = 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
start = 2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Frame Rate Control
The formula for calculating the frame rate of the MT9D015 are shown below:
x_addr_end - x_addr_start + x_odd_inc
line_length_pck =  -------------------------------------------------------------------------------------------------- + min_line_blanking_pck
subsampling factor
(EQ 6)
y_addr_end - y_addr_start + y_odd_inc
frame_length_lines =  -------------------------------------------------------------------------------------------------- + min_frame_blanking_lines


subsampling factor
(EQ 7)
6
 vt_pixel_clock_mhz * 1 10 
frame rate [FPS] = ---------------------------------------------------------------------------------------------- line_length_pck* frame_length_lines 
Note:
(EQ 8)
Subsampling factor = xskip or yskip
xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3
yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3
Minimum Row Time
The minimum row time and blanking values with default register settings are shown in
Table 13.
Table 13:
Minimum Row Time and Blanking Numbers
1
2
4
min_line_blanking_pck
row_speed[2:0]
0x02E1
0x01C9
0x013D
min_line_length_pck
0x03E1
0x0370
0x02E0
In addition, enough time must be given to the output FIFO so it can output all data at the
set frequency within one row time.
There are therefore three checks that must all be met when programming
line_length_pck:
• line_length_pck > min_line_length_pck in Table 13.
• line_length_pck > (x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) +
min_line_blanking_pck in Table 13.
• The row time must allow the FIFO to output all data during each row. That is,
line_length_pck > (x_output_size / 2 ) * (vt_pix_clk_freq)/(op_pix_clk_freq)
Minimum Frame Time
The minimum number of rows in the image is 2, so min_frame_length_lines will always
equal (min_frame_blanking_lines + 2).
Table 14:
Minimum Frame Time and Blanking Numbers
min_frame_blanking_lines
min_frame_length_lines
MT9D015_DS Rev. M Pub. 4/15 EN
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0x0093
0x054B
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Integration Time
The integration (exposure) time of the MT9D015 is controlled by the fine_integration_time and coarse_integration_time registers.
The limits for the fine integration time are defined by:
fine_integration_time_min
< = fine_integration_time < =  line_length_pck-fine_integration_time_max_margin 
(EQ 9)
The limits for the coarse integration time are defined by:
coarse_integration_time_min < = coarse_integration_t
(EQ 10)
If coarse_integration_time > (frame_lenth_lines-coarse_integration_time_max_margin),
then the frame rate will be reduced.
The actual integration time is given by:
  coarse_integration_time * line_length_pck  + fine_integration_time 
integration_time [sec] = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- vt_pix_clk_freq_mhz*1*10 6 
(EQ 11)
With a vt_pix_clk of 64 MHz, the maximum integration time that can be achieved
without reducing the frame rate is given by:
Maximum integration time [sec] =
(EQ 12)
((
 frame_length_lines -1  * line_length_pck) + (line_length_pck - fine_integration_time_max_margin)-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- vt_pix_clk_freq_mhz * 1* 10 6 
   0x0503  *0x0938 +0x7A3 
= --------------------------------------------------------------------------------------- = 47.34ms
 64 MHz*1*10 6 
Setting an integration time that is greater than the frame time increases the frame time
beyond frame_length_lines to make longer exposure times available.
Fine Integration Time Limits
The limits for the fine_integration_time can be found from fine_integration_time_min
and fine_integration_time_max_margin. Values for different mode combinations are
shown in Table 15.
Table 15:
fine_integration_time Limits
row_speed[2:0]
MT9D015_DS Rev. M Pub. 4/15 EN
1
2
4
fine_integration_time_min
0x01E5
0x0104
0x0052
fine_integration_time_max_margin
0x0191
0x00B7
0x008B
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Analog Gain
The MT9D015 provides two mechanisms for setting the analog gain. The first uses the
SMIA gain model; the second uses the traditional ON Semiconductor gain model. The
following sections describe both models, the mapping between the models, and the
operation of the per-color and global gain control.
Using Per-color or Global Gain Control
The read-only analogue_gain_capability register returns a value of “1,” indicating that
the MT9D015 provides per-color gain control. However, the MT9D015 also provides the
option of global gain control. Per-color and global gain control can be used interchangeably. A write to a global gain register is aliased as a write of the same data to the four
associated color-dependent gain registers. A read from a global gain register is aliased to
a read of the associated greenB/greenR gain register.
The read/write gain mode register required by SMIA has no defined function in the
SMIA specification. In the MT9D015 this register has no side effects on the operation of
the gain; per-color and global gain control can be used interchangeably regardless of the
state of the gain_mode register.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
SMIA Gain Model
The SMIA gain model uses the following registers to set the analog gain:
• analogue_gain_code_global
• analogue_gain_code_greenR
• analogue_gain_code_red
• analogue_gain_code_blue
• analogue_gain_code_greenB
The SMIA gain model requires a uniform step size between all gain settings. The analog
gain is given by:
analogue_gain_m0 x analogue_gain_code
analogue_gain_code_<color>
gain = ------------------------------------------------------------------------------------------------------ = -------------------------------------------------------------------------analogue_gain_c1
8
(EQ 13)
ON Semiconductor Gain Model
The ON Semiconductor gain model uses the following registers to set the analog gain:
• global_gain
• greenr_gain
• red_gain
• blue_gain
• greenb_gain
This gain model maps directly to the control settings applied to the gain stages of the
analog signal chain. This provides a 7-bit gain stage and a number of 2X gain stages. As a
result, the step size varies depending upon whether the 2X gain stages are enabled. The
analog gain is given by:
<color>_gain[6:0]
gain =  <color>_gain[8] + 1    <color>_gain[7] + 1   ----------------------------------------------32
(EQ 14)
As a result of the 2X gain stage, many of the possible gain settings can be achieved in two
different ways. In all cases, the preferred setting is the setting that uses <color>_gain[7]
first, <color>_gain[6:0], and then <color>_gain[8] to apply the desired gain range,,
because this will result in lower noise.
Gain Code Mapping
The ON Semiconductor gain model maps directly to the underlying structure of the gain
stages in the analog signal chain. When the SMIA gain model is used, gain codes are
translated into equivalent settings in the ON Semiconductor gain model.
When the SMIA gain model is in use and values have been written to the
analogue_gain_code_<color> registers, the associated value in the ON Semiconductor
gain model can be read from the associated <color>_gain register. In cases where there is
more than one possible mapping, the 2X gain stage is enabled to provide the mapping
with the lowest noise.
When the ON Semiconductor gain model is in use and values have been written to the
gain_<color> registers, data read from the associated analogue_gain_code_<color>
register is undefined. The reason for this is that many of the gain codes available in the
ON Semiconductor gain model have no corresponding value in the SMIA gain model.
The result is that the two gain models can be used interchangeably, but having written
gains through one set of registers, those gains should be read back through the same set
of registers.
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Minimum Gain and Gain Table
To make the sensor reach saturation status in high light condition, the gain value applied
to this part must larger than 1.375X. In other words, the 1.375X is the minimum gain.
Table 16:
MT9D015_DS Rev. M Pub. 4/15 EN
Gain Table
SMIA Gain (R0x0204)
Global Gain
(R0x305E)
Gain
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
0x0017
0x0018
0x0019
0x001A
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
0x0030
0x1020
0x1024
0x1028
0x102C
0x1030
0x1034
0x1038
0x103C
0x10A0
0x10A2
0x10A4
0x10A6
0x10A8
0x10AA
0x10AC
0x10AE
0x10B0
0x10B2
0x10B4
0x10B6
0x10B8
0x10BA
0x10BC
0x10BE
0x10C0
0x10C2
0x10C4
0x10C6
0x10C8
0x10CA
0x10CC
0x10CE
0x10D0
0x10D2
0x10D4
0x10D6
0x10D8
0x10DA
0x10DC
0x10DE
0x10E0
1
1.125
1.25
1.375
1.5
1.625
1.75
1.875
2
2.125
2.25
2.375
2.5
2.625
2.75
2.875
3
3.125
3.25
3.375
3.5
3.625
3.75
3.875
4
4.125
4.25
4.375
4.5
4.625
4.75
4.875
5
5.125
5.25
5.375
5.5
5.625
5.75
5.875
6
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Table 16:
MT9D015_DS Rev. M Pub. 4/15 EN
Gain Table (continued)
SMIA Gain (R0x0204)
Global Gain
(R0x305E)
Gain
0x0031
0x0032
0x0033
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003C
0x003D
0x003E
0x003F
0x0040
0x0041
0x0042
0x0043
0x0044
0x0045
0x0046
0x0047
0x0048
0x0049
0x004A
0x004B
0x004C
0x004D
0x004E
0x004F
0x0050
0x0051
0x0052
0x0053
0x0054
0x0055
0x0056
0x0057
0x0058
0x0059
0x005A
0x005B
0x005C
0x005D
0x10E2
0x10E4
0x10E6
0x10E8
0x10EA
0x10EC
0x10EE
0x10F0
0x10F2
0x10F4
0x10F6
0x10F8
0x10FA
0x10FC
0x10FE
0x11C0
0x11C1
0x11C2
0x11C3
0x11C4
0x11C5
0x11C6
0x11C7
0x11C8
0x11C9
0x11CA
0x11CB
0x11CC
0x11CD
0x11CE
0x11CF
0x11D0
0x11D1
0x11D2
0x11D3
0x11D4
0x11D5
0x11D6
0x11D7
0x11D8
0x11D9
0x11DA
0x11DB
0x11DC
0x11DD
6.125
6.25
6.375
6.5
6.625
6.75
6.875
7
7.125
7.25
7.375
7.5
7.625
7.75
7.875
8
8.125
8.25
8.375
8.5
8.625
8.75
8.875
9
9.125
9.25
9.375
9.5
9.625
9.75
9.875
10
10.125
10.25
10.375
10.5
10.625
10.75
10.875
11
11.125
11.25
11.375
11.5
11.625
53
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Features
Table 16:
Notes:
MT9D015_DS Rev. M Pub. 4/15 EN
Gain Table (continued)
SMIA Gain (R0x0204)
Global Gain
(R0x305E)
Gain
0x005E
0x005F
0x0060
0x0061
0x0062
0x0063
0x0064
0x0065
0x0066
0x0067
0x0068
0x0069
0x006A
0x006B
0x006C
0x006D
0x006E
0x006F
0x0070
0x0071
0x0072
0x0073
0x0074
0x0075
0x0076
0x0077
0x0078
0x0079
0x007A
0x007B
0x007C
0x007D
0x007E
0x007F
0x11DE
0x11DF
0x11E0
0x11E1
0x11E2
0x11E3
0x11E4
0x11E5
0x11E6
0x11E7
0x11E8
0x11E9
0x11EA
0x11EB
0x11EC
0x11ED
0x11EE
0x11EF
0x11F0
0x11F1
0x11F2
0x11F3
0x11F4
0x11F5
0x11F6
0x11F7
0x11F8
0x11F9
0x11FA
0x11FB
0x11FC
0x11FD
0x11FE
0x11FF
11.75
11.875
12
12.125
12.25
12.375
12.5
12.625
12.75
12.875
13
13.125
13.25
13.375
13.5
13.625
13.75
13.875
14
14.125
14.25
14.375
14.5
14.625
14.75
14.875
15
15.125
15.25
15.375
15.5
15.625
15.75
15.875
1. 1-1.25 gains have been grayed out. Customers should not use less than x1.375 gain to avoid un-saturation issue.
2. The gain range 1-7.875 used analog gain only. The range 8 - 15.875 used 2X digital gain. When
R0x0204[6]= R0x305E[8]=1, 2X digital gain is enabled.
54
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Sensor Core Digital Data Path
Test Patterns
The MT9D015 supports a number of test patterns to facilitate system debug. Test
patterns are enabled using test_pattern_mode (R0x0600–1). The test patterns are listed
in Table 17.
Table 17:
Test Patterns
test_pattern_mode
Description
0
1
2
3
4
Normal operation: no test pattern
Solid color
100% color bars
Fade-to-gray color bars
PN9 link integrity pattern
Test patterns 0–3 replace pixel data in the output image (the embedded data rows are
still present). Test pattern 4 replaces all data in the output image (the embedded data
rows are omitted and test pattern data replaces the pixel data).
For all of the test patterns, the MT9D015 registers must be set appropriately to control
the frame rate and output timing. These include:
• All clock divisors
• x_addr_start
• x_addr_end
• y_addr_start
• y_addr_end
• frame_length_lines
• line_length_pck
• x_output_size
• y_output_size
The MT9D015 will disable digital corrections automatically when test patterns are activated. The test cursor is now added to the end of the data path.
Solid Color Test Pattern
In this mode, all pixel data is replaced by fixed Bayer pattern test data. The intensity of
each pixel is set by its associated test data register (test_data_red, test_data_greenR,
test_data_blue, test_data_greenB).
MT9D015_DS Rev. M Pub. 4/15 EN
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
100 Percent Color Bars Test Pattern
In this test pattern, shown in Figure 23 on page 56, all pixel data is replaced by a Bayer
version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and
black). Each bar is 200 pixels wide and occupies the full height of the output image. Each
color component of each bar is set to either “0” (fully off ) or 0x3FF (fully on for
10-bit data). The pattern repeats after 8 * 200 = 1600 pixels. The image size is set by x_addr_start, x_addr_end, y_addr_start, y_addr_end and may be affected by the setting of
x_output_size, y_output_size. The color-bar pattern starts at the column identified by
x_addr_start. The number of colors that are visible in the output is dependent upon
x_addr_end – x_addr_start and the setting of x_output_size. The width of each color-bar
is fixed at 200 pixels.
The effect of setting horizontal_mirror in conjunction with this test pattern is that the
order in which the colors are generated is reversed. The black bar appears at the left side
of the output image. Any pattern repeat occurs at the right side of the output image
regardless of the setting of horizontal_mirror. The state of vertical_flip has no effect on
this test pattern.
The effect of subsampling and scaling of this test pattern is undefined.
Figure 23:
100 Percent Color Bars Test Pattern
Horizontal mirror = 0
MT9D015_DS Rev. M Pub. 4/15 EN
Horizontal mirror = 1
56
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MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Fade-to-Gray Color Bars Test Pattern
In this test pattern, shown in Figure 24 on page 58, all pixel data is replaced by a Bayer
version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and
black). Each bar is 200 pixels wide and occupies 1024 rows of the output image. Each
color bar fades vertically from full intensity at the top of the image to 50 percent intensity (mid-gray) on the 1024th row. Each color bar is divided into a left and a right half, in
which the left half fades smoothly and the right half fades in quantized steps every 8
pixels for a given color. Due to the Bayer pattern of the colors this means that the level
changes every 16 rows. The pattern repeats horizontally after 8 * 200 = 1600 pixels and
vertically after 1024 rows (using 10-bit data, the fade-to-gray pattern goes from 100 to 50
percent or from 0 to 50 percent for each color component, so only half of the 210 states of
the 10-bit data are used. However, to get all of the gray levels, each state must be held for
two rows, hence the vertical size of 210 / 2 * 2 = 1024). The image size is set by x_addr_start, x_addr_end, y_addr_start, and y_addr_end and may be affected by the setting
of x_output_size and y_output_size. The color-bar pattern starts at the column identified by x_addr_start. The number of colors that are visible in the output is dependent
upon x_addr_end – x_addr_start and the setting of x_output_size. The width of each
color-bar is fixed at 200 pixels.
The effect of setting horizontal_mirror or vertical_flip in conjunction with this test
pattern is that the order in which the colors are generated is reversed. The black bar
appears at the left side of the output image. Any pattern repeat occurs at the right side of
the output image regardless of the setting of horizontal_mirror.
The effect of subsampling and scaling of this test pattern is undefined.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Figure 24:
Fade-to-Gray Color Bars Test Pattern
Horizontal mirror = 0, Vertical flip = 0
Horizontal mirror = 0, Vertical flip = 1
Horizontal mirror = 1, Vertical flip = 0
Horizontal mirror = 1, Vertical flip = 1
PN9 Link Integrity Pattern
This test pattern provides a 512-bit pseudo-random test sequence to test the integrity of
the serial pixel data output stream. The polynomial x9 + x5 + 1 is used. The polynomial is
initialized to 0x1FF at the start of each frame.
When this test pattern is enabled:
• The embedded data rows are disabled, and the value of frame_format_decriptor_1
changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are
present.
• The whole output frame, bounded by the limits programmed in x_output_size and
y_output_size, is filled with data from the PN9 sequence.
• The output data format is (effectively) forced into RAW10 mode regardless of the state
of the data_format register.
This polynomial generates the following sequence of 10-bit values: 0x1FF, 0x378, 0x1A1,
0x336, 0x385, and so on. On the serial pixel data output, these values are streamed out
sequentially without performing the RAW10 packing to bytes that normally occurs on
this interface.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Test Cursors
The MT9D015 supports one horizontal and one vertical cursor, allowing a “cross hair” to
be superimposed on the image or on test patterns 1–3.
The position and width of each cursor are programmable in R0x31E8–0x31EE. Each
cursor can be inhibited by setting its width to “0.”
The programmed cursor position corresponds to an absolute row or column in the pixel
array. For example, setting horizontal_cursor_position to the same value as y_addr_start
would result in a horizontal cursor being drawn starting on the first row of the image.
The cursors are opaque (they replace data from the imaged scene or test pattern). The
color of each cursor is set by the values of the Bayer components in the test_data_red,
test_data_greenR, test_data_blue, and test_data_greenB registers. As a consequence, the
cursors are the same color as test pattern 1 and are therefore invisible when test
pattern 1 is selected.
When vertical_cursor_position = 0x0FFF, the vertical cursor operates in an automatic
mode in which its position advances every frame. In this mode the cursor starts at the
column associated with x_addr_start = 0 and advances by a step-size of 8 columns each
frame until it reaches the column associated with x_addr_start = 2040, after which it
wraps (256 steps). Note that the active pixel array is smaller than this, so in the last
56 steps the cursor will not be visible. The width and color of the cursor in this automatic
mode are controlled in the usual way.
The effect of enabling the test cursors when the image_orientation register is non-zero is
not defined by the SMIA specification. The behavior of the MT9D015 is shown in
Figure 25 on page 60. In this figure the test cursors are shown as translucent for clarity. In
practice, they are opaque (they overlay the imaged scene). The manner in which the test
cursors are affected by the value of image_orientation can be understood from the
following implementation details:
• The test cursors are inserted early in the data path, so that they correlate to rows and
to columns of the physical pixel array (rather than to x and to y coordinates of the
output image).
• The drawing of a cursor starts when the pixel array row or column address matches
the value of the associated cursor_position register. As a result, the cursor start position remains fixed relative to the rows and columns of the pixel array for all settings of
image_orientation.
• The cursor generation continues until the appropriate cursor_width pixels have been
drawn. The cursor width is generated from the start position and proceeds in the
direction of pixel array readout. As a result, each cursor is reflected about an axis
corresponding to its start position when the appropriate bit is set in the image_orientation register.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Sensor Core Digital Data Path
Figure 25:
Test Cursor Behavior when image_orientation
Horizontal mirror = 0, Vertical flip = 0
Readout
Direction
Vertical cursor start
Horizontal mirror = 1, Vertical flip = 0
Readout
Direction
Vertical cursor start
Horizontal cursor start
Horizontal cursor start
Horizontal mirror = 0, Vertical flip = 1
Readout
Direction
Horizontal mirror = 1, Vertical flip = 1
Horizontal cursor start
Horizontal cursor start
Readout
Direction
Vertical cursor start
Vertical cursor start
Digital Gain
Integer digital gains in the range 1–7 can be programmed. A digital gain of “0” sets all
pixel values to “0” (the pixel data will simply represent the value applied by the pedestal
block).
Pedestal
This block adds the value from R0x0008-9 (data_pedestal_) to the incoming pixel value.
The data_pedestal register is read-only by default but can be made read/write by
clearing the lock_reg bit in R0x301A–B.
The only way to disable the effect of the pedestal is to set it to “0.”
MT9D015_DS Rev. M Pub. 4/15 EN
60
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Digital Data Path
Digital Data Path
The digital data path after the sensor core is shown in Figure 26.
Figure 26:
Data Path
Registers
Embedded
Data
Interface with
sensor_core
Limiter
Scaler
MT9D015_DS Rev. M Pub. 4/15 EN
Compression
61
Output
Buffer
Serial Pixel
Data Interface
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Timing Specifications
Timing Specifications
Power-Up Specifications
The digital and analog supply voltages can be powered up in any order. However, ON
Semiconductor recommends the following power-up sequence to minimize current
consumption. The power-up sequence corresponds to the requirements described in
section 3.2 of the SMIA functional specification.
Power-Up Sequence
The recommended power-up sequence for the MT9D015 is shown in Figure 27 and
Table 18 on page 63. The available power supplies—VDD, VDD_PLL, VAA, VAA_PIX—can
be turned on at any point or have the separation specified below for reducing current
consumption during power-up sequence.
1. Turn on the VDD power supply.
2. After 0–500ms, turn on VDD_PLL and VAA/VAA_PIX power supplies.
3. After the last power supply is stable, enable EXTCLK.
4. After EXTCLK is stable, assert RESET_BAR for at least 1ms.
5. Wait 1200 EXTCLKs for internal initialization into soft standby.
6. Configure PLL, output, and image settings to desired values.
7. Wait 16000 EXTCLKs for the PLL to lock before streaming state is reached (enforced in
hardware).
8. Set mode_select = 1 (R0x0100) to start streaming.
Figure 27:
Power-Up Sequence
VDD
t1
VDD_PLL
t2
VAA, VAA_PIX
EXTCLK
t3
t4
RESET_BAR
Hard
Reset
Internal
INIT
t5
Software
Standby
Start I2C access
PLL
Lock
t6
Streaming
t7
Software
Standby
t8
Program OTPM
8.5V
2.5V
VPP
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Timing Specifications
Table 18:
Power-Up Sequence
Definition
Min
Typ
Max
Unit
VDD to VDD_PLL time
Symbol
t
0
–
500
ms
VDD to VAA/VAA_PIX time
t
0
–
500
ms
Active hard reset
t
1
–
–
ms
Internal initialization
t
1200
–
–
EXTCLKs
PLL lock time
t
16000
–
–
EXTCLKs
Soft Standby
t
500
–
ms
Delay 1
t
600
–
ms
Delay 2
t
600
–
ms
1
2
3
4
5
6
7
8
Power-Down Specification
The digital and analog supply voltages can be powered down in any order. However, ON
Semiconductor recommends the following power-down sequence to minimize current
consumption. The power-down sequence corresponds to the requirements described in
section 3.2 of the SMIA functional specification.
Power-Down Sequence
The recommended power-down sequence for the MT9D015 is shown in Figure 28 and in
Table 19 on page 64. The available power supplies—VDD, VDD_PLL, VAA, VAA_PIX—can
be turned off at any point or have the separation specified below for reducing current
consumption during power-down sequence.
1. Disable streaming if output is active by setting mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
3. Assert hard reset by setting RESET_BAR to a logic “0” at least 1ms.
4. Stop EXTCLK; drive this pin to logic “0.”
5. Turn off the VAA/VAA_PIX and VDD_PLL power supplies.
6. After 0–500ms, turn off VDD and power supply.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Timing Specifications
Figure 28:
Power-Down Sequence
VDD
t3
VDD_PLL
t2
VAA, VAA_PIX
EXTCLK
t1
RESET_BAR
Streaming
Table 19:
Software
Standby
Hard
Reset
Turning Off Power Supplies
Power-Down Sequence
Definition
Symbol
Min
Typ
Max
Unit
Hard reset
t1
1
–
–
ms
VAA/VAA_PIX to VDD time
t2
0
–
500
ms
VDD_PLL to VDD time
t3
0
–
500
ms
Hard Standby and Hard Reset
The hard standby state is reached by the assertion of the RESET_BAR pad (hard reset).
Register values are not retained by this action, and will be returned to their default
values once hard reset is completed. The minimum power consumption is achieved by
the hard standby state. This operating mode complies with section 3.1 of the SMIA Functional Specification.
Soft Standby and Soft Reset
The MT9D015 can reduce power consumption by switching to the soft standby state
when the output is not needed. Register values are retained in the soft standby state.
Once this state is reached, soft reset can be optionally enabled to return all register
values back to the default. The details of the sequence are shown in Figure 29.
Soft Standby
1. Disable streaming if output is active by setting mode_select = 0 (R0x0100).
2. The soft standby state is reached after the current row or frame, depending on configuration, has ended.
Soft Reset
1. Follow the soft standby sequence list.
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Timing Specifications
2. Delay 1 frame time; set software_reset = 1 (R0x0103) to start the internal initialization
sequence.
3. After 700 EXTCLKs, the internal initialization sequence is completed and the current
state returns to soft standby automatically. All registers, including software_reset,
returns to their default values.
Figure 29:
Soft Standby and Soft Reset
EXTCLK
mode_select
R0x0100
software_reset
R0x0103
next row/frame
Logic “1”
Logic “0”
Logic “0”
Logic “1”
delay 1 frame
Streaming
MT9D015_DS Rev. M Pub. 4/15 EN
Soft Standby
65
Logic “0”
1200 EXTCLKs
Soft Reset
Soft Standby
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Electrical Specifications
EXTCLK
The electrical characteristics of the EXTCLK input are shown in Table . The EXTCLK
input supports an AC-coupled sine-wave input clock or a DC-coupled square-wave
input clock.
Table 20:
Electrical Characteristics (EXTCLK)
Definition
Condition
Symbol
Min
Typ
Max
Unit
fEXTCLK
6
16
27
MHz
Input clock period
tEXTCLK
166.7
62.5
37
ns
Input clock minimum voltage swing
(AC coupled sine wave)
VIN_AC
0.5
1
1.2
V (pk-pk)
45
50
55
%
tJITTER
545
600
tLOCK
3200
Input clock frequency
Input clock duty cycle
Input clock jitter
cycle-to-cycle
PLL VCO lock time ( at 16 MHz EXTCLK)
Input pad capacitance
CIN
Input HIGH leakage current
VIN=VVD
Input LOW leakage current
VIN=DGND
IIH
3.75
-10
-
ps
ext clk cycles
pF
10
A
IIL
-10
-
10
A
Input HIGH voltage(DC coupled)
VIH
0.7 x VDIG
-
2.9
V
Input LOW voltage (DC coupled)
VlL
-0.3
-
0.3 x VDD
V
Two-Wire Serial Register Interface
Table 21 describes the I/O levels, I/O current and pin capacitance for Two-Wire Serial
Interface. Table 22 describes timing specification for Two-Wire Serial Interface. Figure
30: “Definition of Timing for Two-Wire Serial Interface,” on page 67 shows timing
parameters definition.
Table 21:
Two-Wire Serial Interface Electrical Characteristics
VDD = 1.7-1.9V; VAA = 2.4 -3.1V; Environment temperature = -30°C to 50°C
Symbol
Definition
Condition
Min
Max
Unit
VIH
Input High Voltage
0.7VDD
2.9
V
VIL
Input Low Voltage
-0.3
0.3VDD
V
0
0.4
V
VOL=0.4V
3
-
mA
No pull-up resistor; VIN =
VDD or DGND
-10
+10
A
VOL
Output Low voltage at 3mA sink
current
IOL
Output Low current
Ii
Ci
CLOAD
MT9D015_DS Rev. M Pub. 4/15 EN
Input current each I/O pin
Capacitance for each I/O pin
Load capacitance
66
-
6
pF
N/A
N/A
pF
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Table 22:
Two-Wire Serial Interface Timing Specification
VDD = 1.7-1.9V; VAA = 2.4 -3.1V; Environment temperature = -30°C to 50°C
Symbol
Definition
Min
Max
Unit
fSCLK
SCLK Frequency
0
400
KHz
tHIGH
SCLK High Period
0.6
-
s
tLOW
SCLK Low Period
1.3
-
s
tSRTS
START Setup Time
0.6
-
s
tSRTH
START Hold Time
0.6
-
s
tSDS
Data Setup Time
100
-
ns
tSDH
Data Hold Time
0
Note
s
tSDV
Data Valid Time
-
0.9
s
-
0.9
s
tACV
Data Valid Acknowledge Time
tSTPS
STOP Setup Time
0.6
-
s
tBUF
Bus Free Time between STOP and START
1.3
-
s
tr
SCLK and SDATA Rise Time
-
300
ns
tf
SCLK and SDATA Fall Time
-
300
ns
Note:
Figure 30:
Max tSDH could be 0.9s but must be less than max of tSDV and tACV by a transition time.
Definition of Timing for Two-Wire Serial Interface
tF
tR
70%
30%
SDATA
tSDV
70%
30%
30%
30%
//
70%
//
//
70%
SCLK
tACV
70%
30% 30%
S
tSRTH
1
st
Clock
tSDS
30%
9th Clock
tSDH
tHIGH
tBUF
//
70%
SDATA
70%
30%
//
SCLK
70%
70%
Sr
tSRTS
MT9D015_DS Rev. M Pub. 4/15 EN
//
70%
30%
70%
70%
30%
P
th
9
tLOW
67
Clock
S
tSTPS
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Serial Pixel Data Interface
The electrical characteristics of the serial pixel data interface (CLK_P, CLK_N, DATA_P,
DATA_N are shown in Table 23.
Table 23:
Electrical Characteristics (Serial CCP2 Pixel Data Interface)
VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; Ambient Temperature
Definition
Symbol
Operating frequency
Min
Typ
180
Fixed common mode voltage
VCMF
Differential voltage swing
VOD
Drive current range
Max
Unit
360
MHz
0.8
0.9
1
V
100
150
200
mV
0.83
1.5
2
mA
Drive current variation
Output impedance
40
Output impedance mismatch
Clock duty cycle at 416 MHz
45
50
15
%
140

10
%
55
%
Rise time (20–80%)
300
400
ps
Fall time (20–80%)
300
400
ps
Differential skew
500
ps
Channel-to-channel slew
200
ps
Maximum data rate
Data/strobe mode
Data/clock mode
640
208
Mb/s
Power supply rejection ratio (PSRR) 0–100 MHz
30
dB
Power supply rejection ratio (PSRR) 100–1000 MHz
10
dB
Table 24:
Electrical Characteristics (Serial MIPI Pixel Data Interface)
VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VVDD _PLL = 2.8V; Ambient temperature
Definition
High speed transmit differential voltage
High speed transmit static common-mode
voltage
VOD mismatch when output is Differential-1 or
Differential-0
High speed output high voltage mismatch
Symbol
Min
Max
Unit
VOD
140
270
mV
VCMTX
150
250
mV
dVOD
<14
mV
dVCMTX
16
mV
64

Single ended output impedance
ZOS
Single ended output impedance mismatch
dZOS
40
Typ
10

20–80% rise time
t
R
250
ps
20–80% fall time
tF
250
ps
Output LOW level
VOL
50
mV
Output HIGH level
VOH
1.3
V
Output impedance of low power parameter
ZOLP
110

15–85% rise time
TRLP
25
ns
15–85% fall time
TFLP
25
ns
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Table 24:
Electrical Characteristics (Serial MIPI Pixel Data Interface)
VDD = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V; VVDD _PLL = 2.8V; Ambient temperature
Definition
Symbol
Min
Typ
Max
Unit
Slew rate (CLOAD = 5–20pF)
dv/dtsr
235
mV/ns
Slew rate (CLOAD = 20–70pF)
dv/dstr
200
mV/ns
Power supply rejection ratio (PSRR) 0–100 MHz
30
dB
Power supply rejection ratio (PSRR) 100–1000
MHz
10
dB
Control Interface
The electrical characteristics of the control interface (RESET_BAR, TEST, GPI0, GPI1,
GPI2, and GPI3) are shown in Table 25.
Table 25:
Electrical Characteristics
Definition
Condition
Symbol
Min
Input HIGH voltage
VIH
0.7 X VDD
2.9
V
Input LOW voltage
VIL
-0.3
0.3 X VDD
V
10
A
Input leakage current
No pull-up resistor;
VIN = VDD or DGND
Input pad capacitance
Typ
Max
IIN
CIN
Unit
6.5
pF
Power-On Reset
Table 26:
Power-On Reset Characteristics
Definition
Symbol
Min
Typ
Max
Unit
VDD rising, crossing VTRIG_RISING;
Internal reset being released
t1
7
10
15
s
VDD falling, crossing VTRIG_FALLING;
Internal reset active
t2
0.5
1
s
Minimum VDD spike width below
VTRIG_FALLING; considered to be a reset
when POR cell output is HIGH
t3
0.5
s
Minimum VDD spike width below
VTRIG_FALLING; considered to be a reset
when POR cell output is LOW
t4
1
s
t5
50
ns
Minimum VDD spike width above
VTRIG_RISING; considered to be a stable
supply when POR cell output is LOW
Condition
While the POR cell output is LOW,
all VDD spikes above VTRIG_RISING
less than t5 must be ignored
VDD rising trigger voltage
VTRIG_RISING
1.15
1.55
V
VDD falling trigger voltage
VTRIG_FALLING
1
1.45
V
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Figure 31:
Internal Power-On Reset
Burst<t4
t0
90%
Burst >t3 Burst<t5
Burst>t5
VTRIG_RISING
VDD
VTRIG_FALLING
10%
t2
t1
t1
POR Cell Output
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Electrical Specifications
Operating Voltages
VAA and VAA_PIX must be at the same potential for correct operation of the MT9D015.
Table 27:
DC Electrical Definitions and Characteristics
Setup Conditions: TJ = 25°C; Dark lighting conditions
Definition
Core digital voltage
Analog voltage
Pixel supply voltage
PLL supply voltage
Digital operating current
Analog operating current
Digital operating current
Analog operating current
Digital operating current
Analog operating current
Digital operating current
Analog operating current
Digital operating current
Analog operating current
Hard standby
Soft standby (clock off)
Soft standby (clock on 6 MHz)
Soft standby (clock on 27 MHz)
MT9D015_DS Rev. M Pub. 4/15 EN
Condition
1600x1200 at 30 fps
1600x1200 at 15fps
1280x720 at30 fps
Full field of view
640x480 at 30 fps
320x240 at 120 fps
Symbol
Min
Typ
Max
Unit
VDD
VAA
VAA_PIX
VDD_PLL
IDIG
IANA
IDIG
IANA
IDIG
IANA
IDIG
IANA
IDIG
IANA
1.7
2.4
2.4
2.4
10
25
1.8
2.8
2.8
2.8
50
65
25
52
48
65
24
40
30
49
1.9
2.9
2.9
2.9
71
80
30
58
55
73
30
45
35
55
10
15
275
300
275
500
275
3
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
uA
uA
uA
uA
uA
mA
Analog
Digital
Analog
Digital
Analog
Digital
Analog
Digital
20
30
20
50
20
1
71
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Chief Ray Angle
Absolute Maximum Ratings
Caution
Table 28:
Stresses greater than those listed in Table 28 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Values
Definition
Condition
Core digital voltage
Analog voltage
Symbol
Min
Max
Unit
VDD_MAX
-0.3
2.2
V
VAA_MAX
-0.3
3.2
V
Pixel supply voltage
VAA_PIX_MAX
-0.3
3.2
V
PLL supply voltage
VDD_PLL_MAX
-0.3
3.2
V
Input HIGH voltage
VIH_MAX
0.7 X VDD
VAA + 0.3
V
VIH_MAX
-0.3
0.3 X VDD
V
TOP
-30
70
°C
TSTG
-40
125
°C
Input LOW voltage
Operating temperature
Measure at junction
Storage temperature
Note:
This is a stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Chief Ray Angle
Figure 32:
Chief Ray Angle
Image Height
CRA vs. Image Height Plot
30
28
26
24
22
20
CRA (deg)
18
16
14
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
Image Height (%)
MT9D015_DS Rev. M Pub. 4/15 EN
72
80
90
100
110
(%)
(mm)
CRA
(°)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0
0.088
0.175
0.263
0.350
0.438
0.525
0.613
0.700
0.788
0.875
0.963
1.050
1.138
1.225
1.313
1.400
1.488
1.575
1.663
1.750
0
2.14
4.21
6.25
8.27
10.27
12.24
14.16
16.00
17.74
19.36
20.83
22.12
23.23
24.13
24.81
25.26
25.47
25.42
25.07
24.40
©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
SMIA and MIPI Specification Reference
SMIA and MIPI Specification Reference
The sensor design and this documentation is based on the following reference documents:
• SMIA Specifications:
– Functional Specification:
SMIA 1.0 Part 1: Functional Specification (Version 1.0 dated 30 June 2004)
SMIA 1.0 Part 1: Functional Specification ECR0001 (Version 1.0 dated 11 Feb 2005)
– Electrical Specification:
SMIA 1.0 Part 2: CCP2 Specification (Version 1.0 dated 30 June 2004)
SMIA 1.0 Part 2: CCP2 Specification ECR0001 (Version 1.0 dated 11 Feb 2005)
• MIPI Specifications:
– MIPI Alliance Standard for CSI-2 version 1.0
– MIPI Alliance Standard for D-PHY version 1.0
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Revision History
Revision History
Rev. M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15
• Updated “Ordering Information” on page 2
Rev. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/26/15
• Updated to ON Semiconductor template
• Removed Confidential marking
Rev. K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/10/12
• Updated Figure 27: “Power-Up Sequence,” on page 62
• Updated Table 18, “Power-Up Sequence,” on page 63
Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/24/12
• Updated Table 27, “DC Electrical Definitions and Characteristics,” on page 71
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/26/11
• Updated “Minimum Gain and Gain Table” on page 52
• Updated Table 16, “Gain Table,” on page 52
• Updated Table 20, “Electrical Characteristics (EXTCLK),” on page 66
• Updated “Two-Wire Serial Register Interface” on page 66
• Updated Table 26, “Power-On Reset Characteristics,” on page 69
Rev.G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/15/11
• Updated “Features” on page 1
• Updated Table 1, “Key Performance Parameters,” on page 1
• Updated Note 7 and added Note 8 in Figure 3: “Typical Configuration (Connection) –
Serial Output Mode,” on page 8 and in Figure 4: “Typical Configuration (Connection)
– MIPI Mode,” on page 9
• Updated Table 6, “Embedded Data,” on page 19
• Updated Table 11, “Streaming/STANDBY,” on page 36
• Updated “Profile 0 Behavior” on page 37
• Added “One-Time Programmable Memory (OTPM)” on page 41
• Added “Full Resolution Frame Structure With Embedded Data” on page 43
• Added Note to “Frame Rate Control” on page 48
• Added “Minimum Row Time” on page 48
• Added “Minimum Frame Time” on page 48
• Added “Fine Integration Time Limits” on page 49
• Added “Minimum Gain and Gain Table” on page 52
• Updated Table 23, “Electrical Characteristics (Serial CCP2 Pixel Data Interface),” on
page 68
• Updated Table 24, “Electrical Characteristics (Serial MIPI Pixel Data Interface),” on
page 68
• Updated Figure 31: “Internal Power-On Reset,” on page 70
• Updated Table 27, “DC Electrical Definitions and Characteristics,” on page 71
• Updated “SMIA and MIPI Specification Reference” on page 73
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/14/11
• Added information for MIPI functionality
• Added “Chief Ray Angle” on page 72
MT9D015_DS Rev. M Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9D015: 1/5-Inch 2 Mp CMOS Digital Image Sensor
Revision History
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/9/10
• Added maximum values for digital operating current and analog operating current in
Table 22, “DC Electrical Definitions and Characteristics,” on page 62
• Updated Figure 28: “Power-Down Sequence,” on page 64
Rev. D, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/18/10
• Updated to Production
• Applied updated Aptina template
• Updated Table 1, “Key Performance Parameters,” on page 1
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/8/10
• Updated Table 20, “Electrical Characteristics (EXTCLK),” on page 66
• Updated Table 21, “Two-Wire Serial Register Interface Electrical Characteristics,” on
page 65
• Updated Table 23, “Electrical Characteristics (Serial CCP2 Pixel Data Interface),” on
page 68
• Updated Table 25, “Electrical Characteristics,” on page 69
• Updated Table 26, “Power-On Reset Characteristics,” on page 69
• Updated Table 22, “DC Electrical Definitions and Characteristics,” on page 62
• Updated Table 28, “Absolute Maximum Values,” on page 72
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/13/10
• Updated “Effect of CCP2 Class on Legal Range of Output Sizes/Frame Rate” on
page 30
• Updated Figure 13: “MT9D015 System States,” on page 34
• Updated Table 9, “PLL in System States,” on page 35
• Updated “Power-On Reset Sequence” on page 35
• Updated “General Purpose Inputs” on page 36
• Updated Figure 14: “MT9D015 SMIA Profile 1/2 Clocking Structure,” on page 38
• Updated Figure 15: “MT9D015 SMIA Profile 0 Clocking Structure,” on page 39
• Updated Equation 12 on page 49
• Updated “Power-Up Sequence” on page 62
• Updated Table 18, “Power-Up Sequence,” on page 63
• Updated Figure 29: “Soft Standby and Soft Reset,” on page 65
• Deleted note from Table 16, “Electrical Characteristics (EXTCLK),” on page 59
Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/10/10
• Initial release
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