AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Features 1/3.2-Inch 8 Mp CMOS Digital Image Sensor AR0835HS Datasheet, Rev. D For the latest datasheet, please visit www.onsemi.com Features Table 1: • High speed sensor supporting 8 Mp (4:3) and 6 Mp (16:9) up to 60 fps • 1.4 pixel with ON Semiconductor A-PixHS™ technology providing best-in-class low-light performance • Optional on-chip high-quality Bayer scaler to resize image to desired size • Data Output Serial Interface: Four-lane High-Speed Serial Pixel Interface (HiSPi) or mobile industry processor interface (MIPI) • Bit-depth compression available for serial interface: 10-to-8 and 10-6 bit compression to enable lower bandwidth receivers for full frame rate applications • On-chip temperature sensor • On-die phase-locked loop (PLL) oscillator • 5.6 kbits one-time programmable memory (OTPM) for storing module information and calibration data • On-chip 8-bit VCM driver • 3D synchronization controls to enable stereo video capture • Interlaced multi-exposure readout enabling High Dynamic Range (HDR) still and video applications • Programmable controls: gain, horizontal and vertical blanking, auto black level offset correction, frame size/rate, exposure, left–right and top–bottom image reversal, window size, and panning • Support for external mechanical shutter • Support for external LED or Xenon flash Parameter Typical Value Array Format 8 Mp: 3264 x 2448, 6 Mp: 3264 x 1836 Primary modes 4:3 - 8 Mp 46 fps max (HiSPi) and 42 fps max (MIPI) 16:9 - 6 Mp at 60 fps max 1080p 60 fps / 720p 120 fps max 1.4 m Back Side Illuminated (BSI) Pixel size Optical format 1/3.2" Die size 6.86 mm x 6.44 mm (Area: 44.17 mm2) Input Clock Frequency 6 - 27 MHz Interface HiSPi Mode: 4 lanes at 1 Gbps max. MIPI Mode: CSI-2 (2,3,4 lanes) at 896 Mbps max. Subsampling modes X - Bin2, Sum2 Skip: 2x, 4x Output data depth 10-bit Raw, 10-to-8 bit A-Law, 8/6-bit DPCM Analog gain 1x, 2x, 3x, 4x, 6x, 8x High Quality Bayer Scalar Adjustable scaling up to 1/6x scaling Temperature sensor 10-bit, single instance on chip, controlled by two-wire serial I/F VCM AF driver 8-bit resolution with slew rate control 3-D support Analog Applications Frame rate and exposure synchronization 2.5 - 3.1 V (2.8 V nominal) 1.14 - 1.3 V (1.2 V nominal) Pixel 2.5 - 3.1 V (2.8 V nominal) HiSPi/ MIPI 1 Y - Sum2, Skip: 2x, 4x, 8x Digital Supply Voltage I/O • Sports cameras • Digital still cameras • Digital video cameras AR0835HS_DS Rev. D Pub. 5/15 EN Key Performance Parameters 1.7 - 1.9 V (1.8 V nominal) or 2.5 - 3.1 V (2.8 V nominal) 1.14 - 1.3 V (1.2 V nominal) OTPM Program Voltage 6.5V Power consumption Typical 420 mW at 25C for 8M/46 fps and 6M/60 fps Responsivity 0.6 V/lux-sec ©Semiconductor Components Industries, LLC 2015, AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Ordering Information Table 1: Table 2: Key Performance Parameters (continued) Parameter Typical Value SNRMAX 36 dB Dynamic Range 64 dB Operating Temperature Range (at junction) -TJ -30°C to +70°C Modes of Operation and Power Consumption Active Readout Sensor Output Window (col x row) Resolution (col x row) Mode Mode FPS Typical Power Consumption [mW]2 Full mode Full mode 46/42 30 420 370 Full mode Full mode 60 30 420 370 Skip4 Skip4 180 240 370 370 Scaling Scaling Bin2-Sum2 Scaling Bin2 + Scaling 30 60 120 60 60 360 420 390 420 250 Full Resolution 4:3 8Mp 8Mp 3264 x 2448 3264 x 2448 3264x2448 3264x2448 Full Resolution 16:9 6Mp 6Mp 3264x1836 3264x1836 3264x1836 3264x1836 4:3 Video Mode VGA QVGA 3264 x 2448 3264 x 2448 640 x 480 320x240 16:9 Video Mode 1080p 1080p 720p 720p 720p Notes: 3264 x 1836 3264x1836 3264 x 1836 3264 x 1836 3264 x 1836 1920 x 1080 1920x1080 1280 x 720 1280 x 720 1280 x 720 1. 1 Gbps/Lane HiSPi and 896 Mbps/Lane MIPI data transfer rate 2. Values measured at T=25°C and nominal voltages. Ordering Information Table 3: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0835HS3C12SUAA0-DP 8 MP 1/3" CIS Dry Pack with Protective Film AR0835HS3C12SUAA0-DR 8 MP 1/3" CIS Dry Pack without Protective Film AR0835HS_DS Rev. D Pub. 5/15 EN 2 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Sensor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Power-on Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Integration Time for Interlaced HDR Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Internal VCM Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 HiSPi Specification Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 MIPI Specification Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 AR0835HS_DS Rev. D Pub. 5/15 EN 3 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Application Circuit—HiSPi Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Recommended Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Recommended Power-down Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Hard Standby and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Soft Standby and Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Clocking Configuration (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 HDR Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Bayer Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Results of Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Illustration of Resampling Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Effect of horizontal_mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Effect of vertical_flip on Readout Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Effect of x_odd_inc = 3 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Effect of x_odd_inc = 7 on Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Pixel Readout (No Subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Skip2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Skip4 Pixel Readout (x_odd_inc = 7, y_odd_inc = 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Bin2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Bin2Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, x_bin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Pixel Binning and Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 LED Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Overview of Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Entering and Leaving a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Controlling the Reset and Integration Phases of the Global Reset Sequence . . . . . . . . . . . . . . . . . . . .47 Control of the Electromechanical Shutter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Controlling the SHUTTER Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Using FLASH with Global Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Extending FLASH Duration in Global Reset (Reference Readout Start) . . . . . . . . . . . . . . . . . . . . . . . . .50 Global Reset Bulb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Entering Soft Standby During a Global Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Slave Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 VCM Driver Typical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Chief Ray Angle (CRA) vs. Image Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Fall Slew Rates (Cap Load = 25pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Rise Slew Rates (Cap Load = 25pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 HiSPi Transmitter and Receiver Interface Block Diagram (HiSPi Mode Only) . . . . . . . . . . . . . . . . . . .61 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Delaying the clock_lane with Respect to data_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Delaying data_lane with Respect to the clock_lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 CLCC Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 CLCC package Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 AR0835HS_DS Rev. D Pub. 5/15 EN 4 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Modes of Operation and Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pad Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Independent Power and Ground Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Inrush consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Power-down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Address Space Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Row Address Sequencing During Subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Column Address Sequencing During Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Row Address Sequencing During Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Available Skip, Bin, and Sum Modes in the AR0835HS Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Minimum Frame Time and Blanking Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Recommended Analog Gain Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 VCM Driver Typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Two-Wire Serial Register Interface Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Two-Wire Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Electrical Characteristics (EXTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 SLVS Electrical Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 SLVS Electrical DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 DC Electrical Characteristics (Control Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 DC Electrical Definitions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Typical Operating Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Absolute Max Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 AR0835HS_DS Rev. D Pub. 5/15 EN 5 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor General Description General Description The ON Semiconductor AR0835HS is a 1/3.2-inch BSI (back side illuminated) CMOS active-pixel digital image sensor with a pixel array of 3264H x 2448V (3280H x 2464V including border pixels). It incorporates sophisticated on-chip camera functions such as mirroring, column and row skip modes, and context switching for zero shutter lag snapshot mode. It is programmable through a simple two-wire serial interface and has very low power consumption. The AR0835HS digital image sensor features ON Semiconductor's breakthrough lownoise 1.4m pixel CMOS imaging technology that achieves near-CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. Functional Overview In order to meet higher frame rates in AR0835HS sensor, the architecture has been redesigned. The analog core has a column parallel architecture with 4 data paths. Digital block has been re-architected to have 4 data paths. Figure 1 shows the block diagram of the AR0835HS. Top Level Block Diagram 10-bit Temperature Sensor HiSPi FIFO & Optional Compression ADC Image Output Scaler Gain Data Calibration Row Driver VDD_IO, DVDD_1V8, DVDD_1V2 Pixel Array Digital Gain Digital Processing Imaging Sensor Core VAA, VAA_PIX HiSPi/MIPI Serial Data Output [3:0] Test Pattern Generator Figure 1: Gain Control DVDD_1V2_PHY AR0835HS PLL Timing Control External XSHUTDOWN GPIO[1:0] GPI[3:2] Clock VCM VCM Control Register Control Two-Wire Wire Serial Interface SCLK SDATA The core of the sensor is an 8Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing gain), and then through an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). AR0835HS_DS Rev. D Pub. 5/15 EN 6 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Functional Overview The pixel array contains optically active and light-shielded (“dark”) pixels. The dark pixels are used to provide data for on-chip offset-correction algorithms (“black level” control). The sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. These registers can be accessed through a two-wire serial interface. The output from the sensor is a Bayer pattern; alternate rows are a sequence of either green and red pixels or blue and green pixels. The offset and gain stages of the analog signal chain provide per-color control of the pixel data. A flash output signal is provided to allow an external xenon or LED light source to synchronize with the sensor exposure time. Additional I/O signals support the provision of an external mechanical shutter. Pixel Array The sensor core uses a Bayer color pattern, as shown in Figure 2. The even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. Even-numbered columns contain red and green pixels; odd-numbered columns contain blue and green pixels. Figure 2: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction .. . Black Pixels First Pixel (Col. 0, Row 60) Row Readout Direction G2 B G2 B G2 G2 ... R Gr R Gr R R Gb B Gb B Gb G2 R Gr R Gr R R Gb B Gb B Gb G2 Note: AR0835HS_DS Rev. D Pub. 5/15 EN By default the mirror bit is set, so the read-out direction is from right to left. 7 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Typical Connections Typical Connections The chip supports HiSPi/MIPI output protocol. HiSPi and MIPI are configured to work in 4-lane mode. There are no parallel data output ports. Figure 3: Typical Application Circuit—HiSPi Connection 2.8V 2.8V or 1.8V 1.8V 1.2V/0.4V 1.2V 1.2V 6 VDD1V8 VDD_IO (OTPM Read) (I/O) 21.5K 2,31.5K Two-Wire Serial Interface 7 VDD1V2 (Digital) VDDSLVS_PHY 4VAA (HISPI ONLY) (Analog) 4 VAA_PIX 7 VDD_PHY DATA_P DATA_N SCLK SDATA DATA2_P EXTCLK General Purpose Input/Output (6 – 27MHz) DATA2_N GPIO [1:0] DATA3_P DATA3_N GPI [3:2] To HiSPi/MIPI Host Interface DATA4_P DATA4_N XSHUTDOWN CLK_P 8 ATEST CLK_N 8 TEST DGND GND_IO GNDPHY VCM_GND VCM_ISINK 5 VPP AGND (OTPM Write) (only connected while programming OTPM) VCM 0.1 µF VAA, VAA_PIX 2.8V 1µF VDD 1.2V 0.1µF 10 µF 1.0µF VDD_IO VDD_1V8 1µF 10µF 0.1µF 0.1µF For connectivity above: 1. All power supplies should be adequately decoupled; recommended cap values are: • 2.8V: 1.0F, 0.1F, and then 0.01F • 1.2V: 10F, 1F, and then 0.1F • 1.8V: 1F and 0.1F 2. Resistor value 1.5k is recommended, but may be greater for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. VAA and VAA_PIX can be tied together. However, for noise immunity it is recommended to have them separate (i.e. two sets of 2.8V decoupling caps). 5. VPP, 6.5V, is used for programming OTPM. This pad is left unconnected if OTPM is not being programmed. 6. VDD_1V8 can be combined with VDD_IO, if VDD_IO = 1.8V. AR0835HS_DS Rev. D Pub. 5/15 EN 8 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Signal Descriptions 7. VDD_1V2 and VDD_PHY can be tied together. 8. HiSPi mode only: VDDSLVS_PHY is set to 0.4V externally. Alternatively, VDDSLVS_PHY may be tied to 1.2V if the user chooses to have the HiSPi SLVS PHY TX voltage supplied using the AR0835HS's internal 1.2V-to-0.4V regulator. 9. Register 31BE[2:3] can be used to program the option of internal of external regulator, ON Semiconductor recommends using external regulator 10. ATEST can be left floating. 11. TEST pin must be tied to DGND. 12. VDD_1V8 is the OTPM read voltage. Signal Descriptions AR0835HS has 66 pads placed in a two-sided pad frame. It has only serial outputs. The part may be configured as HiSPi with different bit depths. The pad description is tabulated in Table 4: Table 4: Pad Descriptions Pad Name Pad Type Description Sensor Control EXTCLK Input Master clock input; PLL input clock. 6 MHz - 27 MHz. This is a SMIA-compliant pad. GPIO0 Input/Output General Input and one Output function include: a. (Default Output) Flash b. (Input) all options in GPI2 High-Z before XSHUTDOWN going high; default value is ‘0’ after all three voltages in place and XSHUTDOWN being high. After reset, this pad is not powered down since its default use is as Flash pin. If not used, can be left floating. GPIO1 Input/Output General Input and 2 Output functions include: a. (Default Output) Shutter b. (Output) 3-D daisy chain communication output c. (Input) all options in GPI2 High-Z before XSHUTDOWN going high; default value is ‘0’ after all three voltages in place and XSHUTDOWN being high. After reset, this pad is not powered-down since its default use is as Shutter pin. If not used, can be left floating. GPI2 Input General Input; After reset, these pads are powered down by default; this means that it is not necessary to bond to these pads. Functions include: a. SADDR, switch to the second two-wire serial interface device address (see “Slave Address/Data Direction Byte” on page 17) b. Trigger signal for Slave Mode c. Standby If not used, can be left floating. GPI3 Input General Input; After reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. Functions include: a. 3-D daisy chain communication input b. All options in GPI2 If not used, can be left floating. Input Serial clock for access to control and status registers. Two-wire Serial Interface SCLK AR0835HS_DS Rev. D Pub. 5/15 EN 9 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Signal Descriptions Table 4: Pad Descriptions (continued) Pad Name Pad Type SDATA I/O Description Serial data for reads from and writes to control and status registers. Serial Output DATA[4:1]P Output Differential serial data (positive). DATA[4:1]N Output Differential serial data (negative). CLK_P Output Differential serial clock/strobe (positive). CLK_N Output Differential serial clock/strobe (negative). XSHUTDOWN Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are restored to their factory default settings. This pin will turn off the digital power domain and is the lowest power state of the sensor. VCM driver VCM_ISINK Input/Output VCM Driver current sink output. If not used, it could be left floating. VCM_GND Input/Output Ground connection to VCM Driver. If not used, needs to be connected to ground (DGND). This ground must be separate from the other grounds. VPP Supply High-voltage pin for programming OTPM, present on sensors with that capability. This pin can be left floating during normal operation. VAA, VAA_PIX, VDD_1V2_[VDDSW, VDD_ANA, VDD_PLL], VDD_1V8, VDD_IO, VDD_PHY, VDDSLVS_PHY, AGND, PIXGND, DGND Supply Power Power supply. The domains are specified in the next table. The brackets indicate the number of individual pins. VDDSLVS_PHY is for HiSPi mode only. There are standard GPI and GPIO pads, 2 each. Chip can also be communicated to through the two-wire serial interface. The chip has four unique power supply requirements: 1.2 V (digital), 1.8 V, 2.8 V, and an analog 1.2 V or 0.4 V. These are further divided and in all there are seven power domains and five independent ground domains from the ESD perspective. Table 5: Independent Power and Ground Domains Pad Name Power Supply Description Grounds DGND 0V VCM_GND 0V AGND, PIXGND 0V Analog VAA 2.8V Analog VAA_PIX 2.8V Pixel Digital Power VDDSLVS_PHY 0.4V or 1.2V VDDSW, VDD_ANA, VDD_PLL 1.2V AR0835HS_DS Rev. D Pub. 5/15 EN HiSPi PHY. (HiSPi mode only) Digital VDD_IO 1.8v/2.8V VDD_PHY 1.2V HiSPi/MIPI VDD_1V8 1.8V OTPM 10 IO ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor System States System States The system states of the AR0835HS are represented as a state diagram in Figure 4 and described in subsequent sections. The sensor's operation is broken down into three separate states: hardware standby, software standby, and streaming. The transition between these states might take a certain amount of clock cycles as outlined in Figure 4 page 13 and Figure 5 page 14. Figure 4: System States Power supplies turned off (asychronous from any state) Powered Off Power On XSHUTDOWN = 0 Hardware Standby EXTCLK Cycles XSHUTDOWN = 1 Internal Initialization Two-wire Serial Interface Write: software_reset = 1 Timeout Software Standby Two-wire Serial Interface Write: mode_select = 1 PLL not locked PLL Lock Frame in progress PLL locked Streaming Wait for Frame End Streaming Two-wire Serial Interface Write: mode_select = 0 AR0835HS_DS Rev. D Pub. 5/15 EN 11 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Sensor Initialization Sensor Initialization Power-on Sequence AR0835HS has four voltage supplies divided into several domains. The four voltages are 1.2 V (digital), 1.8 V, 2.8 V, and analog 1.2 V or 0.4 V. For proper operation of the chip, a power-up sequence is recommended as shown in Figure 5. The power sequence is governed by controlled vs controlling behavior of a power supply and the inrush current (i.e. current that exists when not all power supplies are present). Table 6: Inrush consideration XSHUTDOWN 1.2V 1.8V (VDDIO) 2.8V x Present Absent Absent Not supported x Absent Present Absent Supported x Absent Absent Present Supported x Present Present Absent Supported x Present Absent Present Not supported x Absent Present Present Supported 0 Present Present Present Powered down state 1 Present Present Present Powered up state Comment Since VDD_IO supply controls the XSHUTDOWN, it should be turned on first. The sequence of powering up the other two domains is not too critical. While turning on 2.8 V supply before 1.2 V supply shouldn't be an issue as shown in Table 1, it is still not recommended since the 2.8 V domain is controlled by 1.2 V signals. The dedicated 1.8 V domain is used only for OTPM read function, so can turn on along with 1.8 V supply. Due to the above considerations, the suggested power-on sequence is as shown in Figure 5 on page 13: AR0835HS_DS Rev. D Pub. 5/15 EN 12 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Power-on Sequence Figure 5: Recommended Power-up Sequence VDD_IO, VDD_SLVS t1 VDD_1V8 t2 VDD_1V2, VDD_1V2_PHY t3 VAA, VAA_PIX EXTCLK t4 XSHUTDOWN t5 Hard Reset Internal Init t6 Soft Standby PLL Lock Streaming S DATA S CLK First Serial Write Table 7: Power-up Sequence Definition Symbol Minimum Typical Maximum Unit VDD_IO to VDD_1V8 VDD_1V8 to VDD_1V2 VDD_1V2 to VAA Active Hard Reset Internal Initialization PLL Lock Time t1 t2 t3 t4 t5 t6 – 0.2 0.2 1 2400 1 – – – – – – 500 500 500 500 – 5 ms ms ms ms EXTCLKs ms AR0835HS_DS Rev. D Pub. 5/15 EN 13 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Power Down Sequence Power Down Sequence The recommended power-down sequence for the AR0835HS is shown in Figure 6. The three power supply domains (1.2 V, 1.8 V, and 2.8 V) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0. 2. After disabling the internal clock EXTCLK, disable XSHUTDOWN. 3. After XSHUTDOWN is LOW disable the 2.8 V/1.8 V supply. 4. After the 2.8 V/1.8 V supply is LOW disable the 1.2 V supply. 5. After the 1.2 V supply is LOW disable the VDD_IO supply. Figure 6: Recommended Power-down Sequence VAA, VAA_PIX t1 VDD_1V2, VDD_1V2_PHY t2 t3 VDD_1V8 VDD_IO, VDD_SLVS EXTCLK t0 XSHUTDOWN Streaming Focal Planes Deactivation Soft Standby Hard Reset Turn Off Power Supplies S DATA S CLK Table 8: Power-down Sequence Definition Symbol Minimum Typical Maximum Unit EXTCLK inactive to XSHUTDOWN active XSHUTDOWN to VAA VAA to VDD_1V2 VDD_1V2 to VDD_1V8 VDD_1V8 to VDD_IO t0 t1 t2 t3 100 200 0 0 0 – – – – – – – – – – s s s s s AR0835HS_DS Rev. D Pub. 5/15 EN 14 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Power Down Sequence Hard Standby and Hard Reset The hard standby state is reached by the assertion of the XSHUTDOWN pad (hard reset). Register values are not retained by this action, and will be returned to their default values once hard reset is completed. The minimum power consumption is achieved by the hard standby state. The details of the sequence are described below and shown in Figure 7. 1. Disable streaming if output is active by setting mode_select 0x301A[2] = 0. 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Assert XSHUTDOWN (active LOW) to reset the sensor. 4. The sensor remains in hard standby state if XSHUTDOWN remains in the logic “0” state. Figure 7: Hard Standby and Hard Reset EXTCLK mode_select R0x0100 next row/frame Logic “1” Logic “0” XSHUTDOWN Streaming Soft Standby Hard Standby Hard Reset Soft Standby and Soft Reset The AR0835HS can reduce power consumption by switching to the soft standby state when the output is not needed. Register values are retained in the soft standby state. The details of the sequence are described below and shown in Figure 8 on page 16. Soft Standby 1. Disable streaming if output is active by setting mode_select 0x301A[2] = 0. 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. Soft Reset 1. Follow the soft standby sequence list above. 2. Set software_reset = 1 (R0x3021) to start the internal initialization sequence. 3. After 2400 EXTCLKs , the internal initialization sequence is completed and the current state returns to soft standby automatically. AR0835HS_DS Rev. D Pub. 5/15 EN 15 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Power Down Sequence Figure 8: Soft Standby and Soft Reset EXTCLK mode_select R0x0100 software_reset R0x0103 next row/frame Logic “1” Logic “0” Logic “0” Logic “1” 480 Streaming AR0835HS_DS Rev. D Pub. 5/15 EN Soft Standby 16 Logic “0” 2400 EXTCLKs Soft Reset Soft Standby ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface A two-wire serial interface bus enables read/write access to control and status registers within the AR0835HS. The two-wire serial interface is fully compatible with the I2C standard. The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW—the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the AR0835HS uses SCLK as an input only and therefore never drives it LOW. The electrical and timing specifications are further detailed on “Two-Wire Serial Register Interface” on page 17. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a “repeated start” or “restart” condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. Alternate slave addresses of 0x6E(write address) and 0x6F(read address) can be selected by enabling and asserting the SADDR signal through the GPI pad. AR0835HS_DS Rev. D Pub. 5/15 EN 17 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface The alternate slave addresses can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a “0” indicates a write and a “1” indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave’s internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. AR0835HS_DS Rev. D Pub. 5/15 EN 18 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 9 on page 19) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a noacknowledge bit followed by a stop condition. Figure 9 shows how the internal register address maintained by the AR0835HS is loaded and incremented as the sequence proceeds. Figure 9: Single READ from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P slave to master master toslave Single READ from Current Location This sequence (Figure 10) performs a read using the current value of the AR0835HS internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 10: Single READ from Current Location Previous Reg Address, N S Slave Address AR0835HS_DS Rev. D Pub. 5/15 EN 1 A Reg Address, N+1 Read Data A P S 19 Slave Address 1 A N+2 Read Data A P ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Random Location This sequence (Figure 11) starts in the same way as the single READ from random location (Figure 9). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 11: Sequential READ, Start from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 A M+2 Read Data A Reg Address, M Reg Address[7:0] Slave Address M+L-2 M+3 Read Data A Sr Read Data 1 A M+L-1 Read Data A M+1 M+L Read Data A A A P Sequential READ, Start from Current Location This sequence (Figure 12) starts in the same way as the single READ from current location (Figure 10 on page 19). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read. Figure 12: Sequential READ, Start from Current Location Previous RegAddress, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A N+L-1 Read Data A N+L Read Data A P Single WRITE to Random Location This sequence (Figure 13) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 13: Single WRITE to Random Location Previous Reg Address, N S Slave Address AR0835HS_DS Rev. D Pub. 5/15 EN 0 A Reg Address[15:8] A 20 Reg Address, M Reg Address[7:0] A Write Data M+1 A P A ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential WRITE, Start at Random Location This sequence (Figure 14) starts in the same way as the single WRITE to random location (Figure 13). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 14: Sequential WRITE, Start at Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Write Data AR0835HS_DS Rev. D Pub. 5/15 EN M+2 A Write Data A Reg Address, M Reg Address[7:0] A Write Data M+L-2 M+3 Write Data A 21 M+1 A M+L-1 A Write Data M+L A A P ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Registers Registers The AR0835HS provides a 16-bit register address space accessed through a serial interface (“Two-Wire Serial Register Interface” on page 17). Each register location is 8 or 16 bits in size. The address space is divided into the five major regions shown in Table 9. The remainder of this section describes these registers in detail. Table 9: Address Space Regions Address Range Description 0x0000–0x0FFF 0x1000–0x1FFF 0x2000–0x2FFF 0x3000–0x3FFF Configuration registers (read-only and read-write dynamic registers) Parameter limit registers (read-only static registers) Image statistics registers (none currently defined) Manufacturer-specific registers (read-only and read-write dynamic registers) Register Notation The underlying mechanism for reading and writing registers provides byte write capability. However, it is convenient to consider some registers as multiple adjacent bytes. The AR0835HS uses 8-bit, 16-bit, and 32-bit registers, all implemented as 1 or more bytes at naturally aligned, contiguous locations in the address space. In this document, registers are described either by address or by name. When registers are described by address, the size of the registers is explicit. For example, R0x3024 is a 2-bit register at address 0x3024, and R0x3000–1 is a 16-bit register at address 0x3000– 0x3001. When registers are described by name, the size of the register is implicit. It is necessary to refer to the register table to determine that model_id is a 16-bit register. Register Aliases A consequence of the internal architecture of the AR0835HS is that some registers are decoded at multiple addresses. Some registers in “configuration space” are also decoded in “manufacturer-specific space.” To provide unique names for all registers, the name of the register within manufacturer-specific register space has a trailing underscore. For example, R0x0202 is coarse_integration_time and R0x3012 is coarse_integration_time_. The effect of reading or writing a register through any of its aliases is identical. Bit Fields Some registers provide control of several different pieces of related functionality, and this makes it necessary to refer to bit fields within registers. As an example of the notation used for this, the least significant 4 bits of the chip_version_reg register are referred to as chip_version_reg[3:0] or R0x0000–1[3:0]. Bit Field Aliases In addition to the register aliases described above, some register fields are aliased in multiple places. For example, R0x0100 (mode_select) has only one operational bit, R0x0100[0]. This bit is aliased to R0x301A–B[2]. The effect of reading or writing a bit field through any of its aliases is identical. AR0835HS_DS Rev. D Pub. 5/15 EN 22 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Registers Byte Ordering Registers that occupy more than one byte of address space are shown with the lowest address in the highest-order byte lane to match the byte-ordering on the data bus. For example, the chip_version_reg register is R0x0000–1. In the register table the default value is shown as 0x4B00. This means that a read from address 0x0000 would return 0x4B, and a read from address 0x0001 would return 0x00. When reading this register as two 8-bit transfers on the serial interface, the 0x4B will appear on the serial interface first, followed by the 0x00. Address Alignment All register addresses are aligned naturally. Registers that occupy 2 bytes of address space are aligned to even 16-bit addresses, and registers that occupy 4 bytes of address space are aligned to 16-bit addresses that are an integer multiple of 4. Bit Representation For clarity, 32-bit hex numbers are shown with an underscore between the upper and lower 16 bits. For example: 0x3000_01AB. Data Format Most registers represent an unsigned binary value or set of bit fields. For all other register formats, the format is stated explicitly at the start of the register description. The notation for these formats is shown in Table 10. Table 10: Data Formats Name Description FIX16 Signed fixed-point, 16-bit number: two’s complement number, 8 fractional bits. Examples: 0x0100 = 1.0, 0x8000 = –128, 0xFFFF = –0.0039065 Unsigned fixed-point, 16-bit number: 8.8 format. Examples: 0x0100 = 1.0, 0x280 = 2.5 Signed floating-point, 32-bit number: IEEE 754 format. Example: 0x4280_0000 = 64.0 UFIX16 FLP32 Register Behavior Registers vary from “read-only,” “read/write,” and “read, write-1-to-clear.” Double-Buffered Registers Some sensor settings cannot be changed during frame readout. For example, changing R0x3004–5 (x_addr_start) partway through frame readout would result in inconsistent row lengths within a frame. To avoid this, the AR0835HS double-buffers many registers by implementing a “pending” and a “live” version. Reads and writes access the pending register. The live register controls the sensor operation. The value in the pending register is transferred to a live register at a fixed point in the frame timing, called frame start. Frame start is defined as the point at which the first dark row is read out internally to the sensor. In the register tables the “Frame Sync’d” column shows which registers or register fields are double-buffered in this way. AR0835HS_DS Rev. D Pub. 5/15 EN 23 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Registers Using grouped_parameter_hold Register grouped_parameter_hold (R0x301A[15]) can be used to inhibit transfers from the pending to the live registers. When the AR0835HS is in streaming mode, this register should be written to “1” before making changes to any group of registers where a set of changes is required to take effect simultaneously. When this register is written to “0,” all transfers from pending to live registers take place on the next frame start. An example of the consequences of failing to set this bit follows: An external auto exposure algorithm might want to change both gain and integration time between two frames. If the next frame starts between these operations, it will have the new gain, but not the new integration time, which would return a frame with the wrong brightness that might lead to a feedback loop with the AE algorithm resulting in flickering. Bad Frames A bad frame is a frame where all rows do not have the same integration time or where offsets to the pixel values have changed during the frame. Many changes to the sensor register settings can cause a bad frame. For example, when line_length_pck (R0x300C) is changed, the new register value does not affect sensor behavior until the next frame start. However, the frame that would be read out at that frame start will have been integrated using the old row width, so reading it out using the new row width would result in a frame with an incorrect integration time. By default, bad frames are masked. If the masked bad frame option is enabled, both LV and FV are inhibited for these frames so that the vertical blanking time between frames is extended by the frame time. In the register tables, the “Bad Frame” column shows where changing a register or register field will cause a bad frame. This notation is used: N—No. Changing the register value will not produce a bad frame. Y—Yes. Changing the register value might produce a bad frame. YM—Yes; but the bad frame will be masked out when mask_corrupted_frames (R0x301A[9]) is set to “1.” Changes to Integration Time If the integration time is changed while FV is asserted for frame n, the first frame output using the new integration time is frame (n + 2). The sequence is as follows: 1. During frame n, the new integration time is held in the pending register. 2. At the start of frame (n + 1), the new integration time is transferred to the live register. Integration for each row of frame (n + 1) has been completed using the old integration time. 3. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent upon the new value of the integration time. 4. When frame (n + 2) is read out, it will have been integrated using the new integration time. If the integration time is changed on successive frames, each value written will be applied for a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. AR0835HS_DS Rev. D Pub. 5/15 EN 24 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Clocking Changes to Gain Settings Usually, when the gain settings are changed, the gain is updated on the next frame start. When the integration time and the gain are changed at the same time, the gain update is held off by one frame so that the first frame output with the new integration time also has the new gain applied. In this case, a new gain should not be set during the extra frame delay. There is an option to turn off the extra frame delay by setting extra_delay (R0x3018). Clocking Default setup gives a physical 73.2 MHz internal clock for an external input clock of 24 MHz. The sensor contains a phase-locked loop (PLL) for timing generation and control. The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and a set of dividers to generate the output clocks. The PLL structure is shown in Figure 15 on page 26. AR0835HS_DS Rev. D Pub. 5/15 EN 25 ©Semiconductor Components Industries, LLC, 2015. AR0835HS_DS Rev. D Pub. 5/15 EN Figure 15: Clocking Configuration (PLL) row_speed (R0x3016[2:0]) (1,2,4) vt_pix_clk_div (R0x300) (4 to 16, 3 with 3064[13]=0) clk _ pixel clk_pixel vt_sys_clk_div (R0x302) Divider (1, 2, 4, 6, 8, 10, 12, 14, 16) vt pix vt_ pix _clk clk PLL input clock pll _ ip _ clk _ freq (4-24 MHz) PLL internal VCO frequency vt sys clk Divider (max freq (450 Mhz)) Divider vt_ sys _clk External input clock EXTCLK (6 to 27 MHz) Pre PLL Divider (n +1) PLL Multiplier (m) pll _multiplier(R0x306) pre_pll_clk_div (R0x304) (even number of 32-255 (1 to 64) max vco freq is 1000MHz) (1 must only be used with even pll_multiplier values) op sys clk op _ sys_clk Divider op pix op _ pix _clk clk clk _op Divider clk_op op_pix_clk_div (R0x308) (8, 10) row_speed(R0x3016[10:8]) (1, 2, 4) Figure 15 shows the different clocks and the names of the registers that contain or are used to control their values. The vt_pix_clk is divided by two to compensate for the fact that the design has 2 digital data paths. This divider should always remain turned on. AR0835HS has 10-to-8 compression. ©Semiconductor Components Industries, LLC, 2015 The usage of the output clocks is shown below: • clk_pixel (vt_pix_clk / row_speed[2:0]) is used by the sensor core to readout and control the timing of the pixel array. The sensor core produces one 10-bit pixel each vt_pix_clk period. The line length (line_length_pck) is controlled in increments of the clk_pixel period. • clk_op (op_pix_clk / row_speed[10:8]) is used to load parallel pixel data from the output FIFO (see Figure 40 on page 52) to the serializer. The output FIFO generates one pixel each op_pix_clk period. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor 26 op_sys_clk_div (R0x30A) (1, 2, 4, 6, 8, 10, 12, 14, 16) Divider AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor • op_sys_clk is used to generate the serial data stream on the output. The relationship between this clock frequency and the op_pix_clk frequency is dependent upon the output data format. The pixel frequency can be calculated in general as: ext_clk_freq_mhz pll_multiplier pixel clock mhz = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------pre_pll_clk_div vt_sys_clk_div 2 vt_pix_clk_div row_speed[2:0] (EQ 1) The output clock frequency can be calculated as: ext_clk_freq_mhz pll_multiplier clk_op_freq_mhz = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------pre_pll_clk_div op_sys_clk_div op_pix_clk_div row_speed[10:8] (EQ 2) ext_clk_freq_mhz pll_multiplier op_sys_clk_freq_mhz = -----------------------------------------------------------------------------------pre_pll_clk_div op_sys_clk_div (EQ 3) PLL Clocking The PLL divisors should be programmed while the AR0835HS is in the software standby state. After programming the divisors, it is necessary to wait for the VCO lock time before enabling the PLL. The PLL is enabled by entering the streaming state. An external timer will need to delay the entrance of the streaming mode by 1 millisecond so that the PLL can lock. The effect of programming the PLL divisors while the AR0835HS is in the streaming state is undefined. Clock Control The AR0835HS uses an aggressive clock-gating methodology to reduce power consumption. The clocked logic is divided into a number of separate domains, each of which is only clocked when required. When the AR0835HS enters a soft standby state, almost all of the internal clocks are stopped. The only exception is that a small amount of logic is clocked so that the twowire serial interface continues to respond to read and write requests. AR0835HS_DS Rev. D Pub. 5/15 EN 27 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Features Features Interlaced HDR Readout The sensor enables HDR by outputting frames where even and odd row pairs within a single frame are captured at different integration times. This output is then matched with an algorithm designed to reconstruct this output into an HDR still image or video. The sensor HDR is controlled by two shutter pointers (Shutter pointer1, Shutter pointer2) that control the integration of the odd (Shutter pointer1) and even (Shutter pointer 2) row pairs. Figure 16: HDR Integration Time I-FRAME 1 Shutter pointer 1 EXPOSURE I-FRAME 1 Tint 1 I-FRAME 2 Shutter pointer 2 Sample pointer EXPOSURE I-FRAME 1 Tint 2 Output Frame from Sensor Output I-FRAME 1 and 2 AR0835HS_DS Rev. D Pub. 5/15 EN 28 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Integration Time for Interlaced HDR Readout Tint1 (integration time 1) and Tint2 (integration time 2) The limits for the coarse integration time are defined by: coarse_integration_time_min coarse_integration_time frame_length_lines – coarse_integration_time_max_margin (EQ 4) coarse_integration_time2_min coarse_integration_time2 frame_length_lines – coarse_integration_time2_max_margin (EQ 5) The actual integration time is given by: coarse_integration_time line_length_pck - integration_time = ----------------------------------------------------------------------------------------------------------6 vt_pix_clk_freq_mhz 10 (EQ 6) coarse_integration_time2 line_length_pck - integration_time2 = -------------------------------------------------------------------------------------------------------------6 vt_pix_clk_freq_mhz 10 (EQ 7) If this limit is broken, the frame time will automatically be extended to (coarse_integration_time + coarse_integration_time_max_margin) to accommodate the larger integration time. The ratio between even and odd rows is typically adjusted to 1x, 2x, 4x, and 8x. AR0835HS_DS Rev. D Pub. 5/15 EN 29 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Bayer Resampler The imaging artifacts found from a 2x2 binning or summing will show image artifacts from aliasing. These can be corrected by resampling the sampled pixels in order to filter these artifacts. Figure 17 shows the pixel location resulting from 2x2 summing or binning located in the middle and the resulting pixel locations after the Bayer resampling function has been applied. Figure 17: Bayer Resampling The improvements from using the Bayer resampling feature can be seen in Figure 18. In this example, image edges seen on a diagonal have smoother edges when the Bayer resampling feature is applied. This feature is only designed to be used with modes configured with 2x2 binning or summing. The feature will not remove aliasing artifacts that are caused skipping pixels. Figure 18: Results of Resampling 2x2 binned - after resampling 2x2 binned - before To enable the Bayer resampling feature: 1. Set R0x400 = 2 // Enable the on-chip scalar. 2. Set R0x306E to 0x90B0 // Configure the on-chip scalar to resample Bayer data. To disable the Bayer resampling feature: 1. Set R0x400 = 0 // Disable the on-chip scalar. 2. Set R0x306E to 0x9080 // Configure the on-chip scalar to resample Bayer data. Note: Figure 19: The image readout (rows and columns) has to have two extra rows and two extra columns when using the resample feature. Illustration of Resampling Operation Image array readout 3264 x 2448 AR0835HS_DS Rev. D Pub. 5/15 EN 2 x 2 binning Image size output 1632 x 1224 30 Resampling Resampled image output 1632 x 1224 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout One-Time Programmable Memory (OTPM) The AR0835HS features 5.6 kbits of one-time programmable memory (OTPM) for storing shading correction coefficients, individual module, and customer-specific information. The user may program the data before shipping. OTPM can be accessed through twowire serial interface. The AR0835HS uses the auto mode for fast OTPM programming and read operations. To read out the OTPM, 1.8V supply is required. As a result, a dedicated DVDD_1V8 pad has been implemented.During the programming process, a dedicated pin for high voltage needs to be provided to perform the anti-fusing operation. This voltage (VPP) would need to be 6.5V. The completion of the programming process will be communicated by a register through the two-wire serial interface. If the VPP pin does not need to be bonded out as a pin on the module, it should be left floating inside the module. The programming of the OTPM requires the sensor to be fully powered and remain in software standby with its clock input applied. The information will be programmed through the use of the two-wire serial interface, and once the data is written to an internal register, the programming host machine will apply a high voltage to the programming pin, and send a program command to initiate the anti-fusing process. After the sensor has finished programming the OTPM, a status bit will be set to indicate the end of the programming cycle, and the host machine can poll the setting of the status bit through the two-wire serial interface. Only one programming cycle for the 16bit word can be performed. Reading the OTPM data requires the sensor to be fully powered and operational with its clock input applied. The data can be read through a register from the two-wire serial interface. Programming and Verifying the OTPM The procedure for programming and verifying the AR0835HS OTPM follows: 1. Apply power to all the power rails of the sensor. 2. Provide a 12-MHz EXTCLK clock input. 3. Set R0x301A = 0x18, to put sensor in the soft standby mode. 4. Set R0x3130 = 0xFF01 (Timing configuration) 5. Set R0x304C[15:8] = Record type (E.g. 0x30) 6. Set R0x304C[7:0] = Length of the record which is the number of OTPM data registers that are filled in. 7. Set R0x3054[9] = 0 to ensure that the error checking and correction is enabled. 8. Write data into all the OTPM data registers: R0x3800-R0x39FE. 9. Ramp up VPP to 6.5V. 10. Set the otpm_control_auto_wr_start bit in the otpm_control register R0x304A[0] = 1, to initiate the auto program sequence. The sensor will now program the data into the OTPM. 11. Poll otpm_control_auto_wr_end (R0x304A [1]) to determine when the sensor is finished programming the word. 12. Verify that the otpm_control_auto_wr_success(0x304A[2]) bit is set. 13. If the above bits are not set to 1, then examine otpm_status register R0x304E[9] to verify if the OTPM memory is full and 0x304E[10] to verify if OTPM memory is insufficient. 14. Remove the high voltage (VPP) and float VPP pin. AR0835HS_DS Rev. D Pub. 5/15 EN 31 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Reading the OTPM 1. Apply power to all the power rails of the sensor (VDD_IO, VAA, VAA_PIX, DVDD_1V2, DVDD_1V2_PHY, and DVDD_1V8) at their nominal voltage. 2. Set EXTCLK to normal operating frequency. 3. Perform proper reset sequence to the sensor. 4. Set R0x3134=0xCD95 (Timing Configuration) 5. Set R0x304C[15:8] = Record Type (for example, 0x30) 6. Set R0x304C[7:0] = Length of the record which is the number of data registers to be read back. This could be set to 0 during OTPM auto read if length is unknown. 7. Set R0x3054 = 0x0400 8. Initiate the auto read sequence by setting the otpm_control_auto_read_start bit (R0x304A[4]) = 1. 9. Poll the otpm_control_auto_rd_end bit (R0x304A[5]) to determine when the sensor is finished reading the word(s). When this bit becomes 1, the otpm_control_auto_rd_success bit (R0x304A[6]) will indicate whether the memory was read successfully or not. 10. Data can now be read back from the otpm_data registers (R0x3800-R0x39FE). Image Acquisition Modes The AR0835HS supports two image acquisition modes: 1. Electronic rolling shutter (ERS) mode. This is the normal mode of operation. When the AR0835HS is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is fixed, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0835HS switches cleanly from the old integration time to the new while only generating frames with uniform integration. See “Changes to Integration Time” on page 24. 2. Global reset release (GRR) mode. This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0835HS provides control signals to interface to that shutter. The operation of this mode is described in detail in “Global Reset Release (GRR)” on page 46. The benefit for the use of an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. The output image size is controlled by the x_output_size and y_output_size registers. AR0835HS_DS Rev. D Pub. 5/15 EN 32 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Pixel Border The default settings of the sensor provide a 3264H x 2448V image. A border of up to 8 pixels (4 in binning) on each edge can be enabled by reprogramming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, x_output_size, and y_output_size registers accordingly. These border pixels can be used but are disabled by default. Readout Modes Horizontal Mirror The horizontal_mirror bit in the image_orientation register is set by default. The result of this is that the order of pixel readout within a row is reversed, so that readout starts from x_addr_end and ends at x_addr_start. Figure 20 on page 33 shows a sequence of 6 pixels being read out with horizontal_mirror = 0 and horizontal_mirror = 1. Changing horizontal_mirror causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. Figure 20: Effect of horizontal_mirror on Readout Order LINE_VALID horizontal_mirror = 0 DOUT[9:0] G0[9:0] R0[9:0] G1[9:0] R1[9:0] G2[9:0] R2[9:0] horizontal_mirror = 1 DOUT[9:0] R2[9:0] G2[9:0] R1[9:0] G1[9:0] R0[9:0] G0[9:0] Vertical Flip When the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. Figure 21 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. Changing vertical_flip causes the Bayer order of the output image to change; the new Bayer order is reflected in the value of the pixel_order register. Figure 21: Effect of vertical_flip on Readout Order FRAME_VALID vertical_flip = 0 DOUT[9:0] Row0[9:0] Row1[9:0] Row2[9:0] Row3[9:0] Row4[9:0] Row5[9:0] vertical_flip = 1 DOUT[9:0] Row5[9:0] Row4[9:0] Row3[9:0] Row2[9:0] Row1[9:0] Row0[9:0] Subsampling The AR0835HS supports subsampling to reduce the amount of data processed by the signal chains in the AR0835HS, thereby allowing the frame rate to be increased and power consumption reduced. Subsampling is enabled by setting x_odd_inc and/or AR0835HS_DS Rev. D Pub. 5/15 EN 33 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout y_odd_inc. Values of 1, 3, and 7 can be supported. Setting both of these variables to 3 reduces the amount of row and column data processed and is equivalent to the 2 x 2 skipping readout mode provided by the AR0835HS. Setting x_odd_inc = 3 and y_odd_inc = 3 results in a quarter reduction in output image size. Figure 22 on page 34 shows a sequence of 8 columns being read out with x_odd_inc = 3 and y_odd_inc = 1. Figure 22: Effect of x_odd_inc = 3 on Readout Sequence LINE_VALID x_odd_inc = 1 DOUT[9:0] G0[9:0] R0[9:0] G1[9:0] R1[9:0] G0[9:0] R0[9:0] G2[9:0] R2[9:0] G2[9:0] R2[9:0] G3[9:0] R3[9:0] LINE_VALID x_odd_inc = 3 DOUT[9:0] A 1/16 reduction in resolution is achieved by setting both x_odd_inc and y_odd_inc to 7. This is equivalent to 4 x 4 skipping readout mode provided by the AR0835HS. Figure 23 shows a sequence of 16 columns being read out with x_odd_inc = 7 and y_odd_inc = 1. Figure 23: Effect of x_odd_inc = 7 on Readout Sequence LINE_VALID x_odd_inc = 1 DOUT[9:0] G0[9:0] R0[9:0] G1[9:0] R1[9:0] G0[9:0] R0[9:0] G4[9:0] R4[9:0] G2[9:0] ... G7[9:0] R7[9:0] LINE_VALID x_odd_inc = 7 DOUT[9:0] The effect of the different subsampling settings on the pixel array readout is shown in Figure 24 through Figure 26 on page 36. AR0835HS_DS Rev. D Pub. 5/15 EN 34 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Figure 24: Pixel Readout (No Subsampling) Y incrementing X incrementing Figure 25: Skip2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 3) Y incrementing X incrementing AR0835HS_DS Rev. D Pub. 5/15 EN 35 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Figure 26: Skip4 Pixel Readout (x_odd_inc = 7, y_odd_inc = 7) Y incrementing X incrementing AR0835HS_DS Rev. D Pub. 5/15 EN 36 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Programming Restrictions when Subsampling When subsampling is enabled and the sensor is switched back and forth between full resolution and subsampling, ON Semiconductor recommends that line_length_pck be kept constant between the two modes. This allows the same integration times to be used in each mode. When subsampling is enabled, it may be necessary to adjust the x_addr_start, x_addr_end, y_addr_start, and y_addr_end settings: the values for these registers are required to correspond with rows/columns that form part of the subsampling sequence. The adjustment should be made in accordance with these rules: x_skip_factor = (x_odd_inc + 1) / 2 y_skip_factor = (y_odd_inc + 1) / 2 • x_addr_start should be a multiple of x_skip_factor * 4 • (x_addr_end - x_addr_start + x_odd_inc) should be a multiple of x_skip_factor * 4 • (y_addr_end - y_addr_start + y_odd_inc) should be a multiple of y_skip_factor * 4 The number of columns/rows read out with subsampling can be found from the equation below: • columns/rows = (addr_end - addr_start + odd_inc) / skip_factor Table 11 shows the row or column address sequencing for normal and subsampled readout. In the 2X skip case, there are two possible subsampling sequences (because the subsampling sequence only reads half of the pixels) depending upon the alignment of the start address. Similarly, there will be four possible subsampling sequences in the 4X skip case (though only the first two are shown in Table 11). Table 11: AR0835HS_DS Rev. D Pub. 5/15 EN Row Address Sequencing During Subsampling odd_inc = 1 (Normal) odd_inc = 3 (2X Skip) odd_inc = 7 (4X Skip) start = 0 start = 0 start = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 0 1 4 5 8 9 8 9 12 13 37 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Binning The AR0835HS supports 2 x 1 (column binning, also called x-binning). Binning has many of the same characteristics as skipping, but because it gathers image data from all pixels in the active window (rather than a subset of them), it achieves superior image quality and avoids the aliasing artifacts that can be a characteristic side effect of skipping. Binning is enabled by selecting the appropriate subsampling settings (in read_mode, the sub-register x_odd_inc = 3 and y_odd_inc = 1 for x-binning and setting the appropriate binning bit in read_mode R0x3040[11] = 1 for x_bin_enable). As with skipping, x_addr_end and y_addr_end may require adjustment when binning is enabled. It is the first of the two columns/rows binned together that should be the end column/row in binning, so the requirements to the end address are exactly the same as in skipping mode. The effect of the different binning is shown in Figure 27 below and Figure 28 on page 39. Binning can also be enabled when the 4X subsampling mode is enabled (x_odd_inc = 7 and y_odd_inc = 1 for x-binning, x_odd_inc = 7 and y_odd_inc = 7 for 4X xy-binning). In this mode, however, not all pixels will be used so this is not a 4X binning implementation. An implementation providing a combination of skip2 and bin2 is used to achieve 4X subsampling with better image quality. The effect of this subsampling mode is shown in Figure 28 on page 39. Figure 27: Bin2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1) Y incrementing X incrementing AR0835HS_DS Rev. D Pub. 5/15 EN 38 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Figure 28: Bin2Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, x_bin = 1) Y incrementing X incrementing Binning address sequencing is a bit more complicated than during subsampling only, because of the implementation of the binning itself. For a given column n, there is only one other column, n_bin, that can be binned with, because of physical limitations in the column readout circuitry. The possible address sequences are shown in Table 12. Table 12: Column Address Sequencing During Binning odd_inc = 1 (Normal) odd_inc = 3 (2X Bin) odd_inc = 7 (2X Skip + 2XBin) x_addr_start = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x_addr_start = 0 0/2 1/3 x_addr_start = 0 0/4 1/5 4/6 5/7 8/10 9/11 8/12 9/13 12/14 13/15 There are no physical limitations on what can be binned together in the row direction. A given row n will always be binned with row n+2 in 2X subsampling mode and with row n+4 in 4X subsampling mode. Therefore, which rows get binned together depends upon the alignment of y_addr_start. The possible sequences are shown in Table 13 on page 40. AR0835HS_DS Rev. D Pub. 5/15 EN 39 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Table 13: AR0835HS_DS Rev. D Pub. 5/15 EN Row Address Sequencing During Binning odd_inc = 1 (Normal) odd_inc = 3 (2X Bin) odd_inc = 7 (2X Skip + 2X Bin) x_addr_start = 0 x_addr_start = 0 x_addr_start = 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0/2 1/3 0/4 1/5 4/6 5/7 8/10 9/11 8/12 9/13 12/14 13/15 40 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Programming Restrictions When Binning and Summing Binning and summing require different sequencing of the pixel array and impose different timing limits on the operation of the sensor. As a result, when xy-subsampling is enabled, some of the programming limits declared in the parameter limit registers are no longer valid. In addition, the default values for some of the manufacturer-specific registers need to be reprogrammed. See “Minimum Frame Time” and "Minimum Row Time" on page 43. Subsampling / binning options: 1. XskipYskip R0x3040[11], x_bin_en: 0 R0x3040[13], row_sum: 0 R0x0382: x_odd_inc = 3 (xskip2) or 7 (xskip4) R0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4) or 15 (yskip8) 2. XbinYskip R0x3040[11], x_bin_en: 1 R0x3040[13], row_sum: 0 R0x0382: x_odd_inc = 3 (xbin2) R0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4) or 15 (yskip8) 3. XskipYsum R0x3040[11], x_bin_en: 0 R0x3040[13], row_sum: 1 R0x0382: x_odd_inc = 3 (xskip2) or 7 (xskip4) R0x0386: y_odd_inc = 3 (ysum2) 4. XbinYsum R0x3040[11], x_bin_en: 1 R0x3040[13], row_sum: 1 R0x0382: x_odd_inc = 3 (xbin2) R0x0386: y_odd_inc = 3 (ysum2) 5. XsumYsum R0x3040[11], x_bin_en: 1 R0x3040[13], row_sum: 1 R0x3EE4[0], sreg_colamp_sum2: 1 (cannot write to this bit when streaming - have to write to entire register) R0x0382: x_odd_inc = 3 (xsum2) R0x0386: y_odd_inc = 3 (ysum2) AR0835HS_DS Rev. D Pub. 5/15 EN 41 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Binning, Skipping, and Summing Mode Summing, skipping, and binning can be combined in the modes listed in Table 14. Unlike binning mode where the values of adjacent same color pixels are averaged together, summing adds the pixel values together resulting in better sensor sensitivity. Summing is supposed to provide two times the sensitivity compared to the binning only mode. Table 14: Figure 29: Available Skip, Bin, and Sum Modes in the AR0835HS Sensor Subsampling Method Horizontal Vertical Skipping Binning Summing 2x, 4x 2x 2x 2x, 4x, 8x 2x Pixel Binning and Summing 2 x2 Binning o r Summing X-Binning Summing av g Σh Σv Σv av g AR0835HS_DS Rev. D Pub. 5/15 EN 42 Σh ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Scaler Scaling reduces the size of the output image while maintaining the same field-of-view. The input and output of the scaler is in Bayer format. When compared to skipping, scaling is advantageous as it avoids aliasing. The scaling factor, programmable in 1/16 steps, is used for horizontal and vertical scalers. The AR0835HS sensor is capable of horizontal scaling and full (horizontal and vertical) scaling. The scale factor is determined by: • n, which is fixed at 16 • m, which is adjustable with register R0x0404 • Legal values for m are 16 through 96, giving the user the ability to scale from 1:1 (m=16) to 1:6 (m=96). Frame Rate Control The formulas for calculating the frame rate of the AR0835HS are shown below. The line length is programmed directly in pixel clock periods through register line_length_pck. For a specific window size, the minimum line length can be found from Equation 8: x_addr_end - x_addr_start + 1 minimum line_length_pck = ---------------------------------------------------------------------------- + min_line_blanking_pck subsampling factor (EQ 8) Note that line_length_pck also needs to meet the minimum line length requirement set in register min_line_length_pck. The row time can either be limited by the time it takes to sample and reset the pixel array for each row, or by the time it takes to sample and read out a row. Values for min_line_blanking_pck are provided in “Minimum Row Time” on page 43. The frame length is programmed directly in number of lines in the register frame_line_length. For a specific window size, the minimum frame length can be found in Equation 9: y_addr_end - y_addr_start + 1 minimum frame_length_lines = ---------------------------------------------------------------------------- + min_frame_blanking_lines (EQ 9) subsampling factor The frame rate can be calculated from these variables and the pixel clock speed as shown in Equation 10: vt_pixel_clock_mhz x 1 x 10 6 frame rate = --------------------------------------------------------------------------------------------line_length_pck_x frame_length_lines (EQ 10) If coarse_integration_time is set larger than frame_length_lines the frame size will be expanded to coarse_integration_time + 1. Minimum Row Time Enough time must be given to the output FIFO so it can output all data at the set frequency within one row time. There are therefore two checks that must all be met when programming line_length_pck: AR0835HS_DS Rev. D Pub. 5/15 EN 43 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout • line_length_pck > min_line_length_pck in Table 15. • The row time must allow the FIFO to output all data during each row. That is, line_length_pck > (x_output_size * 2 + 0x005E) * “vt_pix_clk period” / “op_pix_clk period” Minimum Frame Time The minimum number of rows in the image is 1, so min_frame_length_lines will always equal (min_frame_blanking_lines + 1). Table 15: Minimum Frame Time and Blanking Numbers min_frame_blanking_lines min_frame_length_lines 0x008F 0x0A1F Integration Time The integration (exposure) time of the AR0835HS is controlled by the coarse_integration_time register. The limits for the coarse integration time are defined by: coarse_integration_time_min < coarse_integration_time (EQ 11) The actual integration time is given by: coarse_integration_time * line_length_pck integration_time = --------------------------------------------------------------------------------------------------------- vt_pix_clk_freq_mhz*10 6 (EQ 12) It is required that: coarse_integration_time (frame_length_lines – coarse_integration_time_max_margin) (EQ 13) If this limit is broken, the frame time will automatically be extended to (coarse_integration_time + coarse_integartion_time_max_margin) to accommodate the larger integration time. In binning mode, frame_length_lines should be set larger than coarse_integration_time by at least 3 to avoid column imbalance artifact. AR0835HS_DS Rev. D Pub. 5/15 EN 44 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Flash Timing Control The AR0835HS supports both xenon and LED flash timing through the FLASH output signal. The timing of the FLASH signal with the default settings is shown in Figure 30 (xenon) and Figure 31 on page 45 (LED). The flash and flash_count registers allow the timing of the flash to be changed. The flash can be programmed to fire only once, delayed by a few frames when asserted, and (for xenon flash) the flash duration can be programmed. Enabling the LED flash will cause one bad frame, where several of the rows only have the flash on for part of their integration time. This can be avoided either by first enabling mask bad frames (R0x301A[9] = 1) before the enabling the flash or by forcing a restart (R0x301A[1] = 1) immediately after enabling the flash; the first bad frame will then be masked out, as shown in Figure 31. Read-only bit flash[14] is set during frames that are correctly integrated; the state of this bit is shown in Figures 30 and Figure 31. Figure 30: Xenon Flash Enabled FRAME_VALID Flash STROBE State ofTriggered Bit (R0x3046-7[14]) Figure 31: LED Flash Enabled FRAME_VALID Flash STROBE State of Triggered Bit (R0x3046-7[14]) Bad frame is masked Flash enabled during this frame Note: AR0835HS_DS Rev. D Pub. 5/15 EN Bad frame is masked Good frame Good frame Flash disabled during this frame An option to invert the flash output signal through R0x3046[7] is also available. 45 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Global Reset Release (GRR) Global reset release mode allows the integration time of the AR0835HS to be controlled by an external electromechanical shutter. GRR mode is generally used in conjunction with ERS mode. The ERS mode is used to provide viewfinder information, the sensor is switched into GRR mode to capture a single frame, and the sensor is then returned to ERS mode to restore viewfinder operation. Overview of Global Reset Release Sequence The basic elements of the GRR sequence are: 1. By default, the sensor operates in ERS mode and the SHUTTER output signal is LOW. The electromechanical shutter must be open to allow light to fall on the pixel array. Integration time is controlled by the coarse_integration_time register. 2. A global reset sequence is triggered. 3. All of the rows of the pixel array are placed in reset. 4. All of the rows of the pixel array are taken out of reset simultaneously. All rows start to integrate incident light. The electromechanical shutter may be open or closed at this time. 5. If the electromechanical shutter has been closed, it is opened. 6. After the desired integration time (controlled internally or externally to the AR0835HS), the electromechanical shutter is closed. 7. A single output frame is generated by the sensor with the usual LV, FV, PIXCLK, and DOUT timing. As soon as the output frame has completed (FV negates), the electromechanical shutter may be opened again. 8. The sensor automatically resumes operation in ERS mode. This sequence is shown in Figure 32. The following sections expand to show how the timing of this sequence is controlled. Figure 32: Overview of Global Reset Sequence ERS AR0835HS_DS Rev. D Pub. 5/15 EN Row Reset Integration 46 Readout ERS ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Entering and Leaving the Global Reset Sequence A global reset sequence can be triggered by a register write to R0x315E global_seq_trigger[0] (global trigger, to transition this bit from a 0 to a 1) or by a rising edge on a suitably-configured GPI input). When a global reset sequence is triggered, the sensor waits for the end of the current row. When LV negates for that row, FV is negated 6 PIXCLK periods later, potentially truncating the frame that was in progress. The global reset sequence completes with a frame readout. At the end of this readout phase, the sensor automatically resumes operation in ERS mode. The first frame integrated with ERS will be generated after a delay of approximately ((13 + coarse_integration_time) * line_length_pck). This sequence is shown in Figure 33. While operating in ERS mode, double-buffered registers (“Double-Buffered Registers” on page 23) are updated at the start of each frame in the usual way. During the global reset sequence, double-buffered registers are updated just before the start of the readout phase. Figure 33: Entering and Leaving a Global Reset Sequence Trigger Wait for end of current row ERS Row Reset Automatic at end of frame readout Integration Readout ERS Programmable Settings The registers global_rst_end and global_read_start allow the duration of the row reset phase and the integration phase to be controlled, as shown in Figure 34. The duration of the readout phase is determined by the active image size. The recommended setting for global_rst_end is 0x3160 (for example, 512 s total reset time) with default vt_pix_clk. This allows sufficient time for all rows of the pixel array to be set to the correct reset voltage level. The row reset phase takes a finite amount of time due to the capacitance of the pixel array and the capability of the internal voltage booster circuit that is used to generate the reset voltage level. As soon as the global_rst_end count has expired, all rows in the pixel array are taken out of reset simultaneously and the pixel array begins to integrate incident light. Figure 34: Controlling the Reset and Integration Phases of the Global Reset Sequence Trigger Wait for end of current row ERS Row Reset Automatic at end of frame readout Integration Readout ERS global_rst_end global_read_start AR0835HS_DS Rev. D Pub. 5/15 EN 47 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout Control of the Electromechanical Shutter Figure 35 on page 48 shows two different ways in which a shutter can be controlled during the global reset sequence. In both cases, the maximum integration time is set by the difference between global_read_start and global_rst_end. In shutter example 1, the shutter is open during the initial ERS sequence and during the row reset phase. The shutter closes during the integration phase. The pixel array is integrating incident light from the start of the integration phase to the point at which the shutter closes. Finally, the shutter opens again after the end of the readout phase. In shutter example 2, the shutter is open during the initial ERS sequence and closes sometime during the row reset phase. The shutter both opens and closes during the integration phase. The pixel array is integrating incident light for the part of the integration phase during which the shutter is open. As for the previous example, the shutter opens again after the end of the readout phase. Figure 35: Control of the Electromechanical Shutter Trigger Wait for end of current row ERS Automatic at end of frame readout Row Reset Integration Readout ERS global_rst_end global_read_start maximum integration time actual integration time SHUTTER Example 1 shutter open (physical) SHUTTER Example 2 shutter open (physical) shutter closed shutter open shutter closed shutter open actual integration time closed shutter open It is essential that the shutter remains closed during the entire row readout phase (that is, until FV has negated for the frame readout); otherwise, some rows of data will be corrupted (over-integrated). It is essential that the shutter closes before the end of the integration phase. If the row readout phase is allowed to start before the shutter closes, each row in turn will be integrated for one row-time longer than the previous row. After FV negates to signal the completion of the readout phase, there is a time delay of approximately (10 * line_length_pck) before the sensor starts to integrate light-sensitive rows for the next ERS frame. It is essential that the shutter be opened at some point in this time window; otherwise, the first ERS frame will not be uniformly integrated. The AR0835HS provides a SHUTTER output signal to control (or help the host system control) the electromechanical shutter. The timing of the SHUTTER output is shown in Figure 36 on page 49. SHUTTER is negated by default. The point at which it asserts is controlled by the programming of global_shutter_start. At the end of the global reset readout phase, SHUTTER negates approximately (2 * line_length_pck) after the negation of FV. AR0835HS_DS Rev. D Pub. 5/15 EN 48 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout This programming restriction must be met for correct operation: • global_read_start > global_shutter_start. Figure 36: Controlling the SHUTTER Output Trigger Wait for end of current row ERS Row Reset Automatic at end of frame readout Integration Readout ERS global_rst_end ~2*line_length_pck global_read_start global_shutter_start SHUTTER (signal) Using FLASH with Global Reset If R0x315E global_seq_trigger[2] = 1 (global flash enabled) when a global reset sequence is triggered, the FLASH output signal will be pulsed during the integration phase of the global reset sequence. The FLASH output will assert a fixed number of cycles after the start of the integration phase and will remain asserted for a time that is controlled by the value of the flash_count register. When flash_count is programmed for value N, (where N is 0–0x3FE) the resulting flash duration is given by N * 512 * (1/vt_pix_clk_freq_mhz), as shown in Figure 37. Figure 37: Using FLASH with Global Reset Trigger Automatic at end of frame readout Wait for end of current row ERS ROW RESET INTEGRATION READOUT ERS global_rst_end global_read_start SHUTTER ~2*line_length_pck global_ shutter_start (fixed) flash_count FLASH AR0835HS_DS Rev. D Pub. 5/15 EN 49 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout When the flash_count = 0x3FF, the flash signal will be maximized and goes LOW when readout starts, as shown in Figure 38 on page 50. This would be preferred if the latency in closing the shutter is longer than the latency for turning off the flash. This guarantees that the flash stays on while the shutter is open. Figure 38: Extending FLASH Duration in Global Reset (Reference Readout Start) Trigger Automatic at end of frame readout Wait for end of current row ERS ROW RESET INTEGRATION READOUT ERS global_rst_end global_read_ start ~2*line_length_pck global_ shutter_start SHUTTER (fixed) FLASH External Control of Integration Time If global_seq_trigger[1] = 1 (global bulb enabled) when a global reset sequence is triggered, the end of the integration phase is controlled by the level of trigger (global_seq_trigger[0] or the associated GPI input). This allows the integration time to be controlled directly by an input to the sensor. This operation corresponds to the shutter “B” setting on a traditional camera, where “B” originally stood for “Bulb” (the shutter setting used for synchronization with a magnesium foil flash bulb) and was later considered to stand for “Brief” (an exposure that was longer than the shutter could automatically accommodate). When the trigger is de-asserted to end integration, the integration phase is extended by a further time given by global_read_start – global_shutter_start. Usually this means that global_read_start should be set to global_shutter_start + 1. The operation of this mode is shown in Figure 39 on page 51. The figure shows the global reset sequence being triggered by the GPI2 input, but it could be triggered by any of the GPI inputs or by the setting and subsequence clearing of the global_seq_trigger[0] under software control. The integration time of the GRR sequence is defined as: global_scale [global_read_start – global_shutter_start – global_rst_end] Integration Time = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- (EQ 14) vt_pix_clk_freq_mhz Where: AR0835HS_DS Rev. D Pub. 5/15 EN 50 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout global_read_start = 2 16 global_read_start2 7:0 + global_read_start1 15:0 global_shutter_start = 2 16 (EQ 15) global_shutter_start2 7:0 + global_shutter_start1 15:0 (EQ 16) The integration equation allows for 24-bit precision when calculating both the shutter and readout of the image. The global_rst_end has only 16-bit as the array reset function and requires a short amount of time. The integration time can also be scaled using global_scale. The variable can be set to 0–512, 1–2048, 2–128, and 3–32. These programming restrictions must be met for correct operation of bulb exposures: • global_read_start > global_shutter_start • global_shutter_start > global_rst_end • global_shutter_start must be smaller than the exposure time (that is, this counter must expire before the trigger is de-asserted) Figure 39: Global Reset Bulb Trigger Wait for end of current row ERS Row Reset Automatic at end of frame readout Integration global_rst_end Readout ERS global_read_start - global_shutter_start GPI2 Retriggering the Global Reset Sequence The trigger for the global reset sequence is edge-sensitive; the global reset sequence cannot be retriggered until the global trigger bit (in the R0x315E global_seq_trigger register) has been returned to “0,” and the GPI (if any) associated with the trigger function has been negated. The earliest time that the global reset sequence can be retriggered is the point at which the SHUTTER output negates; this occurs approximately (2 * line_length_pck) after the negation of FV for the global reset readout phase. Using Global Reset with SMIA Data Path When a global reset sequence is triggered, it usually results in the frame in progress being truncated (at the end of the current output line). The SMIA data path limiter function (see Figure 40 on page 52) attempts to extend (pad) all frames to the programmed value of y_output_size. If this padding is still in progress when the global reset readout phase starts, the SMIA data path will not detect the start of the frame correctly. Therefore, to use global reset with the serial data path, this timing scenario must be avoided. One possible way of doing this would be to synchronize (under software control) the assertion of trigger to an end-of-frame marker on the serial data stream. At the end of the readout phase of the global reset sequence, the sensor automatically resumes operation in ERS mode. AR0835HS_DS Rev. D Pub. 5/15 EN 51 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Integration Time for Interlaced HDR Readout The frame that is read out of the sensor during the global reset readout phase has exactly the same format as any other frame out of the serial pixel data interface, including the addition of two lines of embedded data. The value of the coarse_integration_time register within the embedded data matches the programmed values of those registers and does not reflect the integration time used during the global reset sequence. Global Reset and Soft Standby If the R0x301A[2] mode_select[stream] bit is cleared while a global reset sequence is in progress, the AR0835HS will remain in streaming state until the global reset sequence (including frame readout) has completed, as shown in Figure 40 on page 52. Figure 40: Entering Soft Standby During a Global Reset Sequence ERS Row Reset Integration Readout ERS R0x0100 mode_select[streaming] system state Streaming Software Standby Slave Mode Slave mode is to ensure having an ERS-GRR-ERS transition without a broken ERS frame before GRR. It requests to trigger/end the GRR sequence through the pin which is similar to the GRR Bulb mode. The major difference to our existing sensor is to start the GRR sequence after the end of the current frame instead of to start immediately in the next following row. Figure 41: Slave Mode Transition AR0835HS_DS Rev. D Pub. 5/15 EN 52 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Gain Gain AR0835HS supports both analog and digital gain. Analog gain Analog gain is provided by colamp and ADC reference scaling (there is no ASC gain due to column parallel nature of architecture). Only global (not per-color) coarse gain can be set by analog gain. Global gain register (R0x305E) sets the analog gain. Bits [1:0] set the colamp gain while bits [4:2] are reserved for ADC gain. While the 2-bit colamp gain provides up to 4x analog gain, only LSB (bit [2]) of ADC gain bits is utilized to support 2x ADC gain. Table 16 is the recommended gain setting: Table 16: Recommended Analog Gain Setting Colamp Gain Codes (R0x305E[1:0]) 0 0 1 1 1 1 0 1 0 1 0 1 ADC Gain Codes (R0x305E[4:2]) 0 0 0 0 0 0 0 0 0 0 0 0 Colamp Gain ADC Gain Total Gain 1 2 3 4 3 4 1 1 1 1 2 2 1 2 3 4 6 8 0 0 0 0 1 1 Digital Gain Digital gain provides both per-color and fine (sub 1x) gain. The analog and digital gains are multiplicative to give the total gain. Digital gain is set by setting bits R0x305E[15:5] to set global gain or by individually setting digital color gain R0x3056-C[15:5] where these 11 bits are designed in 4p7 format i.e. 4 MSB provide gain up to 15x in step of 1x while 7 LSB provide sub-1x gain with a step size of 1/128. This sub-1x gain provides the fine gain control for the sensor. Total Gain Max. total gain required by design spec is 8x (analog) and 16x (digital) with min. step size of 1/8. The total gain equation can be formulated as: dec R0x305X[15:5] Total gain = 1 + dec R0x305E[1:0] 1 + R0x305E[2] --------------------------------------------------128 (EQ 17) where X is 6, 8, A, C, for Gr, B, R and Gb, respectively Note: ON Semiconductor recommends using the registers mentioned above for gain settings. Avoid R0x3028 to R0x3038 unless their mapping to above registers is well understood and taken into account. Temperature Sensor A standalone PTAT based temperature sensor has been implemented. The block is controlled independent of sensor timing and all communication happens through the two-wire serial interface. AR0835HS_DS Rev. D Pub. 5/15 EN 53 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Internal VCM Driver Internal VCM Driver The AR0835HS utilizes an internal Voice Coil Motor (VCM) driver. The VCM functions are register-controlled through the serial interface. There are two output ports, VCM_ISINK and VCM_GND, which would connect directly to the AF actuator. Take precautions in the design of the power supply routing to provide a low impedance path for the ground connection. Appropriate filtering would also be required on the actuator supply. Typical values would be a 0.1F and 10F in parallel. Figure 42: VCM Driver Typical Diagram VVCM 0.1µF 10µF AR0835HS VCM VCM_ISINK VCM_GND DGND Table 17: VCM Driver Typical Characteristic Parameter Minimum Typical Maximum Units VCM_OUT WVCM INL RES DNL IVCM Voltage at VCM current sink Voltage at VCM actuator Relative accuracy Resolution Differential nonlinearity Output current Slew rate (user programmable) 2.5 2.5 – – –1 90 – 2.8 2.8 ±1.5 8 – 100 – 3.3 3.3 ±4 – +1 110 13 V V LSB bits LSB mA mA/ms AR0835HS_DS Rev. D Pub. 5/15 EN 54 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 43: Quantum Efficiency 70 red 60 greenR greenB 50 blue 40 30 20 10 0 400 AR0835HS_DS Rev. D Pub. 5/15 EN 500 600 55 700 800 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Spectral Characteristics Figure 44: Chief Ray Angle (CRA) vs. Image Height CRA vs. Image Height Plot 20 CRA (%) (mm) (deg) 0 0 0 5 0.143 0.77 18 10 0.286 1.55 17 15 0.428 2.33 16 20 0.571 3.11 15 25 0.714 3.87 30 0.857 4.62 12 35 1.000 5.36 11 40 1.142 6.07 10 45 1.285 6.77 9 50 1.428 7.43 55 1.571 8.06 6 60 1.714 8.66 5 65 1.856 9.22 4 70 1.999 9.73 3 75 2.142 10.19 80 2.285 10.59 85 2.428 10.93 90 2.570 11.18 95 2.713 11.34 100 2.856 11.40 19 14 13 CRA (deg) Image Height 8 7 2 1 0 0 10 20 30 40 50 60 70 Image Height (%) AR0835HS_DS Rev. D Pub. 5/15 EN 56 80 90 100 110 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Electrical Characteristics Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 45 and Table 18. Table 19 on page 58 shows the timing specification for the two-wire serial interface. Figure 45: Two-Wire Serial Bus Timing Parameters tF SDATA tR 70% 30% 70% 30% 70% 30% 30% // 70% // // 70% SCLK tACV tSDV 30% 30% S 1st Clock tSRTH tSDS 30% 9th Clock tSDH tHIGH SDATA SCLK 70% 70% 30% // 70% 70% Sr Note: // 70% 30% 70% 70% 30% P th tLOW tSRTS Table 18: tBUF // 9 Clock S tSTPS Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Two-Wire Serial Register Interface Electrical Characteristics fEXTCLK = 25 MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_IO = 1.8V; VDD_1V2 = 1.2V; VDD_PLL = 1.2V; VDD_1V8 = 1.8V; Output load = 68.5pF; TJ = 55°C Symbol Parameter VIL Input LOW voltage VIH Input HIGH voltage Condition Min Typ Max Unit -0.5 – 0.3 x VDD_IO V 0.7 x VDD_IO – VDD_IO + 0.5 V 10 – 14 A 0.11 – 0.3 V Input leakage current No pull up resistor; VIN = VDD_IO or DGND VOL Output LOW voltage At specified 2mA IOL Output LOW current At specified VOL 0.1V – – 6 mA CIN Input pad capacitance – – 6 pF Load capacitance – – N/A pF IIN CLOAD AR0835HS_DS Rev. D Pub. 5/15 EN 57 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Table 19: Two-Wire Serial Interface Timing Specifications VDD_IO = 1.7-1.9V; VAA = 2.4 -3.1V; Environment temperature = -30°C to 50°C Symbol Definition Min Max Unit fSCLK SCLK Frequency 100 400 KHz tHIGH SCLK High Period 0.6 – s tLOW SCLK Low Period 1.3 – s tSRTS START Setup Time 0.6 – s tSRTH START Hold Time 0.6 – s tSDS Data Setup Time 100 – ns tSDH Data Hold Time 0 Note s tSDV Data Valid Time – 0.9 s tACV Data Valid Acknowledge Time – 0.9 s tSTPS STOP Setup Time 0.6 – s tBUF Bus Free Time between STOP and START 1.3 – s tr SCLK and SDATA Rise Time – 300 ns tf SCLK and SDATA Fall Time – 300 ns EXTCLK The electrical characteristics of the EXTCLK input are shown in Table 20. The EXTCLK input supports an AC-coupled sine-wave input clock or a DC-coupled square-wave input clock. If EXTCLK is AC-coupled to the AR0835HS and the clock is stopped, the EXTCLK input to the AR0835HS must be driven to ground or to VDD_IO. Failure to do this will result in excessive current consumption within the EXTCLK input receiver. Table 20: Electrical Characteristics (EXTCLK) fEXTCLK = 24 MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_IO = 1.8V; VDD_1V2 = 1.2V; Output load = 68.5pF; TJ = 55°C Symbol fEXTCLK1 Parameter Input clock frequency Condition Min Typ Max Unit PLL enabled 6 24 27 MHz t R Input clock rise slew rate CLOAD<20pF – 2.883 – ns tF Input clock fall slew rate CLOAD<20pF – 2.687 – ns VIN_AC Input clock minimum voltage swing (AC coupled) – 0.5 – – V (p-p) VIN_DC Input clock maximum voltage swing (DC coupled) – – – VDD_IO + 0.5 V f CLKMAX(AC) Input clock signaling frequency (low amplitude) VIN = VIN_AC (MIN) – – 25 MHz fCLKMAX(DC) Input clock signaling frequency (full amplitude) VIN = VDD_IO – – 48 MHz Clock duty cycle – 45 50 55 % tJITTER Input clock jitter cycle-to-cycle – 545 600 ps t LOCK PLL VCO lock time – – 0.2 2 ms CIN Input pad capacitance – – 6 – pF IIH Input HIGH leakage current – 0 – 10 A AR0835HS_DS Rev. D Pub. 5/15 EN 58 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Table 20: Electrical Characteristics (EXTCLK) fEXTCLK = 24 MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_IO = 1.8V; VDD_1V2 = 1.2V; Output load = 68.5pF; TJ = 55°C Symbol Parameter Condition Min Typ Max Unit VIH Input HIGH voltage 0.7 x VDD_IO – VDD_IO + 0.5 V VIL Input LOW voltage -0.5 – 0.3 x VDD_IO V Figure 46: Fall Slew Rates (Cap Load = 25pF) VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO AR0835HS_DS Rev. D Pub. 5/15 EN 59 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Figure 47: Rise Slew Rates (Cap Load = 25pF) VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO High Speed Serial Pixel Data Interface The High Speed Serial Pixel (HiSPi) interface uses four data and one clock low voltage differential signaling (LVDS) outputs. • SLVSC_P • SLVSC_N • SLVS0_P • SLVS0_N • SLVS1_P • SLVS1_N • SLVS2_P • SLVS2_N • SLVS3_P • SLVS3_N AR0835HS_DS Rev. D Pub. 5/15 EN 60 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics The HiSPi interface supports three protocols, Streaming S, Streaming SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface Protocol Specification V1.50.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. A collection of one clock lane plus four data lanes is called a PHY.Figure 48 shows the configuration between the HiSPi transmitter and the receiver. Figure 48: HiSPi Transmitter and Receiver Interface Block Diagram (HiSPi Mode Only) A camera containing the HiSPi transmitter Tx PHY0 A host (DSP) containing the HiSPi receiver Dp0 Dp0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 Rx PHY0 HiSPi Physical Layer The AR0835HS PHY will serialize an 8-or 10-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of clock. Figure 49 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. AR0835HS_DS Rev. D Pub. 5/15 EN 61 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Figure 49: Timing Diagram TxPost cp …. cn TxPre dp …. MSB dn LSB 1 UI DLL Timing Adjustment The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. data _lane 0 delay delay del3[2:0] del2[2:0] del1[2:0] delay AR0835HS_DS Rev. D Pub. 5/15 EN delclock[2:0] Block Diagram of DLL Timing Adjustment del0[2:0] Figure 50: delay delay data _lane 1 clock _lane 0 data _lane 2 data _lane 3 62 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Figure 51: Delaying the clock_lane with Respect to data_lane 1 UI dataN (de lN = 000) cp (delclock = 000) cp (delclock = 001) cp (delclock = 010) cp (de lclock = 011) cp (delclock = 100) cp (delcloc k = 101) c p (delclock = 110) cp (delclock =111) increasing delclock_[2:0] increases clock delay Figure 52: Delaying data_lane with Respect to the clock_lane cp (delclock = 000) dataN (delN = 000) dataN(delN = 001) dataNdelN = 010) dataN(delN = 011) dataN(delN = 100) dataN(delN = 101) dataN(delN = 110) dataN(delN = 111) increasing delN_[2:0] increases data delay t DLLSTEP 1 UI HiSPi Streaming Mode Protocol Layer The HiSPi protocol is described HiSPi Protocol V1.50.00. AR0835HS_DS Rev. D Pub. 5/15 EN 63 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Serial Pixel Data Interface (HiSPi Mode) The electrical characteristics of the serial pixel data interface (CLK_P, CLK_N, DATA[4:1]_P, and DATA[4:1]_N) are shown in Table 21 and Table 22 Table 21: SLVS Electrical Timing Specification Parameter Symbol Data Rate Bitrate Period Max Unit 1/UI 280 1000 Mbps 1 tPW 1.00 3.57 ns 1 0.3 UI 1, 2 0.3 UI 1, 2 UI 1, 2 1, 2 Max setup time from transmitter tPRE Max hold time from transmitter tPOST Eye Width tEYE Data Total Jitter (pk-pk) @1e-9 0.6 Notes tTOTALJIT 0.2 UI Clock Period Jitter (RMS) tCKJIT 50 ps 2 Clock Cycle-to-Cycle Jitter (RMS) tCYCJIT 100 ps 2 3 Rise time (20% - 80%) tR 150ps 0.25 UI Fall time (20% - 80%) tF 150ps 0.25 UI 3 DCYC 45 55 % 2 Clock duty cycle Total Clock to Data Skew tCHSKEW -0.2 0.2 UI 1, 4 Mean differential skew tDIFFSKEW -100 100 ps 5 Notes: Table 22: Min 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from the 0V crossing point with the DLL off. 3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3 UI. 4. The total skew between the Clock lane and any Data Lane in the same PHY between any edges; it includes clock duty cycle, mean skew and total peak jitter at BER of 1E-9. 5. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. Note that differential skew also is related to the VCM_AC spec which also must not be exceeded. SLVS Electrical DC Specification Tj = 25°C Parameter Symbol Min Typ Max Unit VCM 0.45*VDD_TX 0.5*VDD_TX 0.55*VDD_TX V SLVS DC mean differential output voltage |VOD| 0.36*VDD_T 0.5*VDD_TX 0.64*VDD_TX V Change in VCM between logic 1 and 0 VCM 25 mV Change in |VOD| between logic 1 and 0 | VOD| 25 mV NM ±30 % Difference in VCM between any two channels |VCM| 30 mV Difference in VOD between any two channels |VOD| 50 mV Common-mode AC Voltage (pk) without VCM cap termination VCM_AC 50 mV Common-mode AC Voltage (pk) with VCM cap termination VCM_AC 30 mV Maximum overshoot peak |VOD| VOD_AC 1.3*|VOD| V Maximum overshoot Vdiff pk-pk Vdiff_pkpk 2.6*VOD V SLVS DC mean common mode voltage VOD noise margin AR0835HS_DS Rev. D Pub. 5/15 EN 64 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Table 22: SLVS Electrical DC Specification Tj = 25°C Parameter Symbol Min Typ Max RO 35 50 70 Ù 20 % Single-ended Output impedance RO Output Impedance Mismatch Unit Control Interface The electrical characteristics of the control interface (RESET_BAR, TEST, GPIO0, GPIO1, GPI2, and GPI3) are shown in Table 23. Table 23: DC Electrical Characteristics (Control Interface) fEXTCLK = 24 MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_IO = 1.8V; DVDD_1V2 = 1.2V; Output load = 68.5pF; TJ = 55°C Symbol Parameter Condition Min Typ Max Unit VIH Input HIGH voltage 0.7 x VDD_IO – VDD_IO + 0.5 V VIL Input LOW voltage –0.5 – VDD_IO X 0.3 V – – 10 A – 6 – pF IIN CIN Input leakage current No pull-up resistor; VIN = VDD_IO or DGND Input pad capacitance Operating Voltages VAA and VAA_PIX must be at the same potential for correct operation of the AR0835HS. Table 24: DC Electrical Definitions and Characteristics fEXTCLK = 24 MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_IO = 1.8V; VDD_1V2 = 1.2V; Output load = 68.5pF; TJ = 70°C; Mode = Full Resolution (3264x2488); Frame rate = 30 fps Symbol Parameter VAA Analog voltage Condition Min Typ Max Unit 2.5 2.8 3.1 V VAA_PIX Pixel supply voltage 2.5 2.8 3.1 V VDD_1V2 Digital voltage 1.14 1.2 1.3 V VDD_1V8 PHY digital voltage 1.7 1.8 1.9 V VDD_IO I/O digital voltage 1.7 1.8 1.9 V 2.5 2.8 3.1 V VDDSLVS_PHY HiSPi analog supply Internal regulator disabled 0.35 0.4 0.45 V Internal regulator enabled 1.14 1.2 1.3 VDD_PHY HiSPi digital supply 1.14 1.2 1.3 V H/W Standby Current Consumption – – 30 A Output Driving Strength 10 – – mA Slew Rate – 0.7 -– V/sec Programming voltage for OTPM (VPP) 6 6.5 7 V AR0835HS_DS Rev. D Pub. 5/15 EN 65 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Electrical Characteristics Typical Operating Current Consumption Table 25: Typical Operating Current Consumption Nominal Voltages: fEXTCLK = 24MHz; VAA = 2.8V; VAA_PIX = 2.8V; VDD_1V8 = 1.8V; VDD_IO = 1.8V; VDD_1V2 = 1.2V Tj = 25°C Symbol Parameter 8Mp, 46fps Analog supply current I(VAA) I(VAA_PIX) Pixel supply current OTPM read supply current I(VDD_1V8) I(VDD_IO) I/O supply current I(VDD_1V2: VDDSW, VDD_ANA, Core supply current VDD_PLL) I(VDD_PHY, VDDSLVS_PHY) PHY supply current Min Typ Max Unit -- 85 110 mA 6Mp, 60fps -- 85 110 mA 1080p, 60fps -- 85 110 mA 720p, 120fps -- 85 110 mA 8Mp, 46fps -- 16 20 mA 6Mp, 60fps -- 16 20 mA 1080p, 60fps -- 16 20 mA 720p, 120fps -- 16 20 mA 8Mp, 46fps -- 0 1 mA 6Mp, 60fps -- 0 1 mA 1080p, 60fps -- 0 1 mA 720p, 120fps -- 0 1 mA 8Mp, 46fps -- 1 2 mA 6Mp, 60fps -- 1 2 mA 1080p, 60fps -- 1 2 mA 720p, 120fps -- 1 2 mA 8Mp, 46fps -- 150 175 mA 6Mp, 60fps -- 150 175 mA 1080p, 60fps -- 130 165 mA 720p, 120fps -- 130 140 mA 8Mp, 46fps -- 12 14 mA 6Mp, 60fps -- 12 14 mA 1080p, 60fps -- 10 12 mA 720p, 120fps -- 8 10 mA Absolute Minimum and Maximum Ratings Caution Stresses greater than those listed in Table 26 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Table 26: AR0835HS_DS Rev. D Pub. 5/15 EN Absolute Max Voltages Symbol Parameter Min Max Unit 1.2V 1.8V 2.8V All1.2V supply All1.8V supply All 2.8V supply -0.3 -0.3 -0.3 1.5 2.1 3.5 V V V 66 ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor HiSPi Specification Reference HiSPi Specification Reference The sensor design and this documentation is based on the following HiSPi Specifications: • HiSPi Protocol Specification V1.50.00 • HiSPi Physical Layer Specification V3.0 MIPI Specification Reference The sensor design and this documentation is based on the following MIPI Specifications: • MIPI Alliance Standard for CSI-2 version 1.0 • MIPI Alliance Standard for D-PHY version 1.0 AR0835HS_DS Rev. D Pub. 5/15 EN 67 ©Semiconductor Components Industries, LLC, 2015. CLCC Package Diagram Figure 53: AR0835HS_DS Rev. D Pub. 5/15 EN Package Diagram ©Semiconductor Components Industries, LLC, 2015 AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Package Diagram 68 AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Package Diagram 43 DGND 46 DGND 45 SDATA 44 SCLK 47 VDD_PLL 48 DGND 1 VDD_SW 2 DGND 3 GPI2 5 VDD_SW 4 GPI3 CLCC package Pinout Diagram 6 GPIO0 Figure 54: GPIO1 7 42 EXTCLK XSHUTDOWN 8 41 VDD_IO VCM_GND 9 40 TEST 39 VDD_SW VCM_ISINK 10 PIXGND 11 38 DGND VAA_PIX 12 ATEST1 13 37 DATA_P 36 DATA_N AGND 14 35 VDD_SLVS 34 DATA2_N VAA 15 33 DATA2_P VAA 16 AGND 17 32 VDD_PHY DGND_ANA 18 AR0835HS_DS Rev. D Pub. 5/15 EN 69 CLK_N 30 DATA3_P 29 VDD_1V8 27 DATA3_N 28 DATA4_N 26 VDD_SW 24 DATA4_P 25 VDD_1V8 23 VDD_ANA 21 VPP 22 VDD_ANA 20 DGND_ANA 19 31 CLK_P ©Semiconductor Components Industries, LLC, 2015. AR0835HS: 1/3.2-Inch 8 Mp CMOS Digital Image Sensor Revision History Revision History Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/13/15 • Converted to ON Semiconductor template • Removed Confidential marking • Updated “Ordering Information” on page 2 Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/9/14 • Updated to Production • Updated “Features” on page 1 • Updated Table 1, “Available Part Numbers,” on page 1 • Updated Table 1, “Key Performance Parameters,” on page 1 • Updated Table 2, “Modes of Operation and Power Consumption,” on page 2 • Updated “General Description” on page 6 • Updated “Functional Overview” on page 6 • Updated Figure 6: “Recommended Power-down Sequence,” on page 14 • Updated “Functional Overview” on page 6 • Updated Table 25, “Typical Operating Current Consumption,” on page 66 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/16/13 • Changed the part no. on page 1. • Updated “Features” on page 1 • Updated Table 1, “Key Performance Parameters,” on page 1 • Updated Table 2, “Modes of Operation and Power Consumption,” on page 2 • Updated “General Description” on page 6 • Updated Figure 15: “Clocking Configuration (PLL),” on page 26 • Updated Figure 53: “CLCC Package Diagram,” on page 68 • Updated Table 27, “Pin Connection Table,” on page 72 Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/1/12 • Initial release“Programming and Verifying the OTPM” on page 31 A-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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