NB3N51054 D

NB3N51054
3.3 V, Crystal to 100 MHz
Quad HCSL/LVDS PCIe
Clock Generator
The NB3N51054 is a precision, low phase noise clock generator that
supports PCI Express requirements. The device accepts a 25 MHz
fundamental mode parallel resonant crystal or a 25 MHz reference
clock signal and generates four differential HCSL/LVDS outputs (See
Figure 7 for LVDS interface) at 100 MHz clock frequency with
maximum skew of 40 ps. Through I2C interface, NB3N51054
provides selectable spread spectrum options of −0.35% and −0.5% for
applications demanding low Electromagnetic Interface (EMI) as well
as optimum performance with no spread option. The I2C interface
further enables control of each output and they can be enabled/
disabled individually.
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MARKING
DIAGRAM
TSSOP−24
CASE 948H
Features
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Uses 25 MHz Fundamental Crystal or Reference Clock Input
Four Low Skew HCSL or LVDS Outputs
I2C Support with Read Back Capability
Spread of −0.35%, −0.5% and No Spread
Individual Output Enable/Disable Control through I2C
PCIe Gen 1, Gen 2, Gen 3 Compliant
Typical Phase Jitter @ 100 MHz (Integrated 12 kHz to 20 MHz):
0.5 ps
Typical Cycle−Cycle Jitter @ 100 MHz (10k cycles): 20 ps
Phase Noise @ 100 MHz:
Offset
Noise Power
100 Hz
−104 dBc/Hz
1 kHz
−121 dBc/Hz
10 kHz
−131 dBc/Hz
100 kHz −136 dBc/Hz
1 MHz
−140 dBc/Hz
10 MHz −155 dBc/Hz
Operating Power Supply: 3.3 V ± 5%
Industrial Temperature Range: −40°C to 85°C
Functionally Compatible with ICS841S104I with enhanced
performance
These are Pb−Free Devices
NB3N5
1054G
ALYW
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Application
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End Products
Networking
Consumer
Computing and Peripherals
Industrial Equipment
PCIe Clock Generation Gen 1, Gen 2 and Gen 3
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 2
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Switch and Router
Set Top Box, LCD TV
Servers, Desktop Computers
Automated Test Equipment
Publication Order Number:
NB3N51054/D
NB3N51054
BLOCK DIAGRAM
VDD
SDATA
SCLK
CLKx_OE
I2C Serial
Interface
SS_EN, SS_SEL
HCSL
buffer
CLK3
Spread
Spectrum
XIN/CLKIN
25 MHz ref
Clock or
25 MHz
Crystal XOUT
Clock Buffer/
Cystal Oscillator
Phase
Detector
CLK3
Charge
Pump
HCSL
buffer
CLK2
HCSL
buffer
CLK1
HCSL
buffer
CLK0
CLK2
Divider
VCO
CLK1
Feedback
Divider
GND
IREF
Figure 1. Block Diagram
PIN CONFIGURATION
CLK2
1
24
CLK3
CLK2
2
23
CLK3
GND
3
22
VDD
VDD
4
21
SDATA
CLK1
5
20
SCLK
CLK1
6
19
XOUT
CLK0
7
18
XIN/CLKIN
CLK0
8
17
VDD
GND
9
16
GND
VDD
10
15
NC
GND
11
14
VDD
IREF
12
13
GND
1
Figure 2. Pin Configuration (Top View)
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2
CLK0
NB3N51054
Table 1. PIN DESCRIPTION
Pin #
Pin Name
Type
1
CLK2
HCSL or LVDS
output
Noninverted clock output. (For LVDS levels see Figure 4)
Description
2
CLK2
HCSL or LVDS
output
Inverted clock output. (For LVDS levels see Figure 4)
3
GND
Ground
Power supply ground 0 V. This pin provides GND return path for the device.
4
VDD
Power
Positive supply voltage pin connected to +3.3 V typical supply voltage.
5
CLK1
HCSL or LVDS
output
Noninverted clock output. (For LVDS levels see Figure 4)
6
CLK1
HCSL or LVDS
output
Inverted clock output. (For LVDS levels see Figure 4)
7
CLK0
HCSL or LVDS
output
Noninverted clock output. (For LVDS levels see Figure 4)
8
CLK0
HCSL or LVDS
output
Inverted clock output. (For LVDS levels see Figure 4)
9
GND
Ground
Power supply ground 0 V. This pin provides GND return path for the device.
10
VDD
Power
Positive supply voltage pin connected to +3.3 V typical supply voltage.
11
GND
Ground
Power supply ground 0 V. This pin provides GND return path for the device.
12
IREF
Output
Output current reference pin. Connect to precision resistor (typical 475 W) to set internal
current reference
13
GND
Ground
Power supply ground 0 V. This pin provides GND return path for the device.
14
VDD
Power
Positive supply voltage pin connected to +3.3 V typical supply voltage.
15
NC
NC
16
GND
Ground
Power supply ground 0 V. This pin provides GND return path for the device.
17
VDD
Power
Positive supply voltage pin connected to +3.3 V typical supply voltage.
18
XIN / CLKIN
Input
Crystal or Clock input. Connect to 25 MHz crystal OR 25 MHz single−ended reference clock
input.
19
XOUT
Input
Crystal input. Connect to 25 MHz crystal or float this pin while using reference clock.
20
SDATA
Input/ Output
I2C compatible data. Internal pull−up resistors
21
SCLK
Input
I2C compatible clock. Internal pull−up resistors
22
VDD
Power
23
CLK3
HCSL or LVDS
output
Noninverted clock output. (For LVDS levels see Figure 4)
24
CLK3
HCSL or LVDS
output
Inverted clock output. (For LVDS levels see Figure 4)
No Connect
Positive supply voltage pin connected to +3.3 V typical supply voltage.
Recommended Crystal Parameters
Crystal
Frequency
Load Capacitance
Shunt Capacitance, C0
Equivalent Series Resistance
Initial Accuracy at 25 °C
Temperature Stability
Aging
Fundamental AT−Cut
25 MHz
16−20 pF
7 pF Max
50 W Max
±20 ppm
±30 ppm
±20 ppm
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3
NB3N51054
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two−signal I2C serial interface is provided. All the clock
outputs can be individually enabled or disabled in a glitch free manner though this serial data interface. In addition, spread
spectrum can be enabled for −0.35% or −0.5% down spread or no spread option can be selected though this interface. The
registers associated with the serial interface initialize to their default settings upon power−up.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write and block read operations from the controller. For
block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first)
with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system
controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described
in Table 2 below.
Table 2. COMMAND CODE DEFINITION
Bit
7
(6:0)
Description
0 = Block read or Block write operation, 1= Byte read or byte write operation
Byte offset for byte read or byte write operation. For Block read or Block write operations, these bits should be ‘0000000’.
The block write and block read protocol is outlined in Table 3, while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. BLOCK READ AND BLOCK WRITE PROTOCOL
Block Write Protocol
Bit
1
2:8
Description
Block Read Protocol
Bit
Start
Slave address – 7 bits
1
2:8
Description
Start
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
28
29:36
37
38:45
Command code – 8 bit
‘00000000’ stands for block operation
11:18
Command code – 8 bit
‘00000000’ stands for block operation
Acknowledge from slave
19
Acknowledge from slave
Byte count – 8 bits
20
Repeat start
Acknowledge from slave
21:27
Slave address – 7 bits
Data byte 0 – 8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 1 – 8 bits
30:37
Acknowledge from slave
…
…………
…
Data byte (N−1) – 8 bits
47
…
Acknowledge from slave
48:55
…
Data byte N – 8 bits
56
Acknowledge from master
Acknowledge from slave
…
Data byte N from slave – 8 bits
Stop
…
Not Acknowledge from master
…
Stop
…
38
Byte count from slave – 8 bits
46
39:46
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
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NB3N51054
Table 4. BYTE READ AND BYTE WRITE PROTOCOL
Byte Write Protocol
Bit
1
2:8
Byte Read Protocol
Description
Bit
Start
1
Slave addresses – 7 bits
2:8
Description
Start
Slave addresses – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
19
20:27
Command code – 8 bit
‘10000000’ stands for byte operation,
bits[1:0] command code represents the offset
of the byte to be accessed
11:18
Command code – 8 bit
‘10000000’ stands for byte operation
bits[1:0] command code represents the offset of the byte
to be accessed
Acknowledge from slave
19
Acknowledge from slave
Data byte from master − 8 bits
20
Repeat start
28
Acknowledge from slave
29
Stop
21:27
Slave address – 7 bits
28
Read = 1
29
Acknowledge from slave
30:37
38
39
Data byte from slave – 8 bits
Not Acknowledge from master stop
CONTROL REGISTERS
Table 5. BYTE 0: CONTROL REGISTER 0
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
1
CLK3_OE
CLK3 Output Enable
0 = Disable (Hi−Z)
1 = Enable
5
1
CLK2_OE
CLK2 Output Enable
0 = Disable (Hi−Z)
1 = Enable
4
1
CLK1_OE
CLK1 Output Enable
0 = Disable (Hi−Z)
1 = Enable
3
1
CLK0_OE
CLK0 Output Enable
0 = Disable (Hi−Z)
1 = Enable
2
1
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
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NB3N51054
Table 6. BYTE 1: CONTROLLER REGISTER 1
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Table 7. BYTE 2: CONTROLLER REGISTER 2
Bit
@Pup
Name
Description
7
1
SS_SEL
Spread Spectrum Selection
0 = −0.35%, 1 = −0.5%
6
1
Reserved
Reserved
5
1
Reserved
Reserved
4
0
Reserved
Reserved
3
1
Reserved
Reserved
2
0
SS_EN
Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
1
1
Reserved
Reserved
0
0
Reserved
Reserved
Table 8. BYTE 3: CONTROLLER REGISTER 3
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
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NB3N51054
Table 9. BYTE 4: CONTROLLER REGISTER 4
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Table 10. BYTE 5: CONTROLLER REGISTER 5
Bit
@Pup
Name
Description
7
0
Reserved
Reserved
6
0
Reserved
Reserved
5
0
Reserved
Reserved
4
0
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
Reserved
Reserved
Table 11. BYTE 6: CONTROLLER REGISTER 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
Reserved
6
0
TEST_MODE
Reserved
5
0
Reserved
Reserved
4
1
Reserved
Reserved
3
0
Reserved
Reserved
2
0
Reserved
Reserved
1
1
Reserved
Reserved
0
1
Reserved
Reserved
Table 12. BYTE 7: CONTROLLER REGISTER 7
Bit
@Pup
Name
Description
7
0
Rev Code [3]
Revision Code (MSB)
6
0
Rev Code [2]
Revision Code
5
0
Rev Code [1]
Revision Code
4
1
Rev Code [0]
Revision Code (LSB)
3
1
Vendor ID [3]
Vendor ID (MSB)
2
1
Vendor ID [2]
Vendor ID
1
1
Vendor ID [1]
Vendor ID
0
1
Vendor ID [0]
Vendor ID (LSB)
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NB3N51054
Table 13. ATTRIBUTES
Characteristic
Value
Internal Pull−up Resistor (SCLK, SDATA)
50 kW
ESD Protection
Human Body Model
Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
2 kV
Level 1
UL 94 V−0 @ 0.125 in
132,000
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 14. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
VDD
Parameter
Rating
Unit
+4.6
V
−0.5 V to VDD + 0.5 V
V
Positive power supply with respect to GND
VI
Input Voltage with respect to device GND
TA
Operating Temperature Range
−40 to +85
°C
TSTG
Storage temperature
−65 to +150
°C
TSOL
Max. Soldering Temperature (10 sec)
265
°C
qJA
Thermal Resistance (Junction−to−ambient) 0 lfpm
(Note 3) 500 lfpm
65
57
°C/W
qJC
Thermal Resistance (Junction−to−case)
50
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 15. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 5%, GND = 0 V, TA = −40°C to 85°C, Note 4)
Symbol
Parameter
VDD
Power Supply Voltage
Min
Typ
Max
Unit
3.135
3.3
3.465
V
125
130
mA
50
mA
IDD
Power Supply Current, spread OFF, all outputs ON
IOFF
Power Supply Current when all outputs are set OFF through I2C, spread OFF
VIH
Input HIGH Voltage (XIN/CLKIN)
2.0
VDD + 0.3
V
VIL
Input LOW Voltage (XIN/CLKIN)
GND − 0.3
0.8
V
IIH
Input HIGH Current (SCLK/SDATA), VDD = VIN = 3.465 V
10
mA
IIL
Input LOW Current (SCLK/SDATA), VDD = 3.465 V, VIN = 0 V
VOH
Output HIGH Voltage for HCSL Output (Note 5)
660
VOL
Output LOW Voltage for HCSL Output (Note 5)
−150
Crossing Voltage Magnitude (Absolute) for HCSL Output (Notes 5, 6, 7)
250
VCROSS
DVCROSS
Change in Magnitude of VCROSS for HCSL Output (Notes 5, 6, 8)
mA
−150
850
mV
mV
550
mV
150
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with RS = 33.2 W, RL = 49.9 W, with test load capacitance of 2 pF and current biasing resistor
set at RREF = 475 W. See Figure 6. Guaranteed by characterization.
5. Measurement taken from single-ended waveform
6. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx-.
7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
8. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx-. This is maximum allowed variance in the VCROSS for
any particular system.
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NB3N51054
Table 16. AC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ± 5%, GND = 0 V, TA = −40°C to 85°C, Note 9)
Symbol
fCLKIN
Parameter
Conditions
Min
Typ
Max
Unit
Clock/ Crystal Input Frequency
25
MHz
fCLKOUT
Output Frequency
100
MHz
FNOISE
Phase Noise Performance
@ 100 Hz offset from carrier
−104
dBc/Hz
@ 1 kHz offset from carrier
−121
@ 10 kHz offset from carrier
−131
@ 100 kHz offset from carrier
−136
@ 1 MHz offset from carrier
−140
@ 10 MHz offset from carrier
−155
RMS Phase Jitter
RMS Phase Jitter, fCLKIN = 25 MHz
Crystal, fCLKOUT = 100 MHz,
Integration Range: 12 kHz − 20 MHz
0.5
ps
tJITTER
Peak Cycle−to−Cycle Jitter
Measured over 10000 cycles
20
ps
tF / tR
Rise / Fall Time
Measured differentially between
−150 mV to +150 mV
Output Rise/ Fall Time Variation
Measured Single−ended
tjit(f)
DtF / tR
fMOD
SSCRED
Spread Spectrum Modulation Frequency
Spectral Reduction, 3rd Harmonic
0.6
30
Measured with frequency spread of
−0.5%
31.5
4.0
V/ns
125
ps
33.33
kHz
−10
dB
VMAX
Absolute Maximum Voltage, measured
single ended including undershoot
VMIN
Absolute Minimum Voltage, measured
single ended including undershoot
tSKEW
Within device Output to Output Skew
All outputs
40
ps
Spread Spectrum Transition Time
Stabilization Time After Spread
Spectrum Changes
50
ms
tDC
Output Clock Duty Cycle
Measured at cross point
55
%
tPLL
PLL Lock Time
50
ms
tPU
Stabilization Time from Power−up
tSPREAD
1150
−300
VDD = 3.3 V
45
mV
mV
50
3.0
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W , RL = 49.9 W , with test load capacitance
of 2 pF and current biasing resistor set at RREF = 475 W . See Figure 6. Guaranteed by characterization.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NB3N51054
Table 17. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS
VDD = 3.3 V ± 5%, TA = −40°C to 85°C
Typ
Max
PCIe
Industry
Spec
SSOFF
10
20
86
ps
SSON
(−0.5%)
19
28
fCLKIN = 25 MHz Crystal,
fCLKOUT = 100 MHz
Input High Band:
1.5 MHz − Nyquist (clock
frequency/2)
SSOFF
1.0
1.8
3.1
ps
SSON
(−0.5%)
1.1
1.9
fCLKIN = 25 MHz Crystal,
fCLKOUT = 100 MHz
Input Low Band:
10 kHz − 1.5 MHz
SSOFF
0.1
0.15
3.0
ps
SSON
(−0.5%)
0.8
1.1
SSOFF
0.35
0.7
1.0
ps
SSON
(−0.5%)
0.55
0.8
Symbol
Parameter
Test Condition
tj (PCIe Gen 1)
Phase Jitter
Peak−to−Peak
(Notes 11 and 14)
fCLKIN = 25 MHz Crystal,
fCLKOUT = 100 MHz
Input Evaluation Band:
0 Hz − Nyquist (clock
frequency/2)
Phase Jitter RMS
(Notes 12 and 14)
tREFCLK_HF_RMS
(PCIe Gen 2)
tREFCLK_LF_RMS
(PCIe Gen 2)
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS
(Notes 12 and 14)
Phase Jitter RMS
(Notes 13 and 14)
fCLKIN = 25 MHz Crystal,
fCLKOUT = 100 MHz
Input Evaluation Band: 0 Hz
Nyquist (clock frequency/2)
Spread
Condition
Min
Unit
10. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
11. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peak−to−peak for a sample size of 106 clock periods.
12. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band)
and 3.0 ps RMS for tREFCLK_LF_RMS (Low Band).
13. RMS jitter after applying system transfer function for the common clock architecture.
14. Measurement taken from differential output on single−ended channel terminated with RS = 33.2 W , RL = 49.9 W , with test load capacitance
of 2 pF and current biasing resistor set at RREF = 475 W . See Figure 6. This parameter is guaranteed by characterization. Not tested in
production
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NB3N51054
NOISE POWEER (dBc/Hz)
PHASE NOISE
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise Plot at 100 MHz (fCLKIN = 25 MHz Crystal , fCLKOUT = 100 MHz,
RMS Phase Jitter = 424 fs for Integration Range of 12 kHz to 20 MHz, Output Termination = HCSL type)
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NB3N51054
APPLICATION INFORMATION
Crystal Input Interface
as nominal values, assuming approximately 2 pF of stray
capacitance per trace and approximately 8 pF of internal
capacitance.
CL = (C1 + Cstray + Cin) / 2; C1 = C2
The frequency accuracy and duty cycle skew can be
fine-tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency.
Figure 4 shows the NB3N51044 device crystal oscillator
interface using a typical parallel resonant crystal. The device
crystal connections should include pads for small capacitors
from X1 to ground and from X2 to ground. These capacitors,
C1 and C2, need to consider the stray capacitances of the
board and are used to match the nominally required crystal
load capacitance CL. A parallel crystal with loading
capacitance CL = 18 pF would use C1 = 26 pF and C2 = 26 pF
C1 = 26 pF
X1
Fundamental Mode
Parallel Resonant Crystal
18 pF Load
X2
C2 = 26 pF
Figure 4. Crystal Interface Loading
Power Supply Filter
decoupling capacitors as close as possible to the device to
minimize lead inductance.
In order to isolate the NB3N51044 from system power
supply, noise decoupling is required. The 10 mF and a 0.1 mF
cap from supply pins to GND decoupling capacitor has to be
connected between VDD (pins 3, 9, 11, 13 and 16) and GND
(pins 4, 10, 14, 17 and 22). It is recommended to place
Termination
The output buffer structure is shown in the Figure 5.
2.6 mA
16 mA
IREF
RREF
CLKx
CLKx
HCSL / LVDS
termination
475 W
Figure 5. Simplified Output Structure
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NB3N51054
require the 100 W near the LVDS receiver if the receiver has
internal 100 W termination. An optional series resistor RL
may be connected to reduce the overshoots in case of
impedance mismatch.
The outputs can be terminated to drive HCSL receiver
(see Figure 6) or LVDS receiver (see Figure 7). HCSL output
interface requires 49.9 W termination resistors to GND for
generating the output levels. LVDS output interface may not
HCSL INTERFACE
RL* = 33.2 W
CLK0
Zo = 50 W
RL* = 33.2 W
Zo = 50 W
CLK0
RL = 49.9 W
RL = 49.9 W
HCSL
Receiver
NB3N51054
RL* = 33.2 W
CLK1
Zo = 50 W
RL* = 33.2 W
Zo = 50 W
CLK1
IREF
RL = 49.9 W
*Optional
RL = 49.9 W
RREF = 475 W
Figure 6. Typical Termination for HCSL Output Driver and Device Evaluation
LVDS COMPATIBLE INTERFACE
CLK0
RL* = 33.2 W
Zo = 50 W
100 W
RL* = 33.2 W
100 W**
Zo = 50 W
CLK0
RL = 150 W
RL = 150 W
NB3N51054
CLK1
RL* = 33.2 W
Zo = 50 W
100 W
RL* = 33.2 W
CLK1
IREF
RREF = 475 W
LVDS
Receiver
100 W**
Zo = 50 W
*Optional
**Not required if LVDS receiver
has 100 W internal termination
RL = 150 W
RL = 150 W
LVDS Device Load
Figure 7. Typical Termination for LVDS Device Load
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13
NB3N51054
150 mV
0 mV
150 mV
tR
tF
Figure 8. HCSL Differential Measurement of tR/tF
ORDERING INFORMATION
Temperature
Package
Shipping†
NB3N51054DTG
−40°C to 85°C
TSSOP−24
(Pb−Free)
96 Units / Rail
NB3N51054DTR2G
−40°C to 85°C
TSSOP−24
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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14
NB3N51054
PACKAGE DIMENSIONS
TSSOP24 7.8x4.4, 0.65P
CASE 948H
ISSUE B
NOTE 4
B
NOTE 5
A
D
NOTE 6
NOTE 6
24
L2
13
GAUGE
PLANE
E1
L
E
C
DETAIL A
PIN 1
1
REFERENCE
12
e
24X
TOP VIEW
0.15 C B
b
0.10
C B
M
S
A
H
A1
0.10 C
24X
SIDE VIEW
S
NOTE 3
A
0.05 C
S
2X 12 TIPS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL BE 0.08 MAX AT MMC. DAMBAR
CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15
PER SIDE. DIMENSION D IS DETERMINED AT DATUM PLANE H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 PER SIDE. DIMENSION E1 IS DETERMINED
AT DATUM PLANE H.
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
C
SEATING
PLANE
DETAIL A
c
END VIEW
M
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MILLIMETERS
MIN
MAX
1.20
--0.05
0.15
0.19
0.30
0.09
0.20
7.90
7.70
6.40 BSC
4.30
4.50
0.65 BSC
0.50
0.75
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
24X
0.42
24X
1.15
6.70
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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15
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3N51054/D