NCP5252 2.0 A, 1.0 MHz Integrated Synchronous Buck Regulator with Light Load Efficiency http://onsemi.com NCP5252 is a synchronous buck regulator with integrated high-side and low-side MOSFETs. The device is capable of operating from a 5 V or 12 V supply and can output a voltage down to 0.6 V. The switching frequency is adjustable from 333 kHz up to 1.0 MHz and has the ability to provide skip mode for light load efficiency. NCP5252 protection features include Under Voltage Lock Out (UVLO), Over Voltage Protection (OVP), Cycle-by-Cycle Current Protection (OCP) and Thermal Shutdown. The part is packaged in a 3x3 mm QFN-16. Features 16 QFN16 CASE 485G N5252 ALYWG G VCC LX LX PGND A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 16 15 14 13 12 PGND 11 PGND 3 10 V5 4 9 FREQ_SET BST 2 PGOOD EN/SKIP NCP5252 5 6 7 8 AGND 1 VO VCC FB 1% Accuracy 0.6 V Reference VCC Voltage 4.5 V to 13.2 V Adjustable Output Voltage Range: 0.6 V to 5.0 V Transient Response Enhancement (TRE) Feature. Low Side Lossless Sense Current Control Input Voltage Feed Forward Control Internal Digital Soft−Start Integrated Output Discharge (Soft−Stop) Cycle−by−Cycle Current Limit Power Good Indication Overvoltage and Undervoltage Protection Thermal Shutdown Protection Power Saving Mode at Light Load Integrated Boost Diode QFN−16 (3 mm x 3 mm) These Devices are Pb−Free and are RoHS Compliant Typical Applications • • • • • • 1 1 COMP • • • • • • • • • • • • • • • • MARKING DIAGRAM QFN16 (Top View) Desktop Application System Power XDSL, Modems, DC−DC Modules Set Top Box HD Driver LED Driver, DVD Recorders ORDERING INFORMATION Device NCP5252MNTXG Package Shipping† QFN16 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 4 1 Publication Order Number: NCP5252/D NCP5252 V5 Thermal Shutdown Level Control EN / SKIP PGOOD LDO VCC UVLO Control OC monitor ENABLE FPWM SKIP BST PGOOD VREF+10% NCP5252 + PGH LX − + VREF−15% − VREF−20% + FB Control Logic, Protection, RAMP Generator, and PWM Logic UVP − − VREF COMP PGL + + VREF+15% Soft stop VO OC monitor VCC OVP − Error Amplifier OSC / DIV FREQ_SET PGND AGND Figure 1. NCP5252 Typical Block Diagram http://onsemi.com 2 NCP5252 vcc BST PGOOD EN / SKIP 4.5 TO 13.2V LX COMP VOUT FB NCP5252 VO PGND V5 FREQSET AGND GND Figure 2. NCP5252 Typical Application Circuits PIN FUNCTION DESCRIPTION Description Pin No Symbol 1 VCC Internal LDO power supply 2 BST Top MOSFET driver input supply, place a ceramic capacitor between LX and BST. 3 PGOOD Output voltage power good indication. The power good pin is an open drain indication flag. The PGOOD pin is low impedance if the output voltage is outside the comparator window and is high impedance if the output voltage is inside the comparator window. 4 EN/SKIP The enable pin is used to enable the part and also set skip mode or forced PWM. 5 COMP Output of the error amplifier 6 FB Output voltage feedback 7 VO Output voltage monitor 8 AGND 9 FREQ_SET 10 V5 11−13 PGND 14−15 LX 16 VCC 17 EPAD Analog ground Frequency selection pin, 0 V = 333k, No connect = 500 kHz, 5 V = 1.0 MHz Output to the internal power supply for the analog circuitry Ground reference and high−current return path for the bottom power MOSFET. Switch node between the top MOSFET and bottom MOSFET. High Side MOSFET input voltage connection Connect to PGND for thermal enhancement. Exposed pad is not electrically connected. http://onsemi.com 3 NCP5252 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit VCC Power Supply Voltage to AGND Rating VCC −0.3, 15 V EN / SKIP to AGND VEN −0.3, 6 V Bootstrap Supply Voltage: BST to LX VBST − VLX −0.3, 15 V LDO regulator: V5 to AGND V5 − VAGND −0.3, 6 V Input / Output Pins to AGND VIO −0.3, 6 V Switch Node to PGND VLX 15 20 (50 ns) −1 (DC) −5 (200 ns) V VPGND −0.3, 0.3 V Thermal Resistance Junction−to−Ambient (0 lfpm) RJA 90 °C/W Thermal Resistance Junction−to−Case (0 lfpm) RJC 15 °C/W PGND Operating Ambient Temperature Range TA −40 to + 85 °C Operating Junction Temperature Range TJ −40 to + 150 °C Storage Temperature Range Tstg −55 to +150 °C Power Dissipation PD 1.4 W MSL 1 − Moisture Sensitivity Level Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. VCC UNDERVOLTAGE Parameter Test Conditions Min Typ Max Unit VCC UVLO Rise Threshold 4.1 4.3 4.5 V VCC UVLO Hysteresis 300 400 500 mV http://onsemi.com 4 NCP5252 ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 13.2 V, TA = −40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit SUPPLY VOLTAGE Input Voltage POR Threshold for Internal Reset Logic VCC 4.5 VCC_POR 13.2 V 3.0 3.7 V 1.0 2.5 mA SUPPLY CURRENT VCC Quiescent Supply Current VCC Shutdown Current BST Quiescent Supply Current BST Shut Down Current ICC_FPWM EN/SKIP = 5 V, VFB = 1 V (No switching), VCC = 4.5 V to 13.2 V IVCC_SD EN/SKIP = 0 V 10 A IBST_FPWM EN/SKIP = H, VFB = 1 V, VBST = 5 V 0.3 mA IBST_SD EN/SKIP = L, VFB = 1 V, VBST = 5 V IVCC FREQ_SET = AGND. FREQ = 333 kHz V5 VCC > 6 V, IV5 = 5 mA V5 Rise Threshold V5_th+ Wake Up V5 UVLO Hysteresis V5HYS V5 Loading V5LOAD V5 Current Limit ILIMIT_V5 VCC Input Current 10 18 A mA LDO REGULATOR V5 Regulator Voltage Drop−out Voltage (VCC − V5) 4.85 5.0 5.15 4.1 4.3 4.45 V 300 400 500 mV 3.0 mA 20 VDR Io = 5 mA, TA = 25°C, VCC = 4.5 V, FB = 1V Power Good High Threshold VPGH PGOOD in from higher Vo (PGOOD goes high) Power Good High Hysteresis VPGH_HYS PGOOD high hysteresis (PGOOD goes low) Power Good Low Threshold VPGL PGOOD in from lower Vo (PGOOD goes high) Power Good Low Hysteresis VPGL_HYS PGOOD low hysteresis (PGOOD goes low) V mA 200 mV 120 % POWER GOOD Power Good High Delay Td_PGH Power Good Low Delay Td_PGL Output Overvoltage Rising Threshold OVPth+ OVPth+ = VPGH + VPGH_SYS Over voltage Fault Propagation Delay OVPTblk FB Forced 2% above trip threshold UVPth UVPth = VPGL + VPGL_HYS Output Undervoltage Trip Threshold Output Undervoltage Protection Blanking Time 100 110 5 75 85 % 95 −5 % 150 s 1.5 105 115 s 125 1.5 70 UVPTblk % 80 % s 90 8.0 % s REFERENCE OUTPUT Internal Reference Voltage VREF Output Voltage Accuracy (Note 1) Line Regulation (Note 1) 25°C −40°C to 85°C 0.594 0.591 VIN = 12 V, Io = 0 A to 2 A −1 VIN = 5 to 12 V, IOUT = 500 mA 0.6 0.6 0.606 0.609 0 +1 0.1 V % %/V OSCILLATOR Operation Frequency FSW FREQ_SET = V5 900 1000 1100 kHz FREQ_SET = NC 450 500 550 kHz FREQ_SET = AGND 300 333 366 kHz INTERNAL SOFT−START Soft−Start Time tSS Digital Soft−Start (VOUT from 10% to 90%) 1. Guaranteed by design, not tested in production. 2. Test mode disables the Ton/Toff min. http://onsemi.com 5 800 s NCP5252 ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 13.2 V, TA = −40°C to 85°C, unless other noted) Characteristics Symbol Test Conditions Min Typ Max Unit Minimum Ton Ton_min (Note 1) 40 Minimum Toff Toff_min (Note 1) 200 50 60 ns 225 250 ns 5.0 10 mV 20 ns SWITCHING MODULATOR PWM Comparator Offset (Note 1) Propagation Delay of PWM Comparator TD_PWM (Note 1) GAIN_VEA (Note 1) 80 PH_EA (Note 1) 50 VOLTAGE ERROR AMPLIFIER DC Gain Open−Loop Phase Margin Unity Gain Bandwidth BW_VEA (Note 1) 15 Slew Rate SR_VEA COMP PIN TO GND = 100 pF (Note 1) 5.0 3.3 FB Bias Current Ibias_FB Output Voltage Swing Vmax_EA Isource_EA = 2mA Vmin_EA Isink_EA = 2mA High Side Peak Current Limit (Cycle−by−Cycle) HSOC Ton Minimum > 100 ns (Notes 1 & 2) Low Side Valley Current Limit, Short−Circuit (4 s) LSOC_S Low Side Valley Current Limit (Current Limit, 16 s) 88 dB Deg 20 MHz V/s 0.1 3.5 A V 0.15 0.3 V 3.4 4.0 4.6 A (Notes 1 & 2) 3.0 3.75 4.5 A LSOC_L (Notes 1 & 2) 2.0 2.5 3.4 A Internal Main FET ON−Resistance RDS(on)_M (ILX=100mA, VBST−LX = 5 V, FB = 0, TA = 25°C) (Note 1) 150 225 m Internal Sync FET ON−Resistance RDS(on)_F (ILX = 100 mA, FB = 1 V, TA = 25°C) (Note 1) 100 150 m LX_LK VEN = 0V, LX = 0, VCC = 13.2 V +5.0 A LX = 13.2, VCC = 13.2 V −5.0 A OVERCURRENT PROTECTION LIMIT POWER OUTPUT SECTION LX Leakage Current CONTROL SECTION EN / SKIP Logic Input Voltage for Disable VEN_DISABLE Set as Disable VEN_HYS Hysteresis EN / SKIP Logic Input Voltage for FPWM VEN_FPWM Set as FCCM mode 1.7 1.95 2.10 V EN / SKIP Logic Input Voltage for Skip Mode VEN_SKIP Set as SKIP Mode 2.25 2.45 2.65 V EN / SKIP Source Current EN / SKIP Sink Current VEN_HYS Hysteresis IEN_SOURCE VEN_SKIP = 0 V IEN_SINK EN_SKIP Logic Input Delay 0.7 1.0 1.3 300 250 mV 0.1 VEN_SKIP = 5 V V mV 0.1 A A Change mode delay active 3 Clk 75 PGOOD Pin ON Resistance PGOOD_R I_PGOOD = 5 mA PGOOD Pin OFF Current PGOOD_LK PGOOD = 5 V Rdischarge EN = 0 V 20 Tsd (Note 1) 150 °C Tsdhys (Note 1) 25 °C 1 A 35 OUTPUT DISCHARGE MODE Output Discharge On−Resistance THERMAL SHUTDOWN Thermal Shutdown Thermal Shutdown Hysteresis 1. Guaranteed by design, not tested in production. 2. Test mode disables the Ton/Toff min. http://onsemi.com 6 NCP5252 175 4.375 VTHUVLO, UVLO THRESHOLD (V) RDS(on), SWITCH ON RESISTANCE (m) TYPICAL OPERATING CHARACTERISTICS 150 125 100 75 50 25 −50 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 4.350 4.325 4.300 4.275 4.250 4.225 −50 100 Figure 3. Sync FET ON Resistance vs. Temperature VFB, FEEDBACK VOLTAGE (mV) fOSC, SWITCHING FREQUENCY (MHz) 603 1050 1025 1000 975 950 ICC, QUIESCENT CURRENT into VCC (A) 1.40 1.35 1.30 1.25 1.20 1.15 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 602 601 600 599 598 597 −50 100 VICC_SD, SHUTDOWN QUIESCENT CURRENT (A) −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 5. Switching Frequency vs. Temperature 1.10 −50 100 Figure 4. UVLO Threshold vs. Temperature 1075 925 −50 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 6. Feedback Input Threshold vs. Temperature 4.75 4.50 4.25 4.00 3.75 3.50 3.25 −50 Figure 7. Quiescent Current into VCC vs. Temperature −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) Figure 8. Shutdown Quiescent Current vs. Temperature http://onsemi.com 7 100 100 NCP5252 0.75 100 90 0.50 OUTPUT EFFICIENCY (%) VOUT, OUTPUT VOLTAGE CHANGE (%) TYPICAL OPERATING CHARACTERISTICS 0.25 0.00 −0.25 VIN = 12 V, VOUT = 3.3 V, L = 5 H, Freq = 500 kHz −0.50 −0.75 0.01 0.1 1 IOUT, OUTPUT CURRENT (A) 80 70 60 50 40 30 20 10 0 0.01 10 0.75 10 100 90 0.50 0.25 0.00 −0.25 VIN = 5 V, VOUT = 3.3 V, L = 5 H, Freq = 500 kHz −0.50 −0.75 0.01 0.1 1 IOUT, OUTPUT CURRENT (A) 80 70 60 50 40 30 20 10 0 0.01 10 Figure 11. Output Voltage Change vs. Output Current VIN = 5 V, VOUT = 3.3 V, L = 5 H, Freq = 500 kHz 0.1 1 IOUT, OUTPUT CURRENT (A) 10 Figure 12. Efficiency vs. Output Current 0.75 100 90 0.50 OUTPUT EFFICIENCY (%) VOUT, OUTPUT VOLTAGE CHANGE (%) 0.1 1 IOUT, OUTPUT CURRENT (A) Figure 10. Efficiency vs. Output Current OUTPUT EFFICIENCY (%) VOUT, OUTPUT VOLTAGE CHANGE (%) Figure 9. Output Voltage Change vs. Output Current VIN = 12 V, VOUT = 3.3 V, L = 5 H, Freq = 500 kHz 0.25 0.00 −0.25 VIN = 5 V, VOUT = 1.2 V, L = 5 H, Freq = 500 kHz −0.50 −0.75 0.01 0.1 1 IOUT, OUTPUT CURRENT (A) 80 70 60 50 40 30 20 10 0 0.01 10 Figure 13. Output Voltage Change vs. Output Current VIN = 12 V, VOUT = 1.2 V, L = 5 H, Freq = 500 kHz 0.1 1 IOUT, OUTPUT CURRENT (A) Figure 14. Efficiency vs. Output Current http://onsemi.com 8 10 NCP5252 (Vin = 12 V, ILOAD = 10 mA, L = 5 H,COUT = 100 F) Upper trace: Input voltage, 5 V/div Lower trace: Output voltage, 1 V/div Time base: 500 s/div (Vin = 12 V, ILOAD = 10 mA, L = 5 H,COUT = 100 F) Upper trace: Input voltage, 5 V/div Lower trace: Output voltage, 1 V/div Time base: 500 s/div Figure 15. Soft−Start Waveforms for Vout = 3.3 V Figure 16. Soft−Start Waveforms for Vout = 1.2 V http://onsemi.com 9 NCP5252 (Vin = 12 V, ILOAD = 1 A, L = 5 H, COUT = 100 F) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 1 A/div Time base: 2 s/div (Vin = 12 V, ILOAD = 200 mA, L = 5 H, COUT = 100 F) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 1 A/div Time base: 2 s/div Figure 17. DCM Switching Waveforms for Vout = 1.2 V Figure 18. CCM Switching Waveforms for Vout = 1.2 V (Vin = 12 V, ILOAD = 500 mA, L = 5 H, COUT = 100 F) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 500 mA/div Time base: 2 s/div (Vin = 12 V, ILOAD = 200 mA, L = 5 H, COUT = 100 F) Upper trace: Output ripple voltage, 50 mV/div Middle trace: Lx pin switching waveform, 5 V/div Lower trace: Inductor current waveforms, 500 mA/div Time base: 2 s/div Figure 19. DCM Switching Waveforms for Vout = 3.3 V Figure 20. CCM Switching Waveforms for Vout = 3.3 V http://onsemi.com 10 NCP5252 (Vin = 12 V, L = 5 H, COUT = 100 F, Freq = 500 kHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 s/div (Vin = 5 V, L = 5 H, COUT = 100 F, Freq = 1 MHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 s/div Figure 21. Load Transient Response for Vout = 1.2 V Figure 22. Load Transient Response for Vout = 1.2 V (Vin = 12 V, L = 5 H, COUT = 100 F, Freq = 1 MHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 s/div (Vin = 5 V, L = 5 H, COUT = 100 F, Freq = 333 kHz) Upper trace: Output dynamic voltage, 100 mV/div Lower trace: Output current, 1 A/div Time base : 50 s/div Figure 23. Load Transient Response for Vout = 3.3 V Figure 24. Load Transient Response for Vout = 3.3 V http://onsemi.com 11 NCP5252 DETAILED OPERATING DESCRIPTION General crosses zero from positive to negative, the low−side MOSFET is shut off so that current is not pulled out of the output capacitor. A high−side MOSFET turn on is not initiated until the COMP voltage exceeds the bottom of the PWM ramp. The NCP5252 is a PWM regulator intended for DC−DC conversion from 5 V & 12 V buses and supplies up to a 2 A load. The NCP5252 is a step down synchronous−rectifier buck topology regulator with integrated high−side and a low−side NMOS switches. The output voltage of the converter can be precisely regulated down to 600 mV ±1.0% when the VFB pin is tied to VOUT. The switching frequency can be adjusted to 333 kHz, 500 kHz, or 1 MHz. A skip mode can be enabled to provide light load efficiency. The NCP5252 includes the following features: power good monitor, internal soft−start, cycle−by−cycle current limit, short circuit protection, output undervoltage/ overvoltage protection, and thermal shutdown. Transient Response Enhancement (TRE) To improve transient response in CCM, a transient response enhancement circuitry is implemented inside the NCP5252. In CCM operation, the controller continuously monitors the COMP pin voltage of the error amplifier and detects load transient events. The functional block diagram of TRE is shown as follows: Control Logic COMP During start−up the internal LDO is activated and power−on reset occurs which resets the logic and all protection faults. The device will begin its start up sequence and the functionality will be determined by the voltage at the EN/SKIP pin. When voltage of EN/SKIP is below VEN_DISABLE, the converter will shut down. If the voltage of EN/SKIP is set between VEN_FPWM and VEN_SKIP, the device will be in PWM mode of operation. When the voltage level of EN/SKIP is above VEN_SKIP, the device will operate in PFM power saving mode. Once VREF reaches its regulation voltage, an internal signal will wake up the output undervoltage supply monitor which will assert a “GOOD” condition. In addition, the NCP5252 continuously monitors the VCC level with an undervoltage lockout (UVLO) function. + TRE R C Internal TRE_TH Figure 25. Block Diagram of TRE Circuit If a large transient occurs, the COMP signal will exceed the comparator threshold indicating that a transient has occurred and action is required. When the comparator trips an extra high−side pulse is generated and the converter appears to run at a higher frequency. Once the transient has passed, the converter returns to normal operation and normal switching frequency. Voltage Feed Forward Forced PWM Operation (FPWM Mode) To place the device into force PWM mode, the EN/SKIP pin voltage should be set between VEN_FPWM and VEN_SKIP thresholds. During the soft−start operation, the NCP5252 will automatically run as FPWM mode until the output voltage is higher than the internal soft−start ramp. In FPWM mode in each switching cycle, the high−side MOSFET turns on for a time period defined by the ratio of input voltage to output voltage known as duty ratio. After a short period of time following high−side MOSFET turn off, the low−side MOSFET turns on and remains on for the remainder of the switching cycle. At currents below the critical conduction point, the low−side MOSFET will sync current out of the output capacitor, reducing overall converter efficiency at light loads. The NCP5252 has a voltage feed forward derived ramp. Voltage feed−forward is employed to ease loop compensation for wide−input−range designs and provide better line transient response. The ramp generator provides voltage feed−forward control by varying the PWM ramp slope with line voltage. One important thing to note is that since the slope changes with the input voltage, the ramp height will also change, resulting in an almost constant gain over input voltages. Varying the PWM ramp directly with line voltage provides excellent response to line variations, because the PWM is not required to wait for loop delays before changing the duty cycle. The peak to peak ramp voltage can be calculated using the following equation: VRAMP_PP = 0.25 VIN Pulse Skipping Operation (Skip Mode/PFM) Overcurrent Protection (OCP) The device operates in skip mode if the EN/SKIP pin voltage is greater than 2.9 V. Skip mode can reduce the switching loss in light load conditions. When the converter inductor current is greater than the critical conduction point, the converter will run in continuous−conduction−mode (CCM) which behaves exactly the same as FPWM mode. When the inductor current The NCP5252 will protect the system if an overcurrent event occurs. The regulator will continuously monitor the output current through the internal MOSFETs. If the high−side MOSFET current exceeds the internal current limit threshold, it will be turned off. If a repetitive overcurrent event occurs, both MOSFETs will be turned off and the device will hold for 3 normal soft−start periods http://onsemi.com 12 NCP5252 voltage for 3 soft−start periods. Once the 3 soft−start periods have ended, the regulator will go through a normal soft−start cycle. before re−starting. A discharge resistor is turned on to discharge Vo before re−starting. Overvoltage Protection (OVP) When the SMPS output voltage is above 115% (typ) of the preset nominal regulation voltage for over 1.5 s, an OV fault is set. The high−side MOSFET will turn off and the low−side MOSFET will be turned on to discharge the output until Vo drops below the default threshold (105%). Once the output voltage is below the overvoltage window, the device will recover to normal operation. LDO Regulator The internal LDO regulator (V5) can provide up to 20 mA (typ) for internal analog circuitry. Connect a capacitor to pin V5 for proper regulation. Undervoltage Logout The UVLO circuit will activate when the VCC voltage is below 3.5 V (typ). At that time both MOSFETs will turn off. When the VCC voltage is higher than 4.0 V, the UVLO flag will be cleared and the soft−start function will activate. Undervoltage Protection (UVP) A UVP circuit monitors the output voltage to detect an undervoltage event. The undervoltage limit is 80% (typ) of the nominal output voltage level. If the output voltage is below this threshold for over 4 switching cycles, a UVP fault is set. The high−side and low−side MOSFETs are turned off and a discharge resistor is turned on to discharge the output Thermal Shutdown The IC will shutdown if the die temperature exceeds 150°C. The IC will restart with soft−start operation only after the junction temperature drops below 125°C. 4.5 TO 13.2V COMP VCC BST PGOOD R1 L1 VOUT LX FB NCP5252 VO R2 PGND C4 C3 V5 AGND R4 FREQSET C2 EN / SKIP C1 R3 GND Figure 26. Typical Application Circuit http://onsemi.com 13 NCP5252 Table 1. Typical Design Value For Vcc = 12 V Application Vin (V) Vout (V) Fsw (kHz) C2 (nF) R1 (kW) R4 (W) C3 (pF) L1 (mH) (kW) R3 (kW) C4 (mF) (pF) C1 R2 12 5 Any 10 2.0 23 10 1.4 200 800 Ceramic 22 F x 2 5.0 12 3.3 Any 10 2.0 23 10 2.2 200 800 Ceramic 22 F x 2 5.0 12 1.2 Any 10 2.0 23 10 10 200 800 Ceramic 22 F x 2 5.0 12 5 Any 10 2.0 54 10 1.4 200 800 SP 100 F / 12 m 5.0 12 3.3 Any 10 2.0 54 10 2.2 200 800 SP 100 F / 12 m 5.0 12 1.2 Any 10 2.0 54 10 10 200 800 SP 100 F / 12 m 5.0 12 5 Any 10 1.0 30 10 1.4 NC NC Electrolytic 470 F/160 m 5.0 12 3.3 Any 10 1.0 30 10 2.2 NC NC Electrolytic 470 F/160 m 5.0 12 1.2 Any 10 1.0 30 10 10 NC NC Electrolytic 470 F/160 m 5.0 C1 R2 For Vcc = 5 V Application Vin (V) Vout (V) Fsw (kHz) C2 (nF) R1 (kW) R4 (W) C3 (pF) L1 (mH) (kW) R3 (kW) C4 (mF) (pF) 5 3.3 Any 10 2.0 56 10 2.2 200 800 Ceramic 22 F x 2, ESR = 4 m 5.0 5 1.2 Any 10 2.0 56 10 10 200 800 Ceramic 22 F x 2, ESR = 4 m 5.0 5 3.3 Any 10 2.0 100 10 2.2 200 800 SP 100 F / ESR = 12 m 5.0 5 1.2 Any 10 2.0 100 10 10 200 800 SP 100 F / ESR = 12 m 5.0 5 3.3 Any 10 1.0 60 10 2.2 NC NC Electrolytic 470 F/ESR = 160 m 5.0 5 1.2 Any 10 1.0 60 10 10 NC NC Electrolytic 470 F/ESR = 160 m 5.0 http://onsemi.com 14 NCP5252 TIMING DIAGRAMS Timing 1 (SMPS Enable and Disable by EN_SKIP) VIN EN_SKIP V5 Discharged by Ridscharge + Ext. Load SMPS VOUT Discharged by Ext. Load Only PGOOD Logic Block Ready when VCC > PORth PGOOD Asserts When VOUT Within Window Device Ready when VCC > VINth SMPS Soft Start Begins After Detection Soft Stop Begins When EN_SKIP=L Note: PORth = ~2.5V Figure 27. Timing 2 (SMPS OVP & UVP Operation) VCC 115% SMPS 110% 110% 105% VOUT 85% 80% SS TG BG 3 soft start time Hiccup PGOOD Outside PGOOD window Hit OVP threshold Outside PGOOD window Inside PGOOD window Figure 28. http://onsemi.com 15 Soft Stop continue discharge Hiccup delay Inside PGOOD window Soft start again NCP5252 PACKAGE DIMENSIONS QFN16, 3x3, 0.5P CASE 485G ISSUE F D PIN 1 LOCATION 2X 0.10 C 2X A B ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉÉ ÉÉÉ TOP VIEW (A3) DETAIL B 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L1 EXPOSED Cu 0.10 C L L ÉÉ ÉÉ ÇÇ A3 A1 DETAIL B A 0.05 C MOLD CMPD ALTERNATE CONSTRUCTIONS NOTE 4 A1 SIDE VIEW C SEATING PLANE DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.18 0.24 0.30 3.00 BSC 1.65 1.75 1.85 3.00 BSC 1.65 1.75 1.85 0.50 BSC 0.18 TYP 0.30 0.40 0.50 0.00 0.08 0.15 RECOMMENDED SOLDERING FOOTPRINT* 0.10 C A B 16X L DETAIL A D2 8 4 16X 16X 0.58 PACKAGE OUTLINE 1 9 2X E2 K 2X 1.84 3.30 1 16X 16 e e/2 BOTTOM VIEW 16X 0.30 b 0.50 PITCH 0.10 C A B 0.05 C NOTE 3 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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