NCP81045 D

NCP81045
Product Preview
Single Synchronous
Step-Down Controller
The NCP81045 is a synchronous stepdown controller for high
performance systems battery−power systems. The NCP81045
includes a high efficiency PWM controller. A pin is provided to allow
two devices in interleaved operation. An internal power good voltage
monitor tracks the SMPS output. NCP81045 also features soft−start
sequence, UVLO for VCC and switcher, overvoltage protection,
overcurrent protection, undervoltage protection and thermal
shutdown. The IC is packaged in QFN16.
NCP81045
ALYWG
G
QFN16
CASE 485AP
1
NCP81045
A
L
Y
W
G
Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
VIN
1
VCC
2
SWM
DH
BST
(Note: Microdot may be in either location)
16
15
14
13
12
VCCP
11
DL/TRESET
NCP81045
10
PGND
EN
4
9
CS+
Typical Applications
• Notebook Application
• System Power
5
6
7
8
CS−/Vo
3
IDRP/OCP
SYN
FB
0.8% accuracy 0.8 V Reference
4.5 V to 27 V Battery/Adaptor Voltage Range
Adjustable Output Voltage Range: 0.8 V to 3.3 V
Synchronization Interleaving between Two NCP81045s
Skip Mode for Power Saving Operation at Light Load
Lossless Inductor Current Sensing
Programmable Transient−Response−Enhancement (TRE) Control
Programmable Adaptive Voltage Positioning (AVP)
Input Supply Feedforward Control
Internal Soft−Start
Integrated Output Discharge (Soft−Stop)
Build−in Adaptive Gate Drivers
PGOOD Indication
Overvoltage, Undervoltage and Overcurrent Protections
Thermal Shutdown
QFN16 Package
These Devices are Pb−Free and are RoHS Compliant
16
1
PGOOD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAM
COMP
Features
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QFN16
(Top View)
ORDERING INFORMATION
Device
NCP81045MNTXG
Package
Shipping†
QFN16 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2012
October, 2012 − Rev. P0
1
Publication Order Number:
NCP81045/D
DH
BST
17
SWN
TPAD
PGOOD
NCP81045
16
15
14
13
IDRP/OCP
Detection
AGND
OVP
UVP
7
8
CS−/Vo
6
IDRP/OCP
5
FB
Error
Amplifier
Figure 1. Detail Block Diagram
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2
VCCP
11
DL/TRESET
10
PGND
9
CS+
−
VREF+15%
DISCH
+
−
+
VREF−20%
−
+
−
VREF−10%
Level
Control
VREF
PGL
PGH
+
VREF+10%
4
Low Side
Driver
CDIFF
COMP
EN
ENABLE
MASTER
SLAVE
OC & TRE Detection
3
NCP81045
Control Logic, Protection,
RAMP Generator and PWM Logic
12
+
SYN
UVLO
Control
−
2
AVP
Control
−
VCC
VCC
OSC
Over Current
Detector
UVLO
Control
1
+
VIN
Thermal
Shutdown
High Side
Driver
PGOOD
Current
Sense
Amplifier
NCP81045
VIN
5V
16
VIN
VCC
BST
DH
14
VOUT
13
12
2
11
NCP81045
AGND
3
10
5
6
7
8
IDRP/OCP
CS−/Vo
9
FB
4
COMP
EN_SKIP
15
1
SYN
EN_SKIP
SWN
PGOOD
PGOOD
VCCP
DL/TRESET
PGND
CS+
Figure 2. Typical Application Circuit (Single Device Operation)
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3
GND
NCP81045
VIN
5V
16
BST
1
12
NCP81045
2
11
AGND
3
10
Master
COMP
5
9
6
7
CS−/Vo
4
BST
EN
VOUT1
13
IDRP/OCP
SYN
EN=VEN_Master
14
DH
VCC
15
FB
VIN
DH
SWN
PGOOD
PGOOD1
VCCP
GND1
DL/TRESET
PGND
CS+
8
SWN
PGOOD
PGOOD2
16
EN
13
1
12
NCP81045
2
11
AGND
3
10
Slave
4
COMP
5
6
7
9
VCCP
DL/TRESET
PGND
CS+
8
CS−/Vo
SYN
EN=VEN_Slave
14
IDRP/OCP
VCC
15
FB
VIN
VOUT2
Figure 3. Typical Application Circuit (Dual Device Operation)
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4
GND2
NCP81045
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
1
VIN
Input voltage used for feed forward in switcher operation.
Description
2
VCC
Supply for analog circuit
3
SYN
Synchronization interleaving use.
4
EN
5
COMP
6
FB
7
IDRP/OCP
Current limit programmable and setting for AVP.
8
CS−/Vo
Inductor current differential sense inverting input.
9
CS+
10
PGND
11
DL/TRESET
12
VCCP
13
BST
Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
14
DH
Gate driver output of top N−channel MOSFET.
15
SWN
16
PGOOD
17
TPAD
This pin serves as two functions. Enable: Logic control for enabling the switcher. MASTER/SLAVE: To
program the device as MASTER or SLAVE mode at dual device operation.
Output of the error amplifier.
Output voltage feed back.
Inductor current differential sense non−inverting input.
Ground reference and high−current return path for the bottom gate driver.
Gate driver output of bottom N−channel MOSFET. It also has the function for TRE threshold setting.
Supply for bottom gate driver.
Switch node between top MOSFET and bottom MOSFET.
Power good indicator of the output voltage. High impendence if power good (in regulation). Low impendence if power not good.
Copper pad on bottom of IC used for heat sinking. This pin should be connected to the analog ground
plane under the IC.
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC Power Supply Voltage to AGND
Rating
VCC
−0.3, 6.0
V
VIN Supply to AGND
VIN
−0.3, 30
V
VBST−VSWN,
VDH−VSWN,
VCCP−VPGND,
VDL−VPGND,
−0.3, 6.0
V
High−side Gate Drive Supply: BST to SWN
High−side Gate Drive Voltage: DH to SWN
Low−side Gate Drive Supply: VCCP to PGND
Low−side Gate Drive Voltage: DL to PGND
Input / Output Pins to AGND
VIO
−0.3, 6.0
V
VSWN
−5 V (< 100 ns)
30 V
V
High−Side Gate Drive/Low−Side Gate Drive Outputs
DH, DL
−3(DC)
V
PGND
VPGND
−0.3, 0.3
Switch Node SWN−PGND
Thermal Characteristics
Thermal Resistance Junction−to−Ambient (QFN16 Package)
V
°C/W
RqJA
48
Operating Junction Temperature Range (Note 1)
TJ
−40 to + 150
°C
Operating Ambient Temperature Range
TA
− 40 to + 85
°C
Storage Temperature Range
Tstg
− 55 to +150
°C
Moisture Sensitivity Level
MSL
1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Internally limited by thermal shutdown, 150°C min.
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NCP81045
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Input Voltage
VIN
4.5
−
27
V
VCC Operating Voltage
VCC
4.5
5.0
5.5
V
SUPPLY CURRENT
VCC Quiescent Supply Current in
Master operation
IVCC_Master
EN = VEN_Master, VFB forced above
regulation point. DH, DL are open
1.5
2.5
mA
VCC Quiescent Supply Current in
Slave Operation
IVCC_Slave
EN = VEN_Slave, VFB forced above
regulation point, DH, DL are open
1.5
2.5
mA
IVCC_SD
EN = VEN_Disable, VCC = 5 V, True
Shutdown
1
mA
BST Quiescent Supply Current in
Master Operation
IBST_Master
EN = VEN_Master, VFB forced above
regulation point, DH and DL are open,
No boost trap diode
0.3
mA
BST Quiescent Supply Current in
Slave Operation
IBST_Slave
EN = VEN_Slave, VFB forced above
regulation point, DH and DL are open
No boost trap diode
0.3
mA
IBST_SD
EN = 0 V
1
mA
IVCCP_SD
EN = 0 V, VCCP = 5 V
1
mA
IVIN
EN = 5V, VIN = 27 V
35
mA
IVIN_SD
EN = 0 V, VIN = 27 V
1
mA
Rising VCC Threshold
VCCth+
Wake Up
VCC UVLO Hysteresis
VCCHYS
VCC Shutdown Current
BST Shutdown Current
VCCP Shutdown Current
VIN Supply Current
VIN Shutdown Current
VOLTAGE−MONITOR
4.05
4.25
4.48
V
200
275
400
mV
Rising VIN Threshold
VINth+
Wake Up, Design Spec. (Note 2)
3.4
3.8
4.2
V
VIN UVLO Hysteresis
VINHYS
(Note 2)
200
500
800
mV
Power Good High Threshold
VPGH
PGOOD in from higher Vo (PGOOD
goes high)
120
125
130
%
Power Good High Hysteresis
VPGH_HYS
PGOOD high hysteresis (PGOOD
goes low)
Power Good Low Threshold
VPGL
PGOOD in from lower Vo (PGOOD
goes high)
Power Good Low Hysteresis
VPGL_HYS
PGOOD low hysteresis (PGOOD goes
low)
−5
%
Power Good High Delay
Td_PGH
After Tss, (Note 2)
1.25
ms
Power Good Low Delay
Td_PGL
(Note 2)
1.5
Output Overvoltage Rising Threshold
OVPth+
With respect to Error Comparator
Threshold of 0.8 V
Overvoltage Fault Propagation Delay
OVPTblk
FB forced 2% above trip threshold
(Note 2)
Output Undervoltage Trip Threshold
UVPth
With respect to Error Comparator
Threshold of 0.8 V
75
80
85
%
UVPTblk
(Note 2)
−
8/fsw
−
s
0.7936
0.8
0.8064
V
Output Undervoltage Protection
Blanking Time
5
80
125
85
130
%
90
%
ms
135
1.5
%
ms
REFERENCE OUTPUT
Internal Reference Voltage
Vref
2. Guaranteed by design, not tested in production.
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6
NCP81045
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
270
300
330
kHz
1.92
2.21
ms
1.47
ms
1.3
ms
OSCILLATOR
Operation Frequency
FSW
OVERCURRENT THRESHOLD
Total Detection Time
OCSET Detection Time
TDETECT
Period of FB shorts to ground before
SS
1.26
T_OCDET
(Note 2)
1.09
INTERNAL SOFT−START
Soft−Start Time
TSS
0.9
1.1
VOLTAGE ERROR AMPLIFIER
DC Gain
GAIN_VEA
(Note 2)
88
dB
Unity Gain Bandwidth
BW_VEA
(Note 2)
15
MHz
Slew Rate
SR_VEA
COMP PIN TO GND = 100 pF
(Note 2)
2.5
V/ms
FB Bias Current
Ibias_FB
Output Voltage Swing
Vmax_EA
Isource_EA = 2 mA
Vmin_EA
Isink_EA = 2 mA
0.1
3.3
3.5
0.15
mA
V
0.3
V
3.5
V
DIFFERENTIAL CURRENT SENSE AMPLIFIER
CS+ and CS− Common−mode Input
Signal Range
VCSCOM_MAX
Refer to AGND
Input Bias Current
CS_IIB
−100
100
nA
Input Signal Range
CS_range
−70
70
mV
Offset Current at IDRP
IDRP_offset
(CS+) − (CS−) = 0 V
−1.0
[(CS+)−(CS−)] to IDRP Gain
IDRP_GAIN
(IDRP/((CS+)
− (CS−)))
(CS+) − (CS−) = 10 mV, V(IDRP) =
0.8 V
0.475
BW_CS
At −3dB to DC Gain (Note 2)
Maximum IDRP Output Voltage
IDRP_Max
(CS+) − (CS−) = 70 mV, Isource drops
to 95% of the value when V(IDRP) =
0.8 V
Minimum IDRP Output Voltage
IDRP_Min
Current−Sense Bandwidth
IDRP Output current
0.525
0.425
1.0
mA
0.575
mA/mV
0.625
mA/mV
20
MHz
2.5
V
0
I_IDRP
−1.0
V
35
mA
26.4
mA
OVERCURRENT PROTECTION SETTING
Overcurrent Threshold (OCTH)
Detection Current
I_OCSET
Sourced from OCP before soft−start,
Rocset = 16.7 kW is connected from
OCP to AGND or FB
Ratio of OC Threshold over OCSET
Votlage
K_OCSET
V((CS+) − (CS−)) / V_OCSET
(Note 2)
OCSET Voltage for Default Fixed OC
Threshold
VOCSET_DFT
Rocset v 2 kW is connected from
OCP to AGND or FB
OCSET Voltage for Adjustable OC
Threshold
VOCSET_ADJ
Rocset = 8.3 ~ 25 kW is connected
from OCP to AGND or FB
200
OCSET Voltage for OC Disable
VOCSET_DIS
Rocset w 35 kW is connected from
OCP to AGND or FB
720
Default Fixed OC Threshold
V_OCTH_DFT
(CS+) – (CS−), Pin OCP is shorted to
AGND or FB
35
2. Guaranteed by design, not tested in production.
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7
21.6
24
0.1
−
100
mV
600
mV
mV
40
45
mV
NCP81045
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
V_OCTH
((CS+)−(CS−))
(CS+) – (CS−),
During OC threshold, set a voltage at
pin OCP
15
20
25
mV
52
60
68
DH Pull−HIGH Resistance
RH_DH
200 mA Source current
1
W
DH Pull−LOW Resistance
RL_DH
200 mA Sink current
1
W
DL Pull−HIGH Resistance
RH_DL
200 mA Source current
1
W
DL Pull−LOW Resistance
RL_DL
200 mA Sink current
0.5
W
Isource_DH
(Note 2)
2.5
A
Isink_DH
(Note 2)
2.5
A
Isource_DL
(Note 2)
2.5
A
Isink_DL
(Note 2)
5
A
TD_LH
DL−off to DH−on (Note 2)
20
ns
TD_HL
DH−off to DL−on (Note 2)
20
ns
Negative Current Detection Threshold
NCD_TH
SWN − PGND, at EN = 5 V
−1
SWN source leakage
ISWN_SD
EN = 0 V, SWN = 0 V
R_DH_SWN
(Note 2)
VEN_Disable
Set as Disable
0.7
1.0
1.3
V
Hysteresis
150
200
250
mV
OVERCURRENT PROTECTION SETTING
Adjustable OC Threshold
GATE DRIVERS
DH Source Current
DH Sink Current
DL Source Current
DL Sink Current
Dead Time
Internal Resistor from DH to SWN
mV
1
100
mA
kW
CONTROL SECTION
EN Logic Input Voltage for Disable
EN Logic Input Voltage for MASTER
Mode
VEN_Master
Set as Master Mode
1.7
1.95
2.25
V
EN Logic Input Voltage for SLAVE
Mode
VEN_Slave
Set as Slave Mode
2.4
2.65
2.9
V
Hysteresis
100
175
250
mV
IEN_SOURCE
VEN = 0 V
0.1
mA
EN Sink Current
IEN_SINK
VEN = 5 V
0.1
mA
PGOOD Pin ON Resistance
PGOOD_R
I_PGOOD = 5 mA
PGOOD Pin OFF Current
PGOOD_LK
EN Source Current
100
W
1
mA
1
uA
SYNC CONTROL
SYNC pin leakage
SYNC frequency
ISYNC_LK
Set as Slave Mode, SYNC = 5 V
F_SYNC
(Note 2)
1.2
MHz
PW_SYNC
(Note 2)
416
ns
Clock Level Low
V_CLKL
(Note 2)
0
V
Clock Level High
V_CLKH
(Note 2)
5
V
SYNC_CL
Set as Master Mode, load capacitor
between SYNC and GND (Note 2)
20
pF
ISYNC
SYNC shorts to ground
20
mApp
Output Discharge On−Resistance
Rdischarge
EN = 0 V
20
35
W
Threshold for Discharge Off
Vth_DisOff
0.3
0.4
V
Pulse Width
SYNC Driving Capability
SYNC Source Current
OUTPUT DISCHARGE MODE
0.2
2. Guaranteed by design, not tested in production.
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8
NCP81045
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VCC = VCCP = 5 V, TA =−40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
I_TRESET
Sourced from DL in the short period
before soft−start. (Rtre = 47 kW is
connected from DL to GND
7.2
8
8.8
mA
VDL_TRE_1
(Default)
Internal TRE_TH is set to 300 mV
500
600
700
mV
VDL_TRE_2
Internal TRE_TH is set to 500 mV
300
450
VDL_TRE_3
TRE is Disabled
0
250
TRE Comparator Offset
TRE_OS
(Note 2)
10
mV
Propagation Delay of TRE
Comparator
TD_PWM
(Note 2)
20
ns
Tsd
(Note 2)
150
°C
Tsdhys
(Note 2)
25
°C
TRE SETTING
TRE Threshold Detection Current
Detection Voltage for TRE Threshold
Selection
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
2. Guaranteed by design, not tested in production.
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9
NCP81045
TYPICAL OPERATING CHARACTERISTICS
0.83
VCC PIN SHUTDOWN CURRENT (nA)
200
VFB Vref VOLTAGE (V)
0.82
0.81
0.80
0.79
0.78
−15
10
35
60
85
100
50
0
−50
−100
−40
−15
10
35
60
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 4. Vref Voltage vs Ambient Temperature
Figure 5. VCC Shutdown Current vs Ambient
Temperature
0.80
310
0.70
IDRP_Gain (mA/mV)
315
305
300
295
290
85
0.60
0.50
0.40
0.30
285
−40
−15
10
35
60
0.20
−40
85
10
35
60
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 7. IDRP Gain vs Ambient Temperature
40
30
20
10
0
−10
−20
−40
−15
Figure 6. Switching Frequency vs Ambient
Temperature
DEFAULT FIX OC THRESHOLD (mV)
BST PIN SHUTDOWN CURRENT (nA)
FSW SWITCHING FREQUENCY (kHz)
0.77
−40
150
−15
10
35
60
AMBIENT TEMPERATURE (°C)
43
42
41
40
39
38
37
−40
85
Figure 8. BST Shutdown Current vs Ambient
Temperature
85
−15
10
35
60
AMBIENT TEMPERATURE (°C)
85
Figure 9. Default Fix OC Threshold vs Ambient
Temperature
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NCP81045
TYPICAL OPERATING CHARACTERISTICS
Top to Bottom: EN, SWN, Vo, PGOOD
Top to Bottom: EN, SWN, Vo, PGOOD
Figure 10. Powerup Sequence
Figure 11. Powerdown Sequence
Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master,
Sync_clk
Top to Bottom: SWN_Slave, Vo_Slave, SWN_Master,
Sync_clk
Figure 12. From Unsync to Sync
Figure 13. From Sync to Unsync
Top to Bottom: SWN, Vo, Io
Figure 14. Typical Transient
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NCP81045
DETAILED OPERATING DESCRIPTION
General
The NCP81045 synchronous stepdown power controller
contains a PWM controller for wide battery/adaptor voltage
range applications
The NCP81045 includes power good voltage monitor,
soft−start, overcurrent protection, undervoltage protection,
overvoltage protection and thermal shutdown. The
NCP81045 features power saving function which can
increase the efficiency at light load. It is ideal for battery
operated systems. The IC is packaged in QFN16.
Control Logic
The internal control logic is powered by VCC. The device
is controlled by an EN pin. The EN pin serves two functions.
When voltage of EN is below VEN_Disable, it shuts down
the device. When the voltage of EN is at the level of
VEN_Master, the device is operating as Master mode. When
voltage level of EN is at VEN_Slave, the device is operating
as Slave mode. It should be noted that no matter the device
is operating either at Master or Slave mode, the device is
operating in the manner of auto power saving condition such
that it operates as skip mode automatically at light load.
When EN is above VEN_Disable, the internal Vref is
activated and power−on reset occurs which resets all the
protection faults. Once Vref reaches its regulation voltage, an
internal signal will wake up the supply undervoltage
monitor which will assert a “GOOD” condition. In addition,
the NCP81045 continuously monitors VCC and VIN levels
with undervoltage lockout (UVLO) function.
Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master
Figure 15. Two Devices are Unsynchronized
Single Device Operation
The device is operating as single device operation when
the SYNC pin is pull to ground. Under this configuration, the
device will use the internal clock for normal PWM
operation.
Top to Bottom: VIN AC Voltage, SWN_Slave, SWN_Master
Figure 16. Two Devices are in Interleaved Operation
Transient Response Enhancement (TRE)
Dual Device Operation (Master/Salve Mode)
For the conventional PWM controller in CCM, the fastest
response time is one switching cycle in the worst case. To
further improve transient response in CCM, a transient
response enhancement circuitry is implemented inside the
NCP81045. In CCM operation, the controller is
continuously monitoring the COMP pin output voltage of
the error amplifier to detect the load transient events. The
functional block diagram of TRE is shown below.
The device is operating as Master/Slave mode if two
devices are tied up together. (Detail configuration please see
the application schematic) One device is served as Master
and another one is served as Slave. Once they already, they
are synchronized to each other and they are operating as
“interleaved” mode such that the phase shift of their
switching clocks is 180°. It has the benefit that the amount
of ripple current at the VIN will be lower and hence lesser
bulk capacitors at VIN to save the confined PCB space and
material cost. Figure 15 and Figure 16 show the difference
when the devices are operating independently
(unsynchronized) and operating at interleaved mode
(Synchronized). It can be seen that at the unsynchronized
condition, the system is obviously noisy because of high
ripple voltage at VIN (ripple voltage directly reflects the
amount of ripple current at VIN). Once the devices are
operating at interleaving mode, the overall VIN ripple
current is significantly reduced.
COMP
+
R
TRE
+
C
internal TRE_TH
Figure 17. Block Diagram of TRE Circuit
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12
NCP81045
Adaptive Voltage Positioning (AVP)
Once the large transient occurs, the COMP signal may be
large enough to exceed the threshold and then TRE “flag”
signal will be asserted in a short period which is typically
around one normal switching cycle. In this short period, the
controller will be running at high frequency and hence has
faster response. After that the controller comes back to
normal switching frequency operation. We can program the
internal TRE threshold (TRE_TH). For detail please see the
electrical table of “TRE Setting” section. Basically, the
recommend internal TRE threshold value is around 1.5
times of peak−to−peak value of the COMP signal at CCM
operation. The higher the internal TRE_TH, the lower
sensitivity to load transient. The TRE function can be
disable by setting the Rtre which is connecting to DL/TRE
pin to less than 25 kW. For system component saving, it is
usually set as default value, that is, Rtre is open (w75 kW)
and internal TRE_TH is 300 mV typical.
For applications with fast transient currents, adaptive
voltage positioning can reduce peak−to−peak output voltage
deviations due to load transients. With the use of AVP, the
output voltage allows to have some controlled sag when load
current is applied. Upon removal of the load, the output
voltage returns no higher than the original level, just
allowing one output transient peak to be cancelled over a
load step up and release cycle. The amount of AVP is
adjustable.
The behaviors of the Vo waveforms with or without AVP
are depicted at Figure 20.
Vo With AVP
Vo Without AVP
Figure 20. Adaptive Voltage Positioning
Vo
Rt
FB
+
COMP
Rb
Rocp
+ Vref
−
IDRP
IDRP/OCP
L
Rs1
DCR
Cs
CS+
+
Top to Bottom SWN, Vo, Transient Signal
Figure 18. Transient Response with TRE Disable
Rs2
CS−
Gi
Figure 21. Configuration for AVP Function
The Figure 21 shows how to realize the AVP function. A
current path is connecting to the FB pin via Rocp resistor.
Rocp is not actually for AVP function, indeed, Rocp is used
for OCP threshold value programming. The IDRP/OCP pin
has dual functions: OCP programming and AVP. At the
IDRP/OCP pin, conceptually there is a current source which
is modulated by current sensing amplifier.
The output voltage Vo with AVP is:
V O + V O0 * I O * R LL
(eq. 1)
Where Io is the load current, no load output voltage Vo0 is
set by the external divider that is:
Top to Bottom SWN, Vo, Transient Signal
ǒ
V O0 + 1 )
Figure 19. Transient Response with TRE Enable
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13
Rt
Rb
Ǔ*V
ref
(eq. 2)
NCP81045
The load line impendence RLL is given by:
R LL + DCR * Gain_CS * Rt *
Rs2
Rs1 ) Rs2
(eq. 3)
Where DCR is inductor DC resistance. Gain_CS is a gain
from [(CS+)−(CS−)] to IDRP Gain (At electrical table, the
symbol is IDRP_GAIN), the typical value is 0.525 mA/mV.
The AVP function can be easily disable by shorting the
Rocp resistor into ground.
From the equation we can see that the value of “top”
resistor Rt can affect the amount of RLL, so it is
recommended to define the amount of RLL FRIST before
defining the compensation component value. And if the user
wants to fine tune the compensation network for optimizing
the transient performance, it is NOT recommend to adjust
the value of Rt. Otherwise, both transient performance and
AVP amount will be affected. The following diagram shows
the typical waveform of AVP. Note that the Rt typical value
should be above 1 kW.
Top to Bottom : SWN, Vo, PGOOD, Io
Figure 23. Overcurrent Protection
The NCP81045 uses lossless inductor current sensing for
acquiring current information. In addition, the threshold
OCP voltage can be programmed to some desired value by
setting the programming resistor Rocp.
Vo
Rt
FB
+
COMP
Rb
IDRP/OCP
Rs1
L
Cs
DCR
Rocp
CS+
Rs2
CS−
+
− Vref
+
IDRP
Gi
Without AVP
Vo
Top to Bottom: SWN, Vo, Transient Signal
Figure 22. Typical waveform of AVP
Rt
FB
+
COMP
Rb
Rocp
Over Current Protection (OCP)
IDRP/OCP
The NCP81045 protects power system if over current
event occurs. The current is continuously monitored by the
differential current sensing circuit. The current limit
threshold voltage VOCSET can be programmed by resistor
ROCSET connecting at the IDRP/OCP pin. However, fixed
default VOCSET can be achieved if ROCSET is less than
2 kW.
If the inductor current exceeds the current threshold
continuously, the top gate driver will be turned off cycle by
cycle. If it happens over consecutive 16 clock cycles time
(16 x 1/fSW), the device is latched off such that top and
bottom gate drivers are off. EN resets or power recycle the
device can exit the fault. The following diagram shows the
typical behavior of OCP.
L
DCR
Rs1
Cs
CS+
Rs2
CS−
+
− Vref
+
IDRP
Gi
With AVP
Figure 24. OCP Configuration
It should be noted that there are two configurations for
Rocp resistor. If Adaptor Voltage Position (AVP) is used, the
Rocp should be connected to FB pin. If AVP is not used, the
Rocp should be connected to ground. At the IDRP/OCP pin,
there is a constant current(24 mA typ.) flowing out during the
programming stage at system start up. This is used to sense
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14
NCP81045
the voltage level which is developed by a resistor Rocp so as
to program the overcurrent detection threshold voltage. For
typical application, the Vocth is set as default value(40 mV
typ) by setting Rocp = 0 W, or directly short the IDRP/OCP
pin to ground. It has the benefit of saving one component at
application board. For other programming values of Vocth,
please refer to the electrical table of “Overcurrent Protection
Setting” section.
following diagram shows the typical waveform when OVP
event occurs.
Guidelines for selecting OCP Trip Component
1. Choose the value of Rocp for Vocth selection.
2. Define the DC value of OCP trip point(IOCP_DC)
that you want. The typical value is 1.5 to 1.8 times
of maximum loading current. For example, if
maximum loading is 10 A, then set OCP trip point
at 15 A to 18 A.
3. Calculate the inductor peak current (Ipk)which is
estimated by the equation:
I pk + IOCP_DC )
V o * (V IN * V o)
2 * V IN * f SW * L o
Top to Bottom : SWN, DL, Vo, PGOOD
Figure 25. Overvoltage Protection
(eq. 4)
Undervoltage Protection (UVP)
4. Check with inductor datasheet to find out the value
of inductor DC resistance DCR, then calculate the
RS1, RS2 dividing factor k based on the equation:
k+
V octh
I pk * DCR
An UVP circuit monitors the VFB voltage to detect under
voltage event. The under voltage limit is 80% (typical) of the
nominal VFB voltage. If the VFB voltage is below this
threshold over consecutive 8 clock cycles, an UV fault is set
and the device is latched off such that both top and bottom
gate drives are off. EN resets or power recycle the device can
exit the fault.
(eq. 5)
5. Select CS value between 100 nF to 200 nF.
Typically, 100 nF will be used.
6. Calculate Rs1 value by the equation:
Rs1 +
L
k * DCR * Cs
(eq. 6)
7. Calculate Rs2 value by the equation:
Rs2 +
k * Rs1
1*k
(eq. 7)
8. Hence, all the current sense components Rs1, Rs2,
Cs had been found for taget IOCP_DC.
9. If Rs2 is not used (open), set k = 1, at that
moment, the Ipk will be restricted by:
I pk +
V octh
DCR
(eq. 8)
Top to Bottom : SWN, Vo, PGOOD
Overvoltage Protection (OVP)
Figure 26. Undervoltage Protection
When VFB voltage is above OVPth+ of the nominal VFB
voltage for over 1.5 ms blanking time, an OV fault is set. At
that moment, the top gate drive is turned off and the bottom
gate drive is turned on until the VFB below lower under
voltage (UV) threshold and bottom gate drive is turned on
again whenever VFB goes above upper UV threshold. EN
resets or power recycle the device can exit the fault. The
Thermal Shutdown
The IC will shutdown if the die temperature exceeds
150°C. The IC restarts operation only after the junction
temperature drops below 125°C.
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NCP81045
C28
R220
D22
C27 C26
R29
R224
R7
PGOOD
LED1
PGOOD
M5
TPAD
C24
SWN
VIN
M1
DH
PGND
M3
R28
C1 C2 C216 D23
L1
DH
BST
2 VCC
CS−/Vo
EN
3 SYN
5
6
7
8
4 EN
SYNC
JP3
R216
JP2 COMP
C214
R213
C213
R22
12
R25
R1
R26
C212
C25
FB
R211
R214 C215
R223
J2
1
3
C3
2
R210
1−2 = OCP Only
3−2 = OCP + AVP
PGND AGND
Figure 27. Demo Board Schematic
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16
J21
D21
M2
CS+ 9
R215
R24
DL
C29
VOUT
PGND
M4 R212
DL/TRESET 11
NCP81045
R27
PGND 10
IDRP/OCP
C22
VCCP
FB
R2
13
COMP
AGND
C21
14
1 VIN
C23
R23
+5V
15
SWN
R21
16
PGOOD
U1
PGND PGND
NCP81045
PACKAGE DIMENSIONS
QFN16 4x4, 0.65P
CASE 485AP
ISSUE A
D
PIN 1
REFERENCE
2X
A
B
ÇÇ
ÇÇ
ÇÇ
DETAIL A
OPTIONAL LEAD
CONSTRUCTIONS
E
ÉÉ
ÉÉ
TOP VIEW
0.15 C
DETAIL B
A
(A3)
MOLD CMPD
ÉÉÉ
ÇÇÇ
ÉÉÉ
SIDE VIEW A1
NOTE 4
DETAIL A
D2
5
C
16X
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
2.00
2.20
4.00 BSC
2.00
2.20
0.65 BSC
0.20
−−−
0.45
0.65
−−−
0.15
MOUNTING FOOTPRINT*
L
4.30
8
4
2.25
9
PKG
OUTLINE
E2
1
1
K
A3
OPTIONAL LEAD
CONSTRUCTIONS
0.08 C
16X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
A1
DETAIL B
0.10 C
16X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
EXPOSED Cu
0.15 C
2X
L
12
16
13
16X
e
b
0.10 C A B
BOTTOM VIEW
0.05 C
0.65
4.30 2.25
NOTE 3
16X
0.78
PITCH
16X
0.35
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP81045/D