NCS36510 Advance Information Low Power System-on-Chip For 2.4 GHz IEEE 802.15.4-2006 Applications The NCS36510 is a low power, fully integrated, System on Chip that integrates a 2.4 GHz IEEE 802.15.4−2006 compliant transceiver, ARM® Cortex®−M3 microprocessor, RAM and FLASH memory, a true random number generator, and multiple peripherals to support design of a complete and secure wireless network with minimal external components. The NCS36510 offers advanced power management techniques that allow operation down to supply voltages as low as 1 V while minimizing current consumption. The NCS36510 is specifically designed for applications requiring maximum battery life while minimizing cost. The NCS36510 incorporates an industry leading 32 bit ARM Cortex−M3 for high performance, low power and low cost processing. The NCS36510 includes 640 kB of embedded FLASH memory for program storage along with 48 kB of RAM for data storage. NCS36510 uses a hardware accelerated MAC to minimize processor overhead while maximizing available processor power for running application software. Peripherals include DMA, UART(2), SPI(2), I2C(2), PWM, RTC, three programmable timers, WDT, 18 GPIO, 10 bit ADC with four external inputs and integrated temperature and voltage sensors. www.onsemi.com MARKING DIAGRAM 1 40 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR A WL YY WW G NCS36510 AWLYYWWG = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information on page 33 of this data sheet. Features • Low Voltage Operation to as low as 1.0 V • 0.18 mA Coma Mode Leakage Current • 0.65 mA Coma Mode Sleep Current • 6.6 mW Receive Power Consumption • −99 dBm Receiver Sensitivity • 6.9 mW Transmit Power Consumption • Programmable Output Power to X8 dBm • 2.4 GHz IEEE 802.15.4−2006 Transceiver • ARM Cortex − M3 Processor • AES 128/256 Encryption Engine • True Random Number Generator • 640 kB Embedded FLASH Memory • 48 kB Internal RAM Memory Typical Applications • Internet of Things • Building and Industrial Automation • ZigBee® / 6LoWPAN / WirelessHART® / Threadt This document contains information on a new product. Specifications and information herein are subject to change without notice. © Semiconductor Components Industries, LLC, 2015 December, 2015 − Rev. P5 1 Publication Order Number: NCS36510/D NCS36510 INTRODUCTION Table 1. REFERENCES Topic Reference Web Link WPAN Standard IEEE 802.15.4−2006 Standard CCM Encryption NIST SP800−38C AES Encryption Standard FIPS 197 http://www.nist.org/nist_plugins/content/content.php?content.39 Cryptography Wikipedia https://en.wikipedia.org/wiki/Block_cipher_mode_of_operation ARM Cortex M3 Product Information and Support ZigBee Alliance Website http://www.zigbee.org/ 6LoWPAN WG Website https://datatracker.ietf.org/wg/6lowpan/charter/ Thread Group Website http://threadgroup.org/ HART Communication Group Website http://en.hartcomm.org/main_article/wirelesshart.html https://standards.ieee.org/findstds/standard/802.15.4−2006.html http://csrc.nist.gov/publications/PubsSPs.html#SP 800 http://www.arm.com/products/processors/cortex−m/cortex−m3.php Table 2. DEFINITIONS Abbreviation Meaning ACK Refers to an acknowledge packet, part of 802.15.4 ADC Analog to Digital Converter AES Advanced Encryption Standard AGC Automatic Gain Control AHB AMBA High−performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus API Application Programming Interface BCD Binary Coded Decimal BO Brownout − loss of power below specified operating threshold BOM Bill Of Materials CBC Cipher Block Chaining CCM Counter with CBC CPU Central Processing Unit CSMA−CA Carrier Sense Multiple Access with Collision Avoidance, part of 802.15.4 CTR Counter mode DMA Direct Memory Access DWT Data Watchpoint and Trace unit ED Energy Detection, part of 802.15.4 ESR Equivalent Series Resistance ETM Embedded Trace Macrocell EVM Error Vector Magnitude FIFO First In First Out fips197 AES encryption standard FPB Flash Patch Breakpoint unit GPIO General Purpose I/O I2C Serial wire interface IF Intermediate frequency www.onsemi.com 2 NCS36510 Table 2. DEFINITIONS Abbreviation Meaning IOH Digital pad current when pad is driven to VOH IOL Digital pad current when pad is driven to VOL ITM Instrumentation Trace Macrocell LFSR Linear Feedback Shift Register LNA Low Noise Amplifier LPF Low Pass Filter LQI Link Quality Indicator, part of 802.15.4 MAC Medium Access Control layer MISO Master In Slave Out, part of I2C protocol MOSI Master Out Slave In, part of I2C protocol MUX Multiplexer NIST National Institute of Standards and Technology NVIC Nested Vectored Interrupt Controller OTA Over The Air PA Power Amplifier PMU Power Management Unit POR Power On Reset PWM Pulse Width Modulation QFN Quad Flat No Leads, package type RF Radio Frequency RSSI Receive Signal Strength Indicator RTC Real Time Clock RX SAR ADC Receive or Receiver Successive Approximation Register Analog to Digital Converter SCLK SPI Clock, part of SPI protocol SDK Software Development Kit SPI Serial Peripheral Interface SW Software SWD Serial Wire Debug TPIU Bridge between the ETM and ITM TRNG True Random Number Generator TX UART Transmit or Transmitter Universal Asynchronous Receiver/Transmitter UVI Under−Voltage Indicator VCO Voltage Controlled Oscillator VOH Digital pad maximum output voltage of pullup driver at a current of IOH VOL Digital pad maximum output voltage of pulldown driver at a current of IOL WDT Watch Dog Timer www.onsemi.com 3 NCS36510 BLOCK DIAGRAM INTERRUPT AND WAKEUP CONTROL ARM CORTEX −M3 NCS36510 Instruction Data BUS MATRIX SWDIO I−code D−code SWDCLK DMA 320 kB FLASH A 320 kB FLASH B SERIAL WIRE DEBUG System Bus 16 kB SRAM A SWO SWD_RESET DIO[13] DIO[12] DIO[11] RESETN AHB to APB BRIDGE 16 kB SRAM B 16 kB SRAM C TEST MODES TEST FLASH CONTROL VDDIO PAD CONTROL TIMERS UART 1 POWER SEQ UART 2 VPA MODULATOR RFPWR TX RADIO MAC SPI 1 DEMODULATOR SPI 2 2 RX I C1 RF ANALOG CONTROL I2 C 2 DIO[17:0] GPIO 32MO 32MI CLOCK CTRL 32KO PWM WATCH DOG 32 kHz SUPPLY MONITOR RTC 32 MHz 32KI RESETN SAR ADC RESET CTRL V3V V1VO V1VI C R O S S B A R PMU FVDDHO DVDDA DVDD AVDDn FVDDL RVDDn TEMP SENSOR 128 AES FVDDHI RANDOM NUMBER GENERATOR DC20150827 Figure 1. NCS36510 Block Diagram www.onsemi.com 4 MUX A[3:0] NCS36510 FUNCTIONAL DESCRIPTION Both clock domains have an internal and external user selectable clock reference. The external clock reference choices are crystal based and more accurate than the internal clock references. The internal clock references can be calibrated against the external 32 MHz clock. A hardware accelerated MAC offloads the processor to do application tasks. An extensive software API manages all hardware peripherals, allowing the developer to focus on application code. The integrated processor is an industry leading 32 bit ARM Cortex−M3 with SWD debugging. Integrated memory modules include 640 kB of embedded FLASH and 48 kB of RAM. The FLASH memory is split into 2 x 320 kB banks, enabling over the air upgrades or lower power consumption if both memories are not needed. Both FLASH banks also include an 8 kB information block. The information block includes ON Semiconductor factory trim values, the bootloader, and customer specific trim values. Details can be found in the SDK documentation. Four different software controlled power modes are available to maximize opportunities to save power in the application. The NCS36510 has an integrated 10 bit ADC. The input is single ended to reduce power consumption, but a pseudo−differential mode is available. Various input scale factors can be used to measure signals up to V3V, regardless of the power supply voltage. Hardware enabled relative measurements are also supported. Four independent external analog inputs are multiplexed at the input to the ADC. The ADC can also measure internal temperature and supply voltage sensors. Up to 18 general purpose digital I/Os are available and are programmable. Options include drive strength and pullup/pulldown resistors. The GPIOs can be used in conjunction with the following integrated peripherals: UART, SPI, I2C, and PWM. The NCS36510 is a system on chip for IEEE 802.15.4−2006 applications. Many functions are integrated to lower cost while delivering high performance at the lowest power consumption. The NCS36510 PMU supports two supply voltage modes: 3 V and 1 V. In 3 V mode a voltage source from 2 V to 3.6 V is applied to V3V which feeds into the internal pre−regulator. The pre−regulator regulates the output, V1V, down to about 1.1 V. From 2 V to 2.6 V the pre−regulator uses an internal linear regulator to generate V1V. From 2.6 V to 3.6 V an internal switching regulator can be used to increase the power conversion efficiency. In 1 V mode the pre−regulator is disabled and the core is supplied directly. V1V can be as low as 1 V and as high as 1.6 V. The RF receive path has been optimized for minimum power while maintaining high sensitivity. The receive chain employs two down conversion stages with the first one using an IF that is the LO divided by 16 and the second with a fixed low IF. After the second down conversion the signal is digitized for baseband processing which includes image rejection and demodulation. Automatic gain control is used to maximize dynamic range in the analog path. The RF transmit path has also been optimized for low power. Direct modulation in the frequency synthesizer is used to remove the need for an additional mixer. A non−linear switching power amplifier is used to maximize power efficiency. To minimize BOM costs, the RF transmit and receive pins can be connected together to avoid an external RF switch. The LO for the IF and RF blocks are generated by a fully integrated fractional N frequency synthesizer. The reference clock for the frequency synthesizer is a 32 MHz external oscillator. The NCS36510 has two clock domains. The low speed 32.768 kHz clock is typically used to periodically cycle between the lowest power coma mode and run mode. The high speed 32 MHz clock is used in run mode and by the internal frequency synthesizer for LO generation. www.onsemi.com 5 NCS36510 PIN CONFIGURATIONS RX TX RFPWR VPA TEST RESETN DIO[13] DIO[12] DIO[11] DIO[17] 31 32 33 34 35 36 37 38 39 40 DIO[10] DIO[9] DIO[8] DIO[16] VDDIO DIO[15] DIO[7] DIO[6] DIO[5] DIO[4] 1 30 2 29 3 28 4 27 5 26 NCS36510 6 25 7 24 8 23 9 22 10 21 20 19 18 17 16 15 14 13 12 11 V1VO NC FVDDHO FVDDHI DVDD DIO[14] DIO[0] DIO[1] DIO[2] DIO[3] 6 X32MI X32MO A1 A0 V3V V1VI DC20150827. Figure 2. 40−Pin QFN Configuration (Top View) www.onsemi.com A3 A2 X32KI X32KO NCS36510 PIN ASSIGNMENT Table 3. 40−PIN QFN CONFIGURATION Pin Pin Name 1 DIO[10] General Purpose Digital I/O Description 2 DIO[9] General Purpose Digital I/O 3 DIO[8] General Purpose Digital I/O 4 DIO[16] General Purpose Digital I/O 5 VDDIO Digital I/O Bank Power 6 DIO[15] General Purpose Digital I/O 7 DIO[7] General Purpose Digital I/O 8 DIO[6] General Purpose Digital I/O 9 DIO[5] General Purpose Digital I/O 10 DIO[4] General Purpose Digital I/O 11 DIO[3] General Purpose Digital I/O 12 DIO[2] General Purpose Digital I/O 13 DIO[1] General Purpose Digital I/O 14 DIO[0] General Purpose Digital I/O 15 DIO[14] General Purpose Digital I/O 16 DVDD Digital 950 mV Regulator 17 FVDDHI Embedded FLASH 1.8 V Regulator, Input to external filter required for 1 V mode 18 FVDDHO Embedded FLASH 1.8 V Regulator, Output from external filter required for 1 V mode 19 NC 20 V1VO Tie to GND or leave floating Core 1.1 V Regulator, Output to external filter required for 3 V mode using the switching regulator 21 V1VI Core 1.1 V Regulator, Input to external filter required for 3 V mode using the switching regulator 22 V3V Main power input 23 A0 ADC Channel Input 24 A1 ADC Channel Input 25 X32MO 32 MHz Crystal Output 26 X32MI 32 MHz Crystal Input 27 X32K0 32.768 kHz Crystal Output 28 X32KI 32.768 kHz Crystal Input 29 A2 ADC Channel Input 30 A3 ADC Channel Input 31 RX RF LNA Input 32 TX RF PA Output 33 RFPWR 34 VPA 35 TEST 36 RESETN 37 DIO[13] General Purpose Digital I/O 38 DIO[12] General Purpose Digital I/O 39 DIO[11] General Purpose Digital I/O 40 DIO[17] General Purpose Digital I/O EP Exposed Pad RF PA Regulator Output RF PA Regulator Input Test Input (used to enable SWD Interface) Active Low Reset GND, thermal pad under package www.onsemi.com 7 NCS36510 CPU Adjustable clock rates and clock switching also provide further means of lowering the power consumption. Typically the CPU is clocked at 32 MHz to execute code as quickly as possible. Next to the regular ARM Cortex−M3 processor interrupts, the NCS36510 implements 20 external source interrupts for peripheral devices. A powerful nested, pre−emptive and priority based interrupt handling assure timely and flexible response to external events. The NCS36510 integrates the powerful and energy efficient ARM Cortex−M3 processor. The processor uses the Thumb−2 instruction set and is optimized for high performance with reduced code size and low power operation. The Cortex−M3 efficiently handles multiple parallel peripherals and has integrated sleep modes including data retention for the lowest possible coma mode current. With industry standard tool chain and support, developing applications on the NCS36510 platform reduces time to market. MEMORY ORGANIZATION This section documents the memory map of the NCS36510. application related trims that can be programmed by the customer: 32.768 kHz external oscillator, 32 MHz external oscillator, and the RSSI offset. At the factory these are set to a nominal value. FLASH NCS36510 contains a total of 640 kB of FLASH memory, organized as two banks of 320 kB each. Two independent banks are used to allow either OTA upgrades or to shut down an unused bank to save power. Both FLASH banks include an 8 kB information block. This information block contains the bootloader and factory programmed trim values. There are a minimum of three RAM NCS36510 has a total of 48 kB of internal RAM, split into three banks of 16 kB. One or two of the RAM banks can be used in coma mode for data retention. www.onsemi.com 8 NCS36510 ROM table 0x3FFFFFFF External private peripheral bus SRAM A (16 kB) 0x3FFFC000 ETM TPIU 0xFFFFFFFF 0x3FFFBFFF Reserved SRAM B (16 kB) 0xE0100000 0xE00FFFFF 0x3FFF8000 0x3FFF7FFF SRAM C (16 kB) NVIC Private Peripheral Bus: Reserved External FPB DWT ITM 0xE0040000 0xE003FFFF Private Peripheral Bus: 0x3FFF4000 0x2400041C DMA (7 B) Internal 0xE0000000 0xDFFFFFFF 0x24000400 0x2400015F 0x24000100 0x240000FF MAC LUT (96 B) External Device (1 GB) MAC RAM (256 B) 0x24000000 0xA0000000 0x9FFFFFFF 0x00351FFF Program Memory B Alias 320 kB) 0x00302000 0x00301FFF 0x00300000 Information Block B Alias (8 kB) External RAM (1 GB) 0x60000000 0x5FFFFFFF Peripherals (0.5 GB) 0x00251FFF Program Memory A Alias (320 kB) 0x00202000 0x00201FFF 0x00200000 Information Block A Alias (8 kB) 0x40000000 0x3FFFFFFF SRAM (0.5 GB) 0x20000000 0x1FFFFFFF Code (0.5 GB) 0x00000000 Program Memory A (320 kB) Information Block A (8 kB) 0x00051FFF Program Memory B (320 kB) 0x00002000 0x00001FFF 0x00000000 Test Modes Device Option PMU Pad Control Clock Control Reserved RF/Analog Control Reset Control FLASH Control AES SAR ADC MAC Configuration Reserved Randomizer Crossbar RTC Reserved I2C #2 GPIO PWM Watchdog SPI #2 UART #2 I2C SPI UART Reserved Timer 2 Timer 1 Timer 0 0x00151FFF 0x00102000 0x00101FFF 0x00100000 Reserved Information Block B (8 kB) Figure 3. Memory Map www.onsemi.com 9 0xE00FF000 0xE00FEFFF 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE000DFFF 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x4001F000 0x4001E000 0x4001D000 0x4001C000 0x4001B000 0x4001A000 0x40019000 0x40018000 0x40017000 0x40016000 0x40015000 0x40014000 0x40013000 0x40012000 0x40011000 0x40010000 0x4000F000 0x4000E000 0x4000D000 0x4000C000 0x4000B000 0x4000A000 0x40009000 0x40008000 0x40007000 0x40006000 0x40005000 0x40004FFF 0x40003000 0x40002000 0x40001000 0x40000000 NCS36510 SYSTEM CLOCKS APB 32.768 kHz X32MO 32 MHz 24 32 MHz Internal OSC 32 MHz OSC X32MI 25 CLOCK CONTROL X32KO 27 32.768 kHz Internal OSC 32.768 kHz OSC X32KI 28 NCS36510 DC20150827 Figure 4. Clock System An internal 32 MHz oscillator is typically used for fast boot up before the external 32 MHz oscillator is enabled and ready. The 32.768 kHz internal oscillator is typically used during low power modes as it has the lowest power consumption. If accuracy is a higher priority over power consumption then the external 32.768 kHz oscillator can be used instead. Both internal oscillators can be trimmed by using the 32 MHz crystal oscillator based clock as a timing reference. The NCS36510 can be run from any of the four available clocks. There are two external oscillators, one 32 MHz and one 32.768 kHz. Both require external crystals to be used. There are two internal oscillators, one 32 MHz and one 32.768 kHz. The 32 MHz external crystal based clock is needed for 802.15.4−2006 timing requirements. The external 32.768 kHz crystal based clock is only needed if an accurate RTC is required. RESET EXTERNAL RESET There are five sources of reset: internal POR and BO, external reset, software reset, and watchdog timer. When the external reset pin is driven low, the NCS36510 is held in reset. The processor debug logic is not reset. INTERNAL POWER−ON RESET AND BROWNOUT SOFTWARE RESET The POR and BO functions are combined in the PMU. During startup, the POR is released when V3V is at a high enough voltage to support the internal digital logic voltage regulators. After power up the voltage at V1V is monitored and if it gets too low, a brownout reset is generated. A POR and a brownout have the same effect on the system which is a full reset including the processor debug logic. Upon POR or BO the processor starts to fetch instructions from address 0x0 where the boot loader resides. The boot loader loads the analog trim values from FLASH into the trim registers, figures out where the most recent application is located (FLASH bank A or B), checks the application binary and finally starts the application. Software reset can be called when switching from one application to the other, after remap of the FLASH banks, or on exit of a processor exception. The software requested reset will not reset all processor or peripheral device registers. WATCHDOG TIMER To help prevent errant software locking up the NCS36510 a WDT is provided. The WDT is disabled upon power up and must be enabled by software. The watchdog is paused when the debugger halts the processor. The processor debug logic is not reset. www.onsemi.com 10 NCS36510 EXCEPTION HANDLING The ARM Cortex−M3 processor supports priority based nested vectored interrupts. The NCS36510 has 35 interrupts with 16 levels of programmable priority. Table 4. Exception Number Exception Type Priority Description 1 Reset −3 (Highest) Reset 2 NMI −2 Non−maskable interrupt. This is set to the watchdog interrupt. 3 Hard fault −1 All fault conditions if the corresponding fault handler is not enabled. 4 MemManage fault Programmable Memory management fault 5 Bus fault Programmable Bus fault 6 Usage fault Programmable Exceptions resulting from program error. 7−10 Reserved 11 SVC Programmable Supervisor Call 12 Debug Monitor Programmable Debug monitor (breakpoints, watchpoints, or external debug requests) 13 Reserved Programmable 14 PendSV Programmable Pendable Service Call 15 SYSTICK Programmable System Tick Timer 16 Timer 0 Programmable Timer 0 interrupt 17 Timer 1 Programmable Timer 1 interrupt 18 Timer 2 Programmable Timer 2 interrupt 19 UART Programmable UART interrupt 20 SPI Programmable SPI interrupt 21 I2C Programmable I2C interrupt 22 GPIO Programmable GPIO interrupt 23 RTC Programmable Real−time−clock interrupt 24 Flash Controller Programmable Flash Controller 25 MAC Programmable MAC interrupt 26 AES Programmable AES interrupt 27 ADC Programmable ADC interrupt 28 Clock Calibration Programmable Clock calibration interrupt 29 UART #2 Programmable UART Interrupt 30 UVI Programmable Under Voltage Indicator Interrupt 31 DMA Programmable DMA interrupt 32 CDBGPWRUPREQ Programmable Debug request 33 SPI #2 Programmable SPI #2 Interrupt 34 I2C #2 Programmable I2C #2 Interrupt 35 FVDDH Comp Programmable FVDDH Supply Comparator Trip www.onsemi.com 11 NCS36510 WIRELESS TRANSCEIVER RADIO The NCS36510 radio is a single ended interface to minimize power consumption and external components. The transmit and receive pins are separated in the package but are typically connected on the application board. When transmitting the receiver is disabled, and vice versa. A biasing inductor is typically shared between the ports to minimize external components. The wireless transceiver consists of a: • Radio ♦ Receiver Transmitter ♦ Antenna Diversity Modem ♦ • RECEIVER GAIN GAIN RX LNA LOI 31 GAIN LO LOI SD ADC OUTI SD ADC OUTQ LOQ FREQ SYNTHESIZER N/M LOI POWER LOQ 33 TRANSMITTER RFPWR TX VCO LO LPF 32 MHz TXRF 32 Switching PA DATA NCS36510 DC20140606.1 Figure 5. Radio Block Diagram An external matching circuit is required to transform the impedance of the connected transmit/receive port to the antenna impedance to maximize power transfer and receiver sensitivity. imaginary components (I and Q). The I and Q signals are then converted to the digital domain for baseband processing. The receive path employs an AGC algorithm to maximize dynamic range. Receiver Transmitter A fully integrated fractional N frequency synthesizer is used to generate the necessary LO. The RF input is amplified by a LNA and is followed by a sliding IF mixer to down convert the signal to the first IF of LO/16. After further gain the signal is down converted again to baseband as real and The transmitter directly modulates the output baseband signal to RF in the frequency synthesizer. This avoids an additional mixer and saves power. The non−linear switching PA offers the highest efficiency theoretically possible. www.onsemi.com 12 NCS36510 34 PWRADJ VPA 33 RFPWR DAC 32 TX_IN TX RF Match NCS36510 DC20140606.2 Figure 6. Transmitter is offered. Antenna diversity requires an external antenna switch to switch between two separate antennas located at least a quarter wavelength away from each other. Using a GPIO port, an external antenna switch can be automatically switched to maximize sensitivity. The PA requires an external inductor from the Tx pin to the RFPWR pin. The supply voltage at VPA can be from 1 V to 3.6 V, independently from the other power domains. Typically VPA is connected to V3V. The RF output power is determined by the power setting set at the RFPWR regulator. The maximum DC voltage at RFPWR is about 2 V. When the transmitter is off, the RFPWR node is pulled to ground through an internal switch. MODEM The NCS36510 modem combines a proprietary blend of hardware and software to implement the requirements of the IEEE 802.15.4−2006 standard. By efficiently splitting the hardware and software interface for the modem, processor bandwidth is maximized and power consumption is minimized. Antenna Diversity Using a single antenna in a RF multi−path environment may make it difficult to receive signals consistently. To combat this natural phenomenon, antenna diversity support PERIPHERAL DEVICES CROSS BAR NCS36510 has 18 digital IO pins to communicate with external devices. These pins are shared between the following internal peripheral devices: 1. UART 1 2. UART 2 3. I2C 1 4. I2C 2 5. SPI 1 6. SPI 2 7. PWM 8. GPIO 9. SWD The application needs to configure the cross bar to wire the desired peripheral device to the desired IO pins, given the system constraints. The tables below indicate what peripheral device can be wired to what pin. www.onsemi.com 13 NCS36510 35 37 SWD 38 PAD CONTROL 39 40 1 UART 1,2 2 3 4 SPI 1,2 6 CROSS BAR 7 2 I C 1,2 8 9 10 GPIO 11 12 13 PWM 14 15 NCS36510 DC20140627 .1 Figure 7. Cross Bar The debug port is wired to digital IO 11, 12 and 13, only when the TEST pin is pulled to logic ‘1’. Debug port IO’s can’t be assigned to different IO’s. www.onsemi.com 14 TEST DIO[13] DIO[12] DIO[11] DIO[17] DIO[10] DIO[9] DIO[8] DIO[16] DIO[15] DIO[7] DIO[6] DIO[5] DIO[4] DIO[3] DIO[2] DIO[1] DIO[0] DIO[14] NCS36510 The software API implements macros to set up the cross bar. Table 5. CROSS BAR DIO 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Transmit Data Receive Data X Clear To Send X Request To Send UART X Data Terminal Ready X Data Set Ready X Data Carrier Detect X Ring Indicator X Transmit Data X Receive Data UART#2 X Clear To Send X Request To Send I2C X SCLK X X SDATA SCLK I2C#2 SDATA X X X X X X X X X SDATAO X X SDATAI X X SSNI X X SSNO<0> SSNO<1> X X SCLK SPI#1 0 X X X X X X X SSNO<2> X X SSNO<3> X www.onsemi.com 15 X X NCS36510 Table 5. CROSS BAR DIO 17 16 15 SCLK PWM x SSNO<0> x Output 15 14 13 X X 11 9 8 7 6 X X 5 4 3 2 1 0 X x X X X X 12 X 11 X 10 X 9 GPIO 10 X SSNI 16 12 X SDATAI 17 13 X SDATAO SPI#2 14 X 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 X PERIPHERAL ENABLE AND DISABLE To save power, each peripheral device can be switched on or off. The software API implements functions to enable and disable the clocks by manipulating the clock control register. • • • • DIGITAL INPUT/OUTPUT NCS36510 has 18 identical GPIO. The following list documents the programmable options available independently for each GPIO. Programming is done with software API calls. Each GPIO input is compatible with CMOS levels and has hysteresis. Options: • Bi−directional capability • Individually configurable interrupt lines • Rising, falling, or both edge interrupt • High, low, or both logic level interrupt SAR ADC The NCS36510 has a fully integrated 10 bit SAR ADC. The ADC is single ended to reduce power consumption. A six input multiplexer allows up to four external signals to be measured. The other two inputs are for internal temperature and battery voltage (V3V) sensors. The SAR ADC completes a conversion as fast as 5 ms with a 4 MHz sample clock in 20 clock cycles. To support a wide range of input voltages, there is a programmable resistive voltage divider on the external inputs. The table below shows the ideal settings. Loopback mode Push pull or open drain Four programmable drive strengths Pullup, pulldown or neither www.onsemi.com 16 NCS36510 V3V t °C REF 0,95 V A0 A1 A2 A3 23 24 MUX SCALE MUX[2:0] SCALE[3:0] SAR ADC 10 OUT[9:0] 29 30 NCS36510 DC20140627. 1 Figure 8. ADC Block Diagram differential voltage is automatically divided by the third conversion resulting in a pseudo−differential ratio. This SAR ADC has a finite input time constant. The mux has a finite resistance, and the input of the ADC has a finite capacitance. The input voltage must be fully settled to get an accurate conversion. The input time constant also depends on the scale factors programmed. The following table contains typical values for time constants as a function of the input scale factor. For maximum accuracy, at least 7 time constants of settling time are recommended. Warning: The user has the responsibility to respect the absolute maximum ratings. The voltage on the ADC pins cannot exceed V3V + 0.3 V, regardless of the input scaling. Several modes of ADC operation are available including absolute, ratio based, and pseudo−differential. All ADC conversions are referenced to an internal fixed reference of nominally 950 mV. Absolute conversions represent the input signal compared to this fixed reference. Table 6. ADC SCALE FACTORS Scale Factor Maximum Input Input Resistance 1.00 950 mV High Impedance 0.69 1.3 V 80 kW 0.53 1.7 V 52 kW 0.43 2.1 V 43 kW 0.36 2.5 V 38 kW 0.31 2.9 V 36 kW 0.28 3.3 V 34 kW 0.24 3.7 V 32 kW Table 7. TYPICAL ADC SETTLING TIMES For applications that require measuring an external signal versus an external reference, a ratio based conversion mode is supported. Two ADC conversions are done back to back and automatically divided to get a ratio. Pseudo−differential mode is similar to ratio based mode, except the final computation is the difference of the two signals instead of the ratio. Ratio based pseudo−differential mode consists of three conversions. The first two are taken as a differential signal, the third is considered as a reference. The resulting Scale Factor Time Constant, t 7t 1.00 160 ns 1.12 ms 0.69 110 ns 770 ns 0.53 85 ns 595 ns 0.43 68 ns 476 ns 0.36 58 ns 406 ns 0.31 50 ns 350 ns 0.28 44 ns 308 ns 0.24 39 ns 273 ns The ADC can be used in either single or continuous conversion modes. There is a status bit that can be polled to determine if the ADC is busy. An interrupt can also be configured to avoid consuming processor cycles polling the status bit. Averaging can improve the accuracy of the SAR ADC conversions as compared to single shot measurements. The ADC is configured and controlled by software API calls. www.onsemi.com 17 NCS36510 PWM The PWM Module is a peripheral that generates a programmable duty cycle output signal. The duty cycle can be programmed from 0% to 100% with 8 bit resolution. The PWM is configured and controlled by software API calls. The first counter is a 15 bit sub−second counter (2^15−1/32768 = 1s). It can be used for wait times less than one second. The other counter is a 32 bit seconds counter. The seconds counter is incremented by the sub−second counter rollover. The second counter can count up to ~136 years so it can be used as a Unix (POSIX or Epoch) time counter if desired. Each counter has programmable independent alarms interrupts. Through software it is possible to enable a combination of second and sub−seconds counter. The RTC is configured and controlled by software API calls. UART NCS36510 implements two UART devices, UART 1 and UART 2. UART 1 is a complete implementation of a 16550 UART. By configuring the crossbar UART1 can be set up as a complete 16550 UART, with all control wires. Configuration registers are written and read by the NCS36510 support code. The baud rate generator produces timing strobes at the baud rate (for the transmitter) and at 16 times the selected baud rate (for the receiver). The receiver examines the incoming data and uses the first edge of the start bit to determine the bit timing. Transmit and receive paths can be configured to use a single register for data or to use FIFOs. Finite State Machines (FSMs) control transmit and receive sections. Various error conditions can cause an interrupt to be generated. UART 2 is similar as UART 1, only RX and TX lines can be wired to IO pins. The UART peripherals are configured and controlled by software API calls. MAC The NCS36510 MAC is comprised of a proprietary mix of hardware and software. The developer interfaces with the MAC through software API calls. The MAC implements all necessary functions of the IEEE 802.15.4−2006 specification as required to develop non−beaconed wireless networks including: • Channel access • Frame validation • Acknowledged frame delivery (ACK) • Association/Disassociation • Hooks for security • 16 bit or 64 bit extended addresses • CSMA−CA • ACK • ED • LQI • 16 channels I2C NCS36510 implements two I2C bus master interfaces. The I2C bus is an industry−standard two−wire (clock and data) serial communication bus. The I2C bus is a single master, multiple slave bus. I2C specifies that the I2C master will initiate all read and write transactions, and that the I2C slave will respond to these requests. The I2C peripherals are configured and controlled by software API calls. SECURITY The AES 128/256 module provides hardware support for the encryption and decryption operations used in IEEE 802.15.4−2006. To support security required for IEEE 802.15.4−2006, the use of CCM is required. CCM is a combination of counter mode (CTR) and cipher block chaining (CBC). It can perform a “Counter” (CTR) or a Cipher Block Chaining (CBC) encryption in 12 clocks for 128 bit encryption, or 16 clocks for 256 bit encryption. The definition of CCM mode encryption is documented in the NIST publication SP800−38C. Details of the implementation of the AES module can be found in federal information processing standard fips197. For more information, visit the following website: https://en.wikipedia.org/wiki/Block_cipher_mode_of_ope ration. The security is configured and controlled by software API calls. SPI NCS36510 implements two SPI Bus Controllers. The SPI peripherals are synchronous serial data link controllers. The SPI bus controller can be configured under software control to be a master or slave device. The data is transmitted synchronously with the MOSI relative to the SCLK generated by the master device. The master also receives data on the MISO signal in a full duplex fashion. The SPI controllers can be used with up to three slave devices. When the core is configured as a slave, the MISO signal is tri−stated to allow for multiple slaves to transmit data to the master when the slave’s SSn control is active (or selected). The SPI is configured and controlled by software API calls. TIMERS NCS36510 has three independent hardware timers. Each timer is a 16 bit down counter with a selectable prescaler. Prescaler values of 1, 16 and 256 can be selected. The RTC The RTC consists of two counters that are clocked by the 32.768 kHz clock (either internal or external references). www.onsemi.com 18 NCS36510 TRUE RANDOM NUMBER GENERATOR NCS36510 implements a TRNG. The randomizer can be used to create uniformly distributed 32−bit random numbers. It can be preloaded with a 32−bit random seed value. The random number is generated using a maximum length LFSR. The polynomial used is x32 + x22 + x2 + 1. The TRNG is configured and controlled by software API calls. prescaler extends the timer’s range at the expense of precision. The timer provides two modes of operation that provide a free running value and also periodic interrupts. The timer contains several configuration registers that can be written and read by the NCS36510 support software. Two 4 bit prescalers precede a 16 bit counter. The counter can be clocked at either the input clock rate, or a choice of 7 pre−scaled rates. The counter can be loaded with a value from a preload register. The counter can optionally generate an interrupt. The timers are configured and controlled by software API calls. DMA The DMA controller is a single channel direct memory access controller. It can be used to directly transfer data from memory to memory, peripheral to memory, memory to peripheral and peripheral to peripheral. After initial setup, the DMA controller initiates data transfer from the user specified source location to the internal DMA FIFO. It then performs another transfer to move the date from the FIFO to the user specified destination location. Through the DMA software API, the DMA complete event can be polled for, or a prior registered interrupt handler can be called upon DMA complete interrupt. SYSTEM TICK TIMER Like most ARM Cortex devices, the NCS36510 implements a system tick timer. This system tick timer is owned by the software and is used for ticking the real time operating system. WATCHDOG TIMER NCS36510 implements one programmable watchdog timer. The watchdog timer is disabled by default and the application software needs to instantiate the watchdog timer driver and enable it. To assist software development, the watchdog timer is paused when the in−circuit debugger halts the CPU. The watchdog is on the 32.768 kHz clock domain so it has a minimum resolution of 30.5 mS. It is 18 bits wide giving it a maximum timeout time of 8 seconds. The WDT is configured and controlled by software API calls. SWD DEBUG INTERFACE NCS36510 implements a standard ARM SWD interface. Use any SWD compliant hardware debugger interface to interact with the internals of the NCS36510. Section 13.2 details how to connect the in circuit debugger hardware. Note that the NCS36510 cannot go into coma mode with the debugger attached. Warning: Some debuggers do not work at 1 V. POWER MANAGEMENT UNIT internal logic signal and the system will be configured in 1 V mode. Warning: Connecting V1VO/I to V3V when V3V is greater than the absolute maximum rating for the V1VO/I domains will result in damage to NCS36510. The pre−regulator voltage is split into two pins, V1VO (V1V Output), and V1VI (V1V Input). Between these pins a power supply filter must be put on the application board to suppress the switching regulator noise. Throughout this document this pre−regulator voltage may be referred to as simply V1V. The user has the responsibility to filter this voltage as specified to obtain the published performance specifications. NCS36510 has an advanced PMU supporting two voltage supply modes: 3 V and 1 V, and four operating modes: Run, Sleep, Deep Sleep, and Coma. PRE−REGULATOR In 3 V mode the V3V voltage is pre−regulated to a voltage of about 1.1 V. The default voltage regulator is the linear regulator. The application is responsible for controlling the switching regulator, including monitoring the V3V voltage with the internal voltage sensor. The switching regulator is only allowed if V3V > 2.6 V. In 1 V mode, the pre−regulator is disabled. Connecting the V3V and V1VO/I pins to 1 V will automatically generate an www.onsemi.com 19 NCS36510 V3V Linear Regulator 22 1 20 V1VO 0 64MHz CLK 1 Switching Regulator 32.768kHz CLK 0 COMA MODE STARTUP /POR V3V < 2.6V NCS36510 DC20140627 .1 Figure 9. Pre−Regulator System SYSTEM OF LINEAR REGULATORS Warning: The DVDD regulator is pinned out for de−coupling only. The application is not allowed to use this regulator to power anything other than the NCS36510 internal circuits. The pre−regulator voltage (V1V) is the input voltage (V1VI) for an array of internal linear regulators that are automatically enabled and disabled in the appropriate modes to minimize power consumption. These internal regulators supply the internal analog and digital blocks. www.onsemi.com 20 NCS36510 V1VI 21 VREF OPA 16 DVDD Digital Blocks VREF OPA AVDD Analog Blocks NCS 36510 DC 20140714 .1 Figure 10. Linear Regulator System EMBEDDED FLASH POWER SUPPLIES To support the embedded FLASH two internal power supplies are implemented. One is the FVDDH, which is 1.8 V, and the other is FVDDL, which is 1.2 V. In 3 V mode, the FVDDH is generated by a linear regulator powered by V3V. In 1 V mode, a voltage multiplier is used to boost the V3V input voltage to the required level. The FVDDH voltage is split into two pins, FVDDHO (FVDDH Output), and FVDDHI (FVDDHI Input). Between these pins a power supply filter must be put on the application board to suppress the voltage multiplier noise. Throughout this document this voltage may be referred to as simply FVDDH. The user has the responsibility to filter this voltage as specified to obtain the published performance specifications. In either 3 V or 1 V modes the FVDDL voltage is generated by a linear regulator from FVDDHI. Warning: The application is not allowed to use this regulator to power anything other than the NCS36510 internal circuits. www.onsemi.com 21 NCS36510 22 V3V Voltage Multiplier 64MHz CLK 1 18 FVDDHO 0 V 3V < 1.65V Linear Regulator Linear Regulator 17 FVDDHI FVDDL NCS 36510 DC20151214 Figure 11. Flash Regulator System • Sleep • Deep Sleep • Coma OPERATING MODES Operating runs are selected by software as highlighted below. • Run Table 8. POWER MODES Mode Digital FLASH Retention SRAM A Retention SRAM B 32 MHz Clock Run ON ON ON ON ON Sleep ON ON ON ON ON Deep Sleep ON OFF ON ON ON COMA OFF OFF Programmable Programmable OFF processor clock is gated, the processor is not executing code. When an interrupt is detected, the FLASH memories are powered up and the processor enters run mode and executes code starting from the last known location. The software application needs to decide when to enter any of the sleep modes. The SDK offers a power management unit API. RUN MODE In run mode all digital systems are powered and running including external and/or internal oscillators. The processor is executing code. COMA MODE In coma mode, only retention registers are powered in the digital system. All processor, trim, and peripheral registers retain their values. The high speed oscillator(s) are powered down. The low speed oscillator clocks the CPU. The processor clock is gated and waiting for an interrupt. When an interrupt is received, the FLASH memory and remaining digital systems will power up and the processor will enter run mode and start executing code from the location, just after where the power saving mode was entered. The processor will stall until the FLASH memories are properly powered. What FLASH banks are powered is decided upon the FLASH power settings in the FLASH control block, managed by the software FLASH driver. SLEEP MODE Sleep mode is the same as run mode except the processor clock is gated. Since the processor clock is gated, the processor is not executing code. When an interrupt is detected, the processor enters run mode and executes code starting from the last known location. DEEP SLEEP MODE Deep sleep mode is the same as sleep mode except the FLASH memories are also powered down. Since the www.onsemi.com 22 NCS36510 ELECTRICAL CHARACTERISTICS Table 9. ABSOLUTE MAXIMUM RATINGS Ratings Symbol Value Unit V3V Pin Voltage −0.3 to 3.9 V VPA Pin Voltage −0.3 to 3.9 V VDDIO Pin Voltage −0.3 to 3.9 V DVDD Pin Voltage −0.3 to 1.8 V FVDDHI/FVDDHO Pin Voltage −0.3 to 2.38 V V1VO/V1VI Pin Voltage −0.3 to 1.8 V −0.3 to VDDIO+0.3, v 3.9 V Analog Pin Voltage (Note 2) −0.3 to V3V+0.3, v 3.9 V Crystal Pin Voltage (Note 3) −0.3 to DVDD+0.3, v 1.8 V RX Pin Voltage −0.3 to VPA+0.3, v 3.9 V TX Pin Voltage −0.3 to VPA+0.3, v 3.9 V RFPWR Pin Voltage −0.3 to VPA+0.3, v 3.9 V TJ(max) 125 °C TSTG −40 to 125 °C ESD Capability, Human Body Model (Note 4) 2000 V ESD Capability, Charged Device Model (Note 5) 250 V Latchup Current Level (Note 6) 100 mA Digital Pin Voltage (Note 1) Maximum Junction Temperature Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. GPIO[17:0], RESETN, TEST 2. A0, A1, A2, A3 3. X32KI, X32KO, X32MI, X32MO 4. ESD Human Body Model tested per JEDEC JS−001−2012. 5. ESD Charged Device Model tested per JEDEC JESD22−C101. 6. JESD78 Rev. D at Room Temperature. Table 10. NORMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit V3V Supply Voltage – 3 V Mode V3V3 2.0 3.0 3.6 V V3V Supply Voltage – 1 V Mode (connected to V1V) V3V1 1.0 1.15 1.6 V VPA Supply Voltage VPA 1.0 3.0 3.6 V VDDIO 1.0 3.3 3.6 V V1V 1.0 1.15 1.6 V TA −40 27 85 °C VDDIO Supply Voltage V1V Supply Voltage (Note 7) Ambient Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 7. V1V is only an input in 1 V mode www.onsemi.com 23 NCS36510 Table 11. ELECTRICAL CHARACTERISTICS For typical values TA = 27°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. Power supplies V3V = VPA = 3 V, VDDIO = 3.3 V, unless otherwise noted. Test Conditions Parameter Symbol Min Typ Max Unit COMA MODE SLEEP CURRENT Coma Mode Sleep Current (Note 8) 1 V Mode (Note 9) 3 V Mode, Switching Regulator 3 V Mode, Linear Regulator (Note 10) 1.0 0.65 4.96 μA 8. Coma mode = CPU running on internal 32 kHz osc and waiting for interrupt, both retention RAMS disabled, all other functions powered down 9. V1V = V3V = VPA = 1.0 V 10. V3V = VPA = 2.0 V COMA MODE LEAKAGE CURRENT Coma Mode Leakage Current (Notes 9 and 11) 1 V Mode μA 0.18 11. Coma mode = No clock present, CPU static, both retention RAMS disabled, all other functions powered down. CORE POWER CONSUMPTION 1V Mode Transmit Current (Notes 12, 13 and 14) +2.6 dBm (Max. Power Setting) 0 dBm −16 dBm (Min. Power Setting) 6.9 6.7 4.7 mA 3V Mode Transmit Current – Switching Regulator (Notes 12, 13 and 14) +7.6 dBm (Max. Power Setting) 0 dBm −16 dBm (Min. Power Setting) 14.3 7 2.64 mA 3V Mode Transmit Current – Linear Regulator (Notes 12, 13 and 14) +7.6 dBm (Max. Power Setting) 0 dBm −16 dBm (Min. Power Setting) 16.2 9 4.7 mA 1V Mode Receive Current (Notes 12 and 14) 6.6 mA 3V Mode Receive Current (Notes 12 and 14) – Switching Regulator 3.6 mA 3V Mode Receive Current (Notes 12 and 14) – Linear Regulator 6.5 mA 12. Peripherals disabled, CPU halted, 32 MHz crystal oscillator, CW Mode, 2.44GHz 13. Transmit power depends on RF matching circuit 14. ON Semiconductor evaluation board, TX and RX pins connected together, conducted measurement, 50W system GENERAL RAM − Total 3 banks of 16 kB RAM, up to two banks retained in COMA mode 16 48 kB FLASH − Total 2 banks of 320 kB FLASH, independent power controls 320 640 kB FLASH Erase Cycles Before Failure (Note 15) 10k cycles FLASH Read Current (Note 15) 2.3 mA FLASH Erase Current (Note 15) 5 mA FLASH Write Current (Note 15) 3 Data Retention at 85°C 10 mA years 15. Guaranteed by design. RF RECEIVER 1V Mode Receive Sensitivity (Notes 16 Maximum of −85 dBm at a PER of 1% as defined by (Note 17) and 18) −99 dBm 3V Mode Receive Sensitivity – Linear Regulator (Notes 16 and 18) −99 dBm Maximum of −85 dBm at a PER of 1% as defined by (Note 17) www.onsemi.com 24 NCS36510 Table 11. ELECTRICAL CHARACTERISTICS For typical values TA = 27°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. Power supplies V3V = VPA = 3 V, VDDIO = 3.3 V, unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit RF RECEIVER 3V Mode Receive Sensitivity – Switching Regulator (Notes 16 and 18) Maximum of −85 dBm at a PER of 1% as defined by (Note 17) −98 dBm Saturation (Note 16) Maximum of −20 dBm at a PER of 1% as defined by (Note 17) −20 dBm High−Side Adjacent Channel Rejection (Note 16) Signal at −82 dBm, O−QPSK modulated interferer ±5 MHz, PER of 1% as defined by (Note 17) Minimum of 0dB required by (Note 17) 28 dB Low−Side Adjacent Channel Rejection (Note 16) Signal at −82 dBm, O−QPSK modulated interferer ±5 MHz, PER of 1% as defined by (Note 17) Minimum of 0 dB required by (Note 17) 29 dB High−Side Alternate Channel Rejection Signal at −82 dBm, O−QPSK modulated (Note 16) interferer ±10 MHz, PER of 1% as defined by (Note 17) Minimum of 30dB required by (Note 17) 34 dB Low−Side Alternate Channel Rejection (Note 16) Signal at −82 dBm, O−QPSK modulated interferer ±10 MHz, PER of 1% as defined by (Note 17) Minimum of 30dB required by (Note 17) 37 dB Co−channel Rejection (Note 16) Signal at −82 dBm, O−QPSK modulated interferer, PER of 1% −7 dB RSSI dynamic range (Note 16) Energy Detect − Minimum of 40 dB required by (Note 17) 80 dB RSSI Accuracy (Note 16) Energy Detect − Maximum of ±6 dB required by (Note 17) ±3 dBm Spurious Emissions 1GHz to 12.75GHz Radiated Measurement, converted to dBm (LO Leakage) (Note 16) ETSI EN 300 328 Requirement is −47dBm −69 dBm Frequency Error Tolerance (Note 19) ±100 ppm 16. ON Semiconductor evaluation board, TX and RX pins connected together, conducted measurement, 50W system. 17. IEEE 802.15.4−2006 Standard. 18. 2.48 GHz 19. Difference between center frequency of the received RF signal and LO frequency, measured on ON Semiconductor bench evaluation board. RF TRANSMITTER Carrier Offset (Note 16) At maximum recommended power setting as defined by (Note 17) Maximum of ±40 ppm as required by (Note 17) 2 ppm 1 V Mode – Maximum Output Power (Note 16) Conducted measurement, 50 W load Minimum of −3 dBm as required by (Note 17) 2.6 dBm 3 V Mode – Maximum Output Power (Note 16) Conducted measurement, 50 W load Minimum of −3 dBm as required by (Note 17) 7.6 dBm Minimum Output Power (Note 16) Conducted measurement, 50 W load −16 dBm Error Vector Magnitude (Note 16) At maximum recommended power setting as defined by (Note 17) Maximum of 35% as required by (Note 17) 3 V mode with switching regulator enabled 20 % www.onsemi.com 25 NCS36510 Table 11. ELECTRICAL CHARACTERISTICS For typical values TA = 27°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. Power supplies V3V = VPA = 3 V, VDDIO = 3.3 V, unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit RF TRANSMITTER Spurious Emissions (Note 16), Worst Case Requirement Maximum power setting, conducted measurement, 50 W load 3 V Mode with switching regulator enabled −41.23 dBm required for (Note 20) Limit 54 dBμV/m = −41.23 dBm EIRP (Note 21) −46 dBm 32.768 kHz 20. FCC Part 15.247, ETSI EN 300 440, ETSI EN 300 328 21. Field strength to dBm converter: http://www.compeng.com.au/radiated−power−calculator/ EXTERNAL OSCILLATOR – 32.768 kHz Crystal frequency Accuracy requirements −100 100 ppm ESR 80 kW Crystal shunt capacitance (C0) 2.0 pF INTERNAL OSCILLATOR – 32.768 kHz Uncalibrated Calibrated frequency 26 36 47 32.68 32.768 32.85 kHz EXTERNAL OSCILLATOR – 32 MHz 32 Crystal frequency Accuracy requirements −30 MHz 30 ppm ESR 50 W Crystal shunt capacitance (C0) 2.0 pF INTERNAL OSCILLATOR – 32 MHz Uncalibrated frequency 28 32 41 MHz Calibrated frequency 31 32 33 MHz 10b SAR ADC Conversion time 5 ms INL (Note 16) No averaging, 16 samples averaged 6, 4 Codes DNL (Note 16) No averaging, 16 samples averaged 4, 1 Codes −40C Value (Note 22) 777 Codes +30C Value (Note 22) 664 Codes +85C Value (Note 22) 546 Codes Uncalibrated Accuracy (Note 23) +/−5 °C 0.654 0.651 V TEMPERATURE SENSOR 22. From Automated Test Equipment (ATE) 23. Guaranteed by design. POR/BROWNOUT Reset trip points (Note 24) Trip high (POR) Trip Low (Brownout) 24. V1V power domain. DIGITAL I/O VIL Highest input voltage recognized as a logic low www.onsemi.com 26 0.3 * VDDIO V NCS36510 Table 11. ELECTRICAL CHARACTERISTICS For typical values TA = 27°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. Power supplies V3V = VPA = 3 V, VDDIO = 3.3 V, unless otherwise noted. Parameter Test Conditions Symbol Min Typ VIH 0.7 * VDDIO Max Unit DIGITAL I/O Lowest input voltage recognized as a logic high Input leakage VDDIO = 2.97 V V 3 Input hysteresis (Note 27) nA Vhyst 375 411 650 mV Logic high source current, IOH VDDIO = 3.3 V Pad driven to VOH = 0.8 * VDDIO IOH3V0 IOH3V1 IOH3V2 IOH3V3 −1.5 −3 −5.5 −12 −1 −2 −4 −8 −0.8 −1.7 −3.1 −6 mA Logic low sink current, IOL VDDIO = 3.3 V Pad driven to VOL = 0.2 * VDDIO IOL3V0 IOL3V1 IOL3V2 IOL3V3 1 2.25 4.25 8.1 1.6 3.1 6 11.6 2.25 4.25 8 15 mA 8 10 12 kW Pullup/Pulldown Resistance (Notes 25 and 26) 25. RESET pin has a fixed pullup 26. TEST has a fixed pulldown 27. Guaranteed by design. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. TYPICAL CHARACTERISTICS − RECEIVER 80 3V Mode − Linear Regulator 60 1V Mode 40 20 0 −106 IEEE 802.15.4 1% Limit −102 53 51 3V Mode − Switching Regulator RELATIVE POWER LEVEL (dBr) PACKET ERROR RATE (%) 100 −98 44 43 35 32 29 26 −50 −30 −10 10 30 50 INPUT POWER (dBm) RELATIVE FREQUENCY (MHz) Figure 12. Packet Error Rate Figure 13. CW Mode Blocking / De−sensitization www.onsemi.com 27 NCS36510 7.6 7.7 7.5 7.6 TRANSMIT POWER (dBm) TRANSMIT POWER (dBm) TYPICAL CHARACTERISTICS − TRANSMITTER 3 V MODE 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.6 2.405 2.415 2.425 2.435 2.445 2.455 7.3 7.2 7.1 7.0 6.9 6.7 2.405 2.415 2.425 2.435 2.445 2.455 2.465 2.475 (GHz) Figure 14. 3 V Mode with Switching Regulator Transmitter Output Power in CW Mode at Maximum Power Figure 15. 3 V Mode with Linear Regulator Transmitter Output Power in CW Mode at Maximum Power 10 10 5 5 0 −5 −10 −15 −20 2 4 6 8 10 12 14 16 18 −5 −10 −15 20 2 4 6 8 10 12 14 16 18 Figure 17. 3 V Mode with Linear Regulator Transmit Power in CW Mode, 2.4425 GHz TRANSMITTER CURRENT (mA) TRANSMIT POWER SETTING CODE Figure 16. 3 V Mode with Switching Regulator Trasmit Power in CW Mode, 2.4425 Hz 7 0 0 TRANSMIT POWER SETTING CODE 12 2 0 −20 0 2.465 2.475 (GHz) TRANSMIT POWER (dBm) TRANSMIT POWER (dBm) 7.4 6.8 6.7 TRANSMITTER CURRENT (mA) 7.5 2 4 6 8 10 12 14 16 18 14 9 4 20 0 TRANSMIT POWER SETTING CODE 2 4 6 8 10 12 14 16 18 TRANSMIT POWER SETTING CODE Figure 18. 3 V Mode with Switching Regulator Transmitter Current versus Power Setting, 2.4425 GHz Figure 19. 3 V Mode with Linear Regulator Transmitter Current versus Power Setting, 2.4425 GHz www.onsemi.com 28 20 20 NCS36510 TYPICAL CHARACTERISTICS − TRANSMITTER 1 V MODE 2.50 TRANSMIT POWER (dBm) 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 2.405 2.415 2.425 2.435 2.445 2.455 2.465 2.475 (GHz) Figure 20. 1 V Mode Transmitter Output Power in CW Mode TRANSMITTER CURRENT (mA) TRANSMIT POWER (dBm) 5 −5 −10 −15 −20 0 2 4 6 8 10 12 14 16 18 7 6.5 6 5.5 5 4.5 20 0 2 4 6 8 10 12 14 16 18 TRANSMIT POWER SETTING CODE TRANSMIT POWER SETTING CODE Figure 21. 1 V Mode Transmit Power in CW Mode, 2.4425 GHz Figure 22. 1 V Mode Transmitter Current versus Power Setting www.onsemi.com 29 20 NCS36510 APPLICATION SECTION TYPICAL APPLICATION DIAGRAMS Application drawings for 3 V and 1 V mode systems and their recommended components are shown below. Because the RF matching components are system dependent their values are not specified. The back of the NCS36510 package has an exposed conductive pad that is required to be soldered to a ground plane for proper operation. This pad is the ground for all of the power domains on NCS36510, including the RF circuitry. 3 V System 3.3V 3V C6 C8 TXD DIO [0] RXD UART1 SWD Debug DIO [1] CTS DIO [2] RTS DIO [3] SWO DIO [11] SWCLK DIO [12] SWDIO DIO [13] SWD_RESET RESETN C9 VPA DVDD VDDIO FVDDH C5 17,18 5 16 34 RFPWR 14 33 C1 13 L1 12 L2 TX 32 L3 11 C4 NCS36510 39 31 C2 RX C3 38 26 37 X32MI X1 36 25 20 C12 V3V V1VI C11 L4 22 V1VO 21 DC20151130 X32MO 3V C10 Figure 23. 3 V System Application Diagram Table 12. COMPONENT LIST Component C1 C2, C3 Description Decoupling RFPWR Value 100 pF RF match and harmonic filter C4 RF DC Block 100 pF C5 Decoupling VDDIO 220 nF C6 Decoupling FVDDH 33 nF C7 Decoupling FVDDL 33 nF C8 Decoupling DVDD 33 nF C9 VPA 220 nF C10 Decoupling V3V 220 nF V1V LC filter 220 nF C11, C12 L1 RF power amplifier bias L2 RF match and harmonic filter L3 RF match L4 V1V LC filter X1 32 MHz crystal 22 mH www.onsemi.com 30 NCS36510 1 V System 3.3V 1V TXD UART1 SWD Debug DIO[0] RXD DIO[1] CTS DIO[2] RTS DIO[3] SWO DIO[11] SWCLK DIO[12] SWDIO DIO[13] SWD_RESET RESETN C8 VPA V1V 5 C9 DVDD C6 VDDIO C5 21,20 16 34 RFPWR 14 33 C1 13 L1 12 L2 TX 32 L3 11 C4 NCS36510 39 31 C2 RX C3 38 26 37 X32MI X1 36 25 18 C11 C12 V3V FVDDHI L4 22 FVDDHO 17 DC20151130 X32MO 1V C10 Figure 24. 1V System Application Diagram Component C1 C2, C3 Description Decoupling RFPWR Value 100 pF RF match and harmonic filter C4 RF DC Block 100 pF C5 Decoupling VDDIO 220 nF C6 Decoupling V1V 1 mF C7 Decoupling FVDDL 33 nF C8 Decoupling DVDD 33 nF C9 VPA 220 nF C10 Decoupling V3V 220 nF C11, C12 FVDDH LC filter 220 nF L1 RF power amplifier bias L2 RF match and harmonic filter L3 RF match L4 FVDDH LC filter X1 32 MHz crystal 22 mH www.onsemi.com 31 NCS36510 DEBUG PORT CONNECTION To connect the Serial Wire Debug interface, TEST pin needs to be tied to logical ‘1’ level and the debugger pins are wired per below. VDDIO 100 kW 5 DIO[13] 4 SWDIO SWDCLK 6 SWO DIO[11 ] 10 SWD_RESET 1 2 3 5 DIO[12] 37 38 39 NCS 36510 35 TEST 100 nF RESETN 36 16 10 pins SWD debugger RESET DVSS DC20151130 GND Figure 25. Debugger Connection Diagram Table 13. DEBUGGER CONNECTIONS TEST State Part Pin Name Part Direction Debugger Pin Name Debugger Pin Number Function 1 DIO[13] Input/Output SWDIO 2 Serial wire data in & out 1 DIO[12] Input SWCLK 4 Serial wire clock 1 DIO[11] Output SWO 6 Trace output RESETN Input RESETn 10 Resets the target Note that when the debugger is connected, most of the power saving modes are disabled. Only deep sleep mode with all FLASH banks powered is supported, when the power management unit is configured accordingly. Not all debuggers will work down to 1 V. So it’s recommended to do debugging at higher voltages to maintain fast and functional operation. www.onsemi.com 32 NCS36510 ORDERING INFORMATION Device NCS36510MNTXG Package Shipping† QFN40 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 33 NCS36510 PACKAGE DIMENSIONS QFN40 6x6, 0.5P CASE 488AR ISSUE A PIN ONE LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B D ÉÉÉ ÉÉÉ ÉÉÉ E DIM A A1 A3 b D D2 E E2 e L K 0.15 C 2X 2X TOP VIEW 0.15 C (A3) 0.10 C A 40X 0.08 C MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 −−− SIDE VIEW A1 C 6.30 D2 L 40X 11 SOLDERING FOOTPRINT* SEATING PLANE K 20 4.20 40X 40X 21 10 0.65 EXPOSED PAD 1 E2 40X b 0.10 C A B 0.05 C 4.20 6.30 30 1 40 31 e 36X BOTTOM VIEW 40X 0.30 36X 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. WirelessHART is a registered trademark of the FieldComm Group. ZigBee is a registered trademark of ZigBee Alliance. Thread is a trademark of Thread Group, Inc. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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