LB1945H D

Ordering number : EN6193B
LB1945H
Monolithic Digital IC
PWM Current Control Type
http://onsemi.com
Stepping Motor Driver
Overview
The LB1945H is a PWM current control type stepping motor driver.
Feature
• PWM current control (external excitation)
• Load current digital selection (1-2, W1-2, and 2 phase excitation drives possible)
• Built-in upper/lower diode
• Simultaneous ON prevention function (feed-through current prevention)
• Built-in thermal shutdown circuit
• Built-in noise canceler
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum motor supply voltage
VBB max
Output peak current
IO peak
Output continuous current
IO max
Logic supply voltage
VCC max
Logic input voltage range
VIN max
Emitter output voltage
VE max
Conditions
tw ≤ 20μs
Mounted on a specified board *
Ratings
Unit
30
V
1.0
A
0.8
A
6.0
V
-0.3 to VCC
V
1.0
V
Allowable power dissipation
Pd max
1.9
W
Operating temperature
Topr
-20 to +90
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
30409 MS / 82799RM(KI) No.6193-1/7
LB1945H
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Motor supply voltage
VBB
10 to 28
V
Logic supply voltage
VCC
4.75 to 5.25
V
Reference voltage
VREF
1.5 to 5.0
V
Electrical Characteristics at Ta = 25°C, VBB = 24V, VCC = 5V, VREF = 5.0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Output Block
Output stage supply current
Output saturation voltage
Output leakage current
Output sustain voltage
IBB ON
I1 = 0.8V, I2 = 0.8V, ENABLE = 0.8V
IBB OFF
ENABLE = 3.2V
VOsat1
IO = +0.5A, sink
VOsat2
IO = +0.8A, sink
0.5
0.7
V
VOsat3
IO = -0.5A, source
1.6
1.8
V
VOsat4
IO = -0.8A, source
1.8
2.0
V
IO1(leak)
VO = VBB, sink
IO2(leak)
VO = 0V, source
VSUS
0.5
1.0
0.3
2.0
mA
0.2
mA
0.5
V
50
μA
-50
μA
L = 3.9mH, IO = 1.0A, Design guarantee value *
30
V
ICC ON
I1 = 0.8V, I2 = 0.8V, ENABLE = 0.8V
50
70
92
mA
ICC OFF
ENABLE = 3.2V
7
10
13
mA
Logic Block
Logic supply current
Input voltage
VIH
3.2
V
VIL
Input current
Set current control threshold
IIH
VIH = 3.2V
IIL
VIL = 0.8V
Vref/Vsen
I1 = 0.8V, I2 = 0.8V
value
35
50
0.8
V
65
μA
μA
7
10
13
9.5
10
10.5
I1 = 3.2V, I2 = 0.8V
13.5
15
16.5
I1 = 0.8V, I2 = 3.2V
25.5
30
34.5
25
32.5
Reference current
Iref
Vref = 5.0V, I1 = 0.8V, I2 = 0.8V
17.5
CR pin current
ICR
CR = 1.0V
-1.0
Thermal shutdown temperature
T-TSD
Design guarantee value *
Temperature hysteresis width
Ts hys
μA
mA
170
°C
40
°C
* Design guarantee value, Do not measurement.
No.6193-2/7
LB1945H
Package Dimensions
unit : mm (typ)
3233B
Pd max -- Ta
Allowable power dissipation, Pd max -- W
2.4
HEAT SPREADER
15.2
(6.2)
0.65
7.9
10.5
15
(4.9)
28
1
14
0.8
0.25
0.3
0.1
2.7
2.0
1.9
1.6
1.2
0.91
0.8
0.4
0
-20
2.45max
2.0
(2.25)
(0.8)
Specified board: 114.3×76.1×1.6mm3
glass epoxy board.
0
20
40
60
80
90
100
Ambient temperature, Ta -- °C
SANYO : HSOP28H(375mil)
Pin Assignment
OUTA 1
28 OUTB
OUTA 2
27 OUTB
NC 3
26 NC
NC 4
25 NC
E1 5
24 VBB2
23 E2
D-GND 6
22 D-GND
VBB1 7
LB1945H
VCC 8
21 CR
PHASE1 9
20 PHASE2
ENABLE1 10
19 ENABLE2
IA2 11
18 IB2
IA1 12
17 IB1
VREF1 13
16 VREF2
GND 14
15 S-GND
No.6193-3/7
Blanking
time
22
23
27
Blanking
time
OUTB
24
VBB2
Current
select
circuit
Control
logic
ciruit
19 ENABLE2
20 PHASE2
8 VCC
GND 14
VREF1 13
6
D-GND
5
E1
CR
21
OSC
D-GND
E2
15 S-GND
16 VREF2
18 IB2
28
OUTB
IA2 11
Thermal
shutdown
circuit
7
VBB1
17 IB1
Current
select
circuit
Control
logic
ciruit
2
1
IA1 12
ENABLE1 10
PHASE1 9
OUTA
OUTA
LB1945H
Block Diagram
No.6193-4/7
LB1945H
Truth Table
ENABLE
PHASE
OUTA
OUTA
L
H
H
L
L
L
L
H
H
−
OFF
OFF
I1
I2
L
L
Vref / (10 × RE) = IOUT
H
L
Vref / (15 × RE) = IOUT × 2/3
L
H
Vref / (30 × RE) = IOUT × 1/3
H
H
Output current
0
Note: Output is OFF when ENABLE = H or when I1 = I2 = H.
Pin Function
Pin No.
Pin name
Function
7
VBB1
24
VBB2
Cathode pin for the upper-side diodes.
5
E1
Insert resistor RE between these pins and ground to control set current.
23
E2
2
OUTA
OUTA
OUTB
1
27
Output stage power supply voltage pin.
Output pins.
28
OUTB
14
GND
Ground pin.
15
S-GND
Sense ground pin.
Lower-side internal diode ground (anode).
6
D-GND
22
D-GND
21
CR
Triangular wave chopping with CR constant setting.
Triangular wave OFF time is noise cancel time.
13
VREF1
VREF2
Output current setting pins.
16
9
PHASE1
Output phase select input pin.
20
PHASE2
High input: OUTA = H, OUTA = L
10
ENABLE1
Output ON/OFF setting input pins.
19
ENABLE2
High input: output OFF
(Output current is set by inputting a 1.5V to 7.5V voltage.)
Low input: OUTA = L, OUTA = H
Low input: output ON
12,11
IA1,IA2
Output current setting digital input pins.
17,18
IB1,IB2
Current is set to 1/3, 2/3, 1 by High and Low combinations.
VCC
Logic block power supply voltage pin.
8
No.6193-5/7
LB1945H
Application Circuit Example
1 OUTA
OUTB 28
2 OUTA
OUTB 27
L
0.51Ω(1W)
L
3 NC
NC 26
4 NC
NC 25
5 E1
VBB2 24
6 D-GND
7 VBB1
E2 23
0.51Ω(1W)
D-GND 22
24V
47μF
LB1945H
10μF
82kΩ
CR 21
820pF
Logic input
9 PHASE1
PHASE2 20
10 ENABLE1
ENABLE2 19
11 IA2
IB2 18
12 IA1
IB1 17
Logic input
8 VCC
5V
0.1μF
Voltage from 1.5 to
5V can be applied.
13 VREF1
VREF2 16
14 GND
S-GND 15
The fin on the bottom of HSOP-28H package and the fins between pins 7 and 8 and 21 and 22 should be grounded.
No.6193-6/7
LB1945H
Usage Notes
1. VREF pin
Because the VREF pin is used as reference voltage input pin for the current setting, care must be taken to prevent
noise from affecting the input.
2. GND pin
Because this IC switches large currents, the ground pattern must be designed with care. The fin on the bottom of the
package and the fins between pins 7 and 8 and 21 and 22 should be grounded. Low-impedance patterns should be used
in blocks where large currents flow, and these blocks should be separated from low-level signal blocks. In particular,
the ground of the sense resistor RE at pin E should be located close to the IC ground. Pattern layout should be
designed so that the capacitors between VCC and ground and VBB and ground are close to VCC and VBB.
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PS No.6193-7/7