N25S818HA 256 kb Low Power Serial SRAMs 32 k x 8 Bit Organization Introduction The ON Semiconductor serial SRAM family includes several integrated memory devices including this 256 kb serially accessed Static Random Access Memory, internally organized as 32 k words by 8 bits. The devices are designed and fabricated using ON Semiconductor’s advanced CMOS technology to provide both high−speed performance and low power. The devices operate with a single chip select (CS) input and use a simple Serial Peripheral Interface (SPI) serial bus. A single data in and data out line is used along with a clock to access data within the devices. The N25S818HA devices include a HOLD pin that allows communication to the device to be paused. While paused, input transitions will be ignored. The devices can operate over a wide temperature range of −40°C to +85°C and can be available in several standard package offerings. Features • • • • • • • • • • • • Power Supply Range: 1.7 to 1.95 V Very Low Standby Current: Typical Isb as low as 200 nA Very Low Operating Current: As low as 3 mA Simple Memory Control: Single chip select (CS) Serial input (SI) and serial output (SO) Flexible Operating Modes: Word read and write Page mode (32 word page) Burst mode (full array) Organization: 32 k x 8 bit Self Timed Write Cycles Built−in Write Protection (CS High) HOLD Pin for Pausing Communication High Reliability: Unlimited write cycles Green SOIC and TSSOP These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2012 June, 2012 − Rev. 12 1 http://onsemi.com MARKING DIAGRAMS C124 XXXXYZZ TSSOP−8 T SUFFIX CASE 948AL C114 XXXXYZZ SOIC−8 S SUFFIX CASE 751BD XXXX Y ZZ = Date Code = Assembly Code = Lot Traceability ORDERING INFORMATION Package Shipping† N25S818HAS21I SOIC−8 (Pb−Free) 100 Units / Tube N25S818HAT21I TSSOP−8 (Pb−Free) 100 Units / Tube N25S818HAS21IT SOIC−8 (Pb−Free) 3000 / Tape & Reel N25S818HAT21IT TSSOP−8 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: N25S818HA/D N25S818HA 1 CS SO NC VSS CS VCC HOLD SCK SI 1 VCC SO HOLD NC SCK SI VSS TSSOP−8 SOIC−8 Figure 1. Pin Connections (Top View) Table 1. DEVICE OPTIONS Part Number N25S818HAS2 N25S818HAT2 Density Power Supply (V) Speed (MHz) 256 Kb 1.8 16 Package SOIC TSSOP Typical Standby Current Read/Write Operating Current 200 nA 3 mA @ 1 Mhz Table 2. PIN NAMES Pin Name Pin Function CS Chip Select Input SCK Serial Clock Input SI Serial Data Input SO Serial Data Output HOLD Hold Input NC No Connect VCC Power VSS Ground SCK Clock Circuitry HOLD CS Decode Logic SRAM Array SI Data In Receiver SO Data Out Buffer Figure 2. Functional Block Diagram http://onsemi.com 2 N25S818HA Table 3. ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT –0.3 to VCC + 0.3 V Voltage on VCC Supply Relative to VSS VCC –0.3 to 4.5 V Power Dissipation PD 500 mW TSTG –40 to 125 °C TA −40 to +85 °C TSOLDER 260°C, 10 sec °C Storage Temperature Operating Temperature Soldering Temperature and Time Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. OPERATING CHARACTERISTICS (Over Specified Temperature Range) Item Symbol Test Conditions Min Supply Voltage VCC 1.8 V Device Input High Voltage Typ (Note 1) Max Unit 1.7 1.95 V VIH 0.7 x VCC VCC + 0.3 V Input Low Voltage VIL −0.3 0.8 V Output High Voltage VOH IOH = −0.4 mA Output Low Voltage VOL IOL = 1 mA 0.2 V VCC – 0.5 V Input Leakage Current ILI CS = VCC, VIN = 0 to VCC 0.5 mA Output Leakage Current ILO CS = VCC, VOUT = 0 to VCC 0.5 mA Read/Write Operating Current ICC1 F = 1 MHz, IOUT = 0 3 mA ICC2 F = 10 MHz, IOUT = 0 6 mA ICC3 F = fCLK MAX, IOUT = 0 10 mA ISB CS = VCC, VIN = VSS or VCC 500 nA Standby Current 200 1. Typical values are measured at Vcc = Vcc Typ., TA = 25°C and are not 100% tested. Table 5. CAPACITANCE (Note 2) Symbol Test Condition Input Capacitance CIN I/O Capacitance CI/O Item Max Unit VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF VIN = 0 V, f = 1 MHz, TA = 25°C 7 pF 2. These parameters are verified in device characterization and are not 100% tested http://onsemi.com 3 Min N25S818HA Table 6. TIMING TEST CONDITIONS Item Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise and Fall Time 5 ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 100 pF Operating Temperature −40 to +85°C Table 7. TIMING Max Units Clock Frequency Item Symbol fCLK 16 MHz Clock Rise Time tR 2 ms Clock Fall Time tF 2 ms Clock High Time tHI 32 ns Clock Low Time tLO 32 ns Clock Delay Time tCLD 32 ns CS Setup Time tCSS 32 ns CS Hold Time tCSH 50 ns CS Disable Time tCSD 32 ns SCK to CS tSCS 5 ns Data Setup Time tSU 10 ns Data Hold Time tHD 10 Output Valid From Clock Low Min tV ns 32 Output Hold Time tHO Output Disable Time tDIS HOLD Setup Time tHS 10 ns HOLD Hold Time tHH 10 ns HOLD Low to Output High−Z tHZ 10 HOLD High to Output Valid tHV http://onsemi.com 4 0 ns ns 20 ns ns 50 ns N25S818HA tCSD CS tCLD tR tF tCSH tSCS tCSS SCK tSU tHD LSB in MSB in SI High−Z SO Figure 3. Serial Input Timing CS tLO tHI tCSH SCK tV SO tDIS LSB out MSB out Don’t Care SI Figure 4. Serial Output Timing CS tHH tHS tHS SCK tHH SO n+2 n+1 n High−Z tHV n tHZ SI n+2 n+1 n−1 tSU n Don’t Care n HOLD Figure 5. Hold Timing http://onsemi.com 5 n−1 N25S818HA Table 8. CONTROL SIGNAL DESCRIPTIONS Signal Name I/O Description CS Chip Select I A low level selects the device and a high level puts the device in standby mode. If CS is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. When CS is high, SO is in high−Z. CS must be driven low after power−up prior to any sequence being started. SCK Serial Clock I Synchronizes all activities between the memory and controller. All incoming addresses, data and instructions are latched on the rising edge of SCK. Data out is updated on SO after the falling edge of SCK. SI Serial Data In I Receives instructions, addresses and data on the rising edge of SCK. SO Serial Data Out O Data is transferred out after the falling edge of SCK. HOLD Hold I A high level is required for normal operation. Once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low, the Hold function will not be invoked until the next SCK high to low transition. The device must remain selected during this sequence. SO is high−Z during the Hold time and SI and SCK are inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low. Lowering the HOLD input at any time will take to SO output to High−Z. Functional Operation Basic Operation The 256 Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI) common on many standard micro−controllers. It may also interface with other non−SPI ports by programming discrete I/O lines to operate the device. The serial SRAM contains an 8−bit instruction register and is accessed via the SI pin. The CS pin must be low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it was held. The following table contains the possible instructions and formats. All instructions, addresses and data are transferred MSB first and LSB last. Table 9. INSTRUCTION SET Instruction Instruction Format READ 0000 0011 Read data from memory starting at selected address Description WRITE 0000 0010 Write data to memory starting at selected address RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register READ Operations addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. If operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (7FFFh), the address counter wraps to the address 0000h. This allows the burst read cycle to be continued indefinitely. All READ operations are terminated by pulling CS high. The serial SRAM READ is selected by enabling CS low. First, the 8−bit READ instruction is transmitted to the device followed by the 16−bit address with the MSB being a don’t care. After the READ instruction and addresses are sent, the data stored at that address in memory is shifted out on the SO pin after the output valid time from the clock edge. If operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. This can be continued for the entire page length of 32 words long. At the end of the page, the http://onsemi.com 6 N25S818HA CS 0 1 2 3 4 5 6 7 8 9 10 21 22 23 2 1 0 11 24 25 26 27 28 29 30 2 1 31 SCK 16−bit address Instruction 0 SI 0 0 0 0 0 1 1 15 14 13 12 Data Out High−Z SO 7 6 5 4 3 0 Figure 6. Word READ Sequence CS 0 1 2 3 4 5 6 7 8 9 10 21 22 23 2 1 0 11 24 25 26 27 28 29 30 31 1 0 SCK Instruction 0 SI 0 0 0 0 16−bit address 0 1 1 15 14 13 12 Don’t Care ADDR 1 Data Out from ADDR 1 7 High−Z SO 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 6 5 4 3 2 47 Don’t Care Data Out from ADDR 2 7 6 5 4 3 2 Data Out from ADDR n Data Out from ADDR 3 1 0 7 6 5 4 3 2 1 0 ... 7 Figure 7. Page and Burst READ Sequence http://onsemi.com 7 6 5 4 3 2 1 0 N25S818HA SI 16−bit address Page address (X) Word address (Y) Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SO Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word Y+2 Word 31 Word 0 Word 1 Figure 8. Page READ Sequence SI Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. 16−bit address Page address (X) Word address (Y) ... SO ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y−1 Word Y Page X+1 Page X+1 Word Y+1 Figure 9. Burst READ Sequence WRITE Operations page and the operation can be continuously looped over the 32 words of the same page. The new data will replace data already stored in the memory locations. If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each word of data is read out. This can be continued for the entire array and when the highest address is reached (7FFFh), the address counter wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new data will replace data already stored in the memory locations. All WRITE operations are terminated by pulling CS high. The serial SRAM WRITE is selected by enabling CS low. First, the 8−bit WRITE instruction is transmitted to the device followed by the 16−bit address with the MSB being a don’t care. After the WRITE instruction and addresses are sent, the data to be stored in memory is shifted in on the SI pin. If operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. Simply write the data on SI pin and continue to provide clock pulses. The internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. This can be continued for the entire page length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word address within the CS 0 1 2 3 4 5 6 7 8 9 15 14 10 11 21 22 23 24 25 26 1 0 7 6 5 27 28 29 30 31 3 2 1 0 SCK Instruction SI SO 0 0 0 0 0 16−bit address 0 1 0 13 12 ... 2 Data In High−Z Figure 10. Word WRITE Sequence http://onsemi.com 8 4 N25S818HA CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 0 SI 0 0 0 16−bit address 0 0 1 15 0 14 13 12 2 1 0 7 6 ADDR 1 5 4 3 2 1 0 Data In to ADDR 1 High−Z SO 32 33 34 35 36 37 38 39 40 Data In to ADDR 2 7 6 5 4 3 41 42 43 44 45 46 47 Data In to ADDR 3 2 1 0 7 6 5 4 3 Data In to ADDR n 2 1 0 ... 7 6 5 4 3 2 1 0 High−Z Figure 11. Page and Burst WRITE Sequence Data Words: sequential, at the end of the page the address wraps back to the beginning of the page SI 16−bit address Page address (X) Word address (Y) Page X Page X Word Y Word Y+1 Word Y+2 SO Page X Page X Page X Page X Word 31 Word 0 Word 1 Page X+1 Page X+1 High−Z Figure 12. Page WRITE Sequence ... SI 16−bit address Page address (X) Word address (Y) ... Page X Page X Page X Page X Page X Page X Word Y Word Y+1 Word 31 Word 0 Word 1 Word Y−1 Word Y Word Y+1 Data Words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. At that time, the address increments to the next page and the burst continues. SO High−Z Figure 13. Burst WRITE Sequence http://onsemi.com 9 N25S818HA WRITE Status Register Instruction (WRSR) This instruction provides the ability to write the status register and select among several operating modes. Several of the register bits must be set to a low ‘0’ if any of the other bits are written. The timing sequence to write to the status register is shown below, followed by the organization of the status register. CS 0 SCK 1 2 3 4 5 6 7 8 9 Instruction SI 0 0 0 0 10 11 12 13 14 15 Status Register Data In 0 0 0 1 7 6 5 4 3 2 1 0 High−Z SO Figure 14. WRITE Status Register Sequence Bit 7 Bit 6 Bit 5 Mode 0 1 0 1 0 = Word Mode (Default) 0 = Page Mode 1 = Burst Mode 1 = Reserved Bit 4 Bit 3 Bit 2 Reserved Reserved Must = 0 Must = 0 Bit 1 Bit 0 Hold Function 0 = Hold (Default) 1 = No Hold Figure 15. Status Register READ Status Register Instruction (RDSR) This instruction provides the ability to read the Status register. The register may be read at any time by performing the following timing sequence. CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 0 0 0 0 0 1 0 1 Status Register Data Out SO 7 High−Z 6 5 4 3 2 1 0 Figure 16. READ Status Register Instruction (RDSR) Power−Up State The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level on CS is required to enter an active state. http://onsemi.com 10 N25S818HA PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 0.15 0.90 1.05 0.30 c 0.09 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.20 0.65 BSC L 1.00 REF L1 0.50 θ 0º 0.60 0.75 8º e TOP VIEW D A2 c q1 A A1 L1 SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 11 N25S818HA PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L END VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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