74LVC574A D

74LVC574A
Low-Voltage CMOS Octal
D-Type Flip-Flop
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The 74LVC574A is a high performance, non−inverting octal D−type
flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5 V allows 74LVC574A inputs to
be safely driven from 5 V devices.
The 74LVC574A consists of 8 edge−triggered flip−flops with
individual D−type inputs and 3−state true outputs. The buffered clock
and buffered Output Enable (OE) are common to all flip−flops. The
eight flip−flops will store the state of individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. With the OE LOW, the contents of the eight flip−flops are
available at the outputs. When the OE is HIGH, the outputs go to the
high impedance state. The OE input level does not affect the operation
of the flip−flops.
•
•
Designed for 1.2 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 1
20
20
1
LCV
574A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
•
•
•
•
•
•
MARKING
DIAGRAM
1
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
Publication Order Number:
74LVC574A/D
74LVC574A
1
OE
CP
11
O0
O1
O2
O3
O4
O5
O6
O7
CP
20
19
18
17
16
15
14
13
12
11
D
D1
D
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
D
D
Function
Output Enable Input
CP
Clock Pulse Input
D0−D7
Data Inputs
O0−O7
3−State Outputs
15
CP
D4
D
14
CP
D
13
CP
8
D6
D
12
CP
9
Q
D
TRUTH TABLE
=
=
=
=
=
=
=
=
=
OUTPUTS
OE
CP
Dn
On
L
L
↑
↑
l
h
L
H
Load and Read Register
L
↑
X
NC
Hold and Read Register
H
↑
X
Z
Hold and Disable Outputs
H
H
↑
↑
l
h
Z
Z
Load Internal Register and Disable Outputs
OPERATING MODE
High Voltage Level
High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
Low Voltage Level
Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
No Change, State Prior to Low−to−High Clock Transition
High or Low Voltage Level and Transitions are Acceptable
High Impedance State
Low−to−High Transition
Not a Low−to−High Transition; For ICC Reasons, DO NOT FLOAT Inputs
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2
O6
Q
Figure 2. Logic Diagram
H
h
L
l
NC
X
Z
↑
↑
O5
Q
D7
INPUTS
O4
Q
D5
OE
O3
Q
7
Pins
16
CP
6
PIN NAMES
O2
Q
D3
Figure 1. Pinout: 20−Lead (Top View)
17
CP
5
3
O1
Q
D2
2
18
CP
3
4
1
O0
Q
D0
VCC
19
CP
2
O7
74LVC574A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Condition
Value
Unit
−0.5 to +6.5
V
−0.5 ≤ VI ≤ +6.5
V
Output in 3−State
−0.5 ≤ VO ≤ +6.5
V
Output in HIGH or LOW State
(Note 1)
−0.5 ≤ VO ≤ VCC + 0.5
V
DC Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
VI < GND
−50
mA
IOK
DC Output Diode Current
VO < GND
−50
mA
VO > VCC
+50
mA
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
IO
TL
Lead Temperature, 1 mm from Case for
10 Seconds
TL = 260
°C
TJ
Junction Temperature Under Bias
TJ = 135
°C
110.7
°C/W
qJA
Thermal Resistance (Note 2)
MSL
Moisture Sensitivity
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Typ
Max
Unit
V
Supply Voltage Operating Functional
1.65
1.2
3.6
3.6
VI
Input Voltage
0
5.5
VO
Output Voltage
HIGH or LOW State
3−State
0
0
VCC
5.5
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V
IOL
LOW Level Output Current
VCC = 3.0 V − 3.6 V VCC = 2.7 V − 3.0 V
TA
Operating Free−Air Temperature
−40
+125
Dt/DV
Input Transition Rise or Fall Rate,
VCC = 1.65 to 2.7 V
VCC = 2.7 to 3.6 V
0
0
20
10
V
V
mA
−24
−12
mA
24
12
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC574A
DC ELECTRICAL CHARACTERISTICS
−40 to +855C
Symbol
VIH
VIL
VOH
VOL
Parameter
HIGH−level input voltage
LOW−level input voltage
HIGH−level output voltage
−40 to +1255C
Conditions
Min
Typ
(Note 3)
Max
Min
Typ
(Note 3)
Max
Unit
VCC = 1.2 V
1.08
−
−
1.08
−
−
V
VCC = 1.65 V to 1.95 V
0.65 x
VCC
−
−
0.65 x
VCC
−
−
VCC = 2.3 V to 2.7 V
1.7
−
−
1.7
−
−
VCC = 2.7 V to 3.6 V
2.0
−
−
2.0
−
−
VCC = 1.2 V
−
−
0.12
−
−
0.12
VCC = 1.65 V to 1.95 V
−
−
0.35 x
VCC
−
−
0.35 x
VCC
VCC = 2.3 V to 2.7 V
−
−
0.7
−
−
0.7
VCC = 2.7 V to 3.6 V
−
−
0.8
−
−
0.8
V
VI = VIH or VIL
IO = −100 mA;
VCC = 1.65 V to 3.6 V
VCC −
0.2
−
−
VCC −
0.3
−
−
IO = −4 mA; VCC = 1.65 V
1.2
−
−
1.05
−
−
IO = −8 mA; VCC = 2.3 V
1.8
−
−
1.65
−
−
IO = −12 mA; VCC = 2.7 V
2.2
−
−
2.05
−
−
IO = −18 mA; VCC = 3.0 V
2.4
−
−
2.25
−
−
IO = −24 mA; VCC = 3.0 V
2.2
−
−
2.0
−
−
V
VI = VIH or VIL
LOW−level output voltage
V
IO = 100 mA;
VCC = 1.65 V to 3.6 V
−
−
0.2
−
−
0.3
IO = 4 mA; VCC = 1.65 V
−
−
0.45
−
−
0.65
IO = 8 mA; VCC = 2.3 V
−
−
0.6
−
−
0.8
IO = 12 mA; VCC = 2.7 V
−
−
0.4
−
−
0.6
IO = 24 mA; VCC = 3.0 V
−
−
0.55
−
−
0.8
Input leakage current
VI = 5.5 V or GND;
VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOZ
OFF−state output current
VI = VIH or VIL;
VO = 5.5 V or GND;
VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOFF
Power−off leakage current
VI or VO = 5.5 V; VCC = 0.0 V
−
±0.1
±10
−
±0.1
±20
mA
ICC
Supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
−
0.1
10
−
0.1
40
mA
Additional supply current
per input pin;
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
−
5
500
−
5
5000
mA
II
DICC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. All typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
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4
74LVC574A
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
−40 to +855C
Symbol
tpd
ten
tdis
tw
tsu
th
fmax
tsk(0)
Parameter
Propagation Delay (Note 5)
CP to On
Enable Time (Note 6)
OE to On
Disable Time (Note 7)
OE to On
Pulse Width
Clock HIGH or LOW
Set−up Time
Dn to CP
Hold Time
Dn to CP
Maximum Frequency
−40 to +1255C
Conditions
Min
Typ
(Note 4)
Max
Min
Typ
(Note 4)
Max
VCC = 1.2 V
−
17.0
−
−
−
−
VCC = 1.65 V to 1.95 V
4.6
6.4
13.1
4.6
−
15.1
VCC = 2.3 V to 2.7 V
2.6
3.9
7.9
2.6
−
9.1
VCC = 2.7 V
1.5
3.7
8.0
1.5
−
10.0
VCC = 3.0 V to 3.6 V
1.5
3.5
7.0
1.5
−
9.0
VCC = 1.2 V
−
19.0
−
−
−
−
VCC = 1.65 V to 1.95 V
1.5
7.0
17.1
1.5
−
19.8
VCC = 2.3 V to 2.7 V
1.5
4.0
9.4
1.5
−
10.9
VCC = 2.7 V
1.5
4.1
8.5
1.5
−
11.0
VCC = 3.0 V to 3.6 V
1.5
3.2
7.5
1.5
−
9.5
VCC = 1.2 V
−
9.0
−
−
−
−
VCC = 1.65 V to 1.95 V
2.5
4.1
10.1
2.5
−
11.6
VCC = 2.3 V to 2.7 V
1.0
2.3
5.7
1.0
−
6.6
VCC = 2.7 V
1.5
3.1
6.5
1.5
−
8.5
VCC = 3.0 V to 3.6 V
1.5
2.9
6.0
1.5
−
7.5
VCC = 1.65 V to 1.95 V
5.0
−
−
5.0
−
−
VCC = 2.3 V to 2.7 V
4.0
−
−
4.0
−
−
VCC = 2.7 V
3.3
−
−
3.3
−
−
VCC = 3.0 V to 3.6 V
3.3
1.7
−
3.3
−
−
VCC = 1.65 V to 1.95 V
4.0
−
−
4.0
−
−
VCC = 2.3 V to 2.7 V
2.5
−
−
2.5
−
−
VCC = 2.7 V
2.0
−
−
2.0
−
−
VCC = 3.0 V to 3.6 V
2.0
0.3
−
2.0
−
−
VCC = 1.65 V to 1.95 V
3.0
−
−
3.0
−
−
VCC = 2.3 V to 2.7 V
2.0
−
−
2.0
−
−
VCC = 2.7 V
1.5
−
−
1.5
−
−
VCC = 3.0 V to 3.6 V
1.5
−0.2
−
1.5
−
−
VCC = 1.65 V to 1.95 V
100
−
−
80
−
−
VCC = 2.3 V to 2.7 V
125
−
−
100
−
−
VCC = 2.7 V
150
−
−
120
−
−
VCC = 3.0 V to 3.6 V
150
200
−
120
−
−
−
−
1.0
−
−
1.5
Output Skew Time (Note 8)
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. tpd is the same as tPLH and tPHL.
6. ten is the same as tPZL and tPZH.
7. tdis is the same as tPLZ and tPHZ.
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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5
74LVC574A
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage
(Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage
(Note 9)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
CIN
COUT
CPD
Parameter
Condition
Typical
Unit
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
5.0
pF
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
6.0
pF
Power Dissipation Capacitance
(Note 10)
VCC = 1.65 V to 1.95 V
11.2
VCC = 2.3 V to 2.7 V
13.2
VCC = 3.0 V to 3.6 V
14.9
10. CPD is used to determine the dynamic power dissipation (PD in mW).
P D + C PD
V CC
2
fi
N ) SǒC L
pF
Per flip−flop; VI = GND or VCC
V CC
2
foǓ where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of outputs switching
∑(CL x VCC2 x fo) = sum of the outputs
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6
74LVC574A
2.7 V
2.7 V
Dn
0V
0V
tPZH
th
ts
1.5 V
1.5 V
OE
1.5 V
tPHZ
2.7 V
CP
VOH - 0.3 V
1.5V
On
1.5 V
≈0V
0V
fmax
tPLH, tPHL
tPZL
tPLZ
VOH
On
1.5V
On
GND
VOL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
WAVEFORM 1 − PROPAGATION DELAYS,
SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
1.5 V
1.5 V
tw
0V
2.7 V
tw
CP
≈ 3.0 V
VOL + 0.3 V
1.5 V
CP
VCC
1.5 V
1.5 V
0V
WAVEFORM 3 − PULSE WIDTH
tR = tF = 2.5 ns (or fast as required) from 10% to 90%;
Output requirements: VOL ≤ 0.8 V, VOH ≥ 2.0 V
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
VCC < 2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
Figure 3. AC Waveforms
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7
74LVC574A
VCC
R1
PULSE
GENERATOR
DUT
RT
Supply Voltage
CL
Input
6V
OPEN
GND
RL
VEXT
Load
tPLH, tPHL tPLZ, tPZL tPHZ, tPZH
VCC (V)
VI
tr, tf
CL
RL
1.2
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
1.65 − 1.95
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
2.3 − 2.7
VCC
≤ 2 ns
30 pF
500 W
Open
2 x VCC
GND
2.7
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
3.0 − 3.6
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
Figure 4. Test Circuit
ORDERING INFORMATION
Device
74LVC574ADTR2G
Package
Shipping†
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
74LVC574A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
K
K1
2X
L/2
20
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
L
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74LVC574A
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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